A semiconductor structure and a method of fabricating the same

Abstract

This application relates to a semiconductor structure and its fabrication method, comprising: a semiconductor substrate, a drift region, a mesh-like shielding doped layer, and a trench gate structure. The drift region is located on the semiconductor substrate and includes an epitaxial layer. The mesh-like shielding doped layer is located in the epitaxial layer and includes cross-connected first and second portions. The first portions are uniformly spaced in a first direction and extend along a second direction, while the second portions are uniformly spaced in the second direction and extend along the first direction, the first and second directions intersecting. The trench gate structure is located in the epitaxial layer, wherein the trench gate structure is located between adjacent first portions, spans multiple second portions in the second direction, and the depth of the trench gate structure is less than the depth of the mesh-like shielding doped layer. The semiconductor structure and its fabrication method of this application effectively alleviate the electric field distribution at the bottom of the trench gate structure, improve device reliability, and reduce manufacturing costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Trench silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have become the core of third-generation semiconductor devices due to their excellent conductivity, high switching speed, and superior thermal stability. However, traditional trench MOSFET devices suffer from electric field concentration at the bottom of the gate trench, which can easily lead to localized breakdown. In particular, the poor reliability of the gate oxide layer limits their long-term stable operation and breakdown voltage improvement.

[0003] Therefore, improving the electric field distribution at the bottom of the trench and enhancing the gate oxide reliability have become key issues in the design of trench MOSFET structures. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem of bottom electric field concentration in existing trench silicon carbide MOSFETs.

[0005] To achieve the above objectives, this application provides a semiconductor structure, comprising:

[0006] Semiconductor substrate of the first conductivity type;

[0007] The drift region, located on the semiconductor substrate, includes an epitaxial layer of a first conductivity type;

[0008] A second conductivity type mesh shielding doped layer is located in the epitaxial layer. The mesh shielding doped layer includes a first part and a second part that are cross-connected. The first part is uniformly spaced in a first direction and extends along a second direction. The second part is uniformly spaced in the second direction and extends along the first direction. The first direction intersects the second direction.

[0009] A trench gate structure is located in the epitaxial layer, wherein the trench gate structure is located between adjacent first portions, the trench gate structure spans multiple second portions in a second direction, and the depth of the trench gate structure is less than the depth of the mesh shielding doped layer.

[0010] In one embodiment, the drift region further includes a well layer of a second conductivity type and a source region of a first conductivity type, the well layer and the source region being stacked on the upper surface of the epitaxial layer, and the doping concentration of the mesh shielding doped layer being greater than the doping concentration of the well layer.

[0011] In one embodiment, the depth of the first part is the same as the depth of the second part.

[0012] In one embodiment, the semiconductor structure further includes a first metal layer covering the first portion and / or the second portion.

[0013] In one embodiment, a first contact layer is further included between the first metal layer and the mesh shielding doped layer, the first contact layer being used to form an electrical connection between the first metal layer and the mesh shielding doped layer.

[0014] In one embodiment, the semiconductor structure further includes an interlayer dielectric layer located above the trench gate structure.

[0015] In one embodiment, the back side of the semiconductor substrate is further provided with a second contact layer and a second metal layer.

[0016] In one embodiment, the trench gate structure includes a gate trench, a gate dielectric layer, and a gate layer, wherein the bottom of the gate trench includes a rounded transition region between the bottom and the sidewall, the gate dielectric layer covers the inner wall of the gate trench, and the gate layer covers the gate dielectric layer and fills the gate trench.

[0017] On the other hand, this application also provides a method for fabricating a semiconductor structure, comprising:

[0018] Provide a semiconductor substrate of a first conductivity type;

[0019] A drift region is formed on the semiconductor substrate, the drift region comprising an epitaxial layer of a first conductivity type;

[0020] A second conductivity type mesh shielding doped layer is formed in the epitaxial layer. The mesh shielding doped layer includes a first part and a second part that are cross-connected. The first part is spaced apart in a first direction and extends along a second direction. The second part is spaced apart in the second direction and extends along the first direction. The first direction and the second direction intersect.

[0021] A trench gate structure is formed in the epitaxial layer, wherein the trench gate structure is located between adjacent first portions, the trench gate structure spans multiple second portions in a second direction, and the depth of the trench gate structure is less than the depth of the mesh shielding doped layer.

[0022] In one embodiment, a mesh-like shielding doped layer of a second conductivity type is formed in the epitaxial layer, including:

[0023] A patterned mask layer is formed above the epitaxial layer;

[0024] Based on the patterned mask layer, ion implantation is performed in the epitaxial layer to form a cross-connected first part and a second part, wherein the first part is spaced apart in a first direction and extends along a second direction, and the second part is spaced apart in the second direction and extends along the first direction to obtain the mesh shielding doped layer.

[0025] The semiconductor structure and its fabrication method described in this application utilize a cross-connected mesh-like shielding doped layer on the epitaxial layer. This mesh-like shielding doped layer includes a first part and a second part that are cross-connected. The first part is uniformly spaced in a first direction and extends along a second direction, while the second part is uniformly spaced in the second direction and extends along the first direction. The first and second directions intersect, effectively mitigating the concentration of the electric field at the bottom of the trench gate structure, reducing the electrical stress and breakdown risk of the gate dielectric layer. Simultaneously, the cross-connected layout of the mesh-like shielding doped layer enhances the protection of the trench gate structure, improves the overall reliability and withstand voltage performance of the device, and maintains good conduction characteristics, thus achieving a high-performance, high-reliability power semiconductor device. Furthermore, the second part is formed synchronously with the first part through doping implantation. In one embodiment, a first metal layer covers the first part and / or the second part. Therefore, electrical connections and signal or current paths can be established from at least one part of the cross-connected mesh structure, simplifying the manufacturing process, avoiding additional interconnect structures, greatly improving the convenience and ease of implementation of the process, effectively reducing the overall manufacturing cost, and improving the integration and operational stability of the device. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in one embodiment;

[0028] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure along the AA' direction provided in the diagram;

[0029] Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure along the BB' direction provided in the diagram;

[0030] Figure 4 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment.

[0031] Explanation of reference numerals in the attached figures:

[0032] 1-Semiconductor substrate, 2-Drift region, 21-Epipolar layer, 22-Well layer, 23-Source region, 3-Mesh shielding doped layer, 31-First part, 32-Second part, 4-Trench gate structure, 41-Gate trench, 411-Rounded corner transition region, 42-Gate dielectric layer, 43-Gate layer, 5-First metal layer, 51-First contact layer, 6-Interlayer dielectric layer. Detailed Implementation

[0033] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0038] Please see Figures 1 to 3 This application provides a semiconductor structure, including: a semiconductor substrate 1 of a first conductivity type, a drift region 2, a mesh shielding doped layer 3 of a second conductivity type, and a trench gate structure 4, wherein the drift region 2 is located on the semiconductor substrate 1 and includes an epitaxial layer 21 of the first conductivity type; the mesh shielding doped layer 3 of the second conductivity type is located in the epitaxial layer 21, and the mesh shielding doped layer 3 includes cross-connected first portions 31 and second portions 32, wherein the first portions 31 are uniformly spaced in a first direction and extend along a second direction, and the second portions 32 are uniformly spaced in the second direction and extend along the first direction, and the first direction intersects the second direction; the trench gate structure 4 is located in the epitaxial layer 21, the trench gate structure 4 is located between adjacent first portions 31, the trench gate structure 4 spans multiple second portions 32 in the second direction, and the depth of the trench gate structure 4 is less than the depth of the mesh shielding doped layer 3.

[0039] In the above example, by setting a cross-connected mesh shielding doped layer 3 on the epitaxial layer 21, the mesh shielding doped layer 3 includes a first part 31 and a second part 32, wherein the first part 31 is uniformly spaced in a first direction and extends along a second direction, and the second part 32 is uniformly spaced in the second direction and extends along the first direction, with the first direction intersecting the second direction. This structural design can effectively alleviate the concentration of electric field at the bottom of the trench gate structure 4, and reduce the electrical stress and breakdown risk of the gate dielectric layer 42. At the same time, the cross-layout of the mesh shielding doped layer 3 enhances the shielding and protection of the trench gate structure 4, improves the overall withstand voltage and operational reliability of the device, and realizes a high-performance, high-reliability power semiconductor device while ensuring conduction performance.

[0040] It should be noted that the first conductivity type and the second conductivity type are opposite conductivity types. Specifically, when the first conductivity type is N-type, the second conductivity type is P-type; and when the first conductivity type is P-type, the second conductivity type is N-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0041] For example, the semiconductor substrate 1 is made of silicon carbide. Compared with traditional silicon materials, silicon carbide has a higher breakdown electric field strength, higher thermal conductivity, wider bandgap, and stronger radiation resistance, making it particularly suitable for fabricating power devices with high voltage resistance, high frequency, and high power density.

[0042] For example, the drift region 2 is used as the formation region for the subsequent trench gate structure 4, source region 23, well layer 22 and mesh shielding doped layer 3.

[0043] The epitaxial layer 21 has the same conductivity type as the semiconductor substrate 1. The epitaxial layer 21 is a lightly doped region, with a doping concentration lower than that of the semiconductor substrate 1, to achieve good electric field spreading characteristics and high breakdown voltage performance. Specifically, the doping concentration of the epitaxial layer 21 is 5 × 10⁻⁶. 11 cm -3 Up to 1.5×10 17 cm -3 The semiconductor substrate 1 is typically a heavily doped region, with a doping concentration much higher than that of the epitaxial layer 21, for example, 1 × 10⁻⁶. 18 cm -3 Or even higher, the heavily doped semiconductor substrate 1 mainly provides good mechanical support and conductivity, ensuring the current carrying capacity of the overall device in high-power applications.

[0044] The thickness of the epitaxial layer 21 is typically designed according to the breakdown voltage required by the device, and the thickness of the epitaxial layer 21 ranges from 5 μm to 20 μm.

[0045] For example, when both the semiconductor substrate 1 and the epitaxial layer 21 are made of silicon carbide, the epitaxial layer 21 has higher breakdown field strength and thermal stability than silicon material, which can meet the structural requirements of high voltage and high power devices.

[0046] In one embodiment, the semiconductor structure further includes a well layer 22 of a second conductivity type and a source region 23 of a first conductivity type, stacked on the upper surface of the epitaxial layer 21. The well layer 22 is formed by implanting impurities of the second conductivity type (such as boron or aluminum) into the surface region of the epitaxial layer 21 to form an effective gate-controlled region and suppress the turn-on of parasitic transistors. The source region 23 is formed on the surface of the well layer by implanting high-concentration impurities of the first conductivity type (such as phosphorus or nitrogen) to achieve ohmic contact with the source metal and form the start end of an inversion channel. In this embodiment, the source region 23 is embedded in the surface region of the well layer 22 to form a P / N junction structure, which is beneficial for forming a gate-controlled inversion channel and improving the device's conduction capability and switching efficiency. In this embodiment, the doping concentration of the well layer 22 is 1×10⁻⁶. 15 cm -3 Up to 1×10 18 cm -3 .

[0047] In one embodiment, such as Figure 1 As shown, the mesh-like shielding doped layer 3 forms a periodically distributed mesh structure through the cross-arranged first part 31 and second part 32. It should be noted that the width and doping depth of the first part 31 and second part 32 in the mesh-like shielding doped layer 3 can be flexibly adjusted according to device design parameters (such as breakdown voltage, electric field distribution, trench location, etc.). The specific size range can be determined by actual application requirements and is not limited here. For example, the doping depth of the first part 31 and the second part 32 can be set to be the same to simplify the process and ensure the overall uniformity of the shielding doped layer; at the same time, the width of the first part 31 is greater than the width of the second part 32, thereby providing a wider coverage area when the trench gate structure 4 is distributed along the first direction, to enhance the electric field suppression effect of the gate dielectric layer 42 at the bottom of the trench gate structure 4.

[0048] In one embodiment, the doping concentration of the mesh shielding doped layer 3 is greater than the doping concentration of the well layer 22. In this embodiment, the doping concentration of the mesh shielding doped layer 3 is 1 × 10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 This concentration difference ensures that the mesh shielding doped layer 3 provides effective electric field suppression for the bottom of the trench gate structure 4, thereby improving the reliability and breakdown resistance of the device.

[0049] In one embodiment, the first part 31 and the second part 32 have the same depth, meaning their implantation depths are consistent. This symmetrical and uniformly deep mesh doping layout is beneficial for forming a uniformly distributed potential field in the epitaxial layer 21, reducing local electric field concentration problems, and thus improving the electric field uniformity of the device. This not only helps suppress local breakdown and improve the device's breakdown voltage characteristics, but also simplifies the implantation process, avoids lateral diffusion runaway caused by differences in doping depth, and improves the overall process controllability and yield.

[0050] Exemplarily, the trench gate structure 4 includes a gate trench 41, a gate dielectric layer 42, and a gate layer 43, which is a groove structure formed by etching downwards from the surface of the epitaxial layer 21. The gate dielectric layer 42 covers the sidewalls and bottom surface of the gate trench 41. The material of the gate dielectric layer 42 includes silicon dioxide or other suitable materials, and its thickness can be adjusted according to the device operating voltage. In this embodiment, the thickness of the gate dielectric layer ranges from 40nm to 80nm. The gate layer 43 fills the trench and covers the gate dielectric layer 42. The material of the gate layer 43 includes polysilicon.

[0051] Furthermore, in order to mitigate the electric field concentration effect at the bottom of the trench gate structure 4, a rounded transition region 411 is included between the bottom of the gate trench 41 and the sidewall to avoid the formation of sharp electric field hot spots, thereby improving the electric field reliability of the gate dielectric layer 42.

[0052] In one embodiment, the depth of the gate trench 41 is greater than the depth of the well layer 22 and the source region 23. This structural design allows the lower part of the trench gate structure 4 to pass through the source region 23 and the well layer 22 and extend into a deeper region of the epitaxial layer 21, thereby achieving stronger channel control capability, helping to suppress short-channel effects, and improving the switching performance and breakdown voltage of the device.

[0053] For example, the trench gate structure 4 is formed in the epitaxial layer 21. The depth of the gate trench 41 is controlled to be greater than the depth of the well layer 22 and the source region 23, but less than the implantation depth of the mesh shielding doped layer 3. This effectively expands and buffers the electric field at the bottom of the trench gate structure 4, which helps to improve the voltage withstand capability and reliability of the overall power device. The trench gate structure 4 is located between adjacent first parts 31, and the trench gate structure 4 spans multiple second parts 32 in the second direction. That is, the bottom of some gate trenches 41 extends further to the location of the second part 32, thereby ensuring effective electric field distribution and protecting the trench gate structure 4.

[0054] Therefore, in this embodiment, the mesh shielding doped layer 3 can form a potential barrier structure with the electric field of the trench gate structure 4 under operating conditions, effectively reducing the electric field strength at the bottom of the trench gate structure 4, mitigating the hot carrier effect and tunneling breakdown risk, thereby significantly improving the reliability and long-term stability of the trench MOS device. The cross-injection structure of the mesh shielding doped layer can provide more uniform protection in two dimensions, making it more suitable for high-voltage applications compared to traditional shielding structures. Furthermore, the structure design of the mesh shielding doped layer 3 is flexible, and the doping width, spacing, and depth of the first part 31 and the second part 32 can be adjusted according to voltage requirements. These parameters can be flexibly configured according to the target voltage level and device design requirements. In addition, the doping concentration and depth of the mesh shielding doped layer 3 can also be adapted to different voltage levels, improving overall reliability and reducing leakage current risk.

[0055] In one embodiment, such as Figure 2 and Figure 3 As shown, the semiconductor structure also includes a first metal layer 5, which covers the upper surface of the epitaxial layer 21 and is electrically connected to the underlying mesh-like shielding doped layer 3. The first metal layer 5 can be made of an aluminum-copper alloy, or other metal materials with good conductivity and process compatibility can be selected, such as titanium / aluminum stacks, cobalt-silicon alloys, etc.

[0056] In one embodiment, the first metal layer 5 covers the first portion 31 and / or the second portion 32, enabling electrical connections and signal or current paths to be led out from at least one portion of the cross-connected mesh structure. By directly connecting the first metal layer 5 to the cross-structure region of the mesh shielding doped layer 3, the wiring path and metallization process are effectively simplified, eliminating the need for additional leads or complex doped lead-out structures, and significantly improving the manufacturing efficiency and consistency of the device.

[0057] The interlayer dielectric layer 6 is used to provide electrical insulation and metallization protection for the trench region. The material of the interlayer dielectric layer 6 includes undoped silicate glass, borophosphate glass, or silicon nitride. The first metal layer 5 may further cover the interlayer dielectric layer 6 to achieve metallization and functional connectivity of the overall device surface.

[0058] In one embodiment, a first contact layer 51 is further included between the first metal layer 5 and the mesh shielding doped layer 3. The first contact layer 51 is used to form an electrical connection between the first metal layer 5 and the mesh shielding doped layer 3. The first contact layer 51 may be made of doped polycrystalline silicon, titanium / titanium-silicon alloy, or nickel / nickel-silicon alloy, and has the characteristic of low contact resistance.

[0059] The mesh shielding doped layer 3 and the first metal layer 5 are electrically connected through the first contact layer 51, which can realize the potential of the mesh shielding doped layer 3 and the first metal layer 5 to be synchronized, effectively avoid the electric field distortion problem caused by the accumulation of charge in the floating region, reduce the channel turn-on voltage drift, and improve the electrical performance stability of the device under high temperature and high pressure.

[0060] In one embodiment, the first metal layer 5 also covers the source region 23, and a first contact layer 51 is also provided between the first metal layer 5 and the source region 23, thereby forming an ohmic contact between the first metal layer 5 and the source region 23, which is responsible for injecting the charge carriers of the external circuit into the source region 23 or extracting the charge carriers from the source region 23, so as to ensure good conductivity and electrical performance of the device.

[0061] The semiconductor structure also includes a gate metal layer, which is made of a low-resistance metal material, and the on and off of the device is controlled by applying a voltage.

[0062] In one embodiment, the back side of the semiconductor substrate 1 is further provided with a second metal layer (not shown) and a second contact layer (not shown). The second contact layer is disposed on the back surface of the semiconductor substrate 1 to reduce the contact resistance between the metal and the semiconductor and improve the ohmic contact performance. The second metal layer is located on the second contact layer and is used to form a drain electrode connected to an external circuit. The material of the second metal layer includes aluminum, nickel, titanium, cobalt and their alloys, such as titanium / aluminum, cobalt / aluminum, etc.

[0063] The second metal layer achieves a low-resistance ohmic contact with the semiconductor substrate 1 of the first conductivity type through the second contact layer, thereby ensuring that the device still has good conduction characteristics and thermal stability under high current operating conditions, which is beneficial for achieving high power density output. In addition, to further improve thermal conductivity and device packaging compatibility, the thickness of the second metal layer can be set according to the power density design requirements, typically in the range of hundreds of nanometers to several micrometers.

[0064] like Figure 4 As shown, in one embodiment, this application also provides a method for fabricating a semiconductor structure, comprising the following steps:

[0065] Step S1: Provide a semiconductor substrate 1 of a first conductivity type;

[0066] Step S2: A drift region 2 is formed on the semiconductor substrate 1, the drift region 2 including an epitaxial layer 21 of a first conductivity type;

[0067] Step S3: A second conductivity type mesh shielding doped layer 3 is formed in the epitaxial layer 21. The mesh shielding doped layer 3 includes a first part 31 and a second part 32 that are cross-connected. The first part 31 is spaced apart in a first direction and extends along a second direction. The second part 32 is spaced apart in the second direction and extends along the first direction. The first direction and the second direction intersect.

[0068] Step S4: A trench gate structure 4 is formed in the epitaxial layer 21. The trench gate structure 4 is located between adjacent first parts 31. The trench gate structure 4 spans multiple second parts 32 in the second direction, and the depth of the trench gate structure 4 is less than the depth of the mesh shielding doped layer 3.

[0069] Specifically, step S1 is performed to provide a semiconductor substrate 1 of a first conductivity type; a drift region 2 is formed on the semiconductor substrate 1, the drift region 2 including an epitaxial layer 21 of the first conductivity type.

[0070] The method for forming the epitaxial layer 21 includes vapor phase epitaxy or other suitable methods. Exemplarily, the epitaxial growth process also includes introducing a suitable dopant to control the conductivity type and doping concentration of the epitaxial layer 21.

[0071] For example, after the epitaxial growth is completed, the epitaxial layer 21 is further subjected to surface treatment processes, such as hydrogen annealing, surface planarization or etching cleaning, to improve the interface quality and crystal integrity of subsequent processes.

[0072] Specifically, step S3 is performed to form a mesh shielding doped layer 3 of the second conductivity type in the epitaxial layer 21. The mesh shielding doped layer 3 includes a first part 31 and a second part 32 that are cross-connected. The first part 31 is spaced apart in a first direction and extends along a second direction, and the second part 32 is spaced apart in the second direction and extends along the first direction. The first direction and the second direction intersect.

[0073] In one embodiment, the drift region 2 further includes a well layer 22 of a second conductivity type and a source region 23 of a first conductivity type, that is, before forming the mesh shielding doped layer 3 of the second conductivity type in the epitaxial layer 21, it further includes:

[0074] A well layer 22 and a source region 23 are formed in a stacked configuration on the upper surface of the epitaxial layer 21, wherein the doping concentration of the mesh shielding doped layer 3 is greater than the doping concentration of the well layer 22. The method for forming the stacked well layer 22 and source region 23 on the upper surface of the epitaxial layer 21 includes ion implantation or other suitable methods.

[0075] In one embodiment, forming a mesh-like shielding doped layer 3 of a second conductivity type in the epitaxial layer 21 includes:

[0076] A patterned mask layer is formed above the epitaxial layer 21;

[0077] The process of forming a patterned mask layer (not shown) includes:

[0078] A photoresist layer is deposited on the surface of the epitaxial layer 21 to form a mask layer with a cross pattern. The mask pattern is used to define the implantation region of doped ions, thereby forming the geometric layout of the subsequent mesh shielding doped layer 3.

[0079] Based on a patterned mask layer, ion implantation is performed in the epitaxial layer 21 to form cross-connected first portions 31 and second portions 32. The first portions 31 are spaced apart in a first direction and extend along a second direction, while the second portions 32 are spaced apart in the second direction and extend along the first direction, resulting in a mesh-like shielding doped layer 3. Based on the formed patterned mask layer, dopant ions with a second conductivity type, such as boron ions or aluminum ions, with a conductivity type opposite to that of the epitaxial layer 21, are implanted into the epitaxial layer 21 using an ion implantation process. Implantation conditions (such as energy, dose, and angle) can be adjusted according to the desired implantation depth and doping concentration.

[0080] In one embodiment, after forming a mesh-like shielding doped layer 3 of the second conductivity type in the epitaxial layer 21, the process further includes: performing an annealing process to activate the implanted dopant ions and repair lattice damage caused during the implantation process. The specific conditions such as the annealing temperature and time can be optimized according to the thermal budget of the device to ensure maximum doping activity while controlling the thermal diffusion range and maintaining the accuracy of the mesh structure.

[0081] The doping implantation in the second step 32 is performed simultaneously with the doping implantation in the first step 31, which simplifies the manufacturing process, avoids additional contact structures, greatly improves the convenience and ease of implementation of the process, effectively reduces the overall manufacturing cost, and improves the integration and operational stability of the device.

[0082] The mesh-like shielding doped layer 3 of this application is achieved through a single mask implantation process. The first part 31 and the second part 32 of the cross-implantation structure can be formed simultaneously based on a one-time mask pattern, without the need for additional mask layers or complex doping steps, thus exhibiting excellent process simplification. This structure not only improves device performance but also balances process cost, batch yield, and process compatibility, making it suitable for mainstream power device manufacturing processes and possessing excellent feasibility and industrial application potential.

[0083] Specifically, step S4 is performed to form a trench gate structure 4 in the epitaxial layer 21. The trench gate structure 4 is located between adjacent first parts 31. The trench gate structure 4 spans multiple second parts 32 in the second direction, and the depth of the trench gate structure 4 is less than the depth of the mesh shielding doped layer 3.

[0084] In one embodiment, a trench gate structure 4 is formed in the epitaxial layer 21, including:

[0085] A gate trench 41 is formed in the epitaxial layer 21. The gate trench 41 is located between adjacent first portions 31. The gate trench 41 spans multiple second portions 32 in the second direction, and the depth of the gate trench 41 is less than the depth of the mesh shielding doped layer 3. The method for forming the gate trench 41 includes plasma reactive ion etching or other suitable methods.

[0086] After forming the gate trench 41 in the epitaxial layer 21, a rounded transition region 411 is formed between the sidewall and the bottom of the gate trench 41. The method for forming the rounded transition region 411 includes: thermal oxidation passivation: the gate trench 41 formed by etching is subjected to low-temperature thermal oxidation treatment, and the oxidation time is controlled according to the depth of the trench and the desired rounded radius, so that the sharp corner structure at the bottom of the trench is slowly oxidized to round it, thereby achieving rounding; plasma passivation treatment: the bottom of the trench is pretreated with hydrogen-containing or fluorine-containing plasma to passivate surface defects and adjust the edge morphology, so as to promote the formation of a smooth transition region; assisted etching passivation: after dry etching, wet etching is used to further modify the bottom structure of the trench, selectively remove micro-defects, and form a rounded structure with a certain curvature at the bottom.

[0087] By introducing a rounded transition region 411 between the sidewalls and bottom of the gate trench 41, the electric field spike phenomenon at the trench corner can be effectively alleviated, electrical breakdown can be suppressed, and the breakdown voltage and long-term reliability of the device can be improved. At the same time, leakage current and hot carrier effects can be reduced, improving the stability of the power device. When used in conjunction with the mesh shielding doped layer 3, the potential profile at the bottom of the trench can be further uniformly distributed, enhancing the turn-off performance of the device.

[0088] A gate dielectric layer 42 is formed covering the inner wall of the gate trench 41; the method of forming the gate dielectric layer 42 includes thermal oxidation, atomic layer deposition (ALD) or other suitable methods, forming a uniform insulating layer and ensuring good dielectric properties.

[0089] A gate layer 43 is formed on the gate dielectric layer 42, covering and filling the entire gate trench 41. The gate layer 43 is formed by chemical vapor deposition or other suitable conductive material deposition processes.

[0090] In one embodiment, after forming the trench gate structure 4, an interlayer dielectric layer 6 is further formed above the trench gate structure 4. Forming the interlayer dielectric layer 6 includes:

[0091] An interlayer dielectric material layer (not shown) is formed above the trench gate structure 4 and the epitaxial layer 21; the method for forming the interlayer dielectric material layer includes chemical vapor deposition or other suitable methods.

[0092] The interlayer dielectric material layer is etched to form the interlayer dielectric layer 6. The etching methods for the interlayer dielectric material layer include dry etching, wet etching, or other suitable methods.

[0093] In one embodiment, after forming the trench gate structure in the epitaxial layer 21, the method further includes:

[0094] A first metal layer 5 is formed, which covers the first portion 31 and / or the second portion 32. The method for forming the first metal layer 5 includes physical vapor deposition or other suitable methods, and the first metal layer 5 also covers an interlayer dielectric layer 6.

[0095] In one embodiment, before forming the first metal layer 5, a first contact layer 51 is formed between the first metal layer 5 and the mesh shielding doped layer 3, so that the first metal layer 5 and the mesh shielding doped layer 3 form an electrical connection.

[0096] The method for forming the first contact layer 51 includes:

[0097] A metal layer is formed on the mesh shielding doped layer 3; the required metal layer is deposited on the surface of the mesh shielding doped layer 3 by physical vapor deposition, chemical vapor deposition or sputtering method.

[0098] The metal layer is subjected to high-temperature annealing treatment; the deposited metal layer is subjected to high-temperature annealing treatment to promote the formation of an alloyed contact layer between the metal and the semiconductor, thereby improving the conductivity and stability of the contact.

[0099] Remove excess metal layers; remove unreacted excess metal layers by wet etching or dry etching to ensure that the size and morphology of the first contact layer 51 meet the design requirements;

[0100] The first contact layer is subjected to low-temperature annealing to stabilize the structure of the first contact layer 51 and reduce interface defects. Low-temperature annealing is usually performed.

[0101] The first metal layer 5 is also formed above the source region 23, and a first contact layer 51 is also provided between the first metal layer 5 and the source region 23, thereby forming an ohmic contact between the first metal layer 5 and the source region 23.

[0102] In one embodiment, after forming the trench gate structure 4, a second contact layer (not shown) and a second metal layer (not shown) are further formed on the back side of the semiconductor substrate 1. The method for forming the second contact layer and the second metal layer can be referred to the method for forming the first contact layer 51 and the first metal layer 5, and will not be described in detail here.

[0103] In one embodiment, before forming the contact layer and the second metal layer, the semiconductor substrate 1 is further thinned. To improve the device's heat dissipation performance, reduce parasitic resistance, and meet subsequent process requirements, the back side of the semiconductor substrate 1 is thinned. The thinning process can be achieved through methods such as mechanical polishing, chemical mechanical polishing (CMP), or wet chemical etching. The thickness of the thinned semiconductor substrate 1 should meet design specifications to ensure the device's mechanical strength and electrical performance.

[0104] After forming the first metal layer 5, the process includes forming a gate metal layer (not shown). The deposited first metal layer 5 and gate metal layer are respectively meshed using photolithography and etching processes. This process step forms independent electrode regions for the first metal layer 5 and the gate metal layer, avoiding short circuits and meeting electrode layout design requirements. The metal mesh structure not only helps reduce resistance but also effectively improves current distribution and thermal management. By forming physically isolated and electrically independent source and gate electrodes, subsequent device packaging and drive circuit connection are facilitated.

[0105] It should be understood that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 4 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0106] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate of the first conductivity type; The drift region, located on the semiconductor substrate, includes an epitaxial layer of a first conductivity type; A second type of conductive mesh shielding doped layer is located in the epitaxial layer. The mesh shielding doped layer includes a first part and a second part that are cross-connected. The first part is evenly spaced in a first direction and extends along a second direction. The second part is evenly spaced in the second direction and extends along the first direction. The first direction and the second direction intersect. The depth of the first part is the same as the depth of the second part. The width of the first part is greater than the width of the second part. A trench gate structure is located in the epitaxial layer, wherein the trench gate structure is located between adjacent first portions, the trench gate structure spans multiple second portions in a second direction, and the depth of the trench gate structure is less than the depth of the mesh shielding doped layer; The semiconductor structure further includes a first metal layer, which covers the first portion and / or the second portion.

2. The semiconductor structure according to claim 1, characterized in that, The drift region further includes a well layer of a second conductivity type and a source region of a first conductivity type. The well layer and the source region are stacked on the upper surface of the epitaxial layer, and the doping concentration of the mesh shielding doped layer is greater than the doping concentration of the well layer.

3. The semiconductor structure according to claim 1, characterized in that, The first metal layer and the mesh shielding doped layer further include a first contact layer, which is used to form an electrical connection between the first metal layer and the mesh shielding doped layer.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes an interlayer dielectric layer located above the trench gate structure.

5. The semiconductor structure according to claim 1, characterized in that, The back side of the semiconductor substrate is further provided with a second contact layer and a second metal layer.

6. The semiconductor structure according to claim 1, characterized in that, The trench gate structure includes a gate trench, a gate dielectric layer, and a gate layer. The bottom and sidewall of the gate trench include a rounded transition region. The gate dielectric layer covers the inner wall of the gate trench, and the gate layer covers the gate dielectric layer and fills the gate trench.

7. A method for fabricating a semiconductor structure, characterized in that, include: Provide a semiconductor substrate of a first conductivity type; A drift region is formed on the semiconductor substrate, the drift region comprising an epitaxial layer of a first conductivity type; A second conductivity type mesh shielding doped layer is formed in the epitaxial layer. The mesh shielding doped layer includes a first part and a second part that are cross-connected. The first part is spaced apart in a first direction and extends along a second direction. The second part is spaced apart in the second direction and extends along the first direction. The first direction and the second direction intersect. The depth of the first part is the same as the depth of the second part. The width of the first part is greater than the width of the second part. A trench gate structure is formed in the epitaxial layer, wherein the trench gate structure is located between adjacent first portions, the trench gate structure spans multiple second portions in a second direction, and the depth of the trench gate structure is less than the depth of the mesh shielding doped layer. A first metal layer is formed covering the first part and / or the second part.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The formation of a mesh-like shielding doped layer of a second conductivity type in the epitaxial layer includes: A patterned mask layer is formed above the epitaxial layer; Based on the patterned mask layer, ion implantation is performed in the epitaxial layer to form a cross-connected first part and a second part, wherein the first part is spaced apart in a first direction and extends along a second direction, and the second part is spaced apart in the second direction and extends along the first direction to obtain the mesh shielding doped layer.

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