Memristor and preparation method thereof

Abstract

The invention provides a memristor and a preparation method thereof, and relates to the technical field of microelectronic devices. The preparation method of the memristor comprises the following steps: transferring a first two-dimensional material to a bottom electrode layer by using a transfer piece; under the condition that the first two-dimensional material is transferred to the bottom electrode layer, a second two-dimensional material is transferred and covers the surface of the first two-dimensional material; and preparing a top electrode layer on the surface of the second two-dimensional material under the condition that the second two-dimensional material is transferred and covers the surface of the first two-dimensional material. By designing a ferroelectric heterojunction interface and introducing a built-in electric field or energy level difference of the heterojunction interface, the separation efficiency of electrons-holes to carriers can be improved, defect trap recombination at the interface can be inhibited, and thus the purpose of reducing the static power consumption of the device is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of microelectronic devices, and in particular to a memristor and a method for preparing the same. Background Art

[0002] The development of microelectronics requires memristors with high sensitivity, high stability, and fast readout modes. Ferroelectric memristors (FeRAM-based memristors or ferroelectric memristors), as key candidates for next-generation non-volatile memory and neuromorphic computing, have attracted considerable attention due to their combination of the polarization-reversal nonvolatility of ferroelectric materials and the continuous resistance tunability of memristors. Their ideal goal is to achieve ultra-high response speed, ultra-low operating voltage / power consumption, excellent multi-state storage capabilities (high discrimination between low-conductance states), and good scalability and reliability to meet the urgent needs of applications such as artificial intelligence and big data processing for high-performance, low-energy storage and computing integration.

[0003] However, current ferroelectric memristor technology based on ferroelectric materials is still immature. This is primarily due to the fact that as ferroelectric memristors continue to shrink to the nanoscale, their ferroelectric polarization properties significantly decrease, disappear, or transition from out-of-plane polarization to in-plane polarization at a critical thickness. Therefore, when applying ferroelectric memristors based on ferroelectric materials, which involve optimal thickness and structure, to integrated computing and storage chips, the thickness of the ferroelectric material must be considered. Existing ferroelectric memristors based on ferroelectric materials suffer from core issues such as slow access speed, low ferroelectric junction resistance (high off-state leakage current / small dynamic range), and fabrication difficulties (resulting in poor uniformity, low yield, and significant integration challenges). Consequently, existing ferroelectric memristor technology struggles to simultaneously meet the key performance requirements of future high-computing, low-power applications, including high response speed, low operating voltage / power consumption, large dynamic range (low conductance off-state), high density, high uniformity, and high reliability. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of the present application is to provide a memristor and a method for preparing the same, so as to improve the existing problems in the prior art: ferroelectric memristors based on ferroelectric materials have slow access speeds, small ferroelectric junction resistance, and difficult device preparation, which makes it difficult to meet the requirements of high response speed, low operating voltage, and low conductivity of memristors.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a memristor, the preparation method comprising: transferring a first two-dimensional material to a bottom electrode layer using a transfer member; when the first two-dimensional material is transferred to the bottom electrode layer, transferring a second two-dimensional material and covering the surface of the first two-dimensional material; when the second two-dimensional material is transferred and covers the surface of the first two-dimensional material, preparing a top electrode layer on the surface of the second two-dimensional material.

[0006] In the above implementation process, the first two-dimensional material is transferred to the bottom electrode layer and then to a designated location. A transfer member is used to apply uniform force to the two-dimensional material, preventing damage such as wrinkling and breakage during the transfer process and maintaining its original structural integrity. After the first two-dimensional material is successfully transferred to the bottom electrode layer, the second two-dimensional material is transferred and covered on the surface of the first two-dimensional material, achieving an orderly stacking of the two two-dimensional materials. By controlling the coverage and position of the second two-dimensional material, a composite two-dimensional material layer with a specific structure and properties can be constructed.

[0007] In one embodiment of the present application, the transferring of the first two-dimensional material to the bottom electrode layer using a transfer member includes: peeling the first two-dimensional material from the first two-dimensional material block using the transfer member; pressing and fixing the first two-dimensional material layer to the surface of the bottom electrode layer when the first two-dimensional material is aligned with the bottom electrode layer; heating the first two-dimensional material layer when the first two-dimensional material layer is pressed and fixed to the surface of the bottom electrode layer; wherein the heating parameters include: heating temperature: 60 to 80°C; insulation time: 3 to 5 minutes.

[0008] In the above implementation process, during the peeling process, the transfer part can accurately control the peeling force to ensure the integrity of the two-dimensional material. Subsequently, when the first two-dimensional material is aligned with the bottom electrode layer, the first two-dimensional material layer is pressed and fixed to the surface of the bottom electrode layer, so that good contact can be formed between the two-dimensional material and the bottom electrode layer, laying the foundation for subsequent electrical connection. After the first two-dimensional material layer is pressed and fixed to the surface of the bottom electrode layer, a heat treatment is performed. The heating parameters are: heating temperature 60 to 80°C, and insulation time 3 to 5 minutes. The heating treatment helps to enhance the bonding force between the first two-dimensional material and the bottom electrode layer, so that the two-dimensional material can better fit the surface of the bottom electrode layer, and further improve the stability of the electrical contact. At the same time, heating can also promote the stabilization of the internal structure of the two-dimensional material, reduce the stress and defects inside the material, and improve its electrical properties.

[0009] In one embodiment of the present application, transferring the second two-dimensional material to the surface of the first two-dimensional material includes: peeling the second two-dimensional material from the second two-dimensional material block using the transfer member; fixing the second two-dimensional material layer to the surface of the first two-dimensional material by pressing when the second two-dimensional material is aligned with the first two-dimensional material; heating when the second two-dimensional material layer is fixed to the surface of the first two-dimensional material; wherein the heating parameters include: heating temperature: 60 to 80°C; insulation time: 3 to 5 minutes.

[0010] In the above implementation process, the second two-dimensional material is peeled off from the second two-dimensional material block by a transfer member. During the peeling process, the transfer member can control the peeling force and direction to avoid damage to the two-dimensional material. When the second two-dimensional material is aligned with the first two-dimensional material, the second two-dimensional material layer is fixed to the surface of the first two-dimensional material by pressing, so that good contact and bonding are formed between the two two-dimensional materials. The pressing operation can provide enough pressure to make the two-dimensional material layers fit tightly together, reduce contact resistance, and improve electrical properties. Heat treatment can effectively enhance the bonding force between the two-dimensional material layers, while avoiding degradation or damage to the material performance due to excessively high temperature. Heat treatment can also promote the stabilization of the internal structure of the two-dimensional material, reduce stress and defects inside the material, and further improve its electrical properties.

[0011] In one embodiment of the present application, the preparation method of the bottom electrode layer includes: performing graphic exposure on the bottom electrode layer while spin-coating photoresist on the surface of the substrate layer; wherein the spin coating parameters include: spin coating speed: 4000 rpm, spin coating time: 60 seconds, heating temperature: 100 to 105°C, heating time: 1 to 1.5 minutes; after completing the graphic exposure of the bottom electrode layer, manufacturing the electrode of the bottom electrode layer; wherein the method of manufacturing the electrode of the bottom electrode layer includes physical vapor deposition or chemical vapor deposition; the electrode of the bottom electrode layer is composed of metal Ti and Au.

[0012] In the above implementation process, high-speed spin coating can ensure that the photoresist is evenly distributed on the surface of the substrate layer, forming a uniform photoresist film. Subsequently, the heat treatment helps to solidify the photoresist, so that it forms a stable thin film structure, ready for subsequent graphic exposure. After completing the photoresist spin coating and heat treatment, the bottom electrode layer is subjected to graphic exposure to improve the resolution and edge clarity of the electrode, thereby optimizing the electrical properties of the electrode. The electrode of the bottom electrode layer is composed of metal Ti and Au. Ti, as the bottom metal, can provide good adhesion and conductivity, while Au, as the upper metal, has excellent oxidation resistance and electrical stability. This double-layer metal structure can ensure that the bottom electrode layer maintains stable electrical properties during long-term use, while reducing the contact resistance between the electrode and the substrate layer.

[0013] In one embodiment of the present application, the preparation method of the top electrode layer includes: performing graphic exposure on the top electrode layer while spin coating photoresist on the surface of the second two-dimensional material; wherein the spin coating parameters include: spin coating speed: 4000 rpm, spin coating time: 60 seconds, heating temperature: 100 to 105°C, heating time: 1 to 1.5 minutes; after completing the graphic exposure of the top electrode layer, manufacturing the electrode of the top electrode layer; wherein the method of manufacturing the electrode of the top electrode layer includes physical vapor deposition or chemical vapor deposition; the electrode of the top electrode layer is composed of metal Ti and Au.

[0014] In the above implementation process, high-speed spin coating can ensure that the photoresist is evenly distributed on the surface of the second two-dimensional material, forming a uniform photoresist film. The heating treatment helps to solidify the photoresist, so that it forms a stable film structure, ready for subsequent graphic exposure. The pre-designed electrode pattern is transferred to the photoresist film through the exposure equipment. The graphic exposure can improve the resolution and edge clarity of the electrode, thereby optimizing the electrical properties of the electrode. After the graphic exposure is completed, the electrode of the top electrode layer is made. The electrode of the top electrode layer is composed of metal Ti and Au. Ti, as the bottom metal, can provide good adhesion and conductivity, while Au, as the top metal, has excellent oxidation resistance and electrical stability.

[0015] In a second aspect, an embodiment of the present application further provides a memristor, comprising: a bottom electrode layer, a two-dimensional material layer, and a top electrode layer; the two-dimensional material layer comprises a first two-dimensional material and a second two-dimensional material; the first two-dimensional material is fixedly connected to the second two-dimensional material; the first two-dimensional material is attached to the surface of the bottom electrode layer; and the top electrode layer is attached to the surface of the second two-dimensional material.

[0016] In the above implementation process, the structure mainly includes a bottom electrode layer, a two-dimensional material layer, and a top electrode layer. The two-dimensional material layer is composed of a first two-dimensional material and a second two-dimensional material, the first two-dimensional material and the second two-dimensional material being fixedly connected, the first two-dimensional material being attached to the surface of the bottom electrode layer, and the top electrode layer being attached to the surface of the second two-dimensional material. The combination of the two two-dimensional materials enables a high switching ratio, meaning that the resistance state of the memristor can be clearly distinguished under different voltage or current conditions, which is very important for data storage and logical operations. The attachment structures between the first two-dimensional material and the bottom electrode layer, and between the second two-dimensional material and the top electrode layer, ensure good electrical contact between the electrodes and the two-dimensional material layers. This good contact reduces contact resistance and improves the stability of electrical performance, maintaining stable electrical performance even under long-term use or in different environmental conditions.

[0017] In one embodiment of the present application, the memristor further includes: a substrate layer; the bottom electrode layer is arranged on the surface of the substrate layer; the substrate layer includes an oxide layer and a non-oxide layer; the constituent materials of the substrate layer include: 300μm to 500μm Si and 350nm SiO2.

[0018] In the above implementation, the non-oxidized layer of the substrate layer consists of 300 to 500 μm of Si. Si, a common semiconductor material, has excellent electrical properties and mechanical stability. The oxide layer of the substrate layer consists of 350 nm of SiO2, a commonly used insulating material with excellent electrical insulation and chemical stability. The substrate layer provides stable mechanical support for the entire memristor, ensuring the structural integrity of the device during manufacturing and use.

[0019] In one embodiment of the present application, the electrode pattern of the bottom electrode layer is a rectangular shape arranged in parallel; the electrode pattern of the top electrode layer is consistent with the bottom electrode layer, and is arranged parallel to the bottom electrode layer and the top electrode layer, and the electrode pattern of the bottom electrode layer and the electrode pattern of the top electrode layer are perpendicular to each other in space.

[0020] In the above implementation process, the electrode pattern of the bottom electrode layer adopts a parallel rectangular shape. This design ensures uniform spacing between the electrodes and reduces electrical interference between the electrodes. The rectangular electrode pattern also provides a larger electrode area, increasing the contact area between the electrode and the two-dimensional material layer, thereby reducing contact resistance and improving electrical performance. The bottom electrode layer and the top electrode layer are arranged in parallel, and the electrode pattern of the bottom electrode layer and the electrode pattern of the top electrode layer are spatially perpendicular to each other. This vertical arrangement design enables cross-connection between the electrodes, forming a cross-array structure. This structure can effectively increase the integration density of the memristor, reduce the size of the device, and improve the efficiency of data storage and processing.

[0021] In one embodiment of the present application, the top electrode layer and the bottom electrode layer are composed of the same material; wherein the composition material includes a Ti layer and an Au layer; the thickness of the Ti layer is 5nm to 10nm, and the thickness of the Au layer is 50nm to 80nm.

[0022] In this implementation, Ti exhibits excellent adhesion and conductivity, ensuring good contact between the electrode and the substrate layer or two-dimensional material layer. The Ti layer also provides mechanical support, enhancing electrode stability. Au exhibits excellent oxidation resistance and electrical stability, maintaining stable electrical performance over long-term use. The Au layer also reduces electrical noise on the electrode surface, improving its conductivity.

[0023] In one embodiment of the present application, the thickness of the two-dimensional material is 20 to 80 nm.

[0024] In this implementation, the thickness of the 2D material was selected to be between 20 and 80 nm. This range ensures good electrical performance and mechanical stability. 2D materials typically have atomic-level thickness, enabling effective electrical control at low voltages, thereby reducing energy consumption. Furthermore, this appropriate thickness provides sufficient mechanical strength, ensuring stability during manufacturing and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A first flow chart of the memristor fabrication method provided in an embodiment of the present application; Figure 2 A second flow chart of the memristor fabrication method provided in an embodiment of the present application; Figure 3 Schematic diagram of the preparation process of mechanically exfoliated two-dimensional materials provided in the embodiments of the present application; Figure 4 A third flow chart of the method for preparing a memristor provided in an embodiment of the present application; Figure 5 A fourth flow chart of the memristor fabrication method provided in an embodiment of the present application; Figure 6 A fifth flow chart of the method for preparing a memristor provided in an embodiment of the present application; Figure 7A schematic diagram of the structure of a memristor provided in an embodiment of the present application; Figure 8 A flow chart for preparing a memristor according to an embodiment of the present application; Figure 9 Raman characterization of the memristor CIPS two-dimensional material provided in the embodiment of the present application; Figure 10 Raman characterization of the MoTe2 two-dimensional memristor material provided in the embodiment of the present application; Figure 11 The voltage-current characteristics of the memristor provided in the embodiment of the present application.

[0027] Icon: 10-substrate layer; 20-bottom electrode layer; 30-first two-dimensional material; 40-second two-dimensional material; 50-top electrode layer. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of them. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of the present application.

[0029] Memristors based on ferroelectric two-dimensional materials such as CuInP2S6, MoTe2, α-In2Se3, β-In2Se3, WTe2, SnS, and SnTe, with continuously electric-field-tunable conductance states, are considered promising storage media. In particular, ferroelectric-based mass storage devices have become highly sought-after products on the market. Furthermore, ferroelectric materials offer advantages such as low cost, high capacity, and high write endurance, making them suitable for a wide range of applications. Developing innovative materials, mechanisms, and device architectures is crucial for advancing the field of microelectronics. However, as ferroelectric memristors continue to shrink in size to the nanoscale, their ferroelectric polarization properties can significantly degrade, disappear, or shift from out-of-plane polarization to in-plane polarization at a critical thickness. Therefore, reducing the thickness and size of ferroelectric memristors, modulating the built-in electric field at the ferroelectric heterojunction interface, improving device response speed, lowering the dielectric constant, and reducing the operating voltage are pressing technical challenges for their application in integrated storage and computing chips.

[0030] First, some of the terms in the embodiments of this application are explained: Memristor: A nonlinear resistor with memory function, belonging to the fourth basic circuit element after resistance, capacitance and inductance. Its resistance value changes with the amount of charge passing through it and can maintain its state after power is removed, thus realizing the function of information storage. Two-dimensional materials: refers to materials in which electrons can only move freely (planar motion) in two dimensions (1-100nm), such as nanofilms, superlattices, and quantum wells; Two-dimensional material heterojunction: an interface structure formed by epitaxial growth of two different two-dimensional materials.

[0031] In the first aspect, the present invention provides a method for preparing a memristor. Figure 1 , Figure 1 This is a first flow chart of the memristor fabrication method provided in an embodiment of the present application.

[0032] The preparation method comprises: S1: Transferring the first two-dimensional material 30 to the bottom electrode layer 20 using a transfer member; In step S1, the transfer member can be polyimide tape, PDMS transparent film, mechanical scraper or spatula, nano transfer film, optical transparent adhesive, etc. By selecting a suitable transfer member, the integrity and high-quality transfer of the two-dimensional material can be ensured, thereby optimizing the overall performance of the memristor.

[0033] S2: When the first two-dimensional material 30 is transferred to the bottom electrode layer 20 , the second two-dimensional material 40 is transferred to cover the surface of the first two-dimensional material 30 ; In step S2, the second two-dimensional material 40 is transferred and covered on the surface of the first two-dimensional material 30, and the two two-dimensional materials are stacked in an orderly manner on the bottom electrode layer 20 to construct a composite two-dimensional material layer with specific structure and properties, or called a heterojunction.

[0034] Optionally, the first two-dimensional material 30 may be a CIPS two-dimensional material (ie, CuInP2S6), or a ferroelectric material with the same structure, such as CuInP2Se6, CuCrP2S6, CuCrP2Se6, etc.

[0035] Optionally, the second two-dimensional material 40 may be MoTe2, or may be a ferroelectric two-dimensional material such as α-In2Se3, β-In2Se3, WTe2, SnS, or SnTe.

[0036] Optionally, the first two-dimensional material 30 and the second two-dimensional material 40 may be two materials selected from ferroelectric two-dimensional materials such as CuInP2S6, MoTe2, α-In2Se3, β-In2Se3, WTe2, SnS, and SnTe.

[0037] S3: When the second two-dimensional material 40 is transferred and covers the surface of the first two-dimensional material 30 , a top electrode layer 50 is prepared on the surface of the second two-dimensional material 40 ; In step S3, the first two-dimensional material 30 and the second two-dimensional material 40 have formed a stable composite structure. The top electrode layer 50 needs to form good electrical contact with the two-dimensional material layer to ensure that the electrical connection between the electrodes is tight and stable, thereby improving the overall performance and reliability of the memristor.

[0038] In one embodiment of the present application, see Figure 2 , Figure 2 This is a second flow chart of the memristor fabrication method provided in an embodiment of the present application.

[0039] Transferring the first two-dimensional material 30 to the bottom electrode layer 20 using a transfer member includes: S11: peeling the first two-dimensional material 30 from the first two-dimensional material 30 block using a transfer member; S12: When the first two-dimensional material 30 is aligned with the bottom electrode layer 20 , the first two-dimensional material 30 is pressed and fixed on the surface of the bottom electrode layer 20 ; S13: When the first two-dimensional material 30 is pressed and fixed on the surface of the bottom electrode layer 20, heating is performed; wherein the heating parameters include: heating temperature: 60 to 80°C; insulation time: 3 to 5 minutes.

[0040] In the above implementation process, the specific process can be combined with Figure 3 , Figure 3 A schematic diagram of the preparation process of mechanically exfoliated two-dimensional materials provided in an embodiment of the present application, using CIPS two-dimensional materials to demonstrate how to mechanically exfoliate two-dimensional materials.

[0041] Taking CIPS two-dimensional materials as an example, the transfer piece used is a blue film tape specifically for mechanical peeling (abbreviated as "blue film" in the figure). A small amount of CIPS two-dimensional material is adhered to the CIPS block, and PDMS and a commercial two-dimensional material transfer system are used to transfer a small amount of CIPS two-dimensional material to the substrate layer 10 with the bottom electrode layer 20. The PDMS film adhered with the CIPS two-dimensional material is placed on the commercial two-dimensional transfer system, aligned and pressed onto the substrate layer 10 with the bottom electrode layer 20, and heated to 60 to 80°C for 3 to 5 minutes. Due to the heating, the PDMS film undergoes a curing reaction, causing the CIPS two-dimensional material to fall onto the substrate, and the PDMS film is lifted. The transfer of the CIPS two-dimensional material is completed.

[0042] Optionally, the small amount of CIPS two-dimensional material peeled off has a thickness of 1 nm to 20 nm.

[0043] Preferably, the heating treatment parameters here are selected to be a heating temperature of 80° C. and maintained for 5 minutes.

[0044] In one embodiment of the present application, see Figure 4 , Figure 4 This is a third flow chart of the memristor fabrication method provided in an embodiment of the present application.

[0045] Transferring the second two-dimensional material 40 to the surface of the first two-dimensional material 30 comprises: S21: peeling the second two-dimensional material 40 from the second two-dimensional material 40 block using a transfer member; S22: When the second two-dimensional material 40 is aligned with the first two-dimensional material 30 , the second two-dimensional material 40 is fixed to the surface of the first two-dimensional material 30 by pressing; S23: When the second two-dimensional material 40 is fixed on the surface of the first two-dimensional material 30, heating is performed; wherein the heating parameters include: heating temperature: 60 to 80°C; insulation time: 3 to 5 minutes.

[0046] In the above implementation process, the specific implementation operation is similar to the step of transferring the first two-dimensional material 30 to the bottom electrode layer 20 using a transfer member.

[0047] Alternatively, taking MoTe2 two-dimensional material as an example, the transfer piece used is a blue film tape specially used for mechanical peeling, which adheres a small amount of MoTe2 two-dimensional material from the MoTe2 block, and uses PDMS and a commercial two-dimensional material transfer system to transfer a small amount of MoTe2 two-dimensional material to the substrate layer 10 with the bottom electrode layer 20. The PDMS film adhered with the MoTe2 two-dimensional material is placed on the commercial two-dimensional transfer system, aligned and pressed onto the substrate layer 10 with the CIPS two-dimensional material and the bottom electrode layer 20, and heated to 60 to 80°C for 3 to 5 minutes. Due to the heating, the PDMS film undergoes a curing reaction, causing the MoTe2 two-dimensional material to fall onto the CIPS two-dimensional material. Due to the van der Waals force, a CIPS / MoTe2 two-dimensional heterojunction is formed, lifting the PDMS film.

[0048] Optionally, the small amount of MoTe2 two-dimensional material exfoliated has a thickness of 1 nm to 20 nm.

[0049] Preferably, the heating treatment parameters here are also selected to be a heating temperature of 80° C. and maintained for 5 minutes.

[0050] In one embodiment of the present application, see Figure 5 , Figure 5 This is the fourth flow chart of the memristor fabrication method provided in an embodiment of the present application.

[0051] The preparation method of the bottom electrode layer 20 includes: S01: When the surface of the substrate layer 10 is spin-coated with photoresist, the bottom electrode layer 20 is subjected to pattern exposure. The spin coating parameters include: spin coating speed: 4000 rpm, spin coating time: 60 seconds, heating temperature: 100 to 105° C., and heating time: 1 to 1.5 minutes. S02: After the pattern exposure of the bottom electrode layer 20 is completed, the electrodes of the bottom electrode layer 20 are manufactured. The method of manufacturing the electrodes of the bottom electrode layer 20 includes physical vapor deposition or chemical vapor deposition. The electrodes of the bottom electrode layer 20 are composed of metal Ti and Au.

[0052] In the above implementation process, photoresist is spin-coated on the surface of the substrate layer 10 using the following spin-coating parameters: a spin-coating speed of 4000 rpm and a spin-coating time of 60 seconds. High-speed spin-coating ensures that the photoresist is evenly distributed on the surface of the substrate layer 10, forming a uniform photoresist film. The spin-coated photoresist is then heated at a temperature of 100 to 105°C for 1 to 1.5 minutes. This heating treatment helps cure the photoresist, forming a stable film structure and preparing it for subsequent pattern exposure. After the photoresist is spin-coated and heated, the bottom electrode layer 20 is pattern-exposed. An exposure device transfers the pre-designed electrode pattern onto the photoresist film. The exposed substrate layer 10 with the photoresist is then immersed in a developer to dissolve the uncured (positive-tone) or unexposed (negative-tone) portions, revealing the electrode pattern to be processed.

[0053] After pattern exposure is completed, the electrodes of the bottom electrode layer 20 are fabricated. Methods for fabricating the electrodes include physical vapor deposition (PVD) or chemical vapor deposition (CVD). PVD can be vacuum evaporation (thermal evaporation or electron beam evaporation), sputtering (magnetron sputtering), etc.; CVD can be atmospheric pressure CVD, low pressure CVD, or plasma CVD.

[0054] Optionally, the electrodes of the bottom electrode layer 20 are composed of metal Ti and Au. Ti, as the bottom metal, can provide good adhesion and conductivity, and Au, as the top metal, has excellent oxidation resistance and electrical stability. This double-layer metal structure can ensure that the bottom electrode layer 20 maintains stable electrical properties during long-term use, while reducing the contact resistance between the electrode and the substrate layer 10. The double-layer metal structure can provide good adhesion and conductivity, while having excellent oxidation resistance and electrical stability.

[0055] In one embodiment of the present application, PMMA photoresist is spin-coated on the substrate layer 10 using a spreader at a spin coating speed of 4000 rpm for 60 seconds. The layer is then placed on a heating table for heating at 100 to 105°C for 1 to 1.5 minutes. The pattern is exposed using a maskless photolithography machine, developed using a developer, and sequentially plated with metal Ti and Au electrodes using magnetron sputtering. The layer is then stripped off using acetone, leaving a bottom electrode pattern on the substrate.

[0056] In one embodiment of the present application, see Figure 6 , Figure 6 This is the fifth flow chart of the memristor fabrication method provided in an embodiment of the present application.

[0057] The preparation method of the top electrode layer 50 includes: S41: When the photoresist is spin-coated on the surface of the second two-dimensional material 40, the top electrode layer 50 is subjected to pattern exposure; wherein the spin coating parameters include: spin coating speed: 4000 rpm, spin coating time: 60 seconds, heating temperature: 100 to 105° C., and heating time: 1 to 1.5 minutes; S42: After the pattern exposure of the top electrode layer 50 is completed, the electrode of the top electrode layer 50 is manufactured; wherein the method of manufacturing the electrode of the top electrode layer 50 includes physical vapor deposition or chemical vapor deposition; the electrode of the top electrode layer 50 is composed of metal Ti and Au.

[0058] The above implementation process is similar to the preparation method of the bottom electrode layer 20 and will not be described in detail here, but an embodiment is provided for ease of understanding.

[0059] In one embodiment of the present application, PMMA photoresist is spin-coated on a substrate with a bottom electrode and a two-dimensional material, and a spreader is used for spread coating. The spin coating speed is 4000 rpm, the spin coating is 60 seconds, and the substrate is placed on a heating table for heating at 100 to 105°C for 1-1.5 minutes. The pattern is exposed by a maskless photolithography machine, developed with a developer, and metal Ti and Au electrodes are sequentially plated by magnetron sputtering. The substrate is stripped by acetone, leaving a top electrode pattern on the substrate.

[0060] In one embodiment of the present application, a maskless lithography technique is used to form a 1×1 cm 2A bottom electrode layer 20 is prepared on a SiO2 / Si substrate layer 10, a few layers of CIPS material on the PDMS are transferred to the substrate layer 10 with the bottom metal electrode of the bottom electrode layer 20 via a two-dimensional transfer system, and a few layers of MoTe2 material on the PDMS are transferred to the substrate layer 10 with the CIPS material and the bottom metal electrode of the bottom electrode layer 20 via a two-dimensional transfer system. Then, a top metal electrode is prepared on the two-dimensional MoTe2 ferroelectric material using maskless lithography. The top metal electrode and the bottom metal electrode of the bottom electrode layer 20 are Ti / Au metal electrodes, respectively, with the Ti metal layer having a thickness of 5nm to 10nm and the Au metal layer having a thickness of 50nm to 80nm.

[0061] In the second aspect, the embodiment of the present application also provides a memristor, see Figure 7 , Figure 7 A schematic diagram of the structure of the memristor provided in an embodiment of the present application.

[0062] The memristor includes: a bottom electrode layer 20, a two-dimensional material layer and a top electrode layer 50; the two-dimensional material layer includes a first two-dimensional material 30 and a second two-dimensional material 40; the first two-dimensional material 30 is fixedly connected to the second two-dimensional material 40; the first two-dimensional material 30 is attached to the surface of the bottom electrode layer 20; and the top electrode layer 50 is attached to the surface of the second two-dimensional material 40.

[0063] In the above-mentioned implementation process, the memristor proposed in the embodiment of the present application includes, from bottom to top, a substrate layer 10, a bottom electrode layer 20, a two-dimensional material layer (including a first two-dimensional material 30 and a second two-dimensional material 40), and a top electrode layer 50, which can achieve a significant reduction in device size down to the nanoscale and still allow the device to operate normally, providing a device with great potential for use in future nanoscale semiconductor devices with high-density integration and low power consumption in chips.

[0064] Optionally, the thickness of the two-dimensional material layer is comprised between 20 and 80 nm.

[0065] Optionally, the two-dimensional material layer is a CuInP2S6 and MoTe2 ferroelectric two-dimensional material heterojunction, both of which have a thickness of 10 to 40 nm, have a typical two-dimensional material layered structure, and the interlayer adsorption force is van der Waals force, which is a typical metal compound.

[0066] In one embodiment of the present application, the memristor further includes: a substrate layer 10; a bottom electrode layer 20 is arranged on the surface of the substrate layer 10; the substrate layer 10 includes an oxide layer and a non-oxide layer; the constituent materials of the substrate layer 10 include: 300μm to 500μm Si and 350nm SiO2.

[0067] In the above implementation, substrate layer 10 is a laminated substrate composed of Si (300 μm-500 μm, preferably 300 μm) with a SiO2 (350 nm) oxide layer on its surface. The SiO2 layer acts as an insulating layer, isolating the Si layer from the electrodes and active layer above, preventing electrical interference and ensuring stable electrical performance of the device, improving the on / off ratio and data storage accuracy. The laminated substrate structure supports high-density integration, facilitating the manufacture of miniaturized, high-performance electronic devices, and meeting the ever-increasing performance requirements of electronic devices.

[0068] In one embodiment of this application, please combine Figure 8 This is a flow chart for preparing the memristor provided in an embodiment of the present application.

[0069] It can be seen that the electrode pattern of the bottom electrode layer 20 is a rectangular shape arranged in parallel; the electrode pattern of the top electrode layer 50 is consistent with the bottom electrode layer 20, and the bottom electrode layer 20 and the top electrode layer 50 are arranged in parallel, and the electrode pattern of the bottom electrode layer 20 and the electrode pattern of the top electrode layer 50 are perpendicular to each other in space.

[0070] In the above implementation process, by constructing a vertical structure memristor, the metal electrode of the bottom electrode layer 20, the heterojunction formed by the first two-dimensional material 30 and the second two-dimensional material 40, and the metal electrode of the top electrode layer 50 constitute a vertical channel conductive filament structure. The carriers directly pass through the conductive filaments formed and disconnected between the top electrode layer 50 and the bottom electrode layer 20 to realize the memristive function. By applying gate voltages of different intensities to regulate the ferroelectric polarization strength of the ferroelectric heterojunction, the built-in electric field at the interface between the heterojunctions can be regulated to achieve faster response speed of the memristor and better storage performance.

[0071] Optionally, the top electrode layer 50 and the bottom electrode layer 20 are made of the same material; wherein the material includes a Ti layer and an Au layer; the thickness of the Ti layer is 5nm to 10nm, and the thickness of the Au layer is 50nm to 80nm.

[0072] Optionally, the two-dimensional material layer is 20 to 80 nm, and the total thickness of the electrode layer is 55 to 90 nm.

[0073] Please continue reading Figure 9 and Figure 10 , Figure 9 Raman characterization of the memristor CIPS two-dimensional material provided in the embodiment of the present application; Figure 10 This is a Raman characterization diagram of the memristor MoTe2 two-dimensional material provided in an embodiment of the present application.

[0074] The two materials of the heterojunction memristor device were irradiated with a 532nm laser respectively, and their Raman spectral curves were recorded to verify the functional layer materials CIPS and MoTe2 two-dimensional materials of the device, indicating that the materials used were correct. Figure 9 The Raman spectrum of the CIPS material shows multiple characteristic peaks corresponding to vibrational modes of SPS, PP, and PS. These specific vibrational modes are the "fingerprint" characteristics of the CIPS material. Furthermore, the "anion" and "cation" are labeled in the image, indicating that the material has ionic characteristics, which is consistent with the composition and structure of the CIPS material, thus verifying the accuracy and correctness of the CIPS material. Figure 10 The Raman spectrum of the corresponding MoTe2 two-dimensional material shows two main characteristic peaks, A1g and E2g, which are the signature vibrational modes of MoTe2. The A1g peak is generally associated with symmetric vibrations of the material, while the E2g peak is associated with in-plane vibrations. Their presence confirms the crystal structure and symmetry characteristics of the MoTe2 material, thereby verifying the accuracy and correctness of the MoTe2 material.

[0075] for Figure 11 , Figure 11 The voltage-current characteristics of the memristor provided in the embodiment of the present application.

[0076] Using a commercial electrical testing system, two test probes were inserted into the bottom and top electrodes of the device. A cyclic sweep voltage of -15V to 15V was applied to the device, and the corresponding current changes were measured to verify the device's memristive performance. The cyclic sweep voltage range for the device can be selected from ±15V to ±5V, with a preferred range of -15V to +15V.

[0077] The curve shows obvious nonlinear characteristics, indicating that the device has nonlinear electrical behavior. In the positive and negative voltage regions, the curve shows asymmetry, indicating that the electrical characteristics of the device are different in the positive and negative voltage directions. When the device is in the "reset" state, the corresponding current value is low, indicating that the resistance of the device is high. This is the non-conducting or off state of the device. When the device is in the "set" state, the corresponding current value is high, indicating that the resistance of the device is low. This is the conducting or on state of the device. Near zero voltage, the current is relatively low, indicating that the device has a higher resistance at low voltage. Figure 11 The ratio of the high-resistance state to the low-resistance state of the device shown is 10 6 This large resistance change is a typical feature of the memristive effect, indicating that the device can remember its resistance state and maintain it when external conditions change until it is next stimulated by an appropriate stimulus (such as a change in voltage or current).

[0078] In summary, the present application provides a memristor and a method for preparing the same, relating to the field of microelectronic device technology. The method for preparing the memristor comprises: transferring a first two-dimensional material 30 to a bottom electrode layer 20 using a transfer member; transferring a second two-dimensional material 40 to cover the surface of the first two-dimensional material 30 when the first two-dimensional material 30 is transferred to the bottom electrode layer 20; and preparing a top electrode layer 50 on the surface of the second two-dimensional material 40 when the second two-dimensional material 40 is transferred to cover the surface of the first two-dimensional material 30. By designing a ferroelectric heterojunction interface and introducing a built-in electric field or energy level difference in the heterojunction interface, the separation efficiency of electron-hole pairs of carriers can be improved, and the recombination of defect traps at the interface can be suppressed, thereby achieving the purpose of reducing the static power consumption of the device. The embodiments of the present application improve the key functional layer materials and overall structural design of the device. Compared with the existing technology, a new ferroelectric heterojunction memristor is constructed entirely based on two-dimensional materials, filling the gaps in the traditional MIM structure and having lower operating voltage, fatigue resistance and cyclic stability. Moreover, the memristor shows a high degree of similarity in simulating information transmission between neurons and that between synapses, and has great application prospects in the future development of brain-like structures.

[0079] In the several embodiments provided in this application, it should be understood that the disclosed devices can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices according to the various embodiments of the present application. It should also be noted that in some alternative implementations, the functions marked in the blocks may also occur in an order different from that marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved.

[0080] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0081] The foregoing is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0082] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

Claims

1. A method for preparing a memristor, characterized in that: The preparation method comprises: transferring the first two-dimensional material to the bottom electrode layer using a transfer member; When the first two-dimensional material is transferred to the bottom electrode layer, a second two-dimensional material is transferred to cover the surface of the first two-dimensional material; When the second two-dimensional material is transferred to and covers the surface of the first two-dimensional material, a top electrode layer is prepared on the surface of the second two-dimensional material.

2. The preparation method according to claim 1, characterized in that The method of transferring the first two-dimensional material to the bottom electrode layer by using a transfer member includes: peeling the first two-dimensional material from the first two-dimensional material block using the transfer member; When the first two-dimensional material layer is aligned with the bottom electrode layer, pressing and fixing the first two-dimensional material layer to the surface of the bottom electrode layer; When the first two-dimensional material layer is pressed and fixed on the surface of the bottom electrode layer, heating is performed; wherein the heating parameters include: heating temperature: 60 to 80° C.; insulation time: 3 to 5 minutes.

3. The preparation method according to claim 1, characterized in that The transferring of the second two-dimensional material to the surface of the first two-dimensional material comprises: peeling the second two-dimensional material from the second two-dimensional material block using the transfer member; When the second two-dimensional material is aligned with the first two-dimensional material, fixing the second two-dimensional material layer to the surface of the first two-dimensional material by pressing; When the second two-dimensional material layer is fixed on the surface of the first two-dimensional material, heating is performed; wherein the heating parameters include: heating temperature: 60 to 80° C.; insulation time: 3 to 5 minutes.

4. The preparation method according to claim 1, characterized in that in, The preparation method of the bottom electrode layer comprises: When the photoresist is spin-coated on the surface of the substrate layer, the bottom electrode layer is subjected to pattern exposure; wherein the spin coating parameters include: spin coating speed: 4000 rpm, spin coating time: 60 seconds, heating temperature: 100 to 105° C., and heating time: 1 to 1.5 minutes; After the pattern exposure of the bottom electrode layer is completed, the electrodes of the bottom electrode layer are manufactured; wherein the method of manufacturing the electrodes of the bottom electrode layer includes physical vapor deposition or chemical vapor deposition; the electrodes of the bottom electrode layer are composed of metal Ti and Au.

5. The preparation method according to claim 1, characterized in that in, The method for preparing the top electrode layer comprises: When a photoresist is spin-coated on the surface of the second two-dimensional material, the top electrode layer is subjected to pattern exposure; wherein the spin coating parameters include: spin coating speed: 4000 rpm, spin coating time: 60 seconds, heating temperature: 100 to 105° C., and heating time: 1 to 1.5 minutes; After the pattern exposure of the top electrode layer is completed, the electrode of the top electrode layer is manufactured; wherein the method of manufacturing the electrode of the top electrode layer includes physical vapor deposition or chemical vapor deposition; the electrode of the top electrode layer is composed of metal Ti and Au.

6. A memristor, characterized in that: The memristor comprises: a bottom electrode layer, a two-dimensional material layer and a top electrode layer; The two-dimensional material layer includes a first two-dimensional material and a second two-dimensional material; the first two-dimensional material is fixedly connected to the second two-dimensional material; The first two-dimensional material is attached to the surface of the bottom electrode layer; The top electrode layer is attached to the surface of the second two-dimensional material.

7. The memristor according to claim 6, wherein: The memristor further includes: a substrate layer; The bottom electrode layer is arranged on the surface of the substrate layer; The substrate layer includes an oxide layer and a non-oxide layer; The substrate layer is formed of materials including: 300 μm to 500 μm Si and 350 nm SiO 2 .

8. The memristor according to claim 6, wherein: in, The electrode pattern of the bottom electrode layer is a rectangular shape arranged in parallel; the electrode pattern of the top electrode layer is consistent with the bottom electrode layer, and is arranged parallel to the bottom electrode layer and the top electrode layer, and the electrode pattern of the bottom electrode layer and the electrode pattern of the top electrode layer are perpendicular to each other in space.

9. The memristor according to claim 6, wherein: The top electrode layer and the bottom electrode layer are made of the same material; The constituent materials include a Ti layer and an Au layer; the thickness of the Ti layer is 5nm to 10nm, and the thickness of the Au layer is 50nm to 80nm.

10. The memristor according to claim 6, characterized in that The thickness of the two-dimensional material layer is comprised between 20 and 80 nm.

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