A method for SNN dynamic PET image processing based on a memristor array

Abstract

The application provides an SNN dynamic PET image processing method based on a memristor array, which comprises the following steps: preprocessing an original image sequence to obtain a normalized space-time feature matrix; generating an initial pulse sequence by using the normalized space-time matrix; adjusting the initial pulse sequence to obtain a verified pulse sequence; generating a cross sequence by using the verified pulse sequence; obtaining a column current signal through the cross sequence; resetting a membrane unit integral and emitting a pulse signal according to a preset state sequence by using a finite state machine based on the column current signal; obtaining a digitized current value based on the pulse signal; obtaining a classification result by using the digitized current value; training a model through the classification result to obtain an optimized model; and generating a classification diagnosis result by using the optimized model. The physical level optimization of dynamic time sequence processing is realized through the constructed memristor cross array and pulse control collaborative architecture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, in particular to a SNN dynamic PET image processing method based on a memristor array. BACKGROUND

[0002] Alzheimer's disease is a neurodegenerative disease, and early diagnosis is of great significance to delay the development of the disease. PET (Positron Emission Tomography) imaging technology can dynamically reflect the brain metabolism state through a tracer, and is an important means to identify early biomarkers of AD. At present, the existing technology in processing dynamic PET time sequence image has the key challenges of physical level energy efficiency bottleneck, insufficient dynamic feature fidelity, poor edge computing adaptability and lack of effective simulation of neuromorphic mechanism, which are specifically manifested as follows:

[0003] As a new type of non-volatile device, the memristor has a natural advantage in supporting neural network storage and computing integration, but at present, its combination with the spiking neural network (SNN) is mostly focused on static task recognition, and its application in time sequence image reasoning tasks is less, and there is a lack of software and hardware collaborative optimization mechanism to balance the control of power consumption and the protection of reasoning performance.

[0004] The existing SNN scheme has not solved the core problems of pulse coding sparsity, timing scheduling inaccuracy, large mapping error of memristor weight, and unconstrained pulse firing, resulting in that the reasoning system is still difficult to make a substantial breakthrough among power consumption, speed and accuracy.

[0005] Dynamic PET image is 4D (i.e. space-time) sequence data, which has typical characteristics such as high noise, low contrast, and sparse features. Although the traditional deep learning method based on convolutional neural network has made certain progress in classification accuracy, it has serious problems such as high energy consumption, long calculation delay, and hardware non-portability, which is not suitable for deployment on actual bedside devices, embedded or edge platforms.

[0006] Most of the existing algorithms rely on high-performance devices such as GPU for reasoning diagnosis, which requires high power, and lacks effective simulation of neuromorphic mechanisms for event-driven and time information coding, making it difficult to capture subtle changes in abnormal brain metabolism with high sensitivity. SUMMARY

[0007] In view of the above situation, the main purpose of the present application is to provide a SNN dynamic PET image processing method based on a memristor array to solve the above technical problems.

[0008] The present application provides a SNN dynamic PET image processing method based on a memristor array, which comprises the following steps:

[0009] Step 1, input the original image sequence into the classification diagnosis model, and pre-process the original image sequence to obtain a standardized space-time feature matrix;

[0010] The metabolic intensity and metabolic rate are calculated using the standardized space-time feature matrix; the adjustable pulse is obtained based on the metabolic intensity and metabolic rate, and the initial pulse sequence is generated based on the adjustable pulse; the initial pulse sequence is shaped and verified to obtain a verified pulse sequence;

[0011] The verified pulse sequence is converted into a row voltage by the word line driving circuit, and is applied to the memristor array row line to generate a cross sequence;

[0012] Based on the row voltage and the memristor conductance in the cross sequence, a column current signal is obtained;

[0013] Step 2, based on the column current signal, using a finite state machine, reset the membrane unit integral and emit a pulse signal according to the preset state sequence;

[0014] Step 3, the pulse signal is converted into a row voltage by the word line driving circuit, and is applied to the memristor array row line to obtain a new cross sequence; based on the new cross sequence, a new column current signal is obtained; after low-pass filtering and operational conversion, a digitized current value is obtained;

[0015] Step 4, the digitized current value is synchronously sampled to obtain a fixed-point digital signal, and the original image sequence is classified and pre-processed based on the fixed-point digital signal to obtain a classification result;

[0016] Step 5, based on the classification result and the clinical diagnosis label, an updated weight is obtained, and the classification diagnosis model is optimized using the updated weight to obtain an optimized classification diagnosis model; the original image sequence is input into the optimized classification diagnosis model to generate a classification diagnosis result.

[0017] Compared with the prior art, the present application has the following advantages:

[0018] 1、The present application converts the metabolic intensity and rate change of dynamic PET into the time sequence feature expression of the pulse sequence by constructing the "metabolic parameter-pulse space-time coding" coupling mechanism. Compared with the traditional static coding or fixed frequency pulse scheme, the present application further retains the space-time correlation in the four-dimensional data of dynamic PET, and significantly improves the detection sensitivity of the hippocampal amyloid deposition rate, temporal lobe glucose metabolic annual change and other super-early pathological features through the physical level time alignment of the pulse emission mode;

[0019] 2. The application realizes physical-level optimization of dynamic timing processing by constructing a cross array of memristors and a pulse control cooperative architecture, wherein the conductance value of each memristor unit directly represents a synaptic weight, an input pulse sequence triggers a transconductance operation through row line driving, and the physical superposition process of column line current essentially completes the space-time integration of dynamic characteristics.

[0020] 3. The application realizes high-fidelity representation of four-dimensional space-time information and improves the detection sensitivity of early weak metabolic abnormalities by constructing a closed-loop technical system of 'dynamic coding reconstruction-computing and storage integrated optimization-edge lightweight adaptation', solving the limitations of traditional static feature extraction based on the dynamic coupling mechanism of metabolic parameters and pulse coding at the dynamic PET timing modeling level; at the computing architecture level, the energy consumption problem of the Von Neumann architecture is solved by relying on the computing and storage integrated characteristics and event-driven mechanism of memristors, and the energy efficiency ratio is greatly improved through physical-level sparse computing; at the device deployment level, the lightweight design of software and hardware is promoted to realize the sinking of high-precision diagnostic capabilities to the edge side, and realize the new mode of 'precise screening instantly accessible' for inclusive medical care.

[0021] Additional aspects and advantages of the application will be made apparent by the following description. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A flowchart of the SNN dynamic PET image processing method based on the memristor array proposed by the application;

[0023] Figure 2 A finite state machine state transition flowchart of the SNN dynamic PET image processing method based on the memristor array proposed by the application;

[0024] Figure 3 A'metabolic parameter-pulse coding' mapping flowchart of the SNN dynamic PET image processing method based on the memristor array proposed by the application;

[0025] Figure 4 A weight update flowchart of the SNN dynamic PET image processing method based on the memristor array proposed by the application. DETAILED DESCRIPTION

[0026] Embodiments of the application are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are only used to explain the application, and cannot be understood as a limitation of the application.

[0027] These and other aspects of embodiments of the present application will become clear from the following description and the accompanying drawings. In the description and drawings, specific embodiments of the embodiments of the present application are disclosed in detail. It should be understood that the scope of the embodiments of the present application is not limited to the specific embodiments described and shown.

[0028] Referring to Figure 1 The embodiment of the present application provides a SNN dynamic PET image processing method based on a memristor array, which comprises the following steps:

[0029] Step 1, inputting an original image sequence into a classification diagnosis model, and pre-processing the original image sequence to obtain a standardized space-time feature matrix;

[0030] The metabolic intensity and metabolic rate are calculated by using the standardized space-time feature matrix; the adjustable pulse is obtained based on the metabolic intensity and metabolic rate, the initial pulse sequence is generated based on the adjustable pulse, and the initial pulse sequence is shaped and verified to obtain a verified pulse sequence;

[0031] The verified pulse sequence is converted into a row voltage by using a word line driving circuit, and is applied to a memristor array row line to generate a cross sequence;

[0032] The column current signal is obtained based on the row voltage and the memristor conductance in the cross sequence;

[0033] In step 1, the metabolic intensity and metabolic rate are calculated by using the standardized space-time feature matrix, and the relationship formula corresponding to the process is:

[0034] ;

[0035] Wherein, S represents the normalized uptake value ratio of the target brain region; S represents the reference value of the age-matched healthy population, which is provided by the ADNI database; K represents the rate of change of the receptor binding rate with time; K represents the specific binding rate constant of the tracer and the target receptor such as amyloid or Tau protein, which is obtained by fitting the compartment model by using the nonlinear least squares method through the time-activity curve (TAC) obtained by dynamic PET scanning; D represents the derivative symbol, t represents the time axis coordinate in dynamic PET scanning, S represents the average normalized uptake value of the radioactive tracer related to amyloid or Tau protein in the target brain region, S represents the average normalized uptake value of the radioactive tracer related to the same pathological protein in the reference brain region, represents the average radioactivity concentration of the amyloid or tau protein radiotracer in the target brain region, represents the ratio of the amyloid or tau protein radiotracer injection dose to the subject's body weight, represents the average radioactivity concentration of the same pathological protein radiotracer in the reference brain region, represents the total number of valid voxels in the target brain region, represents the radioactivity concentration of the amyloid or tau protein radiotracer in the th voxel in the target brain region, represents the total number of valid voxels in the reference brain region, represents the radioactivity concentration of the same pathological protein radiotracer in the th voxel in the reference brain region;

[0036] Based on the adjustable pulse generation, an initial pulse sequence is obtained, and the corresponding process exists the following relationship:

[0037] ;

[0038] wherein, represents the standardized uptake value ratio, represents the time interval between adjacent two pulses in the pulse sequence, represents the rate of change of the receptor binding rate with time;

[0039] Based on the row voltage and the memristor conductance in the cross sequence, the column current signal is obtained, and the corresponding process exists the following relationship:

[0040] ;

[0041] wherein, represents the total output current of the th column, that is, the sum of the currents generated by all the memristor units in the th column in the memristor cross sequence, which is obtained by accumulating the products of all the row voltages and the corresponding memristor conductances in this column; represents the input voltage of the th row, which is determined by the amplitude of the pulse signal output by the pulse timing control module; represents the conductance value of the th memristor in the th row and column, which represents the conductive state of the memristor at the row-column intersection point and is adjusted through the SPI protocol; represents the row index, that is, a certain row in the 64 horizontal row lines of the corresponding memristor array, and the value range is ; represents the column index, that is, a certain column in the 64 vertical column lines of the corresponding memristor array, and the value range is .

[0042] Specifically, in this step, the original image sequence is specifically an original 4D dynamic PET image sequence.

[0043] Further, in the process of pre-processing the original image sequence, the following steps are further included:

[0044] Registered to the MNI152 standard brain template using ANTs to eliminate device differences;

[0045] Based on the cerebellar gray matter reference brain region, the standardized uptake value ratio is calculated, and the Z-score is standardized;

[0046] The double-tissue compartment model is fitted to the time-activity curve to extract the metabolic parameters.

[0047] Further, please refer to Figure 3 Based on metabolic intensity and metabolic rate, the FPGA on-chip DSP module is used to accelerate floating-point operation to obtain metabolic parameters;

[0048] Using metabolic parameters, the DDS technology is used to generate adjustable pulses, and the frequency range of the adjustable pulses is 20-200Hz;

[0049] The IDelayE3 programmable delay unit is used to process the adjustable pulses to generate the initial pulse sequence.

[0050] Further, the initial pulse sequence is sequentially subjected to a synchronous trigger mechanism, pulse amplitude shaping, and the addition of an RC low-pass filter to obtain a shaped pulse sequence (64-channel parallel signal).

[0051] The shaped pulse sequence is subjected to reverse decoding verification and sparsity detection processing to obtain a pulse sequence that passes the test.

[0052] Further, in this step, the memristor cross array module is the core component for implementing synaptic weight calculation and in-memory multiplication and addition operation in the present application, which mainly completes the physical multiplication calculation of input pulse signals and weights, and outputs the vector-matrix multiplication (VMM) result in the form of column current superposition for subsequent processing by the membrane potential integration unit.

[0053] This module adopts a memory-compute integrated structure, uses the conductance adjustable characteristics of the memristor to represent the neural network connection weight, and avoids the "storage-computation-transmission" bottleneck in the traditional von Neumann architecture.

[0054] Step 2, based on the column current signal, using a finite state machine, resetting the membrane unit integration and emitting pulse signals according to the preset state sequence;

[0055] In step 2, based on the column current signal, a finite state machine is used to reset the membrane unit integral and issue pulse signals according to a preset state sequence. The specific steps are as follows:

[0056] The column current signal is converted into a digital current signal, and the digital current signal is differentially discretized to obtain the updated membrane unit integral.

[0057] The updated membrane unit integral is judged by a decision maker and a Boolean signal is generated. Based on the Boolean signal, a high-level pulse is output for one clock cycle. The membrane unit integral is reset based on the high-level pulse for one clock cycle. At the same time as resetting the membrane unit integral, a pulse signal is issued. Based on the pulse signal, the refractory period counter is started to shield the input.

[0058] Differential discretization processing is performed on the digitized current signal to obtain the updated membrane unit integral. The corresponding relationship in this process is as follows:

[0059] ;

[0060] in, This represents the membrane potential at the current moment. Indicates the membrane time constant. Indicates the input resistance. Indicates the input current intensity. Indicates the integration step size. Indicates the index of the discrete time step. This represents the 12-bit digital value output by the ADC. Indicates the first The instantaneous value of the membrane potential at each time step. This represents the resting potential of a neuron. This represents the maximum theoretical value of the input current. This indicates the feedback resistor value of the transimpedance amplifier;

[0061] The updated membrane unit integral is evaluated using a determiner, and a Boolean signal is generated. Based on the Boolean signal, a high-level pulse per unit clock cycle is output. The corresponding relationship in this process is as follows:

[0062] ;

[0063] in, This represents a dynamically configurable membrane potential firing threshold. This indicates a pulse firing event triggered when the integral value of the membrane potential of the current neuron exceeds a preset threshold;

[0064] Based on a Boolean signal, a high-level pulse is output per unit clock cycle. This high-level pulse is used to reset the membrane unit integral. The relationship during the reset process is as follows:

[0065] ;

[0066] wherein, is the configurable membrane unit integral.

[0067] Further, in this step, the column current signal is low-pass filtered and converted by the operational amplifier, and then sampled by the ADC (1 MHz, 12-bit accuracy) to obtain a digitized current signal.

[0068] Further, the differential discrete processing of the digitized current signal is performed using the LIF neuron model to obtain an updated membrane unit integral.

[0069] Further, based on the Boolean signal, a high-level pulse (amplitude 1.2V, width 1ms) is output in a unit clock cycle, and the membrane unit integral is reset.

[0070] Further, please refer to Figure 2 In this step, the state sequence control timing is controlled by the finite state machine control unit, which is the timing scheduling center of the entire pulse timing module. The functional units in step 2 are connected in a state machine manner, including: membrane potential integral unit, voltage threshold determinator, pulse firing and reset unit, and refractory period controller.

[0071] The definition of the finite state machine control unit is shown in Table 1

[0072] Table 1: State definition of finite state machine

[0073]

[0074] When S3 is entered; when Refractory_Counter (refractory period counter) > 0, S4 is entered; otherwise, it is cycled between S1 and S2.

[0075] Specifically, in this step, the input value comes from the column current transmitted by the cross sequence (64x64 memristor cross array), where each current represents a synaptic weight input. These currents are converted to digital values by the ADC in the analog / digital signal conversion module and input to the accumulator.

[0076] Two points need to be considered during the execution of each cycle: first, the membrane potential will gradually increase according to the input current until it reaches the threshold; second, the natural fall of the neuron membrane potential needs to be simulated, i.e. when the neuron is subjected to non-continuous stimulation, it will produce a "leakage" phenomenon, and the membrane potential will fall slightly.

[0077] In FPGA, the cumulative differential update is realized by using fixed-point multiplier and bit shift operation, and the precision is adjustable from 8 to 12 bits; the filter is realized by using IIR structure to realize exponential decay; the voltage value is cached in the potential register, and is updated once per cycle, supporting 64-way parallel operation;

[0078] Finally, the updated membrane unit integral is output, and the next unit is entered for judgment.

[0079] Further, in this step, the parameter configuration adopts a dynamic adjustment mode combined with STDP training or pulse regularization feedback to realize online real-time updating for neuron activity regulation;

[0080] In FPGA, the comparator unit triggered by the clock edge is used to complete the voltage threshold determination, supporting 8-12 bit fixed-point number input; the determinator reads and , and outputs a 1-bit Boolean signal; the determinator is a group of 64 neurons, and uses a pipeline parallel determination structure to improve the throughput.

[0081] When , the output value is a Boolean signal of 1, indicating that the current cycle needs to trigger firing; otherwise, the output value is a Boolean signal of 0, continuing the integration state; the Boolean signal with a value of 1 is sent to the firing and reset unit to trigger the corresponding neuron firing pulse.

[0082] Step 3, convert the pulse signal into a row voltage using the word line driving circuit, and apply it to the memristor array row line to obtain a new cross sequence; based on the new cross sequence, a new column current signal is obtained; after low-pass filtering and operational amplifier conversion of the new column current signal, a digitized current value is obtained.

[0083] Further, in this step, after low-pass filtering and operational amplifier conversion of the new column current signal, ADC sampling (1MHz, 12-bit precision) is performed to obtain a digitized current value (64 columns).

[0084] Step 4, the digitized current value is synchronously sampled to obtain a fixed-point digital signal, and the original image sequence is classified and preprocessed based on the fixed-point digital signal to obtain a classification result.

[0085] Further, in this step, the digitized current value is sampled using a 12-bit SAR ADC (1MHz, 0-1.2V input range) to obtain a 12-bit fixed-point digital signal;

[0086] Based on the 12-bit fixed-point digital signal, the original 4D dynamic PET image sequence is classified and preprocessed (extracting features such as pulse count and firing frequency, generating a classification output vector) using a DDR4 Buffer to obtain a classification result (12-bit fixed-point number).

[0087] Further, in this step, the classification result is converted into an analog voltage (0-1V) by using an R-2R type DAC (12-bit resolution, 1MSps), and an analog metabolic feedback signal is generated.

[0088] Step 5, based on the classification result and the clinical diagnosis label, the updated weight is obtained, the classification diagnosis model is optimized by using the updated weight to obtain the optimized classification diagnosis model, and the original image sequence is input into the optimized classification diagnosis model to generate a classification diagnosis result;

[0089] Please refer to Figure 4 In step 5, error calculation is performed based on the classification result and the clinical diagnosis label, an error signal is generated, and the weight is updated using the surrogate gradient method, and the relationship formula corresponding to the process is:

[0090] ;

[0091] Among them, represents the weight adjustment amount, reflecting the update direction and amplitude of the synaptic connection strength of the neural network in the current training period; represents the cross-entropy loss function, which quantifies the difference between the current SNN output result and the true AD diagnosis label; represents the true label of the sample, if the sample is actually an AD patient, then , if the sample is actually a normal person, then ; represents the probability value predicted by the model, ranging from , representing the probability that the current sample belongs to the positive class (such as AD patients); represents the membrane potential of the neuron, reflecting the cumulative state of the input signal in the time dimension; represents the synaptic weight, corresponding to the conductance value of each unit in the crossbar array of the memristor.

[0092] Further, in this step, error calculation is performed based on the classification result and the clinical diagnosis label and an error signal is generated, and then the weight is updated using the surrogate gradient algorithm to obtain the updated weight.

[0093] In the present application, the overall structure is divided into six core modules, namely, a pulse timing control module, a 64x64 memristor crossbar array module, an analog / digital signal conversion module (ADC / DAC), a data buffer and scheduling module, a pulse precoding module and an FPGA master control module.

[0094] Pulse timing control module:

[0095] The module is deployed in an FPGA platform, adopts Verilog HDL to design a logic circuit, and is mainly responsible for when to generate a nerve pulse, and at what frequency, intensity, and condition to fire the nerve pulse. The module provides a controlled, adjustable, and reasonable rhythm pulse firing behavior for the system, as a "signal-driven" to drive the entire SNN to issue instructions to the memristor array. The module is composed of five sub-units: membrane potential integration unit, voltage threshold determinator, pulse firing and reset unit, refractory period controller, and finite state machine control unit. The five sub-units are connected in a pipeline structure to form a complete pulse processing path.

[0096] Array structure of the 64x64 memristor cross array module:

[0097] Dimensions: 64 rows x 64 columns cross array, a total of 4096 memristor units;

[0098] Physical unit: each cross point is a TaOx metal oxide memristor with a multi-state adjustable conductance;

[0099] Row line: corresponding to neuron input (pulse voltage signal);

[0100] Column line: corresponding to the output membrane potential input current channel.

[0101] Data buffer and scheduling module:

[0102] This module serves as a bridge and hub for system data transmission, mainly responsible for two functions:

[0103] Input path buffer and scheduling: buffer the original or preprocessed data from the PET dynamic image sequence to ensure stable supply in the SNN processing flow;

[0104] Output path result buffer and write-back: store, classify, label, and distribute the results obtained by the memristor array reasoning, for subsequent processing, visualization, or data saving.

[0105] In the system architecture, this module plays a key role in data throughput rate improvement, timing consistency guarantee, and FPGA-peripheral communication coordination;

[0106] Structure design of the data buffer and scheduling module:

[0107] High-speed data buffer area (DDR4 Buffer)

[0108] Storage capacity: 1GB DDR4 (directly connected through Zynq PS);

[0109] Interface: AXI high-performance bus and PL-end data stream;

[0110] Function: Cache multi-frame PET sequence of ADNI image dataset, and preload partial pulse encoding data;

[0111] Features: Support burst transmission, prefetch mechanism, address remapping, and DMA acceleration.

[0112] Input Scheduler

[0113] Function: Distribute pulse sequence (or image data) cached in DDR4 to SNN core inside FPGA on demand according to SNN inference frequency;

[0114] Support three-level scheduling by frame, block, and sequence;

[0115] Built-in scheduling table: set read address, frame number, and neuron mapping index for each frame of PET data.

[0116] Output Cache and Arbitration Controller

[0117] Function: Cache neuron firing records, pulse counts, classification labels, etc. after each round of SNN processing;

[0118] Features: Support output priority arbitration (real-time stream vs. batch processing stream) to avoid resource contention;

[0119] Interface: Interface with on-chip BRAM / URAM of FPGA, or write back to DDR4.

[0120] Data flow and workflow of data cache and scheduling module:

[0121] Input data flow:

[0122] Dynamic PET image sequence is stored in DDR4 in the format of N×T×H×W, where N is the number of samples, and T is the time frame.

[0123] After processing by the pulse pre-encoding module, it is converted into a pulse sequence (Poisson encoding or timing encoding);

[0124] The scheduling controller reads the corresponding frame block and loads it to the on-chip input buffer according to the SNN neuron mapping relationship;

[0125] Trigger SNN forward inference.

[0126] Output data flow:

[0127] Output neuron firing matrix (pulse count or pulse time) after each inference;

[0128] Write to the output FIFO for unified caching;

[0129] According to system setting selection:

[0130] Real-time feedback: Directly transfer to DAC module analog output;

[0131] Offline save: Write back to DDR4 through AXI DMA;

[0132] Intermediate marking: Classification output / AD index write control register.

[0133] FPGA cooperative control mechanism in data cache and scheduling module:

[0134] Scheduling mode:

[0135] Input: "Load-Mapping-Trigger" three stages triggered by SNN master state machine;

[0136] Output: "Transfer-Arbitration-Write" three stages triggered by inference completion signal;

[0137] All data streams are strictly aligned with system clock cycles to prevent out-of-order.

[0138] AXI control:

[0139] Support AXI4-Full and AXI-Stream two paths;

[0140] Use DMA controller to achieve large block burst read and write (Burst Length = 8~16);

[0141] Use Cache-Coherent Interconnect (CCI) to ensure PS-PL high-speed communication consistency.

[0142] Bandwidth and cache strategy:

[0143] Maximum bandwidth of input path: >1.2 GB / s;

[0144] Maximum bandwidth of output path: >800 MB / s;

[0145] Cache strategy: Prefetch window + interleaved loading, improve effective utilization;

[0146] Control strategy: With data valid flag and instruction FIFO, reduce invalid data period.

[0147] Pulse pre-coding module:

[0148] Pulse pre-coding module is the signal transformation hub between dynamic PET image data and memristor array, responsible for converting the time-space metabolic parameters of dynamic PET into pulse sequences suitable for SNN, and achieving precise timing control through hardware programmable logic.

[0149] Overall structure of the pulse pre-encoding module:

[0150] It consists of five sub-units: dynamic PET input interface unit, metabolic parameter calculation unit, pulse frequency / interval encoding unit, timing control and pulse shaping unit, and output buffer and verification unit.

[0151] The module data flow follows a closed-loop process of "metabolic parameter extraction → pulse encoding → timing shaping → output verification", ensuring spatiotemporal feature fidelity and hardware compatibility.

[0152] Structure design of the pulse pre-encoding module:

[0153] Dynamic PET input interface unit

[0154] Function: Receive raw dynamic PET image data (ADNI format), complete frame segmentation, time alignment and noise filtering, and output standardized spatiotemporal feature matrix

[0155] Input format: 4D dynamic PET sequence (spatial HxWxD, temporal T), resolution 1mm³, time frame interval 30s

[0156] Preprocessing: registered to MNI152 standard brain template using ANTs to eliminate device differences; calculate SUVr value based on cerebellar gray matter reference brain region, Z-score standardization; double tissue compartment model fitting time-activity curve, extract k1 (brain transport rate), k3 (receptor binding rate) parameters.

[0157] Output: Spatiotemporal feature matrix (dimension: number of brain regions ROI x time frame x metabolic parameter).

[0158] Metabolic parameter calculation unit

[0159] Function: Quantify metabolic intensity and rate, construct pulse encoding rule input.

[0160] Pulse frequency / interval encoding unit

[0161] Function: Map metabolic parameters to pulse frequency and interval, generate initial pulse sequence.

[0162] Timing control and pulse shaping unit

[0163] Function: Coordinate pulse timing, suppress noise and match the driving requirements of the memristor array.

[0164] Key technology: Synchronous triggering mechanism: align multi-channel pulses through global clock BUFG, timing error <1μs.

[0165] Pulse amplitude shaping: limit pulse amplitude to 1.2V (adapt to memristor row line driving voltage).

[0166] Noise filtering: Add an RC low-pass filter (cutoff frequency 1MHz) to suppress high-frequency interference.

[0167] Hardware resources: SelectIO logic of Xilinx UltraScale+ FPGA;

[0168] Analog switch and level conversion circuit (integrated into FPGA Mezzanine Card).

[0169] Output buffer and verification unit

[0170] Function: Caches pulse sequences and verifies encoding accuracy, ensuring compatibility with SNN inputs.

[0171] Reverse decoding verification: Reconstruct the k3 curve from the pulse sequence and calculate the root mean square error (target: RMSE < 0.05 / min).

[0172] Sparsity monitoring: Statistical pulse density, activation rate must be <30% (to avoid overloading the memristor array).

[0173] Implementation: Use the on-chip BRAM of the FPGA to buffer 64 channels of pulse sequence; transmit the verification results back to the main control module through the AXI-Stream interface.

[0174] FPGA collaborative control mechanism in the pulse precoding module:

[0175] Input scheduling: Dynamic PET data is cached in DDR4 and loaded into the preprocessing unit via AXI DMA burst transfer (Burst Length=8).

[0176] Real-time control: Frame-by-frame scheduling encoding process of the state machine (FSM): State flow: Load data → Calculate parameters → Encode pulse → Verify → Output

[0177] Error handling: If the verification fails (e.g., RMSE exceeds the limit), an interrupt is triggered and the current frame is re-encoded.

[0178] FPGA main control platform module:

[0179] The FPGA main control module is the core of the entire system's scheduling and control, implementing hardware and software collaborative control based on the Zynq UltraScale+ MPSoC platform. Its core tasks include: managing the timing of the pulse timing controller, memristor array, ADC / DAC module, and data buffer module; implementing the SNN core inference logic, state transitions, pulse learning algorithms (such as STBP), and weight updates; and interfacing with the external DDR4 / ADNI data interface to enable image data input and result output feedback.

[0180] The module realizes core algorithm control circuit through programmable logic PL end, cooperates with embedded ARM core of processing system PS end to run, and constitutes a central part of a system-level SNN brain reasoning platform.

[0181] Structure of FPGA master control platform module

[0182] SNN control state machine (SNN FSM)

[0183] Function: Coordinate the timing control of the membrane potential integrator, pulse generator, and memristor array.

[0184] State flow: data loading → pulse firing → weight reading → current accumulation → membrane potential integration → output judgment.

[0185] Characteristics: Synchronize all neurons to execute in each processing cycle, and support 64 parallel path executions.

[0186] STBP training and weight update module

[0187] Supports spike-based temporal backpropagation algorithm.

[0188] Approximates the derivative of the membrane potential function using the surrogate gradient method.

[0189] Supports weight update mechanism.

[0190] The module is directly connected with the memristor SPI controller to complete online or offline weight adjustment.

[0191] Command and control distribution module (command dispatcher)

[0192] Receive command words (load, run, reset, writeback) issued by the ARM of the PS end.

[0193] After decoding, send signals to the cache, ADC, DAC, etc. through the AXI bus.

[0194] Support frame-level command execution, interrupt priority processing, pipeline scheduling, and error rollback.

[0195] Neuron mapping and index table

[0196] Maintain the mapping relationship between 64 input channels and memristor row lines.

[0197] Support physical binding of PET image metabolism partition and SNN channel.

[0198] LUT table (BRAM implementation) is used to quickly find the neuron-image region correspondence.

[0199] Inference flow of FPGA master control platform module and inter-module scheduling mechanism

[0200] Load pulse sequence to on-chip cache;

[0201] SNN FSM schedules pulse firing, current accumulation and membrane potential integration of each cycle;

[0202] If the membrane potential exceeds the threshold, output the pulse count and enter the firing state;

[0203] The output result is forwarded to the DAC or peripheral through the arbitration module;

[0204] If in the training stage, call the STBP module to perform error back propagation and update the weight.

[0205] It should be understood that various parts of the present application can be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, a plurality of steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following technologies known in the art: discrete logic circuit with logic gate circuit for implementing logic functions on data signals, application specific integrated circuit with suitable combination logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA), etc.

[0206] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0207] The above-described embodiments only express several embodiments of the present application, which are described in detail and specifically, but cannot be understood as limiting the scope of the present patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the scope of protection of the present patent should be subject to the appended claims.

Claims

1. A method for SNN dynamic PET image processing based on memristor array, characterized in that, The method includes the following steps: Step 1: Input the original image sequence into the classification and diagnosis model, and preprocess the original image sequence to obtain the standardized spatiotemporal feature matrix; The metabolic intensity and metabolic rate are calculated using a standardized spatiotemporal feature matrix; tunable pulses are obtained based on the metabolic intensity and metabolic rate; an initial pulse sequence is generated based on the tunable pulses; and the initial pulse sequence is shaped and validated to obtain a validated pulse sequence. The verified pulse sequence is converted into a row voltage using a word line driving circuit and applied to the row lines of the memristor array to generate a crossover sequence. The column current signal is obtained based on the row voltage and memristor conductance in the cross sequence; Step 2: Based on the column current signal, use a finite state machine to reset the membrane unit integral and send pulse signals according to a preset state sequence; Step 3: Use the word line driving circuit to convert the pulse signal into a row voltage and apply it to the row lines of the memristor array to obtain a new crossover sequence; obtain a new column current signal based on the new crossover sequence; and obtain the digitized current value by low-pass filtering and operational amplifier conversion of the new column current signal. Step 4: Synchronously sample the digitized current value to obtain a fixed-point digital signal, and perform classification preprocessing on the original image sequence based on the fixed-point digital signal to obtain the classification result; Step 5: Based on the classification results and clinical diagnostic labels, obtain the updated weights, optimize the classification diagnostic model using the updated weights to obtain the optimized classification diagnostic model, and input the original image sequence into the optimized classification diagnostic model to generate the classification diagnostic results.

2. The SNN dynamic PET image processing method based on memristor array according to claim 1, characterized in that, In step 1, metabolic intensity and metabolic rate are calculated using the standardized spatiotemporal feature matrix, and the corresponding relationship in the process is as follows: ； in, This indicates the ratio of standardized uptake values ​​of the target brain region. This represents a reference value for age matching healthy individuals. This represents the rate of change of receptor binding rate over time. This represents the rate constant of specific binding between the tracer and the target receptor. Represents the derivative symbol. This represents the time axis coordinates in a dynamic PET scan. This represents the average standardized uptake of radioactive tracers related to amyloid or tau proteins in the target brain region. This represents the average standardized uptake of radiotracers of the same pathological protein in the reference brain region. This indicates the average radioactivity concentration of radioactive tracers related to amyloid or tau proteins in the target brain region. This represents the ratio of the dose of the radioactive tracer for amyloid or tau protein injected to the subject's body weight. This indicates the average radioactivity concentration of radioactive tracers for the same pathological protein in a reference brain region. This represents the total number of effective voxels within the target brain region. Indicates the first brain region within the target brain region The radioactivity concentration of radioactive tracers related to amyloid or tau proteins in individual proteins. This indicates the total number of effective voxels within the reference brain region. Indicates the reference brain region number The radioactive concentration of the radioactive tracer for the same pathological protein in the individual.

3. The SNN dynamic PET image processing method based on memristor array according to claim 2, characterized in that, In step 1, an initial pulse sequence is obtained based on the adjustable pulse generation, and the corresponding relationship in the process is as follows: ； in, Indicates the standardized intake ratio, This represents the time interval between two adjacent pulses in a pulse sequence. This represents the rate of change of receptor binding rate over time.

4. The SNN dynamic PET image processing method based on memristor array according to claim 3, characterized in that, In step 1, the column current signal is obtained based on the row voltage and memristor conductance in the cross sequence, and the corresponding relationship in the process is: ； in, Indicates the first Total output current of the column Indicates the first The input voltage of the line, Indicates the first Line 1 The conductance of the memristor Indicates row index, Indicates column index.

5. The SNN dynamic PET image processing method based on memristor array according to claim 4, characterized in that, In step 2, based on the column current signal, a finite state machine is used to reset the membrane unit integral and issue pulse signals according to a preset state sequence. The specific steps are as follows: The column current signal is converted into a digital current signal, and the digital current signal is differentially discretized to obtain the updated membrane unit integral. The updated membrane unit integral is evaluated using a decision maker, and a Boolean signal is generated. A high-level pulse per unit clock cycle is output based on a Boolean signal, and the membrane unit integral is reset based on the high-level pulse per unit clock cycle. While resetting the membrane unit integral, a pulse signal is issued, and a refractory period counter is started based on the pulse signal to shield the input.

6. The SNN dynamic PET image processing method based on memristor array according to claim 5, characterized in that, Differential discretization processing is performed on the digitized current signal to obtain the updated membrane unit integral. The corresponding relationship in this process is as follows: ； in, This represents the membrane potential at the current moment. Indicates the membrane time constant. Indicates the input resistance. Indicates the input current intensity. Indicates the integration step size. Indicates the index of the discrete time step. This represents the 12-bit digital value output by the ADC. Indicates the first The instantaneous value of the membrane potential at each time step. This represents the resting potential of a neuron. This represents the maximum theoretical value of the input current. This indicates the feedback resistor value of the transimpedance amplifier.

7. The SNN dynamic PET image processing method based on memristor array according to claim 6, characterized in that, The updated membrane unit integral is evaluated using a determiner, and a Boolean signal is generated. Based on the Boolean signal, a high-level pulse per unit clock cycle is output. The corresponding relationship in this process is as follows: ； in, This represents a dynamically configurable membrane potential firing threshold. This indicates a pulse firing event triggered when the integral value of the membrane potential of the current neuron exceeds a preset threshold.

8. The SNN dynamic PET image processing method based on memristor array according to claim 7, characterized in that, The membrane unity integral is reset based on a high-level pulse per unit clock cycle. The relationship in the reset process is as follows: ； in, For configurable membrane unit integration.

9. The SNN dynamic PET image processing method based on memristor array according to claim 6, characterized in that, In step 2, based on the column current signal, a finite state machine is used to reset the membrane unit integral and issue pulse signals according to a preset state sequence. The preset state sequence is as follows: Idle state, membrane potential integral value calculation state, threshold determination state, pulse generation / potential reset state, and refractory period state; Idle state: described as waiting for input current; Membrane potential integral value calculation status: described as performing membrane potential integral value calculation; Threshold determination status: Described as determining whether the conditions for issuing the threshold are met; Pulse Generation / Potential Reset Status: Described as generating a pulse signal and resetting the potential; Refractory period state: Described as starting the refractory period countdown and blocking input; when When the refractory period counter is greater than 0, it enters the pulse generation state and outputs a high-level pulse for one clock cycle; when the refractory period counter is greater than 0, it enters the refractory period state and starts the refractory period counter to shield the input; otherwise, it cycles between the integration state and the threshold determination state.

10. The SNN dynamic PET image processing method based on memristor array according to claim 9, characterized in that, In step 5, the updated weights are obtained based on the classification results and clinical diagnostic labels. The corresponding relationship in this process is as follows: ； in, Indicates the weight adjustment amount. Represents the cross-entropy loss function. This represents the true label of the sample. This represents the probability value predicted by the model. Represents the neuronal membrane potential. This represents synaptic weights.

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