System time sequence management method and system and electronic equipment

Abstract

The invention relates to the technical field of servers, in particular to a system time sequence management method and system and electronic equipment. The system time sequence management method comprises the steps that after a switch module obtains a power supply signal, a controller performs initial reset on a switch and a graphics processor, and after the switch and the graphics processor complete initial reset, a central processing unit triggers global reset; and during global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processor completes global reset control and recovers power supply, and then the central processor performs link training by using the switch and the graphics processor. According to the method, the technical problem of link training failure easily caused by initialization failure of the graphics processor and reset failure of the switch is solved, and the technical effect of improving the link training reliability and the operation stability is achieved.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a system timing management method, system, and electronic device. Background Art

[0002] As AI (Artificial Intelligence) server architectures evolve towards high-performance heterogeneous computing, the application of multi-stage switching topologies and standardized firmware has improved production efficiency and cabling flexibility. However, differences in initialization processes and reset functions among chips from different vendors have led to compatibility issues due to inconsistent underlying reset timing. In related technologies, when the motherboard module is reset, it typically instructs the switch magic module to initialize the graphics processor and reset the switch simultaneously. This can easily lead to GPU and switch loss, causing GPU initialization and switch reset failures, which in turn can easily cause link training failures. Summary of the Invention

[0003] The present application provides a system timing management method, system, and electronic device to at least solve the technical problem that failure in graphics processor initialization and switch reset easily leads to link training failure.

[0004] The present application provides a system timing management method, which includes: in response to a switch module obtaining a power supply signal, a controller controlling the switch and a graphics processor to perform an initial reset; in response to completing the initial reset, a central processing unit triggering a global reset; in response to the global reset, the controller controlling to stop supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and resumes power supply; in response to the graphics processor and the switch resuming power supply, the central processing unit uses the switch and the graphics processor to perform link training.

[0005] The present application provides a system timing management system, which includes: a mainboard module including a central processing unit; a switch module including a controller and multiple switches and a graphics processor connected to the controller; the controller is used to control the switches and the graphics processor to perform an initial reset in response to the switch module obtaining a power supply signal; in response to the central processing unit triggering a global reset, the controller controls the cessation of power supply to the switches and the graphics processor until the central processing unit completes the global reset control and restores power; the central processing unit is used to trigger a global reset in response to completing the initial reset; and in response to the graphics processor and the switch restoring power, the controller performs link training on a preset device connected to the switch.

[0006] The present application also provides an electronic device, which includes: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned system timing management methods when executing the computer program.

[0007] This application implements a method in which the controller immediately controls the switch and graphics processor to perform an initial reset after the switch module is powered on, so that the switch and graphics processor enter the reset state before the central processor. This timing design avoids the risk of secondary link training caused by traditional normalized firmware; then the central processor triggers a global reset, and the controller simultaneously cuts off the power supply to the switch and graphics processor to match the reset cycle of the central processor, ensuring that the device status is synchronized when the clock environment is interrupted; after the global reset is completed, the power supply is restored and the device status is reconstructed, the central processor performs unified link training on all preset devices to maximize the success rate of the first link training, thereby solving the problems of card loss and bandwidth reduction caused by firmware normalization, and supporting the deployment of a single version of firmware across multiple switches, reducing production and maintenance costs and improving hardware layout flexibility.

[0008] Therefore, this method can solve the technical problem that the graphics processor initialization and switch reset failure easily lead to link training failure, and achieves the technical effect of improving the reliability and operation stability of link training. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1 A hardware architecture diagram of a multi-GPU system provided in an embodiment of the present application; Figure 2 A reset timing diagram of a multi-GPU system provided in an embodiment of the present application; Figure 3 An application environment diagram of a system timing management method provided in an embodiment of the present application; Figure 4 A flowchart of a system timing management method provided in an embodiment of the present application; Figure 5 A timing diagram of a system timing management method provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of a system timing management system provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a system timing management device provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0011] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0012] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0013] It should be noted that the terms "S101," "S102," etc. are used only to describe the steps and do not specifically refer to the order or sequence, nor are they intended to limit this application. They are merely for the convenience of describing the method of this application and should not be understood as indicating the order of the steps. In addition, the technical solutions of the various embodiments may be combined with each other, but this must be based on the ability of ordinary technicians in this field to implement them. If the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this application.

[0014] In recent years, AI servers have become a crucial hardware foundation for the development of artificial intelligence (AI) technology. AI servers boast powerful computing and storage capabilities, enabling them to process massive amounts of data and complex algorithms. They have been widely used in fields such as natural language processing, image recognition, and autonomous driving, leading to continued growth in market demand. Furthermore, AI servers utilize efficient heat dissipation designs and energy-saving technologies to ensure stable operation under high loads and reduce energy consumption. They also support a variety of AI frameworks and algorithm libraries, making it easy for users to quickly build AI applications. Because AI servers must process massive amounts of data and complex algorithms, they place high demands on computing power, storage capacity, and energy efficiency. Advances in chip technology, heterogeneous computing, and other technologies are continuously improving the performance of AI servers. Specifically, the upstream component of AI servers includes chips, the midstream component includes server manufacturers, and the downstream component includes internet vendors and cloud service providers. The application scenarios of AI servers are expanding from centralized AI services to edge AI services, and the AI ​​server foundation is driving the development of terminal devices. Numerous GPU (Graphics Processing Unit) vendors are continuously releasing high-performance AI chips and system integration solutions. Therefore, based on different application scenarios and cost-effectiveness, customers may use CPUs (Central Processing Unit: the computing center of the motherboard, which performs task scheduling and protocol control) from different manufacturers with Switch chips from other manufacturers, and then hang GPU configurations from other platforms under the Switch chip. However, because different CPU manufacturers, Switch chip manufacturers, or GPU manufacturers follow the PCIE protocol specifications, their chips have differences in PCIE controller initialization efficiency, initialization process, and global reset function. Therefore, when chips or component manufacturers with different functions are combined, compatibility issues such as card loss, switch loss, and reduced bus bandwidth may arise.

[0015] This application provides a hardware architecture of a central processing unit platform with a graphics processing unit module. Figure 1 As shown, Figure 1 A hardware architecture diagram of a device equipped with multiple graphics processors provided in an embodiment of the present application.

[0016] Specifically, the hardware architecture includes a mainboard module (MB), the central hardware that carries core computing resources and system control. The MB module contains one or more central processing units (CPUs). The CPUs may include CPU0 and CPU1, which are interconnected via the eXascale Global Memory Interconnect (XGMI), a high-speed bus that allows for data exchange between different CPUs. The MB module also includes controllers, such as field programmable gate arrays (FPGAs) and hardware-level timing controllers.

[0017] The hardware architecture also includes a switch module (SW BOARD, Switch Board, switch board: an independent hardware module for expanding PCIe channels). This switch module can be used as a PCIe channel expansion, and the CPU's limited PCIe channels can be expanded to dozens of channels through multiple Switch chips to meet the parallel computing needs of multiple GPUs or NPUs (Neural Processing Unit, Neural Network Processor: a hardware circuit optimized for neural network operations such as convolutional neural networks, which can replace GPUs and be mounted on switch boards, and apply the same timing control logic). The switch module is connected to the mainboard module. The switch module includes multiple switches (SW: switch), which can be PCIE switches (Peripheral Component Interconnect Express Switch: high-speed peripheral component interconnect switch), or CXL Switch (Compute Express Link Switch: computing express link switch), FPGA soft core switch matrix (Field-Programmable Gate Array: field programmable gate array), DPU accelerator card (Data Processing Unit: data processing unit), and no specific restrictions are made here. Taking PCIE switch as an example, Figure 1The diagram shown includes four switches: Switch_A, Switch_B, Switch_C, and Switch_D. S0, S1, S5, S6, S7, and S8 on the PCIE switch chip represent different controllers. Any switch can include multiple controllers. PCIE Switch A and PCIE Switch D connect to CPU0 and CPU1 via their own S2 and S7 controllers, respectively. PCIE Switch B connects to CPU1 via its own S5 and S6 controllers. PCIE Switch C connects to CPU0 via its own S6 and S7 controllers. This uplink structure design allows for smoother routing of monitored PCIE devices on the PCB and in actual cable layouts.

[0018] When the hardware architecture based on CPU and multi-GPU computing modules is running, the following timing can be generated when resetting the PCIE Switch and multi-GPUs, such as Figure 2 As shown, Figure 2 This is a reset timing diagram of a multi-GPU system provided in an embodiment of the present application.

[0019] Specifically, the motherboard reset signal refers to the reset signal output by the motherboard to the PCIe device. The switch reset signal refers to the reset signal output by the cpld (Complex Programmable Logic Device) on the switch motherboard to the four switch chips, as well as the reset signal output to the PCIe device and GPU on the slot. It can be seen that in the current design, the reset signal output to the switch chip, PCIe device and GPU on the slot is based on the PCIe reset signal of the motherboard CPU. Figure 2 The timing diagram shows that both are pulled high and released simultaneously. In this case, after the CPU releases the PCIe reset signal, it sends the PCIe CPU detection signal to begin searching for PCIe devices. Simultaneously, after the switch chip releases the reset signal, it sends the switch detection signal to the CPU, facilitating handshake interaction between the CPU and PCIe devices. However, the firmware (firmware: underlying software written to rewritable memory that runs after power-on to initialize the chip and its peripherals) of these four PCIE switch chips is identical. This can lead to compatibility issues between different servers during the AC cycle, warm reset, and cold reset processes.

[0020] When different servers share the same FW, the link connecting the CPU to the PCIE switch is at risk of bandwidth loss. This is because the switch FW, for normalization, causes the switch to reset all ports within a certain period of time after the first link training with the CPU. The CPU identifies this reset as an abnormal link loss, and retraining the link will likely fail.

[0021] Related technologies require independent firmware programming for each switch, significantly reducing production efficiency and firmware maintenance costs. Furthermore, when the CPU is reset, the CPU clock is interrupted, and if the GPU is not powered off at this time, timing specifications may not be met, leading to GPU failure.

[0022] In order to solve the technical problem that the switch is prone to reset conflicts and reset clock interruptions leading to link training failures, the present application obtains a power supply signal in response to the switch module, and the controller controls the switch and the graphics processor to perform an initial reset; in response to the completion of the initial reset, the central processing unit triggers a global reset; in response to the global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and restores power; in response to the graphics processor and the switch restoring power, the central processing unit uses the switch and the graphics processor to perform link training, thereby achieving the technical effect of improving the reliability of link training and the stability of operation.

[0023] In order to make those skilled in the art better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods. The system timing management method provided by the present application can be applied to Figure 3 , Figure 3 This diagram illustrates an application environment for a system timing management method according to an embodiment of the present application. Terminal 12 communicates with server 14 via a network. Terminal 12 may be, but is not limited to, various personal computers, laptops, smartphones, tablet computers, and portable wearable devices. Server 14 may be implemented as a standalone server or a server cluster consisting of multiple servers.

[0024] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] The embodiment of the present application provides a system timing management method, such as Figure 4 , Figure 4 A flowchart of a system timing management method provided in an embodiment of the present application is provided, and the method is described in detail in conjunction with the execution process of the system timing management method.

[0026] S101: In response to the switch module obtaining a power supply signal, the controller controls the switch and the graphics processor to perform an initial reset.

[0027] In one embodiment, the controller refers to an FPGA1 chip on a switch board, which is used to execute hardware-level timing control logic. The timing control logic can be written in a coding language, such as Verilog.

[0028] When the switch module receives a power supply signal, the controller immediately responds to the signal, executes its own power-on initialization process, and then actively controls the switch and graphics processor to perform a reset operation. This reset operation includes sending a reset signal to the switch to force it into a reset state, and controlling the initialization of the graphics processor to ensure that both enter a stable initial state before the central processor intervenes. This step uses strict timing control to ensure that the device reset takes precedence over the central processor operation of the motherboard module, laying the foundation for subsequent global link training. This step can avoid compatibility issues caused by firmware normalization to improve the success rate of the system's first link training. This embodiment responds to the power supply signal to reset the switch and graphics processor in advance, ensuring that the device completes reset state synchronization before the central processor starts.

[0029] In one embodiment, the switch module includes a power module. The controller can also monitor the power module's power signal status and determine the reset release timing. The power module refers to the switch board's P1V8 power supply unit, which is used to step down the external 12V input to 1.8V, the PCIe I / O standard voltage, and provide operating voltage for the switch chip and FPGA. The power signal refers to the P1V8 power signal, which indicates voltage stability. A high level power signal indicates that the 1.8V voltage output meets the PCIe I / O standard voltage and is an enable condition for FPGA power-on initialization.

[0030] Specifically, the power module responds to the acquisition of input power, and its switch power signal P1V8 switches from the first level to the second level to form a first timing rising edge and a power supply signal; the controller responds to the first timing rising edge and the power supply signal to perform power-on initialization. Figure 5 , Figure 5 A timing diagram of a system timing management method provided in an embodiment of the present application.

[0031] Specifically, an external 12V power supply is input to the switch module power supply module, and the P1V8 power supply is ready. At this time, when the voltage switches from the first level to the second level, a first timing rising edge is generated, indicating that the P1V8 power supply signal jumps, wherein the first level is a low level, indicating that the power supply is not ready, which may be that the voltage does not reach the threshold or the fluctuation is greater than the fluctuation threshold. The second level is a draft level, indicating that the power supply output is stable. The controller FPGA1 detects the first timing rising edge and starts the initialization process, loads the configuration firmware from the internal memory, starts the reset control state machine, and prepares to receive GPU and switch status signals. In this embodiment, the P1V8 power supply is ready as the only startup source for the entire reset control chain, ensuring that subsequent actions are based on stable power supply.

[0032] In one embodiment, the controller sends an initialization signal to the graphics processor; the graphics processor receives the initialization signal and initializes; in response to the completion of the initialization, the graphics processor generates a graphics processor enable signal; the controller receives the graphics processor enable signal, delays for a first preset time period, and determines that the graphics processor has completed initialization; in response to the completion of the initialization of the graphics processor, the controller sends a reset signal to the switch; and the switch receives the reset signal and resets.

[0033] Specifically, FPGA1 sends an initialization signal to the graphics processor to start the power supply of the GPU core. The graphics processor receives the initialization signal and performs initialization when it detects that the voltage is stable.

[0034] Specifically, the controller controls the GPU to initialize, so that the GPU power signal GPU_BASE_PWRGD is switched from a first level to a second level to form a fourth timing rising edge and a GPU enable signal GPU_BASE_PWRGD.

[0035] Specifically, the motherboard prepares the clock environment to stabilize the CPU clock signal. The controller initializes the graphics processor, switching the graphics power signal from a first level to a second level. A low first level indicates that the GPU core power is off, while a high second level indicates that the GPU core power is enabled. This forms the transition edge of GPU_BASE_PWRGD from a low level to a high level, the fourth timing rising edge, ensuring that power enablement strictly lags behind clock stabilization.

[0036] The controller controls the switch clock signal to switch from the first level to the second level to form a fifth timing rising edge.

[0037] Specifically, at the same time as the fourth rising edge is formed, the clock generator is locked, and the switch clock signal SW_CLK switches from the first level to the second level, forming the fifth rising edge. The clock signal is activated, providing a stable clock reference for the switch. The first level is low, indicating that the switch clock output is disabled, and the second level is high, indicating that the clock output is enabled.

[0038] In response to the fourth timing rising edge and / or the fifth timing rising edge being formed for a duration reaching a first preset duration, the controller controls the switch reset signal SWA / B / C / D / SLOT / PEX_RESE to switch from the first level to the second level to form a sixth timing rising edge and a switch reset signal.

[0039] Specifically, the duration of the fourth timing rising edge reaches the first preset duration, or the duration of the fifth timing rising edge reaches the first preset duration. Since the fourth timing rising edge and the fifth timing rising edge are at the same time, the controller can control the switch reset signal to refer to the fourth timing rising edge or the fifth timing rising edge, so that when GPU_BASE_PWRGD accidentally drops, the continuous timing of SW_CLK can still trigger the release of the switch reset signal. Among them, the delay of the first preset duration has been determined to be set to 5 seconds based on experiments. If the time is too short, individual GPUs may be lost. If the time is too long, it will be consistent with the reset signal of the motherboard. The switch reset signal switches from a first level to a second level. The first level is low, indicating a forced reset state, that is, link training is terminated, and the second level is high, indicating the release of the reset, that is, the initiation of link training. The sixth timing rising edge represents the jump of SWA / B / C / D / SLOT / PEX_RESET from a low level to a high level.

[0040] Furthermore, in response to the completion of the controller initialization, its base preparation signal controller ready signal: GPU_BASE_FPGA_RDY switches from the first level to the second level to form a second timing rising edge.

[0041] Specifically, when the FPGA completes firmware loading, it actively pulls up the controller ready signal, generating a low-to-high transition edge. This rising edge is the trigger condition for subsequent operations and serves as the timing benchmark for the coordinated operation of multiple devices.

[0042] In response to the controller completing initialization and outputting GPU_BASE_PWRGD=1, FPGA1 obtains the graphics processor enable signal and delays it for a first preset time period, then determines that the graphics processor has completed initialization and sends a reset signal to the switch. The switch obtains the reset signal and resets itself, so that the controller controls the switch reset signal to switch from the first level to the second level.

[0043] The output controller ready signal is used as an initialization completion flag. The first level is low, indicating that the FPGA has not completed initialization, such as firmware loading or self-test failure. The second level is high, indicating that the FPGA is ready for initialization and the state machine can receive instructions.

[0044] In this embodiment, after receiving the GPU_BASE_PWRGD enable signal, FPGA1 executes a first preset delay, effectively avoiding the fluctuation period of the GPU core voltage and eliminating the interference of power supply noise on switch link training. At the same time, this delay window covers the forced reset period of the switch normalization firmware. While maintaining the advantage of single firmware production, it reduces the resource conflict rate of parallel training of multiple switches. By releasing the SWA / B / C / D / SLOT / PEX_RESET reset signals in a time-sharing manner, it provides initialization guarantee for the heterogeneous computing architecture.

[0045] In one embodiment, the controller obtains a power supply signal to perform power-on initialization, and in response to the completion of initialization, sends a first feedback signal to the mainboard module; the mainboard module obtains the first feedback signal and constructs a clock environment for coordinating the operation of the switch; in response to the completion of the clock environment construction, the controller controls the initialization of the graphics processor and controls the reset of multiple switches.

[0046] Specifically, in response to the first and second timing rising edges, the controller switches its base power signal, namely the motherboard switch ready signal MB_SW_PWRGD, from a first level to a second level, thereby generating a third timing rising edge and a first feedback signal. In response to the third timing rising edge and the first feedback signal, the motherboard module generates a periodic clock timing signal to establish a clock environment.

[0047] Specifically, after the first timing of P1V8 takes effect and the second timing of GPU_BASE_FPGA _RDY takes effect, and when both conditions are met, MB_SW_PWRGD is immediately pulled high to generate the third timing rising edge. Among them, the first level is a low level, indicating an unready state, that is, the power supply or FPGA is abnormal, and the second level is a high level, indicating that the switch board is ready as a whole, which is the prerequisite for allowing the motherboard to build a clock environment. This dual condition ensures that MB_SW_PWRGD is switched only when both rising edges take effect at the same time, avoiding the risk of false triggering of a single signal. MB_SW_PWRGD serves as the first feedback signal, used to transmit the ready status of the switch board to the motherboard module.

[0048] Specifically, after the mainboard FPGA0 captures the rising edge of MB_SW_PWRGD fed back by FPGA1, it starts the clock generator to prepare the clock environment. This clock environment provides a global clock reference for the switch chip, ensuring phase alignment of data transmission across multiple devices and meeting the manufacturer's timing requirement that the CPU clock remain stable before the GPU is powered on. Furthermore, a unified clock source forces multiple switches to respond synchronously to link training commands, avoiding resource contention caused by asynchronous operation. It also stabilizes the clock and compensates for PCB trace delay variations.

[0049] In this embodiment, MB_SW_PWRGD is generated directly after P1V8 is powered on and GPU_BASE_FPGA_RDY is ready. This MB_SW_PWRGD is fed back to the mainboard module, informing the mainboard that the switchboard is powered on and ready. At this point, the mainboard can prepare the CPU_CLK clock and enter S0. In this embodiment, there is no need to wait for the GPU power-on completion signal, namely the GPU enable signal GPU_BASE_PWRGD. If the mainboard is notified to enter S0 (Working State) after GPU power-on is complete, the mainboard enters S0 upon receiving MB_SW_PWRGD = 1, exiting sleep mode and controlling the entire system to exit low-power mode and enter full-function operation mode. In this embodiment, the mainboard only needs the switchboard to be ready before entering S0, not after all devices are powered on. If the mainboard enters S0 only after all devices are powered on, the CPU_CLK signal issued by the mainboard will be later than the GPU power-on completion signal, which may cause GPU enumeration failure.

[0050] This embodiment restructures key signal dependencies and introduces a delay mechanism. The MB_SW_PWRGD signal is independent and responds only to the switch board base ready signals, namely P1V8 and FPGA_READY. This removes the dependency on the GPU status, preventing the motherboard clock from being delayed due to waiting for the GPU to power on and complete GPU_BASE_PWR_GD. This ensures that CPU_CLK powers up ahead of the GPU to prevent the GPU module clock from lagging and causing the signal regenerator to fail to load, thus failing to meet timing specifications. SWA / B / C / D / SLOT / PEX_RESET is released after a certain delay after the fourth timing GPU_BASE_PWRGD or the fifth timing SW_CLK jumps, avoiding competition among multiple devices and overwriting the forced reset action provided by the switch firmware.

[0051] S102: In response to completing the initial reset, the central processing unit triggers a global reset.

[0052] In this embodiment, after the controller completes the initial reset of the switch and graphics processor, the central processing unit detects this completion and initiates a global reset. A global reset is a system-level event that interrupts the entire system's clock environment and broadcasts a reset command to all relevant devices, ensuring that the motherboard, switch modules, and connected devices enter a comprehensive reset cycle simultaneously. The CPU coordinates the global reset to prevent device state desynchronization. This embodiment ensures device state consistency, eliminating compatibility issues with standardized firmware and improving the reliability of initial link training.

[0053] In one embodiment, in response to triggering a global reset, the mainboard module feeds back a global reset signal to the controller of the switch module; wherein the clock environment is interrupted during the global reset.

[0054] Specifically, in response to completing the initial reset, the central processing unit triggers a global reset. At this point, the clock environment is interrupted, that is, the central processing unit clock is interrupted. CPU0 or CPU1 sends a cold reset signal coldreset to FPGA0, which is then transparently transmitted to FPGA1. FPGA1 obtains the cold reset signal and then sends it down to the PCIE Switch A / B / C / D chips and all GPU modules. In this embodiment, when the central processing unit triggers a global reset, the cascade control chain of FPGA0 and FPGA1 transparently transmits the cold reset signal to all PCIE switch chips and GPU modules, synchronously cutting off the GPU core power supply GPU_BASE_PWRGD and the switch power supply SWA / B / C / D / SLOT / PEX_RESET, eliminating the risk of residual charge and state inconsistency during the clock interruption.

[0055] S103: In response to the global reset, the controller stops supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and resumes power supply.

[0056] In this embodiment, when the CPU triggers a global reset, the controller immediately receives this global reset signal. Subsequently, the controller proactively shuts off power to the switch and GPU, effectively cutting off their power input. This power outage persists until the CPU completes the global reset. At this point, the controller responds to the clock environment recovery and resumes power, ensuring that the switch and GPU power up in a consistent sequence.

[0057] Specifically, FPGA1 obtains a cold reset signal, coldreset. Its motherboard reset signal, MB_SW_PWRGD, switches from a first level to a second level to form a global cold reset signal. MB_SW_PWRGD switches from a first low level to a second high level, indicating global cold reset activation. FPGA1 controls the cessation of power supply to the graphics processor and the switch. After the rising edge of MB_SW_PWRGD, FPGA1 controls the graphics processor's graphics processor enable signal, GPU_BASE_PWRGD, to switch from a second level to a first level to form a first timing falling edge, effectively cutting off power to the GPU core. Since a cold reset disconnects the clock, but the GPU remains powered on, causing residual state, controlling the graphics processor's graphics processor enable signal to the first level can clear residual charge. Simultaneously, the switch reset signals, SWA / B / C / D / SLOT / PEX_RESET, are controlled to switch from a second level to a first level to form a second timing falling edge. This can be achieved by using an open-drain output stage in a CPLD with a resistor pulled down to ground, forcing all switches into a reset state and clearing residual link training parameters.

[0058] S104: In response to the GPU and the switch restoring power, the CPU performs link training using the switch and the GPU.

[0059] In this embodiment, in response to the clock environment being restored, the controller controls the resumption of power supply to the graphics processor after a second preset time delay in response to obtaining a global reset signal; and in response to obtaining a global reset signal, the controller controls the resumption of power supply to the graphics processor after a third preset time delay; wherein the second preset time delay is greater than or equal to the clock interruption time delay, indicating that the global reset is the interruption time delay of the clock environment; and the third preset time delay is greater than the second preset time delay.

[0060] Specifically, in response to obtaining the coldreset signal transmitted by the mainboard, the controller triggers the entire switch board to enter the cold reset state. From the time of occurrence of the first timing falling edge of GPU_BASE_PWRGD and / or the second timing falling edge of SWA / B / C / D / SLOT / PEX_RESET or lagging behind the occurrence time, the controller controls the delayed switch reset signal for the second preset duration, switches from the first level to the second level and controls the switch reset signal, delaying the switch reset signal for the third preset duration to switch from the first level to the second level.

[0061] Among them, the clock interruption duration indicates the interruption duration of the switch reset signal clock environment when the switch reset signal is globally reset. The second preset duration is greater than or equal to the clock interruption duration to ensure that the power supply is restored only after the clock is stably rebuilt, avoiding the risk of "power supply before clock". The second preset duration can be selected as 1 second. The third preset duration is greater than the second preset duration of the switch reset signal, and the third preset duration can be selected as 1 second greater than the second preset duration. Prevent the GPU from entering link training due to unstable voltage. In this embodiment, the clock interruption duration is applied to the third preset duration delay extended by the second preset duration and the voltage regulation margin to avoid clock and power sequence deadlock in the cold reset scenario.

[0062] Furthermore, the mainboard module controls its mainboard reset signal to restore to the first level at a target time; wherein, the target time represents the time when the first timing falling edge and / or the second timing falling edge occurs, or the target time lags behind the occurrence time, or the mainboard module resets to the first level after a global reset is started.

[0063] Specifically, when a falling edge of the GPU or switch is detected, the motherboard releases the reset state, lagging behind the moment when the falling edge of the device occurs, to reserve time for capacitor discharge and avoid false triggering caused by signal rebound. This mechanism eliminates timing conflicts in the cold reset release process while maintaining the advantages of normalized firmware production through device signal priority response and delayed coordination.

[0064] In this embodiment, after the clock environment is restored and the CPU triggers a cold reset, FGPA0 transmits the coldreset signal to FGPA1, which then pulls down and then up GPU_BASE_PWRGD on the GPU and powers the GPU off and on again. This prevents the CPU output from interrupting the CPU clock during a cold reset. This also causes the GPU enable signal clock to be disconnected, resulting in the clock being disconnected but the GPU not being powered off, causing the GPU to lose power because the clock remains stable before powering on. Therefore, when the CPU triggers a cold reset, the GPU is powered off and then on again, and SWA / B / C / D / SLOT / PEX_RESET is also pulled down to ensure that the GPU is stable before being released. FPGA1 also uses a dynamic delay algorithm to achieve hierarchical recovery of device power supply according to the clock's advanced power supply specifications. The switch power supply is further delayed to avoid surge interference. This collaborative mechanism improves the GPU detection rate after a cold reset and reduces the conflict rate in multi-switch training.

[0065] In this embodiment, after the switch module is powered on, the controller immediately controls the switch and GPU to perform an initial reset, allowing them to enter the reset state before the CPU. This timing design avoids the risk of secondary link training caused by traditional normalized firmware. The CPU then triggers a global reset, and the controller simultaneously cuts off power to the switch and GPU to match the CPU's reset cycle, ensuring device status synchronization during clock environment interruptions. After the global reset is completed, power is restored, and device status is reconstructed, the CPU performs unified link training on all preset devices, maximizing the success rate of the first link training. This solves the problems of card loss and bandwidth reduction caused by firmware normalization, while supporting the deployment of a single version of firmware across multiple switches, reducing production and maintenance costs and improving hardware layout flexibility.

[0066] In one embodiment, multiple switch reset signal switches connected to a switch reset signal controller are normalized to form a normalized port; the switch reset signal controls the multiple switch reset signal switches to reset, including the controller sending a reset signal to the switch reset signal normalization port; and the multiple switch reset signal switches connected to the switch reset signal normalization port obtain the switch reset signal via the switch reset signal normalization port for reset.

[0067] In this embodiment, to improve production line efficiency, PCIE switches are normalized. This means that even if multiple PCIE switches have different upstream and downstream ports, they are unified into a single firmware (FW), forming a normalized port. Upstream and downstream ports are adaptively assigned based on the physical pin configurations of the different switch chips. When the switch is powered on, the physical pin levels are read to solidify the port roles. This allows a single firmware to adapt to any port configuration, eliminating the need to burn multiple firmware versions.

[0068] In one embodiment, Figure 6 As shown, Figure 6 A schematic diagram of the structure of a system timing management system provided in an embodiment of the present application.

[0069] The system timing management system includes a mainboard module 10 including a central processing unit 11 , a switch module 20 including a controller 21 and a plurality of switches 22 connected to a switch reset signal controller, and a graphics processor 23 .

[0070] The controller is used to control the switch and graphics processor to perform an initial reset in response to the switch module obtaining a power supply signal; in response to the central processing unit triggering a global reset, it controls the cessation of power supply to the switch and graphics processor until the central processing unit completes the global reset control and resumes power supply.

[0071] The central processing unit is configured to trigger a global reset in response to completion of the initial reset; and perform link training on a preset device connected to the switch in response to power restoration of the graphics processor and the switch.

[0072] In one embodiment, Figure 7 As shown, Figure 7 The schematic diagram of the structure of a system timing management device provided in an embodiment of the present application is as follows: The system timing management device may include a first reset module 31 , a second reset module 32 , a power supply module 33 and a link training module 34 .

[0073] The first reset module 31 is configured to control the switch and the graphics processor to perform an initial reset in response to the switch module obtaining a power supply signal.

[0074] The second reset module 32 is configured to trigger a global reset by the central processing unit in response to completion of the initial reset.

[0075] The power supply module 33 is configured to, in response to a global reset, control the controller to stop supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and resumes power supply.

[0076] The link training module 34 is configured to cause the central processing unit to perform link training on a preset device connected to the switch in response to the graphics processor and the switch restoring power.

[0077] Each module in the above-mentioned system timing management device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in an electronic device in the form of hardware, or can be stored in a memory in the electronic device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0078] An embodiment of the present application further provides an electronic device, including a memory for storing a computer program; and a processor for executing the computer program to perform at least the following steps: In response to the switch module obtaining a power supply signal, the controller controls the switch and the graphics processor to perform an initial reset; in response to completing the initial reset, the central processing unit triggers a global reset; in response to the global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and restores power; in response to the graphics processor and the switch restoring power, the central processing unit uses the switch and the graphics processor to perform link training.

[0079] In one embodiment, the electronic device may be a server, and its internal structure diagram may be as follows: Figure 8As shown. The electronic device includes a processor, memory, network interface and database connected via a system bus. The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the electronic device is used to store software management data. The network interface of the electronic device is used to communicate with an external terminal via a network connection.

[0080] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the electronic device to which the solution of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0081] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the computer program can at least perform the following steps: In response to the switch module obtaining a power supply signal, the controller controls the switch and the graphics processor to perform an initial reset; in response to completing the initial reset, the central processing unit triggers a global reset; in response to the global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and restores power; in response to the graphics processor and the switch restoring power, the central processing unit uses the switch and the graphics processor to perform link training.

[0082] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0083] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it can perform at least the following steps: In response to the switch module obtaining a power supply signal, the controller controls the switch and the graphics processor to perform an initial reset; in response to completing the initial reset, the central processing unit triggers a global reset; in response to the global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and restores power; in response to the graphics processor and the switch restoring power, the central processing unit uses the switch and the graphics processor to perform link training.

[0084] Professionals will understand that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the various embodiments provided herein may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM).

[0085] It can be further appreciated that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0086] The above is a detailed introduction to a system timing management method, system, and electronic device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A system timing management method, characterized in that: The system includes a mainboard module and a switch module connected to the mainboard module; the mainboard module includes a central processing unit; The switch module includes a controller and a plurality of switches and a graphics processor connected to the controller; The timing management method includes: In response to the switch module acquiring a power supply signal, the controller controls the switch and the graphics processor to perform an initial reset; In response to completing the initial reset, the central processing unit triggers a global reset; In response to the global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and resumes power supply; In response to the graphics processor and the switch restoring power, the central processing unit performs link training with the switch and the graphics processor.

2. The system timing management method according to claim 1, characterized in that: The controller controlling the switch and the graphics processor to perform initial reset includes: The controller obtains the power supply signal to perform power-on initialization, and in response to completing the initialization, Sending a first feedback signal to the mainboard module; The mainboard module obtains the first feedback signal and builds a clock environment for coordinating the operation of the switch; In response to the clock environment being constructed, the controller controls the graphics processor to initialize and controls the plurality of switches to reset.

3. The system timing management method according to claim 1, wherein: The controller controlling the graphics processor to initialize and the plurality of switches to reset comprises: The controller sends an initialization signal to the graphics processor; The graphics processor obtains the initialization signal to perform initialization; In response to the graphics processor completing initialization, the controller sends a reset signal to the switch; The switch receives the reset signal and performs reset.

4. The system timing management method according to claim 3, characterized in that: After the graphics processor obtains the initialization signal and performs initialization, the further step includes: The graphics processor generates a graphics processor enable signal in response to the graphics processor completing initialization; The controller obtains the graphics processor enable signal and determines that the graphics processor has completed initialization after a first preset delay.

5. The system timing management method according to claim 4, characterized in that: The switch module includes a power module; The timing management method includes: In response to obtaining input power, the power module switches its power signal from a first level to a second level to form a first timing rising edge and the power signal; The controller performs power-on initialization in response to the first timing rising edge and the power supply signal. In response to the completion of the controller initialization, the basic preparation signal thereof switches from the first level to the second level to form a second timing rising edge; The controller controls the switching of its basic power supply signal from the first level to the second level in response to the first timing rising edge and the second timing rising edge, so as to form a third timing rising edge and a first feedback signal; The mainboard module generates a periodic clock timing signal in response to the third timing rising edge and the first feedback signal to form a clock environment; In response to the clock timing signal, the controller controls the graphics processor to initialize, causing the graphics power signal of the graphics processor to switch from a first level to a second level to form a fourth timing rising edge and a graphics processor enable signal; the controller controls the switch clock signal to switch from a first level to a second level to form a fifth timing rising edge; In response to the fourth timing rising edge and / or the fifth timing rising edge being formed for a duration reaching the first preset duration, the controller controls the switch reset signal to switch from the first level to the second level to form a sixth timing rising edge and the switch reset signal.

6. The system timing management method according to claim 1, characterized in that: The process of restoring power supply until the central processing unit completes global reset control includes: In response to triggering a global reset, the mainboard module feeds back a global reset signal to the controller of the switch module; wherein the clock environment is interrupted during the global reset; In response to obtaining the global reset signal, the controller controls the restoration of power supply to the graphics processor after a second preset time delay; In response to obtaining the global reset signal, the controller controls the restoration of power supply to the graphics processor after a delay of a third preset time period; Among them, the second preset duration is greater than or equal to the clock interruption duration, and the clock interruption duration represents the interruption duration of the clock environment during the global reset; and the third preset duration is greater than the second preset duration.

7. The system timing management method according to claim 6, characterized in that: After the controller controls the graphics processor to initialize and controls the plurality of switches to reset, the controller further includes: In response to triggering a global reset, the motherboard module switches a motherboard reset signal from a first level to a second level to form the global reset signal; The controller obtains the global reset signal, controls the graphics processor enable signal of the graphics processor to switch from the second level to the first level to form a first timing falling edge, and controls the switch reset signal to switch from the second level to the first level to form a second timing falling edge; The mainboard module controls its mainboard reset signal to restore to the first level at a target time; wherein the target time represents the time when the first timing falling edge and / or the second timing falling edge occurs, or the target time lags behind the occurrence time, or the mainboard module resets to the first level after a global reset is initiated; The controller delays the second preset time period from the occurrence moment to control the graphics processor enable signal to switch from the first level to the second level; The controller delays the third preset time period from the occurrence moment to control the switch reset signal to switch from the first level to the second level.

8. The system timing management method according to claim 1, characterized in that: Normalizing the switch ports of the plurality of switches connected to the controller to form a normalized port; and controlling the plurality of switches to reset includes: The controller sends a reset signal to the normalization port; The multiple switches connected to the normalization port obtain the reset signal through the normalization port and are reset.

9. A system timing management system, characterized in that: The system timing management system includes: Motherboard module, including central processing unit; A switch module, comprising a controller, a power module connected to the controller, multiple switches, and a graphics processor; The controller is configured to control the switch and the graphics processor to perform an initial reset in response to the switch module acquiring a power supply signal; and in response to the central processing unit triggering a global reset, control the switch and the graphics processor to stop supplying power until the central processing unit completes the global reset control and resumes power supply; The central processing unit is configured to trigger a global reset in response to completion of the initial reset; and perform link training on a preset device connected to the switch in response to power being restored to the graphics processor and the switch.

10. An electronic device, characterized in that: The electronic device comprises: memory for storing computer programs; A processor, configured to implement the steps of the system timing management method according to any one of claims 1 to 8 when executing the computer program.

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