Command processing method and device, electronic equipment and storage medium

Abstract

The invention discloses a command processing method and device, electronic equipment and a storage medium, and relates to the technical field of data storage, the command processing method comprises the following steps: dividing a write command into a plurality of sub-write commands based on an initial logic address and a logic address length of the write command issued by a host, and sending the plurality of sub-write commands to a target central processing unit core corresponding to the target partition for processing according to the corresponding target partition, and returning sub-write command completion information to the hardware acceleration unit after the target central processing unit core processes the sub-write commands, and the hardware acceleration unit feeds back the completion information of the write command to the host under the condition that the sub-write command completion information of the plurality of sub-write commands corresponding to the write command is received, so that the problem that different central processing unit cores need to exchange messages when cross-partition write commands are processed in related technologies is solved; therefore, the technical problem that the write command processing time is long and the write performance is reduced in the prior art is solved, and the technical effect of improving the write performance is achieved.

Description

Technical Field

[0001] The present application relates to the field of data storage technology, and in particular to a command processing method, device, electronic device, and storage medium. Background Art

[0002] With the advancement of solid-state drive (SSD) technology, its application scope continues to expand. In particular, its advantages in high-speed reading and writing, low noise, low power consumption and shock resistance have made it a new favorite in the data storage market. In order to meet the growing storage demand, the number and capacity of the central processing unit (CPU) of the solid-state drive are also increasing. The Flash Translation Layer (FTL) is responsible for mapping the logical address of the host to the physical address of the flash memory and transferring data from the host to the NAND storage during the write operation. However, in large-capacity solid-state drives, due to the increase in the number of physical addresses (Physical Block Address, PBA), the size of the mapping table also increases, resulting in a waste of resources. In order to solve this problem, the related technology adopts the method of partitioning NAND (PART) to avoid resource waste.

[0003] However, in a multi-core processor, different CPU cores are responsible for managing different partitions. This means that when processing a write command, if the logical address of the write command crosses partitions, different CPU cores need to exchange messages to complete the write command, resulting in longer write command processing time and reduced write performance. Summary of the Invention

[0004] The present application provides a command processing method, device, electronic device and storage medium to at least solve the problem in the related art that when processing a write command, different CPU cores need to interact with each other, resulting in a long write command processing time and reduced write performance.

[0005] A first aspect of the present application provides a command processing method, applied to a hardware acceleration unit, comprising:

[0006] Receive the write command sent by the host;

[0007] Parse the write command to obtain the starting logical address and logical address length of the write command;

[0008] Based on the starting logical address and the logical address length of the write command, the write command is divided into multiple sub-write commands, wherein one sub-write command corresponds to one partition;

[0009] For any sub-write command, based on the target partition corresponding to the sub-write command, determine the target central processing unit core corresponding to the sub-write command, send the sub-write command to the corresponding target central processing unit core, so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns sub-write command completion information after the processing is completed;

[0010] When sub-write command completion information of multiple sub-write commands corresponding to the write command is received, the completion information of the write command is fed back to the host.

[0011] A second aspect of the present application provides a command processing method, applied to a central processing unit core, comprising:

[0012] Receiving a sub-write command sent by a hardware acceleration unit, wherein the hardware acceleration unit receives the write command sent by the host, parses the write command, obtains a starting logical address and a logical address length of the write command, divides the write command into multiple sub-write commands based on the starting logical address and the logical address length of the write command, wherein each sub-write command corresponds to a partition, and for any sub-write command, determines a target central processing unit core corresponding to the sub-write command based on a target partition corresponding to the sub-write command, and sends the sub-write command to the corresponding target central processing unit core;

[0013] The sub-write command is processed and sub-write command completion information is returned after the processing is completed, so that the hardware acceleration unit feeds back the completion information of the write command to the host when receiving the sub-write command completion information of multiple sub-write commands corresponding to the write command.

[0014] A third aspect of the present application provides a command processing device, applied to a hardware acceleration unit, comprising:

[0015] A first receiving module, configured to receive a write command sent by a host;

[0016] A command parsing module is used to parse the write command and obtain the starting logical address and logical address length of the write command;

[0017] a partitioning module, configured to partition a write command into a plurality of sub-write commands based on a starting logical address and a logical address length of the write command, wherein one sub-write command corresponds to one partition;

[0018] a determination module configured to determine, for any sub-write command, a target central processing unit core corresponding to the sub-write command based on a target partition corresponding to the sub-write command, send the sub-write command to the corresponding target central processing unit core, so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns sub-write command completion information after the processing is completed;

[0019] The feedback module is configured to feed back completion information of the write command to the host upon receiving sub-write command completion information of multiple sub-write commands corresponding to the write command.

[0020] A fourth aspect of the present application provides a command processing device, applied to a central processing unit core, comprising:

[0021] a second receiving module, configured to receive a sub-write command sent by the hardware acceleration unit, wherein the hardware acceleration unit receives the write command sent by the host, parses the write command, obtains a starting logical address and a logical address length of the write command, and divides the write command into multiple sub-write commands based on the starting logical address and the logical address length of the write command, wherein each sub-write command corresponds to one partition, and for any sub-write command, determines a target central processing unit core corresponding to the sub-write command based on a target partition corresponding to the sub-write command, and sends the sub-write command to the corresponding target central processing unit core;

[0022] The return module is used to process the sub-write command and return the sub-write command completion information after the processing is completed, so that the hardware acceleration unit can feedback the completion information of the write command to the host when it receives the sub-write command completion information of multiple sub-write commands corresponding to the write command.

[0023] In a fifth aspect, the present application provides an electronic device comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the command processing methods of the first aspect or any one of the command processing methods of the second aspect when executing the computer program.

[0024] In a sixth aspect, the present application provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any one of the command processing methods in the first aspect or the steps of any one of the command processing methods in the second aspect are implemented.

[0025] In a seventh aspect, the present application provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of any one of the command processing methods in the first aspect or the steps of any one of the command processing methods in the second aspect.

[0026] Through the present application, a write command sent by a host is received; the write command is parsed to obtain the starting logical address and logical address length of the write command; based on the starting logical address and logical address length of the write command, the write command is divided into multiple sub-write commands, one sub-write command corresponding to one partition; for any sub-write command, based on the target partition corresponding to the sub-write command, the target central processing unit core corresponding to the sub-write command is determined, and the sub-write command is sent to the corresponding target central processing unit core, so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns the sub-write command completion information after the processing is completed; when the sub-write command completion information of multiple sub-write commands corresponding to the write command is received, the completion information of the write command is fed back to the host side. When processing the write command, there is no need for interaction between different central processing unit cores. Therefore, the technical problem of the need for interaction between different central processing unit cores when processing the write command in the related art, which results in a long write command processing time and reduced write performance, can be solved, thereby achieving the technical effect of reducing the processing time of the write command and improving the write performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 A flowchart of processing a write command in the related art;

[0029] Figure 2 A schematic diagram of the structure of a command processing system provided in an embodiment of the present application;

[0030] Figure 3 A flowchart of a command processing method provided in an embodiment of the present application;

[0031] Figure 4 A flowchart of dividing a write command into multiple sub-write commands provided in an embodiment of the present application;

[0032] Figure 5 A flowchart for determining whether a write command is completed provided in an embodiment of the present application;

[0033] Figure 6 A flowchart of another command processing method provided in an embodiment of the present application;

[0034] Figure 7 A flowchart of another command processing method provided in an embodiment of the present application;

[0035] Figure 8 A flowchart of another command processing method provided in an embodiment of the present application;

[0036] Figure 9 A schematic diagram of the structure of the hardware acceleration unit provided in an embodiment of the present application;

[0037] Figure 10 A schematic diagram of the structure of a command processing device provided in an embodiment of the present application;

[0038] Figure 11 A schematic diagram of the structure of another command processing device provided in an embodiment of the present application;

[0039] Figure 12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0042] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0043] With the continuous advancement of computer technology, the application scope of solid-state drives (SSDs) continues to expand. Their advantages in high-speed read and write speeds, low noise, low power consumption, and shock resistance have made them a new favorite in the data storage market. To meet the ever-increasing storage demand, the number of CPUs and capacity of SSDs are also increasing, from one to multiple, and from standard capacities of 4 terabytes (TB or T) to 8TB, to large capacities of 16TB and 32TB.

[0044] The FTL in an SSD is responsible for mapping host logical blocks (LBAs) to flash physical blocks (PBAs), thereby enabling host read and write operations to the SSD. When the host initiates a write operation, the FTL maps each logical address provided by the host to a corresponding NAND physical address. Once the mapping is complete, the FTL records this mapping in a mapping table. Finally, the FTL is responsible for moving the host data to the corresponding physical address in the NAND flash memory for storage. When the host initiates a read operation, the FTL first reads the mapping table and searches for the physical address corresponding to the logical address provided by the host. Once the physical address is found, the FTL moves the data stored at that physical address in the NAND flash memory to the host. Physical address management is essentially the management of the mapping table, which records the correspondence between logical and physical addresses. The way the mapping table records PBAs determines how efficiently the FTL performs address mapping.

[0045] In a normal-capacity SSD, the mapping table uses a fine-grained "one-to-one" mapping mode, where one LBA corresponds to one PBA. Each PBA can store 4KB of data, and its address space can be fully represented by only 32 bits of binary. However, in large-capacity SSDs (such as 16TB and 32TB), due to the increase in the number of logical units (LUNs) and data blocks, 32 bits are insufficient to represent all PBAs, and one or two more bits are needed to fully represent them. Since computer systems generally follow the 32-bit alignment principle, each PBA requires 64 bits to represent (the portion less than 64 bits is padded with zeros), which doubles the size of the mapping table. However, the actual utilization rate of the high address bits is extremely low, resulting in a large amount of wasted storage space.

[0046] To address this issue, large-capacity solid-state drives use a partition management mechanism: NAND flash memory is divided into multiple logical areas (e.g., 16TB drives have two parts, 32TB drives have four parts), with each part independently allocated address space. By extracting the address segment corresponding to the partition from the LBA, the logical address is mapped to the physical block within the specific part, allowing the PBA of each part to be represented independently using 32 bits. This approach avoids the resource waste caused by global address expansion and improves the parallel processing efficiency of multi-core processors through partition isolation.

[0047] However, in a multi-core processor, different CPU cores are responsible for managing different partitions. This means that when processing a write command, if the logical address of the write command crosses partitions, different CPU cores need to exchange messages to complete the write command, resulting in longer write command processing time and reduced write performance. In addition, the interaction process between multiple CPU cores is cumbersome, performance fluctuates greatly, and is unstable.

[0048] Specifically, Figure 1 This is a flowchart of processing a write command in the related art, such as Figure 1 As shown, the process includes:

[0049] When a CPU core in the SSD receives a write command (hereinafter referred to as the original core), it sends the write command to its FTL layer. The FTL layer receives the write command and parses all the LBAs in the write command to determine the partitions to which they correspond.

[0050] The original core determines whether all LBAs in the write command correspond to partitions that the original core manages. If so, the original core processes the write command and performs table modification, i.e., modifies the mapping table. If not, the original core transfers the write command to the CPU core responsible for managing the partition corresponding to each LBA in the write command, enabling multiple CPU cores to collaboratively process the LBAs in the write command, converting the LBAs to PBAs, and performing the actual data write operation.

[0051] After the CPU core that collaboratively processes the LBA in the write command completes processing the portion of LBAs it is responsible for, it notifies the original core that the process is complete. After the original core receives completion messages from all CPU cores that collaboratively process the write command, it modifies the mapping table based on the LBA in the write command and its corresponding PBA, releases the resources occupied by the original core in processing the write command, and notifies all other CPU cores that collaboratively process the write command to release resources. After all other CPU cores that collaboratively process the write command release resources, they notify the original core that the release is complete. After the original core receives the resource release completion information from all other CPU cores that collaboratively process the write command and completes the resource release itself, it notifies the host that the write command is complete.

[0052] In response to the above problems, an embodiment of the present application provides a command processing method, device, electronic device and storage medium, which is applied to a hardware acceleration unit, including receiving a write command issued by a host; parsing the write command to obtain the starting logical address and logical address length of the write command; dividing the write command into multiple sub-write commands based on the starting logical address and logical address length of the write command, and one sub-write command corresponds to one partition; for any sub-write command, based on the target partition corresponding to the sub-write command, determining the target central processing unit core corresponding to the sub-write command, and sending the sub-write command to the corresponding target central processing unit core, so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns sub-write command completion information after the processing is completed; when the sub-write command completion information of multiple sub-write commands corresponding to the write command is received, the completion information of the write command is fed back to the host. The method provided by the above scheme utilizes a hardware acceleration unit to receive write commands issued by the host and parse the write commands. After the parsing is completed, the write commands are divided into multiple sub-write commands based on the starting logical address and logical address length of the write commands. One sub-write command corresponds to one partition, and the sub-write command is sent to the central processing unit core corresponding to the corresponding partition for processing. After all sub-write commands are processed, the host is notified to complete the write command, thereby reducing the process of interactive messages between different central processing unit cores when processing a cross-partition write command, thereby reducing the processing time of the write command and improving the write performance.

[0053] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the command processing method depends, the specific application environment architecture or specific hardware architecture is described here.

[0054] The command processing method, device, electronic device and storage medium provided in the embodiments of the present application are suitable for processing write commands in a multi-core processor environment. Figure 2As shown, this is a structural diagram of the command processing system on which the present application is based, and the command processing system includes a host and a solid-state drive, wherein the host end is used to send a write command to the solid-state drive, the solid-state drive receives the write command, and sends the write command to the hardware acceleration unit therein, the hardware acceleration unit parses the write command to obtain the starting logical address and logical address length of the write command; based on the starting logical address and logical address length of the write command, the write command is divided into multiple sub-write commands, wherein one sub-write command corresponds to one partition; for any sub-write command, based on the target partition corresponding to the sub-write command, the target central processing unit core corresponding to the sub-write command is determined, and the sub-write command is sent to the corresponding target central processing unit core, so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns the sub-write command completion information after the processing is completed; when the sub-write command completion information of multiple sub-write commands corresponding to the write command is received, the completion information of the write command is fed back to the host.

[0055] The embodiment of the present application provides a command processing method, which is applied to a hardware acceleration unit. Figure 3 A flowchart of a command processing method provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the process includes:

[0056] Step S301: receiving a write command sent by a host.

[0057] It is understandable that the host sends a write command to the solid-state drive, and the solid-state drive sends the write command to the hardware acceleration unit therein, that is, the hardware acceleration unit receives the write command sent by the host.

[0058] Step S302: parse the write command to obtain the starting logical address and logical address length of the write command.

[0059] In a solid-state drive (SSD), the number of partitions is determined by the SSD's capacity. Generally, a 16TB SSD requires two partitions, and a 32TB SSD requires four partitions. The Non-Volatile Memory Express (NVMe) protocol allows the device to specify the maximum number of LBAs that can be processed in each NVMe read or write command within the device's identifier controller. This information is represented by the Maximum Data Transfer Size (MDTS) field. The maximum number of LBAs that the FTL can handle when processing a write command is 2 raised to the MDTS power. If the MDTS is 5, the FTL can process a maximum of 32 LBAs per write command. Therefore, every 32 LBAs are divided into a Partition (PART). For example, LBAs 0-31 correspond to Part 0, LBAs 32-63 correspond to Part 1, LBAs 64-95 correspond to Part 0, and LBAs 96-127 correspond to Part 1, and so on.

[0060] After receiving the write command sent by the host, the write command is parsed to obtain the starting logical address and the logical address length of the write command, that is, the number of logical addresses to be written corresponding to the write command.

[0061] Step S303 : dividing the write command into multiple sub-write commands based on the start logical address and the logical address length of the write command, wherein one sub-write command corresponds to one partition.

[0062] Among them, all logical addresses corresponding to the write command are determined based on the starting logical address and logical address length of the write command. All logical addresses corresponding to the write command are divided into multiple logical address segments according to the order and logical address partition. If the starting logical address of the write command is 20 and the logical address length of the write command, that is, the number of logical addresses included, is 128, then the logical addresses included in the write command can be divided into five small segments: 20-31, 32-63, 64-95, 96-127, and 128-147 according to the order and logical address partition.

[0063] Each logical address segment divided according to the order and logical address partition is repackaged into a sub-write command to obtain multiple sub-write commands corresponding to the write command.

[0064] Step S304: For any sub-write command, based on the target partition corresponding to the sub-write command, determine the target central processing unit core corresponding to the sub-write command, and send the sub-write command to the corresponding target central processing unit core so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns sub-write command completion information after the processing is completed.

[0065] Among them, the target central processing unit core processes the sub-write command including resource allocation and table modification operations. Resource allocation is to assign a corresponding physical address to each logical address in the sub-write command. The table modification operation is to write the mapping relationship between the logical address and its corresponding physical address into the mapping table after writing the data to be written into the NAND according to the physical address assigned to each logical address.

[0066] It is understandable that multiple sub-write commands can be processed in parallel, that is, the target partitions corresponding to the multiple sub-write commands are determined in parallel, the CPU cores corresponding to the multiple sub-write commands are determined, and the multiple sub-write commands are sent to the corresponding CPU cores for processing.

[0067] It should be noted that different central processing unit cores are responsible for managing different partitions, which are specifically pre-set by technical personnel and are not specifically limited here.

[0068] Step S305 : When receiving sub-write command completion information of multiple sub-write commands corresponding to the write command, the completion information of the write command is fed back to the host.

[0069] The command processing method provided in the embodiment of the present application utilizes a hardware acceleration unit to receive a write command issued by a host, parses the write command, and after the parsing is completed, divides the write command into multiple sub-write commands based on the starting logical address and logical address length of the write command, with one sub-write command corresponding to one partition, and sends the sub-write command to the central processing unit core corresponding to the corresponding partition for processing. After all sub-write commands have been processed, the host is notified to complete the write command, thereby reducing the process of interactive messages between different central processing unit cores when processing a cross-partition write command, thereby reducing the processing time of the write command and improving the write performance.

[0070] In some optional implementations, before determining, for any sub-write command, the target central processing unit core corresponding to the sub-write command based on the target partition corresponding to the sub-write command, the command processing method further includes:

[0071] Step a1: Set a unique write command tag for the write command and record it.

[0072] Step a2: Set a unique sub-write command tag for each of the multiple sub-write commands corresponding to the write command, and record the sub-write command tag under the write command tag.

[0073] Figure 4 The flowchart of dividing a write command into multiple sub-write commands provided in the embodiment of the present application is as follows: Figure 4As shown, the process includes receiving a write command issued by the host, parsing the write command, splitting the write command and labeling it, and sending a sub-write command to the FTL of the CPU core corresponding to each sub-write command so that the corresponding CPU core processes the sub-write command. Among them, parsing the write command corresponds to the aforementioned step S302, which will not be repeated here. Splitting the write command and labeling it corresponds to the aforementioned step S303, step a1, and step a2, which will not be repeated here. Sending a sub-write command to the FTL of the CPU core corresponding to each sub-write command so that the corresponding CPU core processes the sub-write command corresponds to the aforementioned step S304, which will not be repeated here.

[0074] The command processing method provided in the embodiments of the present application clearly distinguishes different write operations and their subtasks by assigning a unique tag to each write command and its corresponding sub-write command. This mechanism makes command management clearer and facilitates subsequent tracking, debugging, and maintenance. Recording sub-write command tags under the write command tag establishes a parent-child hierarchical relationship, which can intuitively reflect the sub-write commands contained in a write command. This structured design helps understand the command execution process.

[0075] In some optional implementations, the above step S305 includes:

[0076] Step b1: every time a sub-write command completion message is received, the target sub-write command tag in the sub-write command completion message is obtained.

[0077] Among them, after the central processing unit core processes a sub-write command, it sends the sub-write command completion information of the sub-write command to the hardware acceleration unit. Every time the hardware acceleration unit receives a sub-write command completion information, it obtains the target sub-write command tag in the sub-write command completion information.

[0078] Step b2: determining a target write command tag corresponding to the target sub-write command tag based on the target sub-write command tag.

[0079] Step b3: Based on the target write command tag, update the number of completed sub-write commands of the target write command corresponding to the target write command tag.

[0080] The number of completed sub-write commands of the target write command corresponding to the target write command tag is updated, that is, the number of completed sub-write commands of the target write command is increased by 1.

[0081] Step b4, when the number of completed sub-write commands of the target write command is consistent with the number of sub-write commands divided by the target write command, determine that sub-write command completion information of multiple sub-write commands corresponding to the target write command is received, and feed back the completion information of the target write command to the host end.

[0082] The number of completed sub-write commands of the target write command is consistent with the number of sub-write commands divided by the target write command, indicating that all sub-write commands corresponding to the target write command are completed. The completion information of the target write command is sent to the host, and a signal for completing the target write command is output, indicating that the target write command is completed.

[0083] Figure 5 The flowchart for determining whether a write command is completed is provided in the embodiment of the present application. Figure 5 As shown, the process includes: inputting a sub-write command, wherein, after any CPU core processes a sub-write command, it sends the sub-write command completion information to the hardware acceleration unit. Inputting the sub-write command means that the hardware acceleration unit receives the sub-write command completion information input by any CPU core.

[0084] The original write command is found, that is, the hardware acceleration unit obtains the target sub-write command tag in the input sub-write command completion information; based on the target sub-write command tag, the target write command tag corresponding to the target sub-write command tag is determined.

[0085] The completion count is recorded, that is, based on the target write command tag, the number of completed sub-write commands of the target write command corresponding to the target write command tag is updated.

[0086] Check whether all sub-write commands are completed. If all sub-write commands are completed, output a write command completion message to the host. If all sub-write commands are not completed, return to the step of executing the input sub-write command.

[0087] The command processing method provided in the embodiment of the present application realizes efficient tracking, dynamic updating and reliable feedback of the completion status of the write command and its sub-write commands through the above steps b1 to b4, thereby improving the performance and reliability of the storage system.

[0088] In some optional implementations, the command processing method further includes:

[0089] Step c1: for any sub-write command, if the sub-write command completion information is not received after a preset time period after the sub-write command is sent to the corresponding target CPU core, the step of sending the sub-write command to the corresponding target CPU core is re-executed.

[0090] It is understandable that before re-executing the step of sending the sub-write command to the corresponding target CPU core, it is necessary to pause the previous processing flow of the sub-write command by the target CPU core and roll back the state of the target CPU core to the state before processing the sub-write command.

[0091] The preset duration is set by technical personnel and is not specifically limited here.

[0092] In step c2, if the number of times the sub-write command is sent to the corresponding target CPU core exceeds a preset threshold and the sub-write command completion information of the sub-write command is still not received, it is determined that the sub-write command processing has failed and a failure alarm is issued.

[0093] The preset number threshold is set by technical personnel and is not specifically limited here.

[0094] The command processing method provided in the embodiments of the present application resends a sub-write command if no sub-write command completion message is received within a preset time period after the sub-write command is sent to the target CPU core. This ensures that even if the target CPU core experiences a temporary failure or communication interruption, the system still has the opportunity to re-execute the command, thereby improving system reliability. If the number of times the sub-write command is resent exceeds a preset threshold and no sub-write command completion message is received, the sub-write command processing is determined to have failed and a failure alarm is triggered. This mechanism prevents resource waste caused by infinite retries and avoids possible deadlock issues.

[0095] The embodiment of the present application provides a command processing method, which is applied to a central processing unit core. Figure 6 A flowchart of a command processing method provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the process includes:

[0096] Step S601, receiving a sub-write command sent by a hardware acceleration unit, wherein the hardware acceleration unit receives a write command sent by a host, parses the write command, obtains a starting logical address and a logical address length of the write command, and divides the write command into multiple sub-write commands based on the starting logical address and the logical address length of the write command, wherein one sub-write command corresponds to one partition, and for any sub-write command, determines a target central processing unit core corresponding to the sub-write command based on a target partition corresponding to the sub-write command, and sends the sub-write command to the corresponding target central processing unit core.

[0097] Step S602 , processing the sub-write command and returning sub-write command completion information after the processing is completed, so that the hardware acceleration unit feeds back the write command completion information to the host when receiving the sub-write command completion information of multiple sub-write commands corresponding to the write command.

[0098] Please refer to the description of the aforementioned steps S301 to S305 for details, which will not be repeated here.

[0099] The command processing method provided in the embodiment of the present application utilizes a hardware acceleration unit to receive a write command issued by a host, parses the write command, and after the parsing is completed, divides the write command into multiple sub-write commands based on the starting logical address and logical address length of the write command, with one sub-write command corresponding to one partition, and sends the sub-write command to the central processing unit core corresponding to the corresponding partition for processing. After all sub-write commands have been processed, the host is notified to complete the write command, thereby reducing the process of interactive messages between different central processing unit cores when processing a cross-partition write command, thereby reducing the processing time of the write command and improving the write performance.

[0100] The embodiment of the present application provides a command processing method, which is applied to a central processing unit core. Figure 7 A flowchart of a command processing method provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the process includes:

[0101] Step S701, receiving a sub-write command sent by a hardware acceleration unit, wherein the hardware acceleration unit receives a write command sent by a host, parses the write command, obtains a starting logical address and a logical address length of the write command, and divides the write command into multiple sub-write commands based on the starting logical address and the logical address length of the write command, wherein one sub-write command corresponds to one partition, and for any sub-write command, determines a target central processing unit core corresponding to the sub-write command based on a target partition corresponding to the sub-write command, and sends the sub-write command to the corresponding target central processing unit core.

[0102] Step S702 , processing the sub-write command and returning sub-write command completion information after the processing is completed, so that the hardware acceleration unit feeds back the write command completion information to the host when receiving the sub-write command completion information of multiple sub-write commands corresponding to the write command.

[0103] Specifically, the above step S702 includes:

[0104] Step S7021: Based on the sub-write command, determine the logical address in the sub-write command.

[0105] Step S7022: assign corresponding physical addresses to the logical addresses in the sub-write command, wherein each logical address corresponds to a unique physical address.

[0106] Step S7023, write the mapping relationship between the logical address in the sub-write command and the physical address allocated to the logical address in the sub-write command into the mapping table, and based on the logical address in the sub-write command, write the data to be written corresponding to the sub-write command into the physical address corresponding to the logical address in the sub-write command.

[0107] The command processing method provided in the embodiment of the present application uniquely maps the logical address in the sub-write command with the physical address and records the mapping relationship in a mapping table. This design not only improves the accuracy and reliability of data storage, but also simplifies the data writing process.

[0108] In some optional implementations, step S7022 includes:

[0109] Step d1: For any logical address in the sub-write command, determine whether there is an idle physical block in the partition managed by the CPU core based on the idle block management table of the flash translation layer. The partition managed by the CPU core is the partition managed by the CPU core.

[0110] Step d2: If there are idle physical blocks in the partition that the CPU core is responsible for, the number of erase and write times of the idle physical blocks is obtained.

[0111] Step d3: Based on the erasure counts of the idle physical blocks, a first target physical block having the minimum erasure count is selected from the idle physical blocks.

[0112] Step d4: determining the physical address of the first target physical block as the physical address corresponding to the logical address.

[0113] Step d6: If there is no free physical block in the partition managed by the CPU core, select a second target physical block containing invalid data in a proportion exceeding a preset proportion threshold from all physical blocks corresponding to the partition managed by the CPU core.

[0114] The preset ratio threshold is set by a technician. If the ratio of invalid data exceeds the preset ratio threshold, it means that the physical block contains a lot of invalid data.

[0115] Step d7, obtaining the number of erasures and writes of the second target physical block, and based on the number of erasures and writes of the second target physical block, selecting a third target physical block with the smallest number of erasures and writes from the second target physical block.

[0116] Step d8: Migrate the valid data in the third target physical block to other physical blocks in the partition managed by the central processing unit core.

[0117] Step d9: performing an erase operation on the third target physical block, and after completing the erase operation on the third target physical block, determining the physical address of the third target physical block as the physical address corresponding to the logical address.

[0118] The command processing method provided by the embodiment of the present application, through the free block management table of the flash conversion layer, the system can quickly determine whether there are free physical blocks in the partition that the central processing unit core is responsible for. This mechanism ensures that free blocks can be used first when data is written to avoid overwriting valid data. In the case of free physical blocks, the physical address of the first target physical block with the smallest number of erases and writes is selected as the physical address corresponding to the logical address, thereby reducing the problem of storage medium aging caused by frequent erases and writes, and significantly improving the life and reliability of the storage system. When there are no free physical blocks in the partition, by screening the second target physical block containing invalid data with a ratio exceeding a preset ratio threshold, the third target physical block with the smallest number of erases and writes is further screened out from the second target physical block, the valid data therein is migrated to other physical blocks and then erased, and the physical address of the erased third target physical block is used as the physical address corresponding to the logical address. This method achieves wear leveling and extends the overall service life of the storage device.

[0119] The embodiment of the present application provides a command processing method, Figure 8 A flowchart of a command processing method provided in an embodiment of the present application is shown in FIG. Figure 8 As shown in the figure, taking a multi-core large-capacity solid-state drive with one CPU core responsible for one PART as an example, the process includes:

[0120] 1. The host sends a write command.

[0121] 2. The solid-state drive receives the write command and transmits it to the hardware acceleration unit. Figure 9 A schematic diagram of the structure of the hardware acceleration unit provided in the embodiment of the present application is shown as follows: Figure 9 As shown, the hardware acceleration unit includes a parsing module, a command sending module, a recording module, and a message return module. The parsing module is used to execute steps S301, S302, and S303 described above. The command sending module is used to execute steps a1, a2, and S304 described above. The recording module is used to record the write command tag corresponding to the write command and the sub-write command tag corresponding to the sub-write command. The message return module is used to execute step S305 described above. For details, please refer to the corresponding descriptions of the above steps and will not be repeated here.

[0122] 3. The hardware acceleration unit pre-processes the write command, where the pre-processing includes parsing and splitting the write command, recording the original write command and the number of split sub-write commands, and sending multiple sub-write commands to the central processing unit core of the corresponding partition for processing.

[0123] 4. After receiving the sub-write command, each CPU core performs resource allocation and table modification operations. After completing the sub-write command, it transmits the sub-write command completion information to the hardware acceleration unit. Among them, resource allocation is to assign a corresponding physical address to each logical address of the sub-write command. For example, the partition corresponding to a sub-write command is PART-0, and the partition corresponding to a sub-write command is PART-1. The CPU core corresponding to PART-0 processes the corresponding sub-write command and performs resource allocation and table modification operations. The CPU core corresponding to PART-1 processes the corresponding sub-write command and performs resource allocation and table modification operations.

[0124] 5. The hardware acceleration unit performs post-processing based on the sub-write command completion information. Specifically, it finds the corresponding write command based on the sub-write command tag in the sub-write command completion information, updates the number of completed sub-commands in the corresponding write command, and determines whether the number of completed sub-commands in the corresponding write command is consistent with the number of sub-write commands initially divided. If not, there are still uncompleted sub-write commands, and the hardware acceleration unit continues to wait until they are consistent. If they are consistent, the host is notified to complete the write command processing.

[0125] The command processing method provided by the embodiment of the present application utilizes a hardware acceleration unit to receive the write command of the host, parses the write command, and after the parsing is completed, the LBA of the corresponding part is divided into sub-write commands, a label is assigned to the sub-write command and the write command and recorded, and the sub-write command is sent to the corresponding CPU core for processing. In this way, each sub-write command only needs to be processed on the corresponding CPU core, and each sub-write command is passed to the hardware acceleration unit after processing. The hardware acceleration unit searches for the original write command through the label, and when all the sub-write commands of a write command are completed, the host is notified to complete the write command. For a partitionable write command, the interactive waiting process between different CPU cores is reduced, the completion speed is fast, the processing time of the write command is reduced, and the impact of the need for partitioning on the write performance is reduced. The mutual influence between different CPU cores is reduced, and the idling of the CPU core is reduced, so that the performance of large-capacity solid-state hard drives is improved and the performance is stable.

[0126] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0127] The embodiment of the present application also provides a command processing device, which is applied to a hardware acceleration unit, such as Figure 10 As shown, the command processing device includes:

[0128] The first receiving module 1001 is configured to receive a write command sent by a host.

[0129] The command parsing module 1002 is used to parse the write command and obtain the starting logical address and logical address length of the write command.

[0130] The division module 1003 is configured to divide the write command into multiple sub-write commands based on the start logical address and the logical address length of the write command, wherein one sub-write command corresponds to one partition.

[0131] The determination module 1004 is used to determine, for any sub-write command, the target central processing unit core corresponding to the sub-write command based on the target partition corresponding to the sub-write command, and send the sub-write command to the corresponding target central processing unit core so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns sub-write command completion information after the processing is completed.

[0132] The feedback module 1005 is configured to feed back completion information of the write command to the host upon receiving sub-write command completion information of multiple sub-write commands corresponding to the write command.

[0133] In some optional implementations, the command processing device further includes:

[0134] The first setting unit is configured to set a unique write command tag for the write command and record the tag.

[0135] The second setting unit is configured to set a unique sub-write command tag for each of the multiple sub-write commands corresponding to the write command, and record the sub-write command tag under the write command tag.

[0136] In some optional implementations, the feedback module 1005 includes:

[0137] The first acquiring unit is configured to acquire a target sub-write command tag in each sub-write command completion message received.

[0138] The first determining unit is configured to determine a target write command tag corresponding to the target sub-write command tag based on the target sub-write command tag.

[0139] The updating unit is configured to update, based on the target write command tag, the number of completed sub-write commands of the target write command corresponding to the target write command tag.

[0140] The second determination unit is used to determine the sub-write command completion information of multiple sub-write commands corresponding to the target write command when the number of completed sub-write commands of the target write command is consistent with the number of sub-write commands divided by the target write command, and to feed back the completion information of the target write command to the host.

[0141] For the description of the features in the embodiment corresponding to the command processing device, please refer to the relevant description of the embodiment corresponding to the command processing method, and no further details will be given here.

[0142] The embodiment of the present application also provides a command processing device, which is applied to a central processing unit core, such as Figure 11 As shown, the command processing device includes:

[0143] The second receiving module 1101 is used to receive a sub-write command sent by the hardware acceleration unit, wherein the hardware acceleration unit receives the write command sent by the host, parses the write command, obtains the starting logical address and logical address length of the write command, and divides the write command into multiple sub-write commands based on the starting logical address and logical address length of the write command, wherein one sub-write command corresponds to one partition, and for any sub-write command, based on the target partition corresponding to the sub-write command, determines the target central processing unit core corresponding to the sub-write command, and sends the sub-write command to the corresponding target central processing unit core.

[0144] Return module 1102 is used to process the sub-write command and return the sub-write command completion information after the processing is completed, so that the hardware acceleration unit can feedback the write command completion information to the host when it receives the sub-write command completion information of multiple sub-write commands corresponding to the write command.

[0145] In some optional implementations, the return module 1102 includes:

[0146] The third determining unit is configured to determine a logical address in the sub-write command based on the sub-write command.

[0147] The allocation unit is used to allocate corresponding physical addresses to the logical addresses in the sub-write command, wherein each logical address corresponds to a unique physical address.

[0148] A writing unit is used to write the mapping relationship between the logical address in the sub-write command and the physical address allocated to the logical address in the sub-write command into a mapping table, and based on the logical address in the sub-write command, write the to-be-written data corresponding to the sub-write command into the physical address corresponding to the logical address in the sub-write command.

[0149] In some optional embodiments, the allocating unit includes:

[0150] The fourth determining unit is configured to determine, for any logical address in the sub-write command, based on the free block management table of the flash translation layer, whether there is a free physical block in the partition that the central processing unit core is responsible for.

[0151] The second acquiring unit is configured to acquire the number of erasure and write times of the idle physical blocks if there are idle physical blocks in the partition that the central processing unit core is responsible for.

[0152] The first screening unit is configured to screen out a first target physical block having the minimum erasure count from the idle physical blocks based on the erasure counts of the idle physical blocks.

[0153] The fifth determining unit is configured to determine the physical address of the first target physical block as the physical address corresponding to the logical address.

[0154] The second screening unit is configured to screen out a second target physical block having a ratio of invalid data exceeding a preset ratio threshold from all physical blocks corresponding to the partition that the CPU core is responsible for, if there is no idle physical block in the partition that the CPU core is responsible for.

[0155] The third acquiring unit is configured to acquire the erasure count of the second target physical block, and based on the erasure count of the second target physical block, select a third target physical block having the smallest erasure count from the second target physical block.

[0156] The migration unit is used to migrate valid data in the third target physical block to other physical blocks in the partition managed by the central processing unit core.

[0157] The sixth determining unit is configured to perform an erase operation on the third target physical block, and after completing the erase operation on the third target physical block, determine the physical address of the third target physical block as the physical address corresponding to the logical address.

[0158] For the description of the features in the embodiment corresponding to the command processing device, please refer to the relevant description of the embodiment corresponding to the command processing method, and no further details will be given here.

[0159] The embodiment of the present application also provides an electronic device, such as Figure 12 As shown, it includes a processor 1201 and a memory 1202, in which a computer program is stored. The processor 1201 is configured to run the computer program to execute the steps in any one of the above-mentioned command processing method embodiments applied to the hardware acceleration unit or the steps in any one of the above-mentioned command processing method embodiments applied to the central processing unit core.

[0160] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps of any one of the above-mentioned command processing method embodiments applied to a hardware acceleration unit or the steps of any one of the above-mentioned command processing method embodiments applied to a central processing unit core when running.

[0161] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0162] An embodiment of the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps of any one of the command processing method embodiments applied to a hardware acceleration unit or the steps of any one of the command processing method embodiments applied to a central processing unit core.

[0163] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned command processing method embodiments applied to a hardware acceleration unit or the steps of any of the above-mentioned command processing method embodiments applied to a central processing unit core.

[0164] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0165] The above is a detailed introduction to a command processing method, device, electronic device, and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A command processing method, characterized in that: Applicable to hardware acceleration units, including: Receive the write command sent by the host; Parsing the write command to obtain a starting logical address and a logical address length of the write command; Based on the starting logical address and the logical address length of the write command, the write command is divided into a plurality of sub-write commands, wherein one sub-write command corresponds to one partition; For any sub-write command, based on the target partition corresponding to the sub-write command, determine the target central processing unit core corresponding to the sub-write command, send the sub-write command to the corresponding target central processing unit core, so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns sub-write command completion information after the processing is completed; When sub-write command completion information of a plurality of sub-write commands corresponding to the write command is received, the completion information of the write command is fed back to the host.

2. The method according to claim 1, characterized in that Before determining, for any sub-write command, based on the target partition corresponding to the sub-write command, the target central processing unit core corresponding to the sub-write command, the method further includes: Setting a unique write command tag for the write command and recording the tag; A unique sub-write command tag is set for each of the multiple sub-write commands corresponding to the write command, and the sub-write command tag is recorded under the write command tag.

3. The method according to claim 2, characterized in that The step of feeding back the completion information of the write command to the host upon receiving sub-write command completion information of the multiple sub-write commands corresponding to the write command includes: Each time a sub-write command completion message is received, the target sub-write command tag in the sub-write command completion message is obtained; Based on the target sub-write command tag, determining a target write command tag corresponding to the target sub-write command tag; Based on the target write command tag, updating the number of completed sub-write commands of the target write command corresponding to the target write command tag; When the number of completed sub-write commands of the target write command is consistent with the number of sub-write commands divided by the target write command, it is determined that sub-write command completion information of multiple sub-write commands corresponding to the target write command is received, and the completion information of the target write command is fed back to the host.

4. A command processing method, characterized in that: Applied to CPU cores, including: Receiving a sub-write command sent by a hardware acceleration unit, wherein the hardware acceleration unit receives the write command sent by the host, parses the write command, obtains a starting logical address and a logical address length of the write command, and divides the write command into multiple sub-write commands based on the starting logical address and the logical address length of the write command, wherein each sub-write command corresponds to a partition, and for any sub-write command, determines a target central processing unit core corresponding to the sub-write command based on a target partition corresponding to the sub-write command, and sends the sub-write command to the corresponding target central processing unit core; The sub-write command is processed, and sub-write command completion information is returned after the processing is completed, so that the hardware acceleration unit feeds back the completion information of the write command to the host when receiving the sub-write command completion information of multiple sub-write commands corresponding to the write command.

5. The method according to claim 4, characterized in that The processing of the sub-write command includes: Based on the sub-write command, determining a logical address in the sub-write command; Allocating corresponding physical addresses to the logical addresses in the sub-write command, wherein each logical address corresponds to a unique physical address; The mapping relationship between the logical address in the sub-write command and the physical address assigned to the logical address in the sub-write command is written into a mapping table, and based on the logical address in the sub-write command, the data to be written corresponding to the sub-write command is written into the physical address corresponding to the logical address in the sub-write command.

6. The method according to claim 5, characterized in that The allocating a corresponding physical address to the logical address in the sub-write command includes: For any logical address in the sub-write command, determining whether there is an idle physical block in the partition responsible for the central processing unit core based on the idle block management table of the flash translation layer; If there is an idle physical block in the partition that the central processing unit core is responsible for, obtaining the number of erase and write times of the idle physical block; Based on the number of erasures and writes of the idle physical blocks, selecting a first target physical block with the smallest number of erasures and writes from the idle physical blocks; Determining the physical address of the first target physical block as the physical address corresponding to the logical address; If there is no free physical block in the partition that the CPU core is responsible for, screening out a second target physical block containing invalid data in a proportion exceeding a preset proportion threshold from all physical blocks corresponding to the partition that the CPU core is responsible for; Acquire the number of erasures and writes of the second target physical block, and based on the number of erasures and writes of the second target physical block, select a third target physical block having the smallest number of erasures and writes from the second target physical block; Migrating valid data in the third target physical block to other physical blocks in the partition that the central processing unit core is responsible for; An erase operation is performed on the third target physical block, and after the erase operation on the third target physical block is completed, a physical address of the third target physical block is determined as the physical address corresponding to the logical address.

7. A command processing device, characterized in that: Applicable to hardware acceleration units, including: A first receiving module, configured to receive a write command sent by a host; A command parsing module, configured to parse the write command and obtain a starting logical address and a logical address length of the write command; a partitioning module, configured to partition the write command into a plurality of sub-write commands based on a starting logical address and a logical address length of the write command, wherein one sub-write command corresponds to one partition; a determination module configured to determine, for any sub-write command, a target central processing unit core corresponding to the sub-write command based on a target partition corresponding to the sub-write command, send the sub-write command to the corresponding target central processing unit core, so that the target central processing unit core receives the sub-write command, processes the sub-write command, and returns sub-write command completion information after the processing is completed; A feedback module is configured to feed back completion information of the write command to the host upon receiving sub-write command completion information of a plurality of sub-write commands corresponding to the write command.

8. A command processing device, characterized in that: Applied to CPU cores, including: a second receiving module, configured to receive a sub-write command sent by a hardware acceleration unit, wherein the hardware acceleration unit receives a write command sent by a host, parses the write command, obtains a starting logical address and a logical address length of the write command, and divides the write command into a plurality of sub-write commands based on the starting logical address and the logical address length of the write command, wherein one sub-write command corresponds to one partition, and for any sub-write command, determines a target central processing unit core corresponding to the sub-write command based on a target partition corresponding to the sub-write command, and sends the sub-write command to the corresponding target central processing unit core; A return module is used to process the sub-write command and return sub-write command completion information after the processing is completed, so that the hardware acceleration unit can feedback the completion information of the write command to the host when it receives the sub-write command completion information of multiple sub-write commands corresponding to the write command.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the command processing method according to any one of claims 1 to 3 or the steps of the command processing method according to any one of claims 4 to 6 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the computer program implements the steps of the command processing method according to any one of claims 1 to 3 or the steps of the command processing method according to any one of claims 4 to 6.

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