Method and system for managing NVMe controller through host function model and medium

Abstract

The invention relates to the field of chip verification, in particular to a method and system for managing an NVMe controller through a host function model and a medium. Management of the NVMe controller is packaged into a class, the class is called as a controller manager, the controller manager comprises all information related to a test command preposition step of the to-be-tested NVMe controller, and each piece of information is provided with a valid bit used for representing whether the information is valid or not; when a test command is sent, a user sends a self-defined command, a host function model checks whether all information effective bits of a front step related to the command in a controller manager are 1 or not, if all information effective bits are 1, the command is directly sent, if all information effective bits are not 1, information with the effective bit being 0 is obtained from the NVMe controller to be tested through the command, and the corresponding effective position 1 is sent to the NVMe controller to be tested. And sending the command until the valid bits of all information are 1. According to the method, the pre-steps can be executed only by directly calling related commands, so that the verification efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of digital chip verification, and in particular to a controller management method, system, and medium for simplifying host function model operations when verifying an NVMe controller. Background Art

[0002] In the field of digital chip verification, especially for NVMe controller verification, traditional host functional models require verification engineers to manually perform a series of pre-processing steps, such as reading registers and configuring interrupts, before issuing the corresponding NVMe commands. This manual operation is complex and error-prone, significantly reducing the efficiency of verification platform debugging and increasing the verification engineer's workload and verification cycle. Furthermore, with the increasing complexity of chip design, verification work faces increasing challenges, requiring more efficient and automated verification methods.

[0003] The traditional host functional model exposes specific user functions or tasks, requiring users to schedule these existing functions or tasks to perform NVMe controller initialization, I / O commands, admin commands, and other operations. Before sending various commands, the host functional model typically requires obtaining the controller's supported capabilities through other commands or reading controller registers, referred to here as pre-steps. For example, the pre-steps for sending an I / O write command to an NVMe I / O controller include: reading the CAP, VS, and CMBSZ registers; configuring the interrupt enable register (selecting one of MSI / MSIx / INTx); configuring the interrupt vector table; allocating memory size and base address; creating an admin SQ / CQ by writing to the AQA / ASQ / ACQ registers; writing to the CC.EN register; waiting for the CSTS.RDY register to go high, indicating that controller initialization is complete and ready to process admin commands; sending the Identity command to obtain the Identify Controller Data Structure; and sending the SetFeature(NumberOfQueues) command to the controller to determine the number of I / O submission queues and completion queues supported by the controller. If MSIx supports it, disable MSI / Pin-based interrupt, enable MSIx interrupt, configure the table, and create IO CQ and SQ.

[0004] From the above analysis, we can see that different stimulus scenarios require chip verification engineers to perform different pre-processing steps, which greatly reduces the efficiency of verification platform debugging. Summary of the Invention

[0005] In response to the shortcomings of the prior art, the present invention provides a method, system and medium for managing NVMe controllers with a host function model. There is no need to manually execute complex pre-steps, and the pre-steps can be completed by directly calling relevant commands, which greatly reduces the workload and time when writing test cases.

[0006] In order to solve the technical problem, the technical solution adopted by the present invention is: a method for managing NVMe controllers by a host function model. This method encapsulates the management of NVMe controllers into a class, and the encapsulated class is called a controller manager. The controller manager contains all information related to the pre-steps of the test command of the NVMe controller to be tested. At the same time, a valid bit is set for the information of each controller to indicate whether the information of this controller is valid; when a command to verify the NVMe controller needs to be sent, the user calls the command task in the host function model to send a custom command, and then the host function model checks whether all valid bits of the information of the pre-steps related to this command in the controller manager are all 1. If all are 1, the command is sent directly. If not all are 1, the information with a valid bit of 0 is obtained, and the corresponding valid position is set to 1 until the valid bits of all information are 1 and the command is sent.

[0007] Furthermore, the controller manager includes a controller data structure, a namespace data structure and registers. The controller data structure includes PCI vendor ID, maximum data transfer size, optional management command support and their valid bits. The namespace data structure includes command space size, number of logical block address formats, end-to-end data protection type settings and their valid bits. The registers include controller configuration, controller capabilities, controller memory buffer size and their valid bits.

[0008] Furthermore, the host function model also has tasks for reading registers, tasks for sending admin commands, and tasks for sending IO commands. When the host function model checks that the valid bits of the information of all the preceding steps related to the custom command are not all 1, it continues to check whether the information with valid bits of 0 in the preceding steps is a data structure or register information. If it is register information, the host function model automatically calls the task for reading registers, obtains the relevant register information, and sets the corresponding valid position to 1. If it is not register information, the host function model automatically calls the task for sending admin commands, obtains relevant information, and sets the corresponding valid position to 1.

[0009] Furthermore, the host function model calls a task for reading registers or a task for sending admin commands, obtains information with a valid bit of 0 in the NVMe to be tested, and sets the valid bit to 1 after obtaining the information.

[0010] Furthermore, for multi-controller devices, multiple independent controller managers are configured in the host functional model, and the number of controller managers is equal to the number of NVMe controllers. The NVMe controller is connected to the host functional model through the PCIe bus.

[0011] Furthermore, when the host function model is initialized, the variables managed by the controller are initialized to default values, and the valid bits corresponding to the variables are initialized to 0, indicating that the message is invalid. When the host function model obtains the relevant data, the corresponding valid bit is set to 1, indicating that the message is valid.

[0012] The present invention also discloses a system for managing NVMe controllers with a host function model, including a controller manager and a command for obtaining information related to a pre-step of a test command. The number of controller managers is equal to the number of NVMe controllers to be tested, and the controller managers are used to store all information related to the pre-step of a test command of the NVMe controller to be tested and the valid bits corresponding to the information. When a command to verify the NVMe controller needs to be sent, the user calls the command task in the host function model to send a custom command, and then the host function model checks whether all valid bits of the information of the pre-step related to this command in the controller manager are all 1. If all are 1, the command is sent directly. If not all are 1, information with a valid bit of 0 is obtained, and the corresponding valid bit is set to 1 until the valid bits of all information are 1, and the command is sent.

[0013] Furthermore, the controller manager includes a controller data structure, a namespace data structure and registers. The controller data structure includes PCI vendor ID, maximum data transfer size, optional management command support and their valid bits. The namespace data structure includes command space size, number of logical block address formats, end-to-end data protection type settings and their valid bits. The registers include controller configuration, controller capabilities, controller memory buffer size and their valid bits.

[0014] Furthermore, the host function model also has tasks for reading registers, tasks for sending admin commands, and tasks for sending IO commands. When the host function model checks that the valid bits of the information of all the preceding steps related to the custom command are not all 1, it continues to check whether the information with valid bits of 0 in the preceding steps is a data structure or register information. If it is register information, the host function model automatically calls the task for reading registers, obtains the relevant register information, and sets the corresponding valid position to 1. If it is not register information, the host function model automatically calls the task for sending admin commands, obtains relevant information, and sets the corresponding valid position to 1.

[0015] The present invention also discloses a storage medium storing program instructions, which, when running, execute the method of managing the NVMe controller with the host function model as described above.

[0016] Beneficial effects of the present invention: The present invention sets up a controller manager to store variables for all information about the NVMe controller, and provides commands for obtaining relevant information. When verifying the NVMe controller to be tested, the verification engineer does not need to manually perform complex pre-steps, but only needs to directly call relevant commands, which greatly reduces the workload and time when writing test cases. The automated pre-step execution and information acquisition mechanism makes the debugging of the verification platform more convenient, reducing errors caused by manual operations and the need for repeated debugging. Automated operations reduce the possibility of human error, ensure the consistency and accuracy of the verification process, and improve the reliability of the verification results. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of setting up a controller manager within a host functional model; Figure 2 Flowchart for sending verification command. DETAILED DESCRIPTION

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0019] Example 1 This embodiment discloses a system for managing NVMe controllers using a host function model. Figure 1 As shown in the figure, it includes a host functional model and an NVMe controller. The NVMe controller is the chip to be verified, i.e., the DUT. For a multi-controller device, there are multiple NVMe controllers, which are connected to the host functional model via the PCIe bus.

[0020] In order to realize automatic acquisition of pre-step information of NVMe controller, this embodiment sets multiple controller managers and commands for obtaining information related to the pre-step of test command in the host function model. The number of controller managers is equal to the number of NVMe controllers to be tested, and is used to store all information related to the pre-step of test command of NVMe controller to be tested and the valid bits corresponding to the information. When it is necessary to send a command to verify the NVMe controller, the user calls the command task in the host function model to send a custom command, and then the host function model checks whether all valid bits of the information of the pre-step related to this command in the controller manager are all 1. If all are 1, the command is sent directly. If not all are 1, the information with valid bits of 0 is obtained, and the corresponding valid bits are set to 1 until the valid bits of all information are 1 and the command is sent.

[0021] Specifically, the controller manager stores all protocol-specified register information, namely registers, including CC (Controller Configuration), CAP (Controller Capabilities), and CMBSZ (Controller Memory Buffer Size), with corresponding CC valid bits, CAP valid bits, and CMBSZ valid bits. The controller manager also stores all protocol-related fields in the controller data structure, namely the controller data structure, including VID (PCI Vendor ID), MDTS (Maximum Data Transfer Size), and OACS (Optional Admin Command Support), with corresponding VID valid bits, MDTS valid bits, and OACS valid bits. The controller manager stores all protocol-related fields in the identification namespace data structure, namely the command space data structure, including NSZE (Namespace Size), NLBAF (Number of LBA Formats), DPS (End-to-end Data Protection Type Settings), etc., and has NSZE valid bit, NLBAF valid bit, DPS valid bit, etc.

[0022] When the host function model is initialized, the information in the controller manager is initialized to the default value, and the corresponding valid bit is initialized to 0, indicating that the information is invalid. When the host function model obtains the relevant data, the corresponding valid bit is set to 1, indicating that the information is valid.

[0023] The host functional model also includes tasks for reading registers, sending admin commands, and sending I / O commands. The register reading task is used by the host functional model to send requests to read or write NVMe controller registers. The register reading task is called by the host functional model to read registers in the design under test (DUT). Before reading, the host functional model checks whether the valid bit of the internally stored register value is set. If it is set, it will not repeatedly read the corresponding register in the DUT. The admin command task is used by the host functional model to send Admin commands. Admin commands are a core component of the NVMe protocol, responsible for device lifecycle management, configuration, and monitoring. They provide flexible and powerful management capabilities for high-performance NVMe storage devices, ensuring secure and efficient device operation. The I / O command task is used by the host functional model to send I / O commands. I / O commands are the "executors" of data transmission in the NVMe protocol. Through an efficient queuing mechanism, flexible addressing methods, and data protection features, they enable high-speed data exchange between the host and storage device. It has a clear division of labor with the Admin command: I / O commands focus on reading and writing user data, and Admin commands are responsible for device management and configuration, together forming the core capabilities of NVMe high-performance, low-latency storage.

[0024] When the host function model checks that the valid bits of the information of all the preceding steps related to the custom command are not all 1, it continues to check whether the information with the valid bit of 0 in the preceding step is a data structure or register information. If it is register information, the host function model automatically calls the task for reading the register, obtains the relevant register information, and sets the corresponding valid position to 1. If it is not register information, the host function model automatically calls the task for sending the admin command, obtains the relevant information, and sets the corresponding valid position to 1.

[0025] When chip verification engineers send NVMe commands through the host function model, they do not need to perform the corresponding command pre-steps, but only need to call the relevant commands directly. The specific process is as follows Figure 2 : Step 1: The user calls the command task in the host function model to send a custom command; Step 2: The host function model checks whether the valid bits of all the information in the preceding steps related to this command are all 1, then directly sends this command and jumps directly to step 7; Step 3: If not all bits are 1, the host function model checks whether the information with valid bits set to 0 in the previous step is a data structure or register information; Step 4: If it is register information, the host controller automatically calls the task for reading registers, obtains relevant register information from the NVMe controller under test, and sets the corresponding valid position to 1; Step 5: If it is not register information, the host controller automatically calls the task for sending the admin command, obtains relevant information from the NVMe controller under test, and sets the corresponding valid position to 1; Step 6: Repeat steps 3, 4, and 5 until all valid bits of the preceding step information related to this command are 1; Step 7: Send the command specified by the user; Step 8, command completed; Step nine, the simulation ends.

[0026] Example 2 This embodiment discloses a method for managing an NVMe controller using a host function model. This method encapsulates the management of the NVMe controller into a class, which is called a controller manager. Figure 1 As shown, the controller manager contains all the information related to the pre-steps of the test command of the NVMe controller to be tested. At the same time, a valid bit is set for the information of each controller to indicate whether the information of this controller is valid. When a command to verify the NVMe controller needs to be sent, the user calls the command task in the host function model to send a custom command. Then the host function model checks whether all the valid bits of the information in the pre-steps related to this command in the controller manager are all 1. If all are 1, the command is sent directly. If not all are 1, the information with a valid bit of 0 is obtained and the corresponding valid bit is set to 1 until the valid bits of all information are 1 and the command is sent.

[0027] Specifically, the controller manager stores all protocol-specified register information, namely registers, including CC (Controller Configuration), CAP (Controller Capabilities), and CMBSZ (Controller Memory Buffer Size), with corresponding CC valid bits, CAP valid bits, and CMBSZ valid bits. The controller manager also stores all protocol-related fields in the controller data structure, namely the controller data structure, including VID (PCI Vendor ID), MDTS (Maximum Data Transfer Size), and OACS (Optional Admin Command Support), with corresponding VID valid bits, MDTS valid bits, and OACS valid bits. The controller manager stores all protocol-related fields in the identification namespace data structure, namely the command space data structure, including NSZE (Namespace Size), NLBAF (Number of LBA Formats), DPS (End-to-end Data Protection Type Settings), etc., and has NSZE valid bit, NLBAF valid bit, DPS valid bit, etc.

[0028] When the host function model is initialized, the information in the controller manager is initialized to the default value, and the corresponding valid bit is initialized to 0, indicating that the information is invalid. When the host function model obtains the relevant data, the corresponding valid bit is set to 1, indicating that the information is valid.

[0029] The host functional model also includes tasks for reading registers, sending admin commands, and sending I / O commands. The register reading task is used by the host functional model to send requests to read or write NVMe controller registers. The register reading task is called by the host functional model to read registers in the design under test (DUT). Before reading, the host functional model checks whether the valid bit of the internally stored register value is set. If it is set, it will not repeatedly read the corresponding register in the DUT. The admin command task is used by the host functional model to send Admin commands. Admin commands are a core component of the NVMe protocol, responsible for device lifecycle management, configuration, and monitoring. They provide flexible and powerful management capabilities for high-performance NVMe storage devices, ensuring secure and efficient device operation. The I / O command task is used by the host functional model to send I / O commands. I / O commands are the "executors" of data transmission in the NVMe protocol. Through an efficient queuing mechanism, flexible addressing methods, and data protection features, they enable high-speed data exchange between the host and storage device. It has a clear division of labor with the Admin command: I / O commands focus on reading and writing user data, and Admin commands are responsible for device management and configuration, together forming the core capabilities of NVMe high-performance, low-latency storage.

[0030] When the host function model checks that the valid bits of the information of all the preceding steps related to the custom command are not all 1, it continues to check whether the information with the valid bit of 0 in the preceding step is a data structure or register information. If it is register information, the host function model automatically calls the task for reading the register, obtains the relevant register information, and sets the corresponding valid position to 1. If it is not register information, the host function model automatically calls the task for sending the admin command, obtains the relevant information, and sets the corresponding valid position to 1.

[0031] When chip verification engineers send NVMe commands through the host function model, they do not need to perform the corresponding command pre-steps, but only need to call the relevant commands directly. The specific process is as follows Figure 2 : Step 1: The user calls the command task in the host function model to send a custom command; Step 2: The host function model checks whether the valid bits of all the information in the preceding steps related to this command are all 1, then directly sends this command and jumps directly to step 7; Step 3: If not all bits are 1, the host function model checks whether the information with valid bits set to 0 in the previous step is a data structure or register information; Step 4: If it is register information, the host controller automatically calls the task for reading registers, obtains relevant register information from the NVMe controller under test, and sets the corresponding valid position to 1; Step 5: If it is not register information, the host controller automatically calls the task for sending the admin command, obtains relevant information from the NVMe controller under test, and sets the corresponding valid position to 1; Step 6: Repeat steps 3, 4, and 5 until all valid bits of the preceding step information related to this command are 1; Step 7: Send the command specified by the user; Step 8, command completed; Step nine, the simulation ends.

[0032] The following two examples illustrate this method: Example 1: When the user sends an IO write command, the pre-step is empty: 1. The user calls the host function model IO related commands to send IO write commands; 2. The host functional model checks that the CAP valid bit in the controller manager is 0, automatically initiates a read request from the register to obtain the CAP value of the NVMe controller, and sets the CAP valid bit to 1; 3. The host functional model checks that the VS valid bit in the controller manager is 0, automatically sends a read request from the register to obtain the VS value of the NVMe controller, and sets the VS valid bit to 1; 4. The host functional model checks that the CMBSZ valid bit in the controller manager is 0, automatically sends a read request from the register to obtain the CMBSZ value of the NVMe controller, and sets the CMBSZ valid bit to 1; 5. The host functional model continuously checks the preceding steps of the IO write command and sends requests to obtain information from all controllers until all valid bits of the preceding steps are 1; 6. The host functional model sends an IO write command.

[0033] Example 2: When the user sends an IO write command, all valid bits of the information required in the preceding step are 1: 1. The user calls the host function model IO related commands to send IO write commands; 2. The host functional model checks that the CAP valid bit in the controller manager is 1 and automatically enters the next pre-step check; 3. The host function model checks that the VS valid bit in the controller manager is 1 and automatically enters the next pre-step check; 4. The host function model checks that the CMBSZ valid bit in the controller manager is 1 and automatically enters the next pre-step check; 5. The host functional model continuously checks the pre-steps of the IO write command and finds that the valid bits of the information required by all pre-steps are 1; 6. The host functional model sends an IO write command.

[0034] Example 3 This embodiment discloses a storage medium storing program instructions, which, when run, execute the method of managing the NVMe controller with a host function model as described in Example 1.

[0035] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. A method for managing an NVMe controller using a host function model, characterized in that: This method encapsulates the management of NVMe controllers into a class called controller manager. The controller manager contains all information related to the pre-steps of the test command of the NVMe controller to be tested. At the same time, a valid bit is set for each controller's information to indicate whether the information is valid. When a command to verify the NVMe controller needs to be sent, the user calls the command task in the host function model to send a custom command. Then the host function model checks whether all valid bits of the information in the pre-steps related to this command in the controller manager are all 1. If all are 1, the command is sent directly. If not all are 1, the information with a valid bit of 0 is obtained from the NVMe controller to be tested through a command, and the corresponding valid bit is set to 1 until the valid bits of all information are 1 and the command is sent.

2. The method for managing an NVMe controller using a host function model according to claim 1, wherein: The controller manager includes controller data structure, namespace data structure and registers. The controller data structure includes PCI vendor ID, maximum data transfer size, optional management command support and their valid bits. The namespace data structure includes command space size, number of logical block address formats, end-to-end data protection type setting and their valid bits. The registers include controller configuration, controller capability, controller memory buffer size and their valid bits.

3. The method for managing an NVMe controller using a host function model according to claim 2, wherein: The host function model also has tasks for reading registers, sending admin commands, and sending IO commands. When the host function model checks that the valid bits of all information in the preceding steps related to the custom command are not all 1, it continues to check whether the information with valid bits of 0 in the preceding steps is a data structure or register information. If it is register information, the host function model automatically calls the task for reading registers, obtains the relevant register information, and sets the corresponding valid position to 1. If it is not register information, the host function model automatically calls the task for sending admin commands, obtains relevant information, and sets the corresponding valid position to 1.

4. The method for managing an NVMe controller using a host function model according to claim 3, wherein: The host function model calls a task for reading registers or a task for sending admin commands, obtains information with a valid bit of 0 in the NVMe to be tested, and sets the valid bit to 1 after obtaining the information.

5. The method for managing an NVMe controller using a host function model according to claim 1, wherein: For multi-controller devices, multiple independent controller managers are configured in the host functional model. The number of controller managers is equal to the number of NVMe controllers. The NVMe controllers are connected to the host functional model through the PCIe bus.

6. The method for managing an NVMe controller using a host function model according to claim 1, wherein: When the host function model is initialized, the information in the controller manager is initialized to the default value, and the valid bit corresponding to the information is initialized to 0, indicating that the message is invalid. When the host function model obtains the relevant data, the corresponding valid bit is set to 1, indicating that the message is valid.

7. A system for managing an NVMe controller using a host function model, characterized in that: It includes a controller manager and a command for obtaining information related to the pre-steps of the test command. The number of controller managers is equal to the number of NVMe controllers to be tested. It is used to store all information related to the pre-steps of the test command of the NVMe controller to be tested and the valid bits corresponding to the information. When a command to verify the NVMe controller needs to be sent, the user calls the command task in the host function model to send a custom command. Then the host function model checks whether all valid bits of the information in the pre-steps related to this command in the controller manager are all 1. If all are 1, the command is sent directly. If not all are 1, the information with a valid bit of 0 is obtained through the command for obtaining information related to the pre-steps of the test command, and the corresponding valid bit is set to 1 until the valid bits of all information are 1 and the command is sent.

8. The system for managing an NVMe controller using a host function model according to claim 7, wherein: The controller manager includes controller data structure, namespace data structure and registers. The controller data structure includes PCI vendor ID, maximum data transfer size, optional management command support and their valid bits. The namespace data structure includes command space size, number of logical block address formats, end-to-end data protection type setting and their valid bits. The registers include controller configuration, controller capability, controller memory buffer size and their valid bits.

9. The system for managing an NVMe controller using a host function model according to claim 8, wherein: The host function model also has tasks for reading registers, sending admin commands, and sending IO commands. When the host function model checks that the valid bits of the information of all the preceding steps related to the custom command are not all 1, it continues to check whether the information with valid bits of 0 in the preceding steps is a data structure or register information. If it is register information, the host function model automatically calls the task for reading registers, obtains the relevant register information, and sets the corresponding valid position to 1. If it is not register information, the host function model automatically calls the task for sending admin commands, obtains relevant information, and sets the corresponding valid position to 1.

10. A storage medium storing program instructions, characterized in that: When the program instructions are run, they execute the method for managing the NVMe controller with a host function model as described in any one of claims 1 to 6.

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