BGA and CGA packaging device interconnection structure stress analysis method based on equivalent connection unit

Abstract

The invention belongs to the technical field of electronic packaging board level interconnection, and particularly relates to a BGA and CGA packaging device interconnection structure stress analysis method based on an equivalent connection unit. According to the technical scheme, the BGA and CGA packaging device interconnection structure stress analysis method based on the equivalent connection unit comprises the following steps that a BGA / CGA interconnection structure geometric model is established; determining elastic-plastic mechanical behavior characteristics of the BGA / CGA; determining BGA / CGA mechanical property characteristic parameters; establishing a BGA / CGA packaging device and a printed board model; establishing an equivalent connection unit; establishing a finite element calculation model; determining a welding spot which is most likely to fail; and calculating and analyzing the thermal fatigue life. The invention provides a BGA and CGA packaging device interconnection structure stress analysis method based on an equivalent connection unit, which can efficiently and accurately obtain the stress characteristics and response process of a chip corner BGA / CGA welding spot, and effectively support the reliability quantitative analysis research of welding spot creep, fatigue and the like. And a key data support is provided for design evaluation of the BGA / CGA packaging device board-level interconnection reliability.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic packaging board-level interconnection, and in particular relates to a stress analysis method for interconnection structures of BGA and CGA packaging devices based on equivalent connection units. Background Art

[0002] The application and development of ball / column grid array (BGA / CGA) packaging technology has ushered in a new era for surface mount technology. BGA solder balls / CGA solder columns replace the original metal pins and wires, appearing in a surface array on the surface of the printed circuit board (PCB). This enables interconnection and reliable transmission of various electrical signals between the two, significantly increasing the number of device I / O interfaces.

[0003] Within the BGA / CGA package family, BGA / CGA can be categorized by package type: PBGA (plastic package) and CBGA / CCGA (ceramic package). The CBGA / CCGA substrate is a multilayer ceramic substrate, with a metal cover soldered to the substrate with sealing solder to protect the chip, leads, and pads. With improvements in manufacturing processes, the number of I / O pins has continued to increase, while solder pitch has also decreased, with center-to-center distances dropping from 1.27mm to 0.4mm or even smaller.

[0004] Assembled electronic products are subject to complex thermal, electrical, and mechanical forces during their service life. Due to large variations in material thermal expansion coefficients, uncoordinated deformation across the entire temperature range accelerates solder joint fatigue. BGA / CGA packaged devices are soldered to the substrate via an array of solder balls and pillars. They lack the flexible leads of traditional surface-mount devices to effectively reduce stress and strain within the solder joints. Therefore, BGA / CGA chips are prone to thermal fatigue failure during use, especially CBGA / CCGA chips.

[0005] Using experimental methods to study the reliability of solder joints requires a lot of manpower and material resources, while numerical simulation methods can effectively analyze the stress and strain of solder joints and effectively predict the life of electronic devices in a short period of time. They have been widely used in the study of solder joint thermal fatigue behavior.

[0006] Due to the small dimensions of solder ball diameter, solder height, and pad thickness (all less than 1mm), the mesh size is typically smaller to ensure accurate calculation results. BGA / CGA solder ball / pillar arrays are 16*16, 26*26, 34*34, and so on, resulting in hundreds of thousands to millions of meshes across the chip. Even with fine meshing (for corner solder joints) and coarse meshing (for other solder joints), the overall mesh size still reaches hundreds of thousands. Solder point stress calculations under temperature cycling loading, taking into account material creep nonlinearity, are time-consuming and inefficient. Summary of the Invention

[0007] In order to solve the above-mentioned problems existing in the prior art, the purpose of the present invention is to provide a stress analysis method for the interconnection structure of BGA and CGA packaged devices based on equivalent connection units, which can efficiently and accurately obtain the stress characteristics and response history of BGA / CGA solder joints at the corners of the chip, effectively support the reliability quantitative analysis research such as solder joint creep and fatigue, and provide key data support for the design evaluation of the board-level interconnection reliability of BGA / CGA packaged devices.

[0008] The technical solution adopted in the present invention is:

[0009] A stress analysis method for interconnection structures of BGA and CGA packaged devices based on equivalent connection units comprises the following steps:

[0010] S1: Establish the geometric model of BGA / CGA interconnect structure;

[0011] S2: Determine the elastic-plastic mechanical behavior characteristics of BGA / CGA;

[0012] S3: Determine the mechanical properties characteristic parameters of BGA / CGA;

[0013] S4: Establish BGA / CGA package device and printed circuit board model;

[0014] S5: Establish equivalent connection units;

[0015] S6: Establish finite element calculation model;

[0016] S7: Identify the solder joints most susceptible to failure;

[0017] S8: Calculation and analysis of thermal fatigue life.

[0018] Connection elements are special types of elements that establish connections between different components or between components and supporting structures, enabling efficient and accurate simulation of the physical properties of equivalent systems. By properly selecting and setting the element type, setting parameters, and applying them to the corresponding parts of the model, the accuracy and reliability of the simulation results can be ensured. A simplified CBGA package model was established by combining refined meshing (corner solder joints) with equivalent connection elements (remaining solder joints), effectively reducing the number of model meshes and achieving efficient calculations.

[0019] The present invention is a finite element modeling method for stress calculation of interconnection structures of BGA and CGA packaged devices based on equivalent connection units. While significantly reducing the scale of model calculation (the overall number of grids can be reduced by generally more than 60%, and up to more than 90%), it can accurately obtain the stress characteristics and response history of BGA / CGA solder joints at chip corners (the stress result error is less than 5%), thereby efficiently supporting reliability evaluation and analysis of solder joint creep, fatigue, etc. of related packaged devices, and providing key data support for the reliability design evaluation of board-level interconnections of BGA / CGA packaged devices.

[0020] As a preferred solution of the present invention, step S1 specifically includes: determining the geometric dimensions of the pads, solder balls / solder columns, and solder in the interconnect structure according to the BGA / CGA package chip parameters, and establishing a BGA / CGA interconnect structure geometric model.

[0021] As a preferred embodiment of the present invention, step S2 specifically includes: establishing a finite element model of the BGA / CGA interconnection structure, and obtaining a load-displacement curve of the interconnection structure considering the temperature effect by conducting elastic-plastic behavior analysis of the interconnection structure under uniaxial load conditions under different temperature conditions.

[0022] As a preferred solution of the present invention, step S3 specifically includes: according to the load-displacement curve under different temperature conditions and formula F i =D ii u i Calculate the elastic parameters of the connection unit according to the load-plastic displacement curve and formula under different temperature conditions Calculate the plastic parameters of the connection unit and assign the calculated elastic and plastic parameters to the connection unit attribute parameters.

[0023] As a preferred solution of the present invention, step S4 specifically includes: establishing a model based on the geometric parameters of the BGA / CGA packaged device and the printed circuit board, and connecting the BGA / CGA packaged chip and the printed circuit board through four groups of BGA / CGA interconnect structures at the corners.

[0024] As a preferred embodiment of the present invention, step S5 specifically includes: determining the position and effective area of ​​the chip pad coupling area control point and the printed circuit board pad coupling area control point according to the center position and diameter of the interconnect structure pad, establishing an equivalent connection unit of the BGA / CGA interconnect structure according to the two control points, and assigning the connection unit attributes to the equivalent connection unit.

[0025] As a preferred embodiment of the present invention, step S6 specifically includes: performing fine mesh division for the corner BGA / CGA interconnection structure and the chip and printed circuit board, completing the material, contact, boundary, load and solution settings, the material parameters need to set the thermal expansion coefficient, and the solder joints and solder balls need to additionally set the viscoplastic deformation related parameters.

[0026] As a preferred embodiment of the present invention, step S7 specifically includes: after the temperature cycle is completed, extracting the equivalent stress and equivalent plastic strain distribution of the solder joint at the end of the high-temperature dwell stage of the last temperature cycle for analysis to determine the location of the solder joint most prone to thermal fatigue failure.

[0027] As a preferred embodiment of the present invention, step S8 specifically includes: after determining the key welding points and key positions, extracting and analyzing the changes of equivalent stress, equivalent plastic strain and inelastic strain energy density of the nodes at the key positions with temperature cycle load.

[0028] As a preferred embodiment of the present invention, in step S8, the Manson-Coffin model is used to calculate the thermal fatigue life of the solder joint, and the formula is:

[0029]

[0030] Where Δε p is the plastic strain amplitude of each cycle of the weld; ε f and c are the fatigue ductility coefficient and fatigue ductility index respectively; the value of c is between -0.5 and 0.7.

[0031] The beneficial effects of the present invention are:

[0032] The present invention is a finite element modeling method for stress calculation of interconnection structures of BGA and CGA packaged devices based on equivalent connection units. While significantly reducing the scale of model calculation (the overall number of grids can be reduced by generally more than 60%, and up to more than 90%), it can accurately obtain the stress characteristics and response history of BGA / CGA solder joints at chip corners (the stress result error is less than 5%), thereby efficiently supporting reliability evaluation and analysis of solder joint creep, fatigue, etc. of related packaged devices, and providing key data support for the reliability design evaluation of board-level interconnections of BGA / CGA packaged devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flow chart of the method of the present invention;

[0034] Figure 2 This is a schematic diagram of a typical BGA / CGA solder joint interconnection structure;

[0035] Figure 3 This is a schematic diagram of the typical CBGA solder joint interconnection structure;

[0036] Figure 4 It is a schematic diagram of a typical connection unit model;

[0037] Figure 5 It is the traditional modeling method CBGA chip geometric model and mesh division diagram;

[0038] Figure 6 It is the geometric model and mesh division diagram of CBGA chip using equivalent connection unit modeling method;

[0039] Figure 7 It is the traditional modeling method CBGA chip solder joint stress cloud map;

[0040] Figure 8 It is a stress cloud diagram of CBGA chip solder joints using the equivalent connection unit modeling method.

[0041] In the figure: 1-pad; 2-solder paste; 3-solder ball; 4-packaged chip; 5-printed circuit board; 6-CBGA solder joint interconnection structure; 7-chip pad coupling area control point; 8-printed circuit board pad coupling area control point; 9-equivalent connection unit; 10-CBGA chip geometric model using traditional modeling method; 11-CBGA chip mesh division using traditional modeling method; 12-CBGA chip four-corner interconnection structure mesh division; 13-CBGA chip other interconnection structure mesh division; 14-CBGA chip geometric model using equivalent connection unit modeling method; 15-CBGA chip mesh division using equivalent connection unit modeling method. DETAILED DESCRIPTION

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention. It should be noted that the embodiments of the present invention and the features therein may be combined with each other unless there is a conflict.

[0044] Figure 3 In the figure, both sides of the solder ball 3 are connected to the solder pad 1 through the solder paste 2. Figure 4 In the figure, the CBGA solder joint interconnection structure 6 includes a chip pad coupling area control point 7, a printed circuit board pad coupling area control point 8 and an equivalent connection unit 9, and the chip pad coupling area control point 7 and the printed circuit board pad coupling area control point 8 are respectively connected to the two ends of the equivalent connection unit 9. Figure 5The four structures in the figure are the traditional modeling method CBGA chip geometric model, the traditional modeling method CBGA chip mesh division 11, the CBGA chip four-corner interconnection structure mesh division 12 and the CBGA chip other interconnection structure mesh division 14. Figure 6 The two structures in the figure are respectively the CBGA chip geometric model 14 using the equivalent connection unit modeling method and the CBGA chip mesh division 15 using the equivalent connection unit modeling method.

[0045] like Figures 1 to 8 As shown, the stress analysis method of the interconnection structure of BGA and CGA packaged devices based on equivalent connection units in this embodiment includes the following steps:

[0046] S1: Establish the geometric model of BGA interconnect structure:

[0047] According to the parameters of BGA package chip 4, the geometric dimensions of pad 1 (PCB end diameter 0.7mm, chip end diameter 0.6mm, thickness 0.15mm), solder ball 3 (diameter 0.6mm), and solder (interconnection height 0.65mm) in the interconnection structure are determined, and the geometric model of BGA / CGA interconnection structure is established ( Figure 3 ).

[0048] S2: Determine the elastic-plastic mechanical behavior characteristics of BGA:

[0049] A finite element model of the BGA interconnection structure was established, and elastic-plastic analysis of the interconnection structure under unit force and moment load conditions along the X, Y, and Z directions at temperatures of 0℃, 25℃, 50℃, 75℃, and 100℃ was carried out to obtain the load-displacement curve of the interconnection structure considering the temperature effect.

[0050] S3: Determine the mechanical performance characteristic parameters of BGA:

[0051] According to the load-displacement curve and formula F under different temperature conditions i =D ii u i Calculate the elastic parameters of the connection unit according to the load-plastic displacement curve and formula under different temperature conditions Calculate the plastic parameters of the connection unit and assign the calculated elastic and plastic parameters to the connection unit attribute parameters.

[0052] S4: Establish BGA package device and printed circuit board 5 model:

[0053] The model is established based on the geometric parameters of the BGA package device (length, width and height are 25mm*25mm*2mm) and the printed circuit board 5 (length, width and height are 215mm*140mm*2mm). The BGA package chip 4 and the printed circuit board 5 are connected through 4 groups of BGA interconnection structures at the corners ( Figure 4 ).

[0054] S5: Establish equivalent connection unit (9):

[0055] According to the center position and diameter of the interconnect structure pad 1, the position and effective area (i.e., the diameter of the pad (1)) of the chip pad coupling area control point 7 and the printed circuit board pad coupling area control point 8 are determined. According to the two control points, the equivalent connection unit 9 of the BGA interconnect structure is established, and the connection unit attributes are assigned to the equivalent connection unit 9 ( Figure 4 ).

[0056] S6: Establish finite element calculation model:

[0057] Perform fine mesh division for the corner BGA interconnection structure and chip, printed circuit board 5, complete the material, contact, boundary, load and solution settings, the material parameters need to set the thermal expansion coefficient, among which the solder joints and solder balls 3 need to set additional viscoplastic deformation related parameters ( Figure 6 ).

[0058] S7: Identify the solder joints most prone to failure (critical solder joints):

[0059] Equivalent stress and equivalent plastic strain under temperature cycling are important factors affecting solder joint thermal fatigue, and the impact is more pronounced during the high-temperature dwell phase. After the temperature cycle is completed, the equivalent stress and equivalent plastic strain distribution of the solder joint at the end of the last high-temperature dwell phase of the temperature cycle are extracted and analyzed to identify the solder joint locations most susceptible to thermal fatigue failure.

[0060] S8: Thermal fatigue life calculation analysis:

[0061] After determining the key welding points and key positions, the equivalent stress, equivalent plastic strain and inelastic strain energy density of the nodes at the key positions are extracted and analyzed as they change with temperature cycling loads.

[0062] Existing methods for calculating the thermal fatigue life of solder joints are mainly based on energy or strain prediction models. In the energy (or strain)-based fatigue life prediction model, the inelastic strain energy density (or equivalent plastic strain) of the stable hysteresis loop is calculated, and the relationship between the inelastic strain energy density (or equivalent plastic strain) and fatigue life is established to obtain the thermal fatigue life.

[0063] The fatigue life prediction models that can be used mainly include plastic deformation fatigue prediction models (Manson-Coffin model, Ostergren model, Miller model, Engelmaier model, etc.), creep deformation fatigue prediction models (Syed model and Kencht-Fox model), and energy fatigue prediction models (Akay model and Darveaux model).

[0064] In this embodiment, the Manson-Coffin model is used to calculate the thermal fatigue life of the solder joint, and the formula is:

[0065]

[0066] Where Δε p is the plastic strain amplitude of each cycle of the weld; ε f and c are the fatigue ductility coefficient and fatigue ductility index respectively; the value of c is between -0.5 and 0.7.

[0067] ε of Sn60Pb37 material f and c are 0.853 and 9.2 respectively. According to the plastic strain calculation result of 0.00695, the fatigue life of the weld is 4569 times.

[0068] Table 1 is a comparison chart of the number of meshes in the simulation model of typical CBGA devices.

[0069]

[0070] Equivalent connection unit 9 is a special type of unit that establishes connections between different components or between components and supporting structures, enabling efficient and accurate simulation of the physical properties of the equivalent system. By properly selecting the unit type, setting parameters, and correctly applying it to the corresponding parts of the model, the accuracy and reliability of the simulation results can be ensured. A simplified CBGA package model is created by combining refined meshing (corner solder joints) with equivalent connection unit 9 (remaining solder joints), effectively reducing the number of model meshes and achieving efficient calculations.

[0071] The present invention is a finite element modeling method for stress calculation of the interconnection structure of BGA / CGA packaged devices based on the equivalent connection unit 9. While significantly reducing the scale of model calculation (the overall mesh number reduction ratio can generally reach more than 60%, and can reach more than 90% at most), it can accurately obtain the stress characteristics and response history of the BGA / CGA solder joints at the corners of the chip (the stress result error is less than 5%), thereby efficiently supporting the reliability evaluation analysis of the solder joint creep, fatigue, etc. of related packaged devices, and providing key data support for the reliability design evaluation of the board-level interconnection of BGA / CGA packaged devices.

[0072] The present invention is not limited to the above-mentioned optional implementation modes. Anyone can derive other forms of products under the inspiration of the present invention. However, no matter what changes are made in the shape or structure, any technical solution that falls within the scope defined by the claims of the present invention falls within the scope of protection of the present invention.

Claims

1. A stress analysis method for interconnection structure of BGA and CGA packaged devices based on equivalent connection units, characterized by: The following steps are involved: S1: Establish the geometric model of BGA / CGA interconnect structure; S2: Determine the elastic-plastic mechanical behavior characteristics of BGA / CGA; S3: Determine the mechanical properties characteristic parameters of BGA / CGA; S4: Establish BGA / CGA package device and printed circuit board (5) model; S5: establishing equivalent connection units (9); S6: Establish finite element calculation model; S7: Identify the solder joints most susceptible to failure; S8: Calculation and analysis of thermal fatigue life.

2. The method for analyzing the interconnect structure stress of BGA and CGA packaged devices based on equivalent connection units according to claim 1, characterized in that: Step S1 specifically includes: determining the geometric dimensions of the solder pad (1), solder ball (3) / solder column, and solder in the interconnection structure according to the parameters of the BGA / CGA package chip (4), and establishing a BGA / CGA interconnection structure geometric model.

3. The method for stress analysis of interconnection structure of BGA and CGA packaged devices based on equivalent connection units according to claim 1, characterized in that: Step S2 specifically includes: establishing a finite element model of the BGA / CGA interconnection structure, and obtaining a load-displacement curve of the interconnection structure considering the temperature effect by conducting elastic-plastic behavior analysis of the interconnection structure under uniaxial load conditions under different temperature conditions.

4. The method for analyzing the interconnection structure stress of BGA and CGA packaged devices based on equivalent connection units according to claim 1, characterized in that: Step S3 specifically includes: according to the load-displacement curve under different temperature conditions and formula F i =D ii u i Calculate the elastic parameters of the connection unit according to the load-plastic displacement curve and formula under different temperature conditions Calculate the plastic parameters of the connection unit and assign the calculated elastic and plastic parameters to the connection unit attribute parameters.

5. The method for stress analysis of interconnection structure of BGA and CGA packaged devices based on equivalent connection units according to claim 1, characterized in that: Step S4 specifically includes: establishing a model based on the geometric parameters of the BGA / CGA packaged device and the printed circuit board (5); the BGA / CGA packaged chip (4) and the printed circuit board (5) are connected via four groups of BGA / CGA interconnection structures at the corners.

6. The method for analyzing the interconnection structure stress of BGA and CGA packaged devices based on equivalent connection units according to claim 1, characterized in that: Step S5 specifically includes: determining the position and effective area of ​​the chip pad coupling area control point (7) and the printed circuit board pad coupling area control point (8) according to the center position and diameter of the interconnection structure pad (1), establishing an equivalent connection unit (9) of the BGA / CGA interconnection structure according to the two control points, and assigning connection unit attributes to the equivalent connection unit (9).

7. The method for analyzing the interconnection structure stress of BGA and CGA packaged devices based on equivalent connection units according to claim 1, characterized in that: Step S6 specifically includes: performing fine mesh division on the corner BGA / CGA interconnection structure and the chip and printed circuit board (5), completing material, contact, boundary, load and solution settings, the material parameters need to set the thermal expansion coefficient, and the solder joints and solder balls (3) need to additionally set viscoplastic deformation related parameters.

8. The method for analyzing the interconnection structure stress of BGA and CGA packaged devices based on equivalent connection units according to claim 1, characterized in that: Step S7 specifically includes: after the temperature cycle is completed, extracting the equivalent stress and equivalent plastic strain distribution of the solder joint at the end of the high temperature dwell stage of the last temperature cycle for analysis to determine the location of the solder joint most susceptible to thermal fatigue failure.

9. The method for analyzing the interconnection structure stress of BGA and CGA packaged devices based on equivalent connection units according to claim 1, characterized in that: Step S8 specifically includes: after determining the key solder joints and key positions, extracting and analyzing the changes of equivalent stress, equivalent plastic strain and inelastic strain energy density of the nodes at the key positions with temperature cycle load.

10. The method for analyzing the interconnection structure stress of BGA and CGA packaged devices based on equivalent connection units according to claim 9, characterized in that: In step S8, the Manson-Coffin model is used to calculate the thermal fatigue life of the solder joint, and the formula is: Where Δε p is the plastic strain amplitude of the weld in each cycle; ε f and c are the fatigue ductility coefficient and fatigue ductility index respectively; the value of c is between -0.5 and 0.7.

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