CNFET device-based logic unit circuit optimization method and system
By adjusting the structural parameters of CNFET devices and optimizing the logic unit circuit, the delay time challenge of the CNFET device ternary logic circuit was solved, the circuit performance and speed were improved, and the stability was enhanced.
Patent Information
- Application Number
- CN202510711447.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-26
AI Technical Summary
Existing ternary logic circuits based on CNFET devices face significant challenges in delay time and are more sensitive to voltage fluctuations and noise, affecting circuit performance and speed.
By repeatedly adjusting the structural parameters of the CNFET device, such as the physical channel length and drain length, the optimal average conversion delay time is obtained through simulation, and the logic unit circuit of the CNFET device is optimized, including the negative ternary inverter, positive ternary inverter, ternary inverter, dual-input ternary NAND gate, dual-input ternary NOR gate, low-threshold comparison-medium-high output circuit, equal-threshold comparison-medium-high output circuit and ternary XOR gate circuit designs.
The average switching delay time is reduced, the performance and speed of the CNFET device logic unit circuit are improved, and the stability and reliability of the circuit are enhanced.
Smart Images
Figure CN120706334A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a logic circuit design technology in the field of integrated circuits, and in particular to an optimization method and system for a logic unit circuit based on a CNFET device. Background Art
[0002] Currently, digital circuits and computer systems built on classic CMOS devices are almost entirely based on binary logic operations using Boolean functions. With the continuous advancement of integrated circuit manufacturing, device density and power density on chips continue to increase. The feature sizes of manufacturing processes are approaching the physical limits of CMOS devices, making the process improvement rate predicted by Moore's Law increasingly difficult to maintain.
[0003] In nanoscale CMOS devices, leakage power is a significant component of their total energy consumption. Other key challenges are reducing gate control and speed saturation. Therefore, to continue the historic progress in chip transistor count, density, and low-power performance, a number of emerging devices and technologies have attracted considerable attention in recent years as CMOS alternatives, including quantum dot cellular automata (QCAs), carbon nanotube field-effect transistors (CNFETs), single-electron transistors (SETs), and nanomagnetic devices. Among these new technologies, CNFETs have attracted significant attention due to their similarities to MOSFETs, high carrier mobility, high Ion / Ioff ratio, unique one-dimensional band structure, and near-ballistic transport. Due to their ballistic transport and low off-current characteristics, they are a promising alternative to bulk silicon transistors for low-power and high-performance designs. MVL circuit design is based on multi-threshold design techniques, and the threshold voltage of CNFETs can be easily adjusted by varying the nanotube diameter. In recent years, several MOSFET and CNFET MVL circuits have been used for ternary and quaternary logic. However, they have several key drawbacks, such as the use of very large ohmic resistors, the requirement for outdated depletion-mode MOSFETs, non-full-swing nodes, and limited fan-out. Meanwhile, large language models (LLMs) have been actively researched in the past two years, demonstrating their significant advantages and potential. Recent work has demonstrated lightweight LLMs by using dense layers (bit-linear layers) that eliminate matrix multiplications using ternary weights, approaching the power consumption of the human brain. This demonstrates that ternary logic circuits meet these characteristics and can help LLMs reduce computational costs and memory utilization. In modern nanoelectronics, utilizing the same CNFET device to build a variety of ternary logic basic circuits is crucial. This unified device platform not only simplifies circuit design and fabrication but also significantly improves circuit consistency and reliability, facilitating the development of ternary logic standard cell libraries. However, current CNFET-based ternary logic circuits still face significant challenges in terms of latency. Because ternary logic must handle a greater number of voltage states, the circuits are more sensitive to voltage fluctuations and noise. Therefore, reducing latency and improving performance speed are crucial. Summary of the Invention
[0004] Technical problem to be solved by the present invention: In response to the above-mentioned problems in the prior art, a method and system for optimizing logic unit circuits based on CNFET devices are provided. The present invention aims to optimize logic unit circuits based on CNFET devices to reduce the average conversion delay and improve the performance and speed of logic unit circuits based on CNFET devices.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for optimizing a logic unit circuit based on a CNFET device, comprising: for an optimized logic unit circuit based on a CNFET device, adjusting the structural parameters of the CNFET device multiple times and simulating the structural parameters after each adjustment to obtain an average conversion delay time of the optimized logic unit circuit based on the CNFET device, and selecting the structural parameters corresponding to the optimal average conversion delay time as the optimal structural parameters of the optimized logic unit circuit based on the CNFET device, wherein the structural parameters of the CNFET device include the physical channel length of the CNFET device. , source length and drain length Part or all of .
[0006] Optionally, the logic unit circuit based on the CNFET device is a negative ternary inverter NTI, a positive ternary inverter PTI or a ternary inverter STI, wherein the negative ternary inverter NTI is composed of transistors T1 and T2, wherein transistor T1 is an NCNFET transistor, and transistor T2 is a PCNFET transistor. The gate of transistor T1 is connected to the input signal IN, the source is grounded GND, and the drain is connected to the source of T2 and connected to the output terminal OUT. The gate of transistor T2 is connected to the input signal IN, the source is connected to the drain of transistor T1 and the output terminal OUT, and the drain is connected to the power supply Vdd. The chirality vector of transistor T1 is (19, 0), and the chirality vector of transistor T2 is (10, 0), so that the negative ternary inverter NT I outputs 2 when the input is 0, and outputs 0 when the input is 1 or 2; the positive ternary inverter PTI is composed of transistors T3 and T4, transistor T3 is an NCNFET transistor, transistor T4 is a PCNFET transistor, the gate of transistor T3 is connected to the input signal IN, the source is connected to the ground GND, the drain is connected to the source of transistor T4 and the output terminal OUT, the gate of transistor T4 is connected to the input signal IN, the source is connected to the drain of T1 and further connected to the output terminal OUT, and the drain is connected to the power supply Vdd, the chirality vector of transistor T3 is (10, 0), and the chirality vector of transistor T4 is (19, 0), so that the positive ternary inverter PTI outputs 2 when the input is 0 and 1 when the input is When the input is 2, the output is 2, and when the input is 2, the output is 0; the ternary inverter STI is composed of transistors T5 to T10, the gate of transistor T5 is connected to the input signal IN, the source is connected to the ground GND, and the drain is connected to the source of transistor T7, the gate of transistor T6 is also connected to the input signal IN, the source is connected to the ground GND, and the drain is connected to the output terminal OUT, the gate of transistor T7 is connected to the drain of T7, the source is connected to the drain of transistor T5, the drain is connected to the gate of transistor T7, the drain of T8, and the output terminal OUT, the gate of transistor T8 is connected to the drain of T8, the source is connected to the source of transistor T9, the drain is connected to the drain of transistor T7 and further connected to the output terminal OUT; the gate of transistor T9 is connected to The input signal IN, the source is connected to the input signal IN and the source of transistor T8, the gate and drain of T10 are connected to the power supply Vdd, the gate of transistor T10 is connected to the input signal IN, the source is connected to the output terminal OUT, and the drain is connected to the power supply Vdd, transistor T5, transistor T6, and transistor T7 are all NCNFET transistors and the chirality vectors are (19, 0), (10, 0) and (13, 0) respectively, transistor T8, transistor T9, and transistor T10 are all PCNFET transistors and the chirality vectors are (13, 0), (19, 0) and (10, 0) respectively, so that the ternary inverter STI outputs 2 when the input is 0, outputs 1 when the input is 1, and outputs 0 when the input is 2.
[0007] Optionally, the logic unit circuit based on the CNFET device is a dual-input ternary NAND gate or a dual-input ternary NOR gate, the dual-input ternary NAND gate is composed of transistors T11 to T20, transistors T11 to T15 are NCNFET transistors, transistors T16 to T20 are PCNFET transistors, the chirality vectors of transistors T11, T13, T17, and T18 are all (19, 0), and the chirality vectors of transistors T12, T14, T19, and T20 are all (1 0,0), the chirality vectors of transistors T15 and T16 are both (13,0), the gate of transistor T11 is connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the source of transistor T13, the gate of transistor T12 is also connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the source of transistor T14, the gate of transistor T13 is connected to the input signal INA, the source is connected to the drain of transistor T11, and the drain is connected to the source of transistor T15, the gate of transistor T14 is connected to the input signal INA, the source is connected to the drain of transistor T11, and the drain is connected to the source of transistor T15. connected to the input signal INA, the source is connected to the drain of the transistor T12, the drain is connected to the output terminal OUT1, the gate of the transistor T15 is connected to the drain of T15, the source is connected to the drain of the transistor T13, the drain is connected to the gate of the transistor T15, the drain of the transistor T16, and the output terminal OUT1, the gate of the transistor T16 is connected to the drain of T16, the source is connected to the source of the transistor T18, the drain is connected to the gate of the transistor T16, and the drain of the transistor T15, the gate of the transistor T17 is connected to the input signal INA, the source is connected to the source of the transistor T18, the source of the transistor T16, and the drain is connected to the power supply Vdd, the gate of the transistor T18 is connected to the input signal INB, the source is connected to the source of the transistor T16, the drain is connected to the power supply Vdd, the gate of the transistor T19 is connected to INA, the source is connected to the source of the transistor T20, the output terminal OUT1, and the drain is connected to the power supply Vdd, the gate of the transistor T20 is connected to the input signal INB, the source is connected to the source of the transistor T19, the output terminal OUT1, and the drain is connected to the power supply Vdd;The dual-input ternary NOR gate is composed of transistors T21 to T30, wherein transistors T21 to T25 are NCNFET transistors, and transistors T26 to T30 are PCNFET transistors. The chirality vectors of transistors T21, T22, T27, and T29 are all (19, 0), the chirality vectors of transistors T23, T24, T28, and T30 are all (10, 0), and the chirality vectors of transistors T25 and T26 are (13, 0). The gate of transistor T21 is connected to the input signal INA, the source is connected to the ground GND, and the drain is connected to the drain of transistor T22 and the source of transistor T25. The gate of transistor T22 is connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the drain of transistor T21 and the source of transistor T25. The gate of transistor T23 is connected to the input signal INA, the source is connected to the ground GND, and the drain is connected to the output terminal OUT2. The gate of transistor T24 is connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the output terminal OUT2. The drain of transistor T25 is connected to the output terminal OUT2. The gate of transistor T25 is connected to the drain of transistor T25, the source is connected to the drain of transistor T21 and the drain of transistor T22, the drain is connected to the gate of transistor T25 and the drain of transistor T26, and the output terminal OUT2. The gate of transistor T26 is connected to the drain of transistor T26, the source is connected to the source of transistor T27 and the source of transistor T28, the drain is connected to the gate of transistor T26 and the drain of transistor T25, and the output terminal OUT2. The gate of transistor T27 is connected to the input signal INB, the source is connected to the source of transistor T28 and the source of transistor T26, and the drain is connected to the source of transistor T29. The gate of transistor T28 is connected to the input signal INB, the source is connected to the output terminal OUT2, and the drain is connected to the source of T30. The gate of transistor T29 is connected to INA, the source is connected to the drain of transistor T27, and the drain is connected to the power supply Vdd. The gate of transistor T30 is connected to the input signal INA, the source is connected to the gate of transistor T28, and the drain is connected to the power supply Vdd.
[0008] Optionally, the logic unit circuit based on the CNFET device is a low threshold comparison-medium-high output circuit GTL-BH() and an equal threshold comparison-medium-high output circuit EQL-BH(), wherein the low threshold comparison-medium-high output circuit GTL-BH() is composed of a positive ternary inverter PTI and a negative ternary inverter NTI connected in series, so that when the input of the low threshold comparison-medium-high output circuit GTL-BH() is logic 2, the output is logic 2, and when the input is logic 0 or 1, the output is logic 0; the equal threshold comparison-medium-high output circuit EQL-B The H() circuit consists of two negative ternary inverters NTI, a positive ternary inverter PTI and a NOR gate. The input signals are respectively sent to the two negative ternary inverters NTI, wherein the output of one negative ternary inverter NTI is directly used as the first input of the NOR gate, and the output of the other negative ternary inverter NTI is used as the second input of the NOR gate after passing through a positive ternary inverter PTI, so that the equal threshold comparator-medium-high output circuit EQL-BH() outputs a logic 2 when the input is a logic 1, and outputs a logic 0 when the input is a logic 0 or 2.
[0009] Optionally, the logic unit circuit based on the CNFET device is a ternary XOR gate, which is composed of four NAND gates and includes two input variables INA and INB and an output variable XOR. The NAND gate is a dual-input ternary NAND gate, and the input signal INA is simultaneously connected to one input terminal of the first NAND gate and one input terminal of the second NAND gate; the input signal INB is simultaneously connected to the other input terminal of the first NAND gate and one input terminal of the third NAND gate; the output of the first NAND gate is connected to the other input terminal of the second NAND gate and the other input terminal of the third NAND gate, and the output of the second NAND gate is connected to the third NAND gate. The output is connected to the two input terminals of the fourth NAND gate, and the fourth NAND gate is connected to the output terminal Q to obtain the output variable XOR, so that when the input variable INA is 0 and INB is 0, the output variable XOR is 0; when the input variable INA is 0 and INB is 1, the output variable XOR is 1; when the input variable INA is 0 and INB is 2, the output variable XOR is 2; when the input variable INA is 1 and INB is 1, the output variable XOR is 1; when the input variable INA is 1 and INB is 2, the output variable XOR is 1; when the input variable INA is 2 and INB is 2, the output variable XOR is 0.
[0010] Optionally, the logic unit circuit based on the CNFET device is a ternary D latch circuit, which is composed of four NAND gates NAND 1 to NAND gate 4, a negative ternary inverter NTI and a ternary inverter STI, and includes an enable terminal EN, an input terminal DIN and an output terminal Q; the NAND gates NAND 1 to NAND gate 4 are all dual-input ternary NAND gates; the data input DIN is directly connected to one input terminal of the NAND gate NAND 1 and the input terminal of the ternary inverter STI; the enable signal EN is connected to the negative ternary inverter NTI, and after inversion processing, is connected to the other input terminal of the NAND gate NAND 1 and one input terminal of the NAND gate NAND 2; the ternary inverter STI is connected to the other input terminal of the NAND gate NAND 2; the output of the NAND gate NAND 1 is connected to one input terminal of the NAND gate NAND 3, and the output of the NAND gate NAND 2 is connected to one input terminal of the NAND gate NAND 4; the NAND gate NAND 3 A cross-coupling structure is formed with the NAND gate NAND 4, so that the output of the NAND gate NAND 3 is not only connected to the normal output Q of the circuit but also to the other input terminal of the NAND gate NAND 4; the output of the NAND gate NAND 4 is used as the inverted output and is also connected to the other input terminal of the NAND gate NAND 3. When the enable terminal EN is at a low level (a logic 0), the D latch circuit samples the input terminal DIN, and the output terminal Q changes with the change of the input terminal DIN. When the enable terminal EN is at a high level (a logic 2), the value of the output terminal Q before the change of the enable terminal EN remains unchanged until the enable terminal EN becomes a low level again, at which time the input terminal DIN is sampled again.
[0011] Optionally, before the method of adjusting the structural parameters of the CNFET device multiple times and simulating the structural parameters after each adjustment to obtain the average conversion delay time of the optimized logic unit circuit based on the CNFET device, it also includes: using the optimized logic unit circuit based on the CNFET device to build a specified logic circuit, and simulating the built specified logic circuit through HSPICE to obtain its truth table. If the obtained truth table is consistent with the theoretical truth table, it is determined that the logic verification of the optimized logic unit circuit based on the CNFET device has passed.
[0012] In addition, the present invention also provides an optimization system for a logic unit circuit based on a CNFET device, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the optimization method for the logic unit circuit based on the CNFET device.
[0013] In addition, the present invention also provides a computer-readable storage medium, which stores a computer program or instruction. The computer program or instruction is programmed or configured to execute the optimization method of the logic unit circuit based on the CNFET device through a processor.
[0014] In addition, the present invention also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the method for optimizing a logic unit circuit based on a CNFET device through a processor.
[0015] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: 1. The method of the present invention comprises adjusting the structural parameters of the CNFET device multiple times and simulating the structural parameters after each adjustment to obtain the average conversion delay time of the optimized logic unit circuit based on the CNFET device, and selecting the structural parameters corresponding to the optimal average conversion delay time as the optimal structural parameters of the optimized logic unit circuit based on the CNFET device. The structural parameters of the CNFET device include the physical channel length of the CNFET device. , source length and drain length Part or all of the , thus being able to optimize logic cell circuits based on CNFET devices to reduce average switching delay and improve circuit performance and speed.
[0016] 2. The present invention is applicable to various logic unit circuits based on CNFET devices and has the advantage of good versatility. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 Schematic diagram of the basic process of the method of the embodiment of the present invention.
[0018] Figure 2 Schematic diagram of the threshold voltage of a CNFET device for n (m = 0) in an embodiment of the present invention.
[0019] Figure 3 2 is a relationship diagram of the logical transfer functions in an embodiment of the present invention.
[0020] Figure 4 4 is a circuit diagram of a negative ternary inverter NTI in an embodiment of the present invention.
[0021] Figure 5 4 is a circuit diagram of a positive ternary inverter PTI in an embodiment of the present invention.
[0022] Figure 6Schematic diagram of the symbols of the negative ternary inverter NTI and the positive ternary inverter PTI in an embodiment of the present invention, where (a) is the symbol of the negative ternary inverter NTI, and (b) is the symbol of the positive ternary inverter PTI.
[0023] Figure 7 FIG. 4 is a circuit diagram of a ternary inverter STI according to an embodiment of the present invention.
[0024] Figure 8 These are the simulation results of three ternary inverters in the embodiments of the present invention.
[0025] Figure 9 4 is a circuit diagram of a dual-input ternary NAND gate in an embodiment of the present invention.
[0026] Figure 10 4 is a circuit diagram of a dual-input ternary NOR gate in an embodiment of the present invention.
[0027] Figure 11 1 is the simulation result of the dual-input ternary NAND gate and NOR gate in the embodiment of the present invention.
[0028] Figure 12 FIG. 4 is a circuit diagram of a low threshold comparison-medium-high output circuit GTL-BH() in an embodiment of the present invention.
[0029] Figure 13 FIG. 4 is a circuit diagram of an equal threshold comparison-medium-high output circuit EQL-BH() in an embodiment of the present invention.
[0030] Figure 14 1 and 2 are simulation results of the low threshold comparison-medium-high output circuit GTL-BH() and the equal threshold comparison-medium-high output circuit EQL-BH() in the embodiments of the present invention.
[0031] Figure 15 4 is a circuit diagram of a ternary XOR gate in an embodiment of the present invention.
[0032] Figure 16 4 is the simulation result of the ternary XOR gate in the embodiment of the present invention.
[0033] Figure 17 4 is a circuit diagram of a ternary D latch circuit in an embodiment of the present invention.
[0034] Figure 18 1 is a simulation result of a ternary D latch circuit in an embodiment of the present invention.
[0035] Figure 19 4 is a circuit diagram of a one-bit multiplier in an embodiment of the present invention.
[0036] Figure 20 This is the simulation result of a one-bit multiplier in an embodiment of the present invention.
[0037] Figure 21 1-bit multiplier average conversion delay comparison diagram of the embodiment of the present invention and the existing method. DETAILED DESCRIPTION
[0038] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.
[0039] like Figure 1 As shown, the optimization method of the logic unit circuit based on the CNFET device of this embodiment includes: for the optimized logic unit circuit based on the CNFET device, adjusting the structural parameters of the CNFET device multiple times and simulating the structural parameters after each adjustment to obtain the average conversion delay time of the optimized logic unit circuit based on the CNFET device, and selecting the structural parameters corresponding to the optimal average conversion delay time as the optimal structural parameters of the optimized logic unit circuit based on the CNFET device. The structural parameters of the CNFET device include the physical channel length of the CNFET device. , source length and drain length (You can also adjust only part of it.) The principle of optimizing the average conversion delay in this embodiment is as follows: The delay of the CNFET device can be expressed as: , , , , in, is the delay of the CNFET device, is the pre-factor of the gate parasitic capacitance, is the prefactor for the extended series resistance, is the gate capacitance, is the gate length, is the power supply voltage, For the transconductance of each carbon nanotube, is the threshold voltage of the carbon nanotube transistor, is the gate-to-gate parasitic capacitance, is the gate width, is the number of carbon nanotubes, is the source length, is the source resistance per unit length of the doped carbon nanotube, is a measure of the intrinsic gate delay of a single CNT without considering source / drain series resistance and parasitic capacitance. Therefore, the intrinsic speed of a CNFET device is pre-factored by the gate parasitic capacitance. and the pre-factor of the extended series resistance Within the quantum capacitance limit of high-performance CNFET devices, is almost constant, in traditional device scaling scenarios, and / The ratios of are constant. Therefore, decreases with the increase of the number of carbon nanotubes per device. On the other hand, is almost constant, limited by the maximum achievable doping level, and is also constant. Therefore, As the source / drain length Therefore, the actual circuit diagram can be combined with the actual circuit diagram to adjust the physical channel length multiple times. and source / drain length and After simulating the parameters, the optimal result of average conversion delay time was obtained.
[0040] The logic unit circuit based on CNFET devices in this embodiment is a ternary logic circuit. Compared with traditional binary logic, ternary logic also contains an additional logic value, which is usually called "undetermined". In this embodiment, logic 0 represents false, logic 1 represents undetermined, and logic 2 represents true. The following is the basic arithmetic definition of ternary logic: , (1) , (2) , (3) in, is the operand, . The three equations (1), (2) and (3) above are respectively called OR, AND and NOT in ternary logic. According to the assumed logic symbols 0, 1, 2, and the arithmetic definitions of equations (1) to (3), basic gates in digital logic systems can be designed, such as inverters, NAND, and NOR. CNFET (Carbon Nanotube Field-Effect Transistors) devices are field-effect transistors based on carbon nanotubes with unique electron transport properties. The structure of CNFET devices consists of a single or multiple carbon nanotubes, which can be divided into n-type (NCNFET) and p-type (PCNFET), which are used to carry electrons and holes, respectively. The angle at which the atoms of a single-walled carbon nanotube are arranged along the tube is called the chirality vector, which is represented by the integer pair ( n , m ) to express that the chirality vector determines whether the single-walled carbon nanotube is a metallic conductor or a semiconductor. n =m or n - m =3i, i When is an integer, the single-walled carbon nanotube is a conductor, otherwise it is a semiconductor. The threshold voltage of the intrinsic CNT can be approximated as half the band gap in the first order, which is an inverse function of the diameter: , (4) in, is the threshold voltage, is the band gap, is the unit electron charge, is the distance between carbon atoms ( ), Carbon for fastening Bond energy ( ), is the diameter of the carbon nanotube. The threshold voltages of the n-type CNFET device (NCNFET) and the p-type CNFET device (PCNFET) obtained from Equation (4), as well as various chiral vectors ( m =0 n The results of HSPICE simulation are as follows: Figure 2 shown.
[0041] CNFETs play a key role in ternary logic circuit design. Due to the excellent properties of CNFETs, such as high electron mobility and low power consumption, they are an ideal choice for implementing high-performance, low-power ternary logic gates. By leveraging the characteristics of CNFETs, designers can implement more complex ternary logic functions, including flexible processing of 0, 1, and unknown states. The high integration density and nanoscale characteristics of CNFETs make it possible to achieve more compact designs in ternary logic circuits while maintaining high performance under different input states.
[0042] To build a standard cell library for ternary logic, a complete set of ternary logic operations is required. The binary complete set of operations consists of three logical operations: NOT, AND, and OR. Existing technology has proven six combinations of the complete set of ternary logic operations. Each combination constitutes an independent complete set of operations, which can be implemented as follows: (1) GTL-BH(), EQL-BH(), LTL-BH(), ,
[0043] (2) GEL-BH(), NEL-BH(), LEL-BH(), ,
[0044] (3) GTL-BL(), EQL-BL(), LTL-BL(), ,
[0045] (4) GEL-BL(), NEL-BL(), LEL-BL(), ,
[0046] (5) GTL-LH(), EQL-LH(), LTL-LH(), ,
[0047] (6) GEL-LH(), NEL-LH(), LEL-LH(), ,
[0048] Among them, H, B, and L represent the "high", "medium", and "low" states of three-valued logic respectively; the suffixes "-BH, -BL, and -LH" indicate that the output states of the logic function are "BH", "BL", and "LH", respectively. GTL represents the logic function "greater than Low", that is, ">". Similarly, EQL is the logic function "Equal", that is, "="; LTL is the logic function "less than Low", that is, "<"; GEL is the logic function "greater than or equal to Low", that is, "≥"; NEL is the logic "not equal to Low", that is, "≠"; LEL is "less than or equal to Low", that is, "≤"; is the ternary "BH" transfer logic "AND", + is the ternary "BH" transfer logic "OR"; and is the ternary "BL" transfer logic "AND", is a ternary "BL" transfer logical "OR"; is the ternary "LH" transfer logic "AND", is a ternary "LH" transfer logical "OR". The relationship between these logical transfer functions can be expressed as follows Figure 3 shown.
[0049] As an optional implementation, the logic unit circuit based on the CNFET device can be a negative ternary inverter NTI. Figure 4As shown, the negative ternary inverter NTI is composed of transistors T1 and T2, where transistor T1 is an NCNFET transistor and transistor T2 is a PCNFET transistor. The gate of transistor T1 is connected to the input signal IN, the source is grounded GND, and the drain is connected to the source of T2 and the output terminal OUT. The gate of transistor T2 is connected to the input signal IN, the source is connected to the drain of transistor T1 and the output terminal OUT, and the drain is connected to the power supply Vdd. The chirality vector of transistor T1 is (19, 0), that is, the threshold voltage is 0.289V, and the chirality vector of transistor T2 is (10, 0). , that is, the threshold voltage is -0.557V respectively. Since the power supply Vdd is 0.9V, when the input voltage is lower than 0.3V (logic 0), transistor T1 is OFF, transistor T2 is ON, and the output OUT is 0.9V (logic 2). When the input voltage exceeds 0.3V, transistor T1 is ON, transistor T2 is OFF, and the output OUT is 0 (logic 0). That is, the negative ternary inverter NTI outputs 2 when the input is 0, and outputs 0 when the input is 1 or 2.
[0050] As an optional implementation, the logic unit circuit based on the CNFET device can be a positive ternary inverter PTI. Figure 5 As shown, the positive ternary inverter PTI is composed of transistors T3 and T4. Transistor T3 is an NCNFET transistor, and transistor T4 is a PCNFET transistor. The gate of transistor T3 is connected to the input signal IN, the source is connected to the ground GND, and the drain is connected to the source of transistor T4 and the output terminal OUT. The gate of transistor T4 is connected to the input signal IN, the source is connected to the drain of T1 and further connected to the output terminal OUT, and the drain is connected to the power supply Vdd. The chirality vector of transistor T3 is (10, 0). The chirality vector of transistor T4 is (19,0), that is, the threshold voltages of transistors T3 and T4 are 0.557V and -0.289V respectively. When the input voltage is lower than 0.6V (logic 1), T3 is OFF, T4 is ON, and the output OUT is 0.9V (logic 2). When the input voltage exceeds 0.6V, T3 is ON, T4 is OFF, and the output OUT is 0 (logic 0), so that the positive ternary inverter PTI outputs 2 when the input is 0, outputs 2 when the input is 1, and outputs 0 when the input is 2. Figure 6 Schematic diagram of the symbols of the negative ternary inverter NTI and the positive ternary inverter PTI in this embodiment, where (a) is the symbol of the negative ternary inverter NTI, and (b) is the symbol of the positive ternary inverter PTI.
[0051] As an optional implementation, the logic unit circuit based on the CNFET device can be a ternary inverter STI. Figure 7As shown, the ternary inverter STI is composed of transistors T5 to T10, the gate of transistor T5 is connected to the input signal IN, the source is connected to the ground GND, and the drain is connected to the source of transistor T7, the gate of transistor T6 is also connected to the input signal IN, the source is connected to the ground GND, and the drain is connected to the output terminal OUT, the gate of transistor T7 is connected to the drain of T7, the source is connected to the drain of transistor T5, the drain is connected to the gate of transistor T7, the drain of T8, and the output terminal OUT, the gate of transistor T8 is connected to the drain of T8, the source is connected to the source of transistor T9, the drain is connected to the drain of transistor T7 and further connected to the output terminal OUT; the gate of transistor T9 is connected to the input signal IN, the source is connected to the input signal IN and the source of transistor T8, the gate and drain of T10 are connected to the power supply. Source Vdd, the gate of transistor T10 is connected to the input signal IN, the source is connected to the output terminal OUT, and the drain is connected to the power supply Vdd. Transistor T5, transistor T6, and transistor T7 are all NCNFET transistors and the chirality vectors are (19, 0), (10, 0), and (13, 0), respectively, that is, the threshold voltages are 0.289V, 0.557V, and 0.428V, respectively. Transistor T8, transistor T9, and transistor T10 are all PCNFET transistors and the chirality vectors are (13, 0), (19, 0), and (10, 0), respectively. When the input voltage is lower than 0.3V, transistors T9 and T10 are ON, transistors T5 and T6 are OFF, and the output is 0.9V (logic 2). When the input voltage is 0.3V-0.6V, transistors T5 and T9 are ON. Transistors T6 and T10 are OFF, and the output voltage is 0.45V (logic 1). When the input voltage exceeds 0.6V, transistor T6 is ON, transistors T9 and T10 are OFF, and the output is 0 (logic 0). That is, the ternary inverter STI outputs 2 when the input is 0, outputs 1 when the input is 1, and outputs 0 when the input is 2.
[0052] The NOT gate is one of the most basic unit logic gates. A ternary inverter usually has one input and three outputs: a false NOT is true, and a true NOT is false. However, the indeterminate state in the three-valued logic, that is, the output of logic 1 defined in this article, has three values: 0, 1, and 2. This requires three inverters to be implemented in the ternary inverter: a negative ternary inverter NTI, a positive ternary inverter PTI, and a standard ternary inverter STI. The truth table of the negative ternary inverter NTI, the positive ternary inverter PTI, or the ternary inverter STI in this embodiment is shown in Table 1.
[0053] Table 1: Truth table of three inverters
[0054] According to the circuit diagram of the negative ternary inverter NTI, the positive ternary inverter PTI or the ternary inverter STI, this embodiment builds the circuit of the negative ternary inverter NTI, the positive ternary inverter PTI or the ternary inverter STI and simulates it through HSPICE. Figure 8 The simulation results of three ternary inverters are shown in Figure 8 It can be seen that the negative ternary inverter NTI, the positive ternary inverter PTI or the ternary inverter STI meets the circuit principle in the schematic diagram.
[0055] In this embodiment, the logic unit circuit based on the CNFET device can be a dual-input ternary NAND gate or a dual-input ternary NOR gate. The principles of the dual-input ternary NAND gate and NOR gate are similar to those of building NAND gates and NOR gates using MOS for binary logic.
[0056] As an optional implementation, the logic unit circuit based on the CNFET device can be a dual-input ternary NAND gate, such as Figure 9As shown, the dual-input ternary NAND gate is composed of transistors T11 to T20, where transistors T11 to T15 are NCNFET transistors, and transistors T16 to T20 are PCNFET transistors. The chirality vectors of transistors T11, T13, T17, and T18 are all (19, 0), the chirality vectors of transistors T12, T14, T19, and T20 are all (10, 0), and the chirality vectors of transistors T15 and T16 are all (13, 0). The gate of transistor T11 is connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the source of transistor T13. The gate of transistor T12 is also connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the source of transistor T14. The gate of transistor T13 is connected to the input signal INA, the source is connected to the drain of transistor T11, and the drain is connected to the source of transistor T15. The gate of transistor T14 is connected to the input signal INA, the source is connected to the drain of transistor T11, and the drain is connected to the source of transistor T15. 2, the drain is connected to the output terminal OUT1, the gate of transistor T15 is connected to the drain of T15, the source is connected to the drain of transistor T13, the drain is connected to the gate of transistor T15, the drain of transistor T16, and the output terminal OUT1, the gate of transistor T16 is connected to the drain of T16, the source is connected to the source of transistor T18, the drain is connected to the gate of transistor T16, and the drain of transistor T15, the gate of transistor T17 is connected to the input signal INA, the source is connected to the source of transistor T18, the source of transistor T16, and the drain is connected to the power supply Vdd, the gate of transistor T18 is connected to the input signal INB, the source is connected to the source of transistor T16, and the drain is connected to the power supply Vdd, the gate of transistor T19 is connected to INA, the source is connected to the source of transistor T20, the output terminal OUT1, and the drain is connected to the power supply Vdd, the gate of transistor T20 is connected to the input signal INB, the source is connected to the source of transistor T19, the output terminal OUT1, and the drain is connected to the power supply Vdd; As an optional implementation, the logic unit circuit based on the CNFET device can be a dual-input ternary NOR gate, such as Figure 10As shown, the dual-input ternary NOR gate is composed of transistors T21 to T30, transistors T21 to T25 are NCNFET transistors, transistors T26 to T30 are PCNFET transistors, the chirality vectors of transistors T21, T22, T27, and T29 are all (19, 0), the chirality vectors of transistors T23, T24, T28, and T30 are all (10, 0), the chirality vectors of transistors T25 and T26 are (13, 0), the gate of transistor T21 is connected to the input signal INA, the source is connected to the ground GND, the drain is connected to the drain of transistor T22 and the source of transistor T25, the gate of transistor T22 is connected to the input signal INB, the source is connected to the ground GND, the drain is connected to the drain of transistor T21 and the source of transistor T25, the gate of transistor T23 is connected to the input signal INA, the source is connected to the ground GND, and the drain is connected to the output terminal OUT2, the gate of transistor T24 is connected to the input signal INB, the source is connected to the ground GND, The drain is connected to the output terminal OUT2, the gate of transistor T25 is connected to the drain of T25, the source is connected to the drain of transistor T21 and the drain of transistor T22, the drain is connected to the gate of transistor T25 and the drain of transistor T26, and the output terminal OUT2, the gate of transistor T26 is connected to the drain of T26, the source is connected to the source of transistor T27 and the source of transistor T28, the drain is connected to the gate of transistor T26 and the drain of transistor T25, and the output terminal OUT2, the gate of transistor T27 is connected to the input signal INB, the source is connected to the source of transistor T28 and the source of transistor T26, and the drain is connected to the source of transistor T29, the gate of transistor T28 is connected to the input signal INB, the source is connected to the output terminal OUT2, and the drain is connected to the source of T30, the gate of transistor T29 is connected to INA, the source is connected to the drain of transistor T27, and the drain is connected to the power supply Vdd, and the gate of transistor T30 is connected to the input signal INA, the source is connected to the gate of transistor T28, and the drain is connected to the power supply Vdd. The circuit schematics for the dual-input ternary NAND and NOR gates are identical to those for the ternary STI inverter, constructed using CNFET devices with chiral vectors of (19, 0), (13, 0), and (10, 0). Similar to binary logic, the ternary NAND gate builds on the STI ternary inverter by adding two PCNFETs in parallel and two NCNFETs in series. The ternary NOR gate uses two PCNFETs in series and two NCNFETs in parallel. The truth table for the dual-input ternary NAND and NOR gates is shown in Table 2.
[0057] Table 2: Truth table of a two-input ternary NAND gate or a two-input ternary NOR gate
[0058] In this embodiment, ten CNFETs are used to build a dual-input ternary NAND gate and a NOR gate according to the circuit diagram, and HSPICE is used for simulation. The results are as follows: Figure 11 As shown, see Figure 11 It can be seen that the dual-input ternary NAND gate and NOR gate successfully realize the NAND and NOR functions.
[0059] As an optional implementation, the logic unit circuit based on the CNFET device can be a low threshold comparison-medium high output circuit GTL-BH() and, as shown in FIG. Figure 12 As shown, the low threshold comparator-medium-high output circuit GTL-BH() is composed of a positive ternary inverter PTI and a negative ternary inverter NTI connected in series, so that when the input of the low threshold comparator-medium-high output circuit GTL-BH() is logic 2, the output is logic 2, and when the input is logic 0 or 1, the output is logic 0.
[0060] As an optional implementation, the logic unit circuit based on the CNFET device can be a low threshold comparison-medium high output circuit GTL-BH() and, as shown in FIG. Figure 13 As shown, the equal threshold comparison-mid-high output circuit EQL-BH() is composed of two negative ternary inverters NTI, a positive ternary inverter PTI and a NOR gate. The input signals are respectively sent to the two negative ternary inverters NTI, where the output of one negative ternary inverter NTI is directly used as the first input of the NOR gate, and the output of the other negative ternary inverter NTI is used as the second input of the NOR gate after passing through a positive ternary inverter PTI, so that the equal threshold comparison-mid-high output circuit EQL-BH() outputs a logic 2 when the input is a logic 1, and outputs a logic 0 when the input is a logic 0 or 2.
[0061] In this embodiment, a medium-low threshold comparison-medium-high output circuit GTL-BH() and an equal threshold comparison-medium-high output circuit EQL-BH() were built according to the circuit diagram and simulated using HSPICE. The results are as follows: Figure 14 As shown, see Figure 14 It can be seen that the low threshold comparison-medium-high output circuit GTL-BH() and the equal threshold comparison-medium-high output circuit EQL-BH() successfully realize their logic functions.
[0062] As an optional implementation, the logic unit circuit based on CNFET devices can be an LTL-BH() circuit. The LTL-BH() circuit is an NTI circuit that realizes the function of outputting a logic 2 when the input is a logic 0, and outputting a logic 0 when the input is a logic 1 or 2.
[0063] As an optional implementation, the logic unit circuit based on the CNFET device may be an "AND" circuit, where the "AND" circuit is a circuit obtained by connecting a dual-input ternary NAND gate and a ternary inverter STI in series.
[0064] As an optional implementation, the logic unit circuit based on the CNFET device may be an "OR" circuit, which is a circuit obtained by connecting a dual-input ternary NOR gate and a ternary inverter STI in series.
[0065] As an optional implementation, the logic unit circuit based on the CNFET device can be a ternary XOR gate, such as Figure 15 As shown, the ternary XOR gate is composed of four NAND gates and includes two input variables INA and INB and an output variable XOR. The NAND gate is a dual-input ternary NAND gate. The input signal INA is simultaneously connected to one input terminal of the first NAND gate and one input terminal of the second NAND gate; the input signal INB is simultaneously connected to the other input terminal of the first NAND gate and one input terminal of the third NAND gate. The output of the first NAND gate is connected to the other input terminal of the second NAND gate and the other input terminal of the third NAND gate. The output of the second NAND gate and the output of the third NAND gate are connected to the two input terminals of the fourth NAND gate. Four NAND gates are connected to the output terminal Q to obtain the output variable XOR, so that when the input variable INA is 0 and INB is 0, the output variable XOR is 0; when the input variable INA is 0 and INB is 1, the output variable XOR is 1; when the input variable INA is 0 and INB is 2, the output variable XOR is 2; when the input variable INA is 1 and INB is 1, the output variable XOR is 1; when the input variable INA is 1 and INB is 2, the output variable XOR is 1; when the input variable INA is 2 and INB is 2, the output variable XOR is 0, and its truth table is shown in Table 3.
[0066] Table 3: Truth table of a ternary XOR gate
[0067] In this embodiment, a ternary XOR gate is built according to the circuit diagram and simulated using HSPICE. The results are as follows: Figure 16 As shown, see Figure 16 It can be seen that the ternary XOR gate successfully realizes its logical function.
[0068] As an optional implementation, the logic unit circuit based on the CNFET device can be a three-valued D latch circuit, such as Figure 17As shown, the ternary D latch circuit is composed of four NAND gates NAND 1 to NAND gate 4, a negative ternary inverter NTI and a ternary inverter STI, and includes an enable terminal EN, an input terminal DIN and an output terminal Q; the NAND gates NAND 1 to NAND gate 4 are all dual-input ternary NAND gates; the data input DIN is directly connected to one input terminal of the NAND gate NAND 1 and the input terminal of the ternary inverter STI; the enable signal EN is connected to the negative ternary inverter NTI, and after inversion processing, is connected to the other input terminal of the NAND gate NAND 1 and one input terminal of the NAND gate NAND 2; the ternary inverter STI is connected to the other input terminal of the NAND gate NAND 2; the output of the NAND gate NAND 1 is connected to one input terminal of the NAND gate NAND 3, and the output of the NAND gate NAND 2 is connected to one input terminal of the NAND gate NAND 4; the NAND gates NAND 3 and NAND 4 A cross-coupling structure is formed, so that the output of the NAND gate NAND 3 is not only connected to the normal output Q of the circuit but also to the other input terminal of the NAND gate NAND 4; the output of the NAND gate NAND 4 is used as the inverted output and is also connected to the other input terminal of the NAND gate NAND 3. When the enable terminal EN is at a low level, which represents a logic 0, the D latch circuit samples the input terminal DIN and the output terminal Q changes with the change of the input terminal DIN. When the enable terminal EN is at a high level, which represents a logic 2, the value of the output terminal Q before the change of the enable terminal EN remains unchanged until the enable terminal EN becomes a low level again, and then the input terminal DIN is sampled again. In this embodiment, a three-valued D latch circuit is built according to the circuit diagram and simulated using HSPICE. The results are as follows: Figure 18 As shown, see Figure 18 It can be seen that the three-valued D latch circuit successfully realizes its logical function.
[0069] As an optional implementation, before the average conversion delay time of the optimized logic unit circuit based on the CNFET device is obtained by adjusting the structural parameters of the CNFET device multiple times and simulating the structural parameters after each adjustment, it also includes: using the optimized logic unit circuit based on the CNFET device to build a specified logic circuit, and simulating the built specified logic circuit through HSPICE to obtain its truth table. If the obtained truth table is consistent with the theoretical truth table, it is determined that the logic verification of the optimized logic unit circuit based on the CNFET device has passed. For example, as an optional implementation, the specified logic circuit in this embodiment is a one-bit multiplier. The circuit diagram of the one-bit multiplier is as shown below. Figure 19As shown, the one-bit multiplier has input signal terminals INA and INB for receiving external signals, multiple inverters perform inversion operations on INA and INB to change the signal logic states, multiple AND gates perform logical AND operations, and multiple OR gates perform logical OR operations. Product is the multiplication result output terminal, Carry is the carry output terminal, and Vdd / 2 is used to provide a specific bias voltage. INA and INB are connected to multiple inverters respectively, and their inverter outputs and themselves are connected to multiple AND gate inputs in different combinations. The AND gate outputs are then connected to the OR gate inputs, some of which are connected to the gates that generate Product, and some of which are connected to the gates that generate Carry. The way in which a one-bit multiplier obtains the product and carry for the input multipliers A and B is: when multiplier A is 0 and multiplier B is 0, the product is 0 and the carry is 0; when multiplier A is 0 and multiplier B is 1, the product is 0 and the carry is 0; when multiplier A is 0 and multiplier B is 2, the product is 0 and the carry is 0; when multiplier A is 1 and multiplier B is 1, the product is 1 and the carry is 0; when multiplier A is 1 and multiplier B is 2, the product is 2 and the carry is 0; when multiplier A is 2 and multiplier B is 2, the product is 1 and the carry is 1. Its truth table is shown in Table 4.
[0070] Table 4: Truth table for a one-bit multiplier
[0071] In this embodiment, a one-bit multiplier is built according to the circuit diagram and simulated using HSPICE. The results are as follows: Figure 20 As shown, see Figure 20 It can be seen that the one-bit multiplier successfully realizes its logical function, indicating that the designed unit circuit can meet the design requirements of more complex circuits.
[0072] In order to verify the optimization method of the logic unit circuit based on the CNFET device in this embodiment, a simulation experiment was conducted in this embodiment. In the experiment, it was found that the physical channel length of the CNFET device is The source length of the CNFET device has been reduced from 32nm to 25nm. and drain length The optimum value is when the thickness is reduced from 32nm to 1nm, as shown in Table 5.
[0073] Table 5: Comparison of average circuit delay time
[0074] In Table 5, the circuit names in the first column are the names of the different optimized CNFET-based logic unit circuits, including: negative ternary inverter NTI (NTI), positive ternary inverter PTI (PTI) or ternary inverter STI (STI), dual-input ternary NAND gate (NAND) or dual-input ternary NOR gate (NOR), ternary XOR gate (XOR), and ternary D-latch circuit (D-latch). As shown in Table 1, compared with previous work, the method of this embodiment significantly reduces the average conversion delay time of each CNFET-based ternary logic circuit. Among them, the average conversion delay time of the XOR circuit, which has the smallest reduction, is reduced by 58.97%, and the average conversion delay time of the NAND circuit, which has the largest reduction, is reduced by 76.61%. It can be seen that the method of this embodiment has achieved significant results in optimizing the average circuit delay in various optimized CNFET-based logic unit circuits.
[0075] In addition, the average conversion delay of the 1-bit multiplier based on CNFET devices is also verified in this embodiment, and the results are as follows: Figure 21As shown, prior art 1 to prior art 3 are the average conversion delays of 1-bit multipliers obtained by existing unoptimized methods. Prior art 1 refers to the literature: Raychowdhury and K. Roy, “Carbon-nanotube-based voltage-mode multiple-valued logic design,” IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 168–179, Mar. 2005. Prior art 2 refers to the literature: P. Dhande and VTIngole, “Design \&Implementation of 2-Bit Ternary ALU slice,” in Proc. Int.Conf. IEEE-Sci. Electron., Technol. Inf. Telecommun., Mar. 2005, pp. 17–21. Prior art 3, see reference: S. Lin, Y. -B. Kim and F. Lombardi, "CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits," in IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 217-225, March 2011, doi: 10.1109 / TNANO.2009.2036845. Figure 21 It can be seen that the average conversion delay time of the 1-bit multiplier obtained by the method of this embodiment is significantly reduced compared to the 1-bit multiplier of the existing method, which is 47ps lower than the average conversion delay time of the 1-bit multiplier in the existing technology 3. The results show that the method of this embodiment optimizes the physical channel length. , source length and drain length The ternary logic circuit built with the CNFET device has a lower average conversion delay than the ternary logic circuit built with the CNFET device without adjusting the parameters.
[0076] In addition, this embodiment also provides an optimization system for a logic unit circuit based on a CNFET device, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the optimization method for the logic unit circuit based on the CNFET device.
[0077] In addition, this embodiment also provides a computer-readable storage medium, which stores a computer program or instruction. The computer program or instruction is programmed or configured to execute the optimization method of the logic unit circuit based on the CNFET device through a processor.
[0078] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the method for optimizing the logic unit circuit based on the CNFET device through a processor.
[0079] Those skilled in the art should understand that the technical solutions that can be provided by the embodiments of the present invention may be in the form of methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment that combines software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0080] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.
Claims
1. A method for optimizing a logic unit circuit based on a CNFET device, characterized in that: include: For the optimized logic unit circuit based on CNFET devices, the average conversion delay time of the optimized logic unit circuit based on CNFET devices is obtained by adjusting the structural parameters of the CNFET devices multiple times and simulating the structural parameters after each adjustment, and the structural parameters corresponding to the optimal average conversion delay time are selected as the optimal structural parameters of the optimized logic unit circuit based on CNFET devices. The structural parameters of the CNFET devices include the physical channel length of the CNFET devices. , source length and drain length Part or all of .
2. The method for optimizing a logic unit circuit based on a CNFET device according to claim 1, wherein: The logic unit circuit based on the CNFET device is a negative ternary inverter NTI, a positive ternary inverter PTI or a ternary inverter STI. The negative ternary inverter NTI is composed of transistors T1 and T2. The transistor T1 is an NCNFET transistor and the transistor T2 is a PCNFET transistor. The gate of the transistor T1 is connected to the input signal IN, the source is grounded GND, the drain is connected to the source of T2 and connected to the output terminal OUT. The gate of the transistor T2 is connected to the input signal IN, the source is connected to the drain of the transistor T1 and the output terminal OUT, and the drain is connected to the power supply Vdd. The chirality vector of the transistor T1 is (19, 0) and the chirality vector of the transistor T2 is (10, 0). When the input is 0, the output is 2, and when the input is 1 or 2, the output is 0; the positive ternary inverter PTI is composed of transistors T3 and T4, transistor T3 is an NCNFET transistor, transistor T4 is a PCNFET transistor, the gate of transistor T3 is connected to the input signal IN, the source is connected to the ground GND, the drain is connected to the source of transistor T4 and the output terminal OUT, the gate of transistor T4 is connected to the input signal IN, the source is connected to the drain of T1 and further connected to the output terminal OUT, and the drain is connected to the power supply Vdd, the chirality vector of transistor T3 is (10, 0), and the chirality vector of transistor T4 is (19, 0), so that the positive ternary inverter PTI outputs 2 when the input is 0, and outputs 1 when the input is 1. When the output is 2, the output is 0 when the input is 2; the ternary inverter STI is composed of transistors T5 to T10, the gate of transistor T5 is connected to the input signal IN, the source is connected to the ground GND, and the drain is connected to the source of transistor T7, the gate of transistor T6 is also connected to the input signal IN, the source is connected to the ground GND, and the drain is connected to the output terminal OUT, the gate of transistor T7 is connected to the drain of T7, the source is connected to the drain of transistor T5, the drain is connected to the gate of transistor T7, the drain of T8, and the output terminal OUT, the gate of transistor T8 is connected to the drain of T8, the source is connected to the source of transistor T9, the drain is connected to the drain of transistor T7 and is further connected to the output terminal OUT; the gate of transistor T9 is connected to the input The input signal IN, the source is connected to the input signal IN and the source of the transistor T8, the gate and drain of T10 are connected to the power supply Vdd, the gate of the transistor T10 is connected to the input signal IN, the source is connected to the output terminal OUT, and the drain is connected to the power supply Vdd, the transistor T5, the transistor T6, and the transistor T7 are all NCNFET transistors and the chirality vectors are (19, 0), (10, 0) and (13, 0) respectively, the transistor T8, the transistor T9, and the transistor T10 are all PCNFET transistors and the chirality vectors are (13, 0), (19, 0) and (10, 0) respectively, so that the ternary inverter STI outputs 2 when the input is 0, outputs 1 when the input is 1, and outputs 0 when the input is 2.
3. The method for optimizing a logic unit circuit based on a CNFET device according to claim 2, wherein: The logic unit circuit based on the CNFET device is a dual-input ternary NAND gate or a dual-input ternary NOR gate. The dual-input ternary NAND gate is composed of transistors T11 to T20. Transistors T11 to T15 are NCNFET transistors, and transistors T16 to T20 are PCNFET transistors. The chirality vectors of transistors T11, T13, T17, and T18 are all (19, 0), and the chirality vectors of transistors T12, T14, T19, and T20 are all (10, 0). ), the chirality vectors of transistors T15 and T16 are both (13,0), the gate of transistor T11 is connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the source of transistor T13, the gate of transistor T12 is also connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the source of transistor T14, the gate of transistor T13 is connected to the input signal INA, the source is connected to the drain of transistor T11, and the drain is connected to the source of transistor T15, and the gate of transistor T14 is connected to the input signal INA, the source is connected to the drain of the transistor T12, the drain is connected to the output terminal OUT1, the gate of the transistor T15 is connected to the drain of T15, the source is connected to the drain of the transistor T13, the drain is connected to the gate of the transistor T15, the drain of the transistor T16, and the output terminal OUT1, the gate of the transistor T16 is connected to the drain of T16, the source is connected to the source of the transistor T18, the drain is connected to the gate of the transistor T16, and the drain of the transistor T15, the gate of the transistor T17 is connected to the input signal INA, the source is connected to the source of the transistor T18, the source of the transistor T16, and the drain is connected to the power supply Vdd, the gate of the transistor T18 is connected to the input signal INB, the source is connected to the source of the transistor T16, the drain is connected to the power supply Vdd, the gate of the transistor T19 is connected to INA, the source is connected to the source of the transistor T20, the output terminal OUT1, and the drain is connected to the power supply Vdd, the gate of the transistor T20 is connected to the input signal INB, the source is connected to the source of the transistor T19, the output terminal OUT1, and the drain is connected to the power supply Vdd;The dual-input ternary NOR gate is composed of transistors T21 to T30, wherein transistors T21 to T25 are NCNFET transistors, and transistors T26 to T30 are PCNFET transistors. The chirality vectors of transistors T21, T22, T27, and T29 are all (19, 0), the chirality vectors of transistors T23, T24, T28, and T30 are all (10, 0), and the chirality vectors of transistors T25 and T26 are (13, 0). The gate of transistor T21 is connected to the input signal INA, the source is connected to the ground GND, and the drain is connected to the drain of transistor T22 and the source of transistor T25. The gate of transistor T22 is connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the drain of transistor T21 and the source of transistor T25. The gate of transistor T23 is connected to the input signal INA, the source is connected to the ground GND, and the drain is connected to the output terminal OUT2. The gate of transistor T24 is connected to the input signal INB, the source is connected to the ground GND, and the drain is connected to the output terminal OUT2. The drain of transistor T25 is connected to the output terminal OUT2. The gate of transistor T25 is connected to the drain of transistor T25, the source is connected to the drain of transistor T21 and the drain of transistor T22, the drain is connected to the gate of transistor T25 and the drain of transistor T26, and the output terminal OUT2. The gate of transistor T26 is connected to the drain of transistor T26, the source is connected to the source of transistor T27 and the source of transistor T28, the drain is connected to the gate of transistor T26 and the drain of transistor T25, and the output terminal OUT2. The gate of transistor T27 is connected to the input signal INB, the source is connected to the source of transistor T28 and the source of transistor T26, and the drain is connected to the source of transistor T29. The gate of transistor T28 is connected to the input signal INB, the source is connected to the output terminal OUT2, and the drain is connected to the source of T30. The gate of transistor T29 is connected to INA, the source is connected to the drain of transistor T27, and the drain is connected to the power supply Vdd. The gate of transistor T30 is connected to the input signal INA, the source is connected to the gate of transistor T28, and the drain is connected to the power supply Vdd.
4. The method for optimizing a logic unit circuit based on a CNFET device according to claim 3, wherein: The logic unit circuit based on the CNFET device is a low threshold comparison-medium-high output circuit GTL-BH() and an equal threshold comparison-medium-high output circuit EQL-BH(). The low threshold comparison-medium-high output circuit GTL-BH() is composed of a positive ternary inverter PTI and a negative ternary inverter NTI connected in series, so that when the input of the low threshold comparison-medium-high output circuit GTL-BH() is logic 2, the output is logic 2, and when the input is logic 0 or 1, the output is logic 0; the equal threshold comparison-medium-high output circuit EQL-BH( ) circuit consists of two negative ternary inverters NTI, a positive ternary inverter PTI and a NOR gate. The input signals are respectively sent to the two negative ternary inverters NTI, wherein the output of one negative ternary inverter NTI is directly used as the first input of the NOR gate, and the output of the other negative ternary inverter NTI is used as the second input of the NOR gate after passing through a positive ternary inverter PTI, so that the equal threshold comparator-mid-high output circuit EQL-BH() outputs a logic 2 when the input is a logic 1, and outputs a logic 0 when the input is a logic 0 or 2.
5. The method for optimizing a logic unit circuit based on a CNFET device according to claim 3, wherein: The logic unit circuit based on the CNFET device is a ternary XOR gate, which is composed of four NAND gates and includes two input variables INA and INB and an output variable XOR. The NAND gate is a dual-input ternary NAND gate, wherein the input signal INA is simultaneously connected to one input end of the first NAND gate and one input end of the second NAND gate; the input signal INB is simultaneously connected to the other input end of the first NAND gate and one input end of the third NAND gate; the output of the first NAND gate is connected to the other input end of the second NAND gate and the other input end of the third NAND gate; the output of the second NAND gate is connected to the input end of the third NAND gate. The outputs are connected to two input terminals of a fourth NAND gate, and the fourth NAND gate is connected to the output terminal Q to obtain the output variable XOR, so that when the input variables INA are 0 and INB are 0, the output variable XOR is 0; when the input variables INA are 0 and INB are 1, the output variable XOR is 1; when the input variables INA are 0 and INB are 2, the output variable XOR is 2; when the input variables INA are 1 and INB are 1, the output variable XOR is 1; when the input variables INA are 1 and INB are 2, the output variable XOR is 1; when the input variables INA are 2 and INB are 2, the output variable XOR is 0.
6. The method for optimizing a logic unit circuit based on a CNFET device according to claim 3, wherein: The logic unit circuit based on the CNFET device is a ternary D latch circuit, which is composed of four NAND gates NAND 1 to NAND gate 4, a negative ternary inverter NTI and a ternary inverter STI, and includes an enable terminal EN, an input terminal DIN and an output terminal Q; the NAND gates NAND 1 to NAND gate 4 are all dual-input ternary NAND gates; the data input DIN is directly connected to one input terminal of the NAND gate NAND 1 and the input terminal of the ternary inverter STI; the enable signal EN is connected to the negative ternary inverter NTI, and after inversion processing, is connected to the other input terminal of the NAND gate NAND 1 and one input terminal of the NAND gate NAND 2; the ternary inverter STI is connected to the other input terminal of the NAND gate NAND 2; the output of the NAND gate NAND 1 is connected to one input terminal of the NAND gate NAND 3, and the output of the NAND gate NAND 2 is connected to one input terminal of the NAND gate NAND4; the NAND gate NAND 3 A cross-coupling structure is formed with the NAND gate NAND 4, so that the output of the NAND gate NAND 3 is not only connected to the normal output Q of the circuit but also to the other input terminal of the NAND gate NAND 4; the output of the NAND gate NAND 4 is used as the inverted output and is also connected to the other input terminal of the NAND gate NAND 3. When the enable terminal EN is at a low level (a logic 0), the D latch circuit samples the input terminal DIN, and the output terminal Q changes with the change of the input terminal DIN. When the enable terminal EN is at a high level (a logic 2), the value of the output terminal Q before the change of the enable terminal EN remains unchanged until the enable terminal EN becomes a low level again, at which time the input terminal DIN is sampled again.
7. The method for optimizing a logic unit circuit based on a CNFET device according to claim 1, wherein: Before the average conversion delay time of the optimized logic unit circuit based on the CNFET device is obtained by adjusting the structural parameters of the CNFET device multiple times and simulating the structural parameters after each adjustment, the method also includes: using the optimized logic unit circuit based on the CNFET device to build a specified logic circuit, and simulating the built specified logic circuit through HSPICE to obtain its truth table. If the obtained truth table is consistent with the theoretical truth table, it is determined that the logic verification of the optimized logic unit circuit based on the CNFET device has passed.
8. An optimization system for a logic unit circuit based on a CNFET device, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for optimizing a logic unit circuit based on a CNFET device according to any one of claims 1 to 7.
9. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the method for optimizing a logic unit circuit based on a CNFET device according to any one of claims 1 to 7 through a processor.
10. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the method for optimizing a logic unit circuit based on a CNFET device according to any one of claims 1 to 7 through a processor.