OPC-based STA timing analysis and optimization methods, devices, media, program products, and terminals

Abstract

This application provides an OPC-based STA timing analysis and optimization method, apparatus, medium, program product, and terminal. Before extracting parasitic parameters, it acquires layout data, performs a first STA timing analysis to quickly locate the critical path, and then applies optical proximity effect correction and fitting to the critical path to generate a layout that highly fits the actual manufacturing state. A second STA timing analysis is then used to achieve a comprehensive and detailed evaluation of the corrected path, ensuring accurate verification and optimization of timing convergence. This solves the problems of traditional timing verification being too conservative and lacking accuracy, leading to wasted design resources, inaccurate timing verification, and uncontrollable chip timing risks. It significantly improves the accuracy and efficiency of timing verification, reduces redundant computation and resource consumption in non-critical areas, is suitable for advanced process chip design, and achieves efficient and reliable timing convergence under manufacturing deviation environments, ensuring chip performance and production yield.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and in particular to OPC-based STA timing analysis and optimization methods, devices, media, program products and terminals. Background Technology

[0002] As process nodes continue to shrink and chip logic complexity increases, layout deviations during manufacturing, such as linewidth variations and proximity effects, are having an increasingly significant impact on chip timing performance. Currently, in Static Timing Analysis (STA), the design phase typically employs a method of reserving timing margins to conservatively estimate performance fluctuations that may be caused by manufacturing deviations, thereby ensuring timing convergence after chip manufacturing. These methods are mostly based on empirical models to make rough estimates of process variations, assisting in STA timing verification during the design phase.

[0003] However, conservative estimation methods struggle to accurately reflect actual layout changes caused by the manufacturing process and their impact on timing. This leads to overly pessimistic margins in the design, wasting design resources and failing to accurately predict timing deviations caused by manufacturing errors. Ignoring real manufacturing effects can significantly increase STA timing analysis errors, sometimes reaching as high as 15%. Timing convergence issues are particularly pronounced in advanced process nodes and complex logic chips, where the lack of effective means to comprehensively assess manufacturing impacts during the design phase makes it difficult to accurately control the timing risks of the final chip. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide an OPC-based STA timing analysis and optimization method, device, medium, program product and terminal to solve the problem that under advanced process nodes, manufacturing deviations have a significant impact on chip timing performance, and existing design methods are too conservative and lack precision, resulting in inaccurate timing verification, wasted design resources and difficulty in effectively controlling the timing risks of the final chip.

[0005] To achieve the above and other related objectives, a first aspect of this application provides an OPC-based STA timing analysis optimization method, comprising: obtaining a first layout; when the first layout meets a first preset standard, performing a first STA timing analysis operation on the first layout to generate a critical path; performing an OPC correction operation on the first layout based on the critical path to generate a second layout; performing an OPC fitting operation on the second layout to generate a third layout; and performing a second STA timing analysis operation on the third layout to generate STA analysis results.

[0006] In some embodiments of the first aspect of this application, the first preset standard includes: if the advanced process node in the first layout shown is greater than a preset threshold, then the first layout does not meet the first preset standard; if the advanced process node in the first layout shown is less than or equal to the preset threshold, then the first layout meets the first preset standard.

[0007] In some embodiments of the first aspect of this application, the process of performing a first STA timing analysis operation on the first layout to generate a critical path includes: extracting corresponding circuit description data from the first layout; constructing a timing network model based on the circuit description data; calculating the signal arrival time from the input port to each node in the timing network model to generate arrival time data; calculating the timing margin corresponding to each node through the arrival time data and preset timing constraints; and identifying and extracting paths that meet preset conditions as critical paths based on the timing margin.

[0008] In some embodiments of the first aspect of this application, the process of identifying and extracting paths that meet preset conditions as critical paths includes: identifying and extracting paths with timing violations as critical paths; and / or identifying and extracting paths that cannot converge as critical paths.

[0009] In some embodiments of the first aspect of this application, the process of performing an OPC correction operation on the first layout based on the critical path to generate a second layout includes: acquiring and loading an OPC model file; performing simulated exposure calculations on the corresponding region of the critical path in the first layout to generate light intensity distribution data; calculating the edge offset of the region corresponding to the critical path based on the light intensity distribution data, and performing offset correction on the corresponding region of the critical path in the first layout to generate a second layout.

[0010] In some embodiments of the first aspect of this application, the process of performing an OPC fitting operation on the second layout to generate a third layout includes: performing manufacturing process simulation and fitting calculations on the second layout based on the process sub-model in the OPC model file to generate a third layout representing the actual process deformation.

[0011] To achieve the above and other related objectives, a second aspect of this application provides an OPC-based STA timing analysis and optimization apparatus, comprising: a data acquisition module for acquiring a first layout; a path optimization module for performing a first STA timing analysis operation on the first layout to generate a critical path when the first layout meets a first preset standard; performing an OPC correction operation on the first layout based on the critical path to generate a second layout; performing an OPC fitting operation on the second layout to generate a third layout; and an STA analysis module for performing a second STA timing analysis operation on the third layout to generate STA analysis results.

[0012] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the OPC-based STA timing analysis optimization method.

[0013] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code, which, when executed on a computer, enables the computer to implement the OPC-based STA timing analysis optimization method.

[0014] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the OPC-based STA timing analysis optimization method.

[0015] As described above, the OPC-based STA timing analysis optimization method, apparatus, medium, program product, and terminal of this application have the following beneficial effects: This application adopts a hierarchical and targeted STA analysis process, effectively avoiding the blind optimization of the entire layout in traditional methods, thereby achieving efficient utilization of design resources. By focusing on precise optimization of the critical path, it not only solves the problem of insufficient accuracy in existing timing verification but also significantly improves the overall verification efficiency. In addition, this application reduces redundant calculations and resource waste in non-critical areas, further enhancing the rationality and economy of the design process. With this optimization strategy, this application is particularly suitable for chip design under advanced processes, and can achieve efficient and reliable timing convergence in environments where manufacturing deviations have a significant impact, ultimately ensuring stable chip performance and significantly improved production yield. Attached Figure Description

[0016] Figure 1 The diagram shows a flowchart of an embodiment of the STA timing analysis optimization method based on OPC of this application.

[0017] Figure 2 This paper presents a flowchart illustrating another embodiment of the STA timing analysis optimization method based on OPC of this application.

[0018] Figure 3 This diagram illustrates the timing constraints of setup time and hold time in one embodiment of the OPC-based STA timing analysis optimization method of this application.

[0019] Figure 4 This paper shows a schematic diagram of an embodiment of the STA timing analysis and optimization device based on OPC of this application.

[0020] Figure 5 The diagram shows a structural schematic of an embodiment of the STA timing analysis and optimization terminal based on OPC of this application. Detailed Implementation

[0021] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0022] Before providing a further detailed description of this application, the nouns and terms used in the embodiments of this application are explained, and the nouns and terms used in the embodiments of this application shall be interpreted as follows:

[0023] <1> OPC Correction Operation: In integrated circuit manufacturing, OPC (Optical Proximity Correction) refers to the pre-adjustment of the mask pattern's geometry to compensate for pattern distortion caused by optical effects such as diffraction and interference during photolithography, ensuring that the circuit structure formed on the silicon wafer is highly consistent with the design drawings.

[0024] <2> OPC fitting operation: OPC fitting operation refers to the process of comparing the actual lithographic imaging result with the ideal design pattern through mathematical models and algorithms during OPC correction, and calculating the optimal correction parameters and correction pattern to minimize lithographic errors and achieve higher pattern fidelity.

[0025] <3> Static Timing Analysis (STA) is a method for verifying the timing performance of digital integrated circuits by calculating the delays of all possible signal propagation paths in a circuit without running the circuit. It is used to ensure that signals arrive on time and meet timing requirements such as setup and hold times at a given clock frequency.

[0026] <4> Circuit description data: Circuit description data refers to the digital information used to fully describe the function, structure, and interconnection relationships of an integrated circuit. This includes gate-level netlists, transistor-level netlists, physical layout information, timing models, power consumption models, etc., and is the foundation for circuit design, verification, and manufacturing.

[0027] <5> Timing network model: A timing network model is an abstract model used to represent the signal propagation path and delay characteristics in an integrated circuit. It typically consists of logic gates, interconnects, and the timing relationships between them (such as propagation delay, setup time, and hold time), and serves as the basis for static timing analysis and timing verification.

[0028] <6> Advanced process nodes: Advanced process nodes refer to semiconductor manufacturing technologies where transistor feature dimensions (such as gate length) reach or are smaller than a specific micrometer or nanometer level. For example, 28nm, 14nm, 7nm, and 5nm are all advanced process nodes, which typically mean higher transistor density, lower power consumption, and higher performance.

[0029] <7> Setup time: Setup time refers to the minimum time required for the data signal to remain stable before the clock's effective edge arrives. If the data signal changes within the setup time window, the D-type flip-flop may fail to capture the data correctly, resulting in a timing violation.

[0030] <8> Hold time: Hold time refers to the minimum time required for the data signal to remain stable after the arrival of the clock's active edge. If the data signal changes within the hold time window, the D-type flip-flop may fail to capture the data correctly, resulting in a timing violation.

[0031] <9> D-type flip-flop: A D-type flip-flop is a basic digital logic storage unit with one data input (D), one clock input (CLK), and one output (Q). It latches the state of the data input to the output at a specific edge of the clock (usually the rising or falling edge), thus storing one bit of data.

[0032] <10> Timing margin: Timing margin refers to the difference between the actual arrival time of a signal and the required arrival time of a signal in a circuit. A positive timing margin indicates that the circuit meets the timing requirements and has a margin; a negative timing margin indicates that there is a timing violation in the circuit and the signal fails to arrive on time.

[0033] <11> Parasitic parameters: Parasitic parameters refer to non-ideal electrical effects in integrated circuits caused by the physical characteristics of device structure and interconnects, such as parasitic resistance, parasitic capacitance, and parasitic inductance. These parameters affect the circuit's performance, power consumption, and reliability, and require accurate modeling and analysis during the design process.

[0034] To facilitate understanding of the embodiments of this application, the following will be discussed first. Figure 1 Please provide an explanation. Figure 1 A flowchart illustrating an OPC-based STA timing analysis optimization method is shown in an embodiment of this application. Figure 2 A flowchart illustrating another embodiment of this application is shown. The OPC-based STA timing analysis optimization method in this embodiment mainly includes the following steps:

[0035] Step S11: Obtain the first map.

[0036] In one embodiment of this application, the first layout refers to the graphic data layer contained in the GDSII (Graphic Data System II) format layout file before parasitic parameter extraction. It should be noted that the method proposed in this application, by taking into account the influence of optical proximity effect (OPC) when extracting the chip parasitic parameter RC, obtains an RC value that is closer to the actual situation. This application helps improve the accuracy of chip timing analysis, thereby enabling more effective timing convergence.

[0037] Step S12: When the first layout meets the first preset standard, perform a first STA timing analysis operation on the first layout to generate a critical path; based on the critical path, perform an OPC correction operation on the first layout to generate a second layout; perform an OPC fitting operation on the second layout to generate a third layout.

[0038] In one embodiment of this application, the first preset standard includes: if the advanced process node in the first layout shown is greater than a preset threshold, then the first layout does not meet the first preset standard; if the advanced process node in the first layout shown is less than or equal to the preset threshold, then the first layout meets the first preset standard.

[0039] In this embodiment, the first preset criterion includes determining the relationship between advanced process nodes in the layout and a preset threshold. When the value of an advanced process node in the first layout is greater than the preset threshold, the first layout is considered not to meet the first preset criterion. Conversely, when the value of an advanced process node in the first layout is less than or equal to the preset threshold, the first layout is considered to meet the first preset criterion. More preferably, the preset threshold is set to 28nm. That is, if the advanced process node shown in the layout is 28nm or smaller, the layout is determined to meet the first preset criterion; if the advanced process node shown in the layout is greater than 28nm, the layout is determined not to meet the first preset criterion. This setting aims to filter out layouts that may cause STA timing analysis to have difficulty converging.

[0040] In one embodiment of this application, the process of performing a first STA timing analysis operation on the first layout to generate a critical path includes: extracting corresponding circuit description data from the first layout; constructing a timing network model based on the circuit description data; calculating the signal arrival time from the input port to each node in the timing network model to generate arrival time data; calculating the timing margin corresponding to each node through the arrival time data and preset timing constraints; and identifying and extracting paths that meet preset conditions as critical paths based on the timing margin.

[0041] The process of identifying and extracting paths that meet preset conditions as critical paths includes: identifying and extracting paths with timing violations as critical paths; and / or identifying and extracting non-convergent paths as critical paths. Non-convergent refers to paths that fail to achieve stable arrival times and delays after multiple iterations.

[0042] In this embodiment, firstly, circuit description data is extracted from the first layout. This circuit description data includes, but is not limited to, netlists, cell delays, and topology. The netlist is used to fully characterize the interconnection relationships of each circuit unit; the cell delay represents the delay variation of each gate or flip-flop under different input transition times and load conditions; and the topology clearly describes the propagation path of signals in each unit and network node.

[0043] Furthermore, the process of constructing a timing network model based on the circuit description data includes establishing all clock-related flip-flops, combinational logic of data paths, and their connection methods. Specifically, by parsing the netlist and topology, and combining unit delays, a timing network model covering the data and clock propagation paths of the entire circuit is established. The timing network model includes mapping the signal flow on each data path, from the signal initiation port to each downstream node, and associated key nodes such as clock enable and data sampling. In the timing network model, each propagation path is accompanied by corresponding timing constraints, including setup time and hold time, and other time windows used for synchronization with the clock signal.

[0044] Specifically, Figure 3 This illustration shows a timing constraint diagram for setup and hold times in one embodiment of this application. It includes two D-type flip-flops, DFF1 and DFF2, and an intermediate logic module. A clock signal (clk) is synchronously fed into the CK terminals of both DFFs through a buffer. The Q terminal of DFF1 is connected to the D terminal of DFF2 via the logic module, forming a data timing path. The buffer represents the clock delay. This model is the basis for STA timing analysis, used to evaluate key parameters such as data path delay, clock path delay, setup time, and hold time. This embodiment compares the data arrival time and required time with the flip-flop timing requirements to determine if a timing violation exists, ensuring the correctness of circuit function.

[0045] Furthermore, after the model is established, detailed signal arrival times are calculated for each data path. Signal arrival time The calculation process is shown in Formula 1. This indicates the delay at the clock-initiated port. This indicates the response delay from CK to Q of the trigger. This represents the corresponding delay of the combinational logic path. For a specific data path, such as from the first-level flip-flop (DFF1) through combinational logic to the next flip-flop (DFF2), calculate the propagation time of the data along the paths with the maximum and minimum logic delays, respectively. This also represents the latest time point at which the data is expected to arrive. The calculation process is shown in Formula 2, where Indicates one clock cycle. This indicates the delay time for the clock signal to reach the clock input of flip-flop DFF2. This indicates the trigger's setup time.

[0046] (Formula 1)

[0047] (Formula 2)

[0048] In this embodiment, the process of calculating the timing margin corresponding to each node using the arrival time data and preset timing constraints includes: using the establishment time of the current node in Formula 3 to characterize the margin of data arriving early or late. When the margin is positive, it indicates that the data arrives within the agreed window and does not violate the timing constraints; when the margin is negative, a timing violation occurs, indicating that the path cannot meet the establishment time requirements; and using Formula 4 to calculate the hold time of the current node, which also needs to ensure that the result is greater than zero. Once a negative margin occurs, the path is a timing abnormal path.

[0049] (Formula 3)

[0050] (Formula 4)

[0051] Finally, based on the timing margin, the process of identifying and extracting problem paths that meet preset conditions includes: traversing all signal paths and determining the timing margin of each path based on its setup and hold times. Paths with setup or hold time margin violations are directly extracted as critical paths to be optimized. More preferably, paths whose timing margin is close to critical, whose stability cannot be guaranteed, or whose timing convergence is difficult under various process corner conditions (such as Cmax, Cmin, RCmax, RCmin, etc.) are also identified as critical paths.

[0052] The reason for adopting the above standard is that the formation of the critical path is not only affected by cell delay, combinational logic delay, and network topology, but also closely related to metal layer resistance, capacitance, and manufacturing process parameters. Fluctuations in process parameters such as metal layer width, thickness, and insulation spacing directly affect RC parameter changes, thereby affecting signal propagation time. This causes the timing margin of the aforementioned paths to become a bottleneck for performance and stability. Therefore, by extracting these paths with timing risks, subsequent OPC correction operations can better avoid chip timing risks.

[0053] In one embodiment of this application, the process of performing a first STA timing analysis operation on the first layout to generate a critical path further includes: the circuit description data also includes register clock pins and their clock tree topology information, which is used to construct a timing network model. During the timing network model construction process, clock edges are established between the chip's external clock port and each register CK pin, and their weights are set to the clk2reg delay. Subsequently, for each data node, the arrival time of the data signal from the input port to the D terminal of register is calculated; and for each clock node, the arrival time of the clock signal from the chip's external clock port to the CK terminal of register is calculated to obtain clk2reg. Using clk2reg as the arrival time of the register clock edge, a preset setup / hold time constraint is calculated to obtain the timing margin corresponding to each node.

[0054] In one embodiment of this application, the process of performing an OPC correction operation on the first layout based on the critical path to generate a second layout includes: acquiring and loading an OPC model file; performing simulated exposure calculations on the corresponding area of ​​the critical path in the first layout to generate light intensity distribution data; calculating the edge offset of the corresponding area of ​​the critical path based on the light intensity distribution data, and performing offset correction on the corresponding area of ​​the critical path in the first layout to generate a second layout.

[0055] In this embodiment, an OPC model file is acquired and loaded. This file contains parameters and algorithms for performing optical proximity correction. In the first layout, simulated exposure calculations are performed on specific regions corresponding to the critical path to simulate the propagation of light through the mask during photolithography, generating light intensity distribution data that reflects the intensity distribution of light within the layout area. Subsequently, based on the generated light intensity distribution data, the edge offset of the region corresponding to the critical path is calculated. This offset characterizes the deviation between the layout edge and the ideal design position caused by the optical proximity effect. Finally, based on the calculated edge offset, the region corresponding to the critical path in the first layout is offset corrected, i.e., the layout pattern of that region is adjusted to compensate for the influence of the optical proximity effect, thereby generating a corrected second layout.

[0056] Preferably, the OPC correction operation can use OPC scripts provided by the foundry to process specific layers. Here, "foundry" refers to a semiconductor wafer foundry that provides integrated circuit manufacturing services and offers dedicated OPC scripts and models to ensure the manufacturability of patterns under its manufacturing process. By applying OPC correction, the manufacturability of patterns can be effectively improved, and the consistency of patterns between the edge and center areas of the wafer can be enhanced, thereby ensuring the performance and yield of the manufactured chips.

[0057] In one embodiment of this application, the process of performing an OPC fitting operation on the second layout to generate a third layout includes: performing manufacturing process simulation and fitting calculations on the second layout based on the process sub-model in the OPC model file to generate a third layout representing the actual process deformation.

[0058] In this embodiment, based on the process sub-model contained in the OPC model file, the manufacturing process simulation and fitting calculation are performed on the second layout. Specifically, after all wiring layers have completed OPC processing and obtained the corrected graphic shape, based on the layer model provided by the foundry for a specific process node, different layers are fitted with graphics so that the graphics of each layer are adjusted according to its corresponding process model parameters, and the deformation of the layer under actual manufacturing conditions is simulated.

[0059] It should be noted that this application adopts a layered STA timing analysis strategy, where the operations of the first STA timing analysis and the second STA timing analysis can be the same or different. When the operations differ, the first STA timing analysis is first performed on the post-routing layout for basic screening to quickly identify critical paths (i.e., timing violations or paths that are difficult to converge); then, only these critical paths are subjected to OPC correction and fitting to generate a third layout representing the true wafer state; finally, a more comprehensive second STA timing analysis is performed to accurately evaluate the correction effect and ensure timing convergence. This process achieves precise positioning, targeted handling of critical paths, and optimization of resources throughout the entire process through differentiated STA analysis, significantly improving efficiency while ensuring performance.

[0060] Step S13: Perform the second STA timing analysis operation on the third layout to generate STA analysis results.

[0061] In one embodiment of this application, based on the above steps, a parasitic parameter extraction operation is further performed on the third layout. The parasitic parameters include, but are not limited to, resistance, capacitance, and inductance on interconnects. Accurate parasitic parameters are crucial for STAR timing analysis, relying on precise R, C, and L parasitic parameters to accurately calculate and evaluate timing characteristics such as circuit delay, setup time, and hold time. By extracting layout parasitic parameters that more realistically reflect the manufacturing process, higher-precision input data can be provided for the STAR process, thereby significantly improving the accuracy and reliability of timing verification, effectively reducing unnecessary design margins, and ultimately achieving precise control over chip timing risks.

[0062] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and purpose. For example, "first layout" and "second layout" are merely used to distinguish different layouts and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0063] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0064] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0065] Figure 4 This is a schematic block diagram of the OPC-based STA timing analysis and optimization device 400 provided in an embodiment of this application. Figure 4 As shown, the device includes a data acquisition module 401, a path optimization module 402, and an STA analysis module 403.

[0066] Data acquisition module 401: Used to acquire the first map.

[0067] Path optimization module 402: When the first layout meets the first preset standard, it performs a first STA timing analysis operation on the first layout to generate a critical path; based on the critical path, it performs an OPC correction operation on the first layout to generate a second layout; and performs an OPC fitting operation on the second layout to generate a third layout.

[0068] STA analysis module 403: used to perform the second STA timing analysis operation on the third layout to generate STA analysis results.

[0069] It should be understood that the specific process of each module performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0070] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0071] Figure 5 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 5 As shown, the electronic terminal includes at least one processor 501, a memory 502, at least one network interface 503, and a user interface 505. The various components in the device are coupled together via a bus system 504. It is understood that the bus system 504 is used to implement communication between these components. In addition to a data bus, the bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 5 The general will label all buses as bus systems.

[0072] The user interface 505 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0073] It is understood that memory 502 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this application are intended to include, but are not limited to, these and any other suitable categories of memory.

[0074] In this embodiment, the memory 502 is used to store various types of data to support the operation of the electronic terminal 500. Examples of this data include any executable program that operates on the electronic terminal 500, such as the operating system 5021 and application programs 5022. The operating system 5021 contains various system programs, such as the framework layer, core library layer, and driver layer, used to implement various basic services and handle hardware-based tasks. The application program 5022 may contain various applications, such as a media player and a browser, used to implement various application services. The OPC-based STA timing analysis optimization method provided in this embodiment can be included in the application program 5022.

[0075] The methods disclosed in the embodiments of this application can be applied to or implemented by processor 501. Processor 501 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 501 or by instructions in software form. The processor 501 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 501 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. General-purpose processor 501 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0076] In an exemplary embodiment, the electronic terminal 500 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0077] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute the OPC-based STA timing analysis optimization method as described in any of the embodiments above.

[0078] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to execute the OPC-based STA timing analysis optimization method as described in any of the embodiments above.

[0079] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0080] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0081] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0085] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)).

[0086] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0088] In summary, this application provides an OPC-based STA timing analysis and optimization method, apparatus, medium, program product, and terminal. Before extracting parasitic parameters, it acquires layout data, performs a first STA timing analysis to quickly locate the critical path, and then applies optical proximity effect correction and fitting to the critical path to generate a layout that highly fits the actual manufacturing state. A second STA timing analysis is then used to achieve a comprehensive and detailed evaluation of the corrected path, ensuring accurate verification and optimization of timing convergence. This solves the problems of traditional timing verification being too conservative and lacking accuracy, leading to wasted design resources, inaccurate timing verification, and uncontrollable chip timing risks. It significantly improves the accuracy and efficiency of timing verification, reduces redundant computation and resource consumption in non-critical areas, is suitable for advanced process chip design, and achieves efficient and reliable timing convergence under manufacturing deviation environments, ensuring chip performance and production yield. Therefore, this application effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0089] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A time series analysis and optimization method based on OPC, characterized in that, include: Acquire the first map; When the first layout meets the first preset standard, a first STA timing analysis operation is performed on the first layout to generate a critical path. The process of performing the first STA timing analysis operation on the first layout to generate a critical path includes: extracting corresponding circuit description data from the first layout; constructing a timing network model based on the circuit description data; calculating the signal arrival time from the input port to each node in the timing network model to generate arrival time data; calculating the timing margin corresponding to each node using the arrival time data and preset timing constraints; identifying and extracting paths that meet preset conditions as critical paths based on the timing margin; performing an OPC correction operation on the first layout based on the critical path to generate a second layout; and performing an OPC fitting operation on the second layout to generate a third layout. Perform a second STA timing analysis operation on the third layout to generate STA analysis results.

2. The OPC-based STA timing analysis and optimization method according to claim 1, characterized in that, The first preset standard includes: If the advanced process nodes in the first layout shown are greater than a preset threshold, then the first layout does not meet the first preset standard. If the advanced process nodes in the first layout shown are less than or equal to a preset threshold, then the first layout meets the first preset standard.

3. The OPC-based STA timing analysis and optimization method according to claim 1, characterized in that, The process of identifying and extracting paths that meet preset criteria as critical paths includes: Identify and extract the paths of timing violations as critical paths; And / or, identify and extract non-convergent paths as critical paths.

4. The OPC-based STA timing analysis and optimization method according to claim 1, characterized in that, Based on the critical path, the process of performing an OPC correction operation on the first layout to generate the second layout includes: Obtain and load the OPC model file; In the first version, simulated exposure calculations are performed for the corresponding regions of the critical path to generate light intensity distribution data; Based on the light intensity distribution data, the edge offset of the region corresponding to the critical path is calculated, and the offset of the region corresponding to the critical path in the first map is corrected to generate the second map.

5. The OPC-based STA timing analysis and optimization method according to claim 4, characterized in that, The process of performing an OPC fitting operation on the second layout to generate the third layout includes: Based on the process sub-model in the OPC model file, the manufacturing process is simulated and fitted to the second layout to generate a third layout representing the actual process deformation.

6. A STA timing analysis and optimization device based on OPC, characterized in that, include: Data acquisition module: used to acquire the first map; Path optimization module: When the first layout meets a first preset standard, it performs a first STA timing analysis operation on the first layout to generate a critical path; wherein, the process of performing the first STA timing analysis operation on the first layout to generate a critical path includes: extracting corresponding circuit description data from the first layout; constructing a timing network model based on the circuit description data; calculating the signal arrival time from the input port to each node in the timing network model to generate arrival time data; calculating the timing margin corresponding to each node through the arrival time data and preset timing constraints; identifying and extracting paths that meet preset conditions as critical paths based on the timing margin; performing an OPC correction operation on the first layout based on the critical path to generate a second layout; and performing an OPC fitting operation on the second layout to generate a third layout. STA Analysis Module: Used to perform a second STA timing analysis operation on the third layout to generate STA analysis results.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the OPC-based STA timing analysis and optimization method according to any one of claims 1 to 5.

8. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, causes the computer to implement the OPC-based STA timing analysis optimization method as described in any one of claims 1 to 5.

9. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the OPC-based STA timing analysis optimization method according to any one of claims 1 to 5.

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