Circuit layout method, circuit layout device, electronic equipment and storage medium

Abstract

The invention provides a circuit layout method, a circuit layout device, electronic equipment and a storage medium. The circuit layout method comprises the following steps: for a target circuit, acquiring a first standard cell layout which is determined based on first voltage domain information and meets a first time sequence convergence condition; determining first voltage domain cluster information comprising at least one voltage domain cluster corresponding to the standard units in the physical region of the object voltage domain for a plurality of standard units in the object voltage domain of which the physical region is not determined in the first standard unit layout, and obtaining second voltage domain information based on the first voltage domain cluster information; in response to the situation that a second standard cell layout obtained based on the second voltage domain information does not meet a second time sequence convergence condition, new first voltage domain cluster information of the standard cells is determined again; or the second standard cell layout is adopted for the target circuit in response to the second standard cell layout meeting the second time sequence convergence condition. According to the circuit layout method, the influence of the time sequence can be fully considered when the circuit layout is determined.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a circuit layout method, a circuit layout device, an electronic device, and a storage medium. Background Art

[0002] In modern integrated circuit design, multiple voltage domains (MVDs) are one of the most effective low-power design methods. However, if only power consumption is considered when allocating different circuit logics to different voltage domains, it will have a certain impact on circuit performance. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a circuit layout method, the method comprising: for a target circuit, obtaining a first standard cell layout that satisfies a first timing closure condition and is determined based on first voltage domain information; for a plurality of standard cells in an object voltage domain whose physical area is not determined in the first standard cell layout, determining first voltage domain cluster information of at least one voltage domain cluster corresponding to the standard cells in the physical area of ​​the object voltage domain, and obtaining second voltage domain information based on the first voltage domain cluster information; and in response to a second standard cell layout obtained based on the second voltage domain information not satisfying a second timing closure condition, re-determining new first voltage domain cluster information for the standard cells, and obtaining updated second voltage domain information based on the first voltage domain cluster information for updating the second standard cell layout; or in response to a second standard cell layout obtained based on the second voltage domain information satisfying a second timing closure condition, adopting the second standard cell layout for the target circuit.

[0004] At least one embodiment of the present disclosure provides a circuit layout device, which includes an acquisition device and a determination device, wherein the acquisition module is configured to acquire, for a target circuit, a first standard cell layout that satisfies a first timing closure condition and is determined based on first voltage domain information; the determination module is configured to determine, for a plurality of standard cells in an object voltage domain whose physical areas are not determined in the first standard cell layout, first voltage domain cluster information of at least one voltage domain cluster corresponding to the standard cells in the physical area of ​​the object voltage domain, and obtain second voltage domain information based on the first voltage domain cluster information; in response to a second standard cell layout obtained based on the second voltage domain information not satisfying a second timing closure condition, re-determine new first voltage domain cluster information for the standard cells, and obtain updated second voltage domain information based on the first voltage domain cluster information for updating the second standard cell layout; or in response to a second standard cell layout obtained based on the second voltage domain information satisfying a second timing closure condition, adopt the second standard cell layout for the target circuit.

[0005] At least some embodiments of the present disclosure further provide an electronic device, comprising the cache device provided by any embodiment of the present disclosure or the processor provided by any embodiment of the present disclosure.

[0006] At least some embodiments of the present disclosure further provide a non-transitory storage medium that non-transitory stores computer-executable instructions. When the computer-executable instructions are executed by at least one processor, the circuit layout method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0008] Figure 1A A block diagram of a voltage domain is shown;

[0009] Figure 1B A schematic diagram of a voltage domain timing path is shown;

[0010] Figure 2 A schematic flow chart of a circuit layout method provided by at least one embodiment of the present disclosure is shown;

[0011] Figure 3 An exemplary layout diagram of a physical area of ​​an object voltage domain including multiple interactive modules provided by at least one embodiment of the present disclosure is shown;

[0012] Figure 4 A schematic diagram of a DBSCAN algorithm provided by at least one embodiment of the present disclosure is shown;

[0013] Figure 5 An exemplary flow chart of determining a voltage domain cluster provided by at least one embodiment of the present disclosure is shown;

[0014] Figure 6 A schematic diagram of a Delaunay triangulation algorithm provided by at least one embodiment of the present disclosure is shown;

[0015] Figure 7 A schematic diagram of the empty circle property of a Delaunay triangulation algorithm provided by at least one embodiment of the present disclosure is shown;

[0016] Figure 8 A schematic diagram of a right-angle conversion provided by at least one embodiment of the present disclosure is shown;

[0017] Figure 9 A schematic diagram illustrating an exemplary flow chart of a circuit layout provided by at least one embodiment of the present disclosure is shown;

[0018] Figure 10 An exemplary layout diagram of a voltage domain cluster divided by multiple interactive modules provided by at least one embodiment of the present disclosure is shown;

[0019] Figure 11 A block diagram of a circuit layout device provided by at least one embodiment of the present disclosure is shown;

[0020] Figure 12 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0021] Figure 13 A block diagram illustrating an electronic device provided by at least one embodiment of the present disclosure; and

[0022] Figure 14 A schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0025] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components. When any component of an embodiment of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0026] When the circuits of electronic devices such as chips are in a static state without any operation (for example, no switching operation or data transmission), static leakage power (Static Leakage Power) is generated due to carrier leakage in the semiconductor device (such as the phenomenon that a small amount of current still leaks when the transistor is in the off state), thereby increasing the overall power consumption of the chip. Using multiple voltage domains to allocate different circuit logic to different voltage domains can reduce the generation of static leakage power. Moreover, if power gating technology is further adopted on this basis, power consumption can be saved by directly shutting down non-operating modules.

[0027] Figure 1A A block diagram of a voltage domain is shown, such as Figure 1A As shown, the voltage domains are divided according to whether the circuit logic can be turned off or not.

[0028] As shown in the figure, the circuit logic that is not turned off is placed in the normally open voltage domain AON (Always On Domain), and the circuit logic that can be turned off is placed in the off voltage domain ON / OFF (On Off Domain), so as to reduce the static leakage power consumption of the circuit logic in the off voltage domain in the static state. Figure 1A Building on this foundation, power gating technology is further employed during the layout and routing of the on / off voltage domains to control the power network's shutdown. As shown in the figure, controlling the power network's shutdown can be achieved using either an external switch or an internal switch. For example, an external switch can directly shut down the independent power inputs of modules within a voltage domain through the power supply control module, thereby powering down that voltage domain. For example, using an internal switch requires designing a dedicated power network for the voltage domain and connecting it to the upper-level network through switch cells. This disconnects the power network through the switch cells, thereby powering down the voltage domain.

[0029] However, whether using external or internal switches to shut down the control power network, each voltage domain must be individually connected to its own power network, and the power networks of different voltage domains must be physically separated to prevent abnormal chip operation. Therefore, the above-mentioned solution to reduce circuit power consumption increases the complexity of the power network and also increases the difficulty of timing convergence testing. In particular, when timing paths exist between different voltage domains, it further increases the difficulty of meeting timing convergence requirements.

[0030] A timing path is the path along which a signal travels from one register to another. This path includes logic gates, wiring, and other circuit elements. The delay of a timing path is a key factor affecting integrated circuit performance; the magnitude of this delay determines the signal's propagation time within the circuit.

[0031] Figure 1B A schematic diagram of a voltage domain timing path is shown, as shown in FIG. Figure 1B As shown in the figure, the timing path path1 is the timing path between the internal modules of the normally open voltage domain AON. Since the timing path path1 is located in the same voltage domain, when the timing convergence condition is not met, the starting module and the end module of the timing path path1 can be placed closer. However, due to Figure 1B The timing path Path2 in the example is the timing path between the module in the normally-on voltage domain AON and the module in the turn-off voltage domain ON / OFF. These timing paths reside in different voltage domains. Therefore, if the timing closure conditions are not met, the physical regions corresponding to the two voltage domains involved in Path2 must also be considered. For example, if the physical regions of the two voltage domains involved are set close together to meet the timing closure conditions, additional power management devices such as level shifters or isolation cells may be required due to the different supply voltages or large voltage differential between the two voltage domains. However, the additional addition of these devices is not conducive to meeting the timing closure conditions. Therefore, when there are a large number of timing paths between different modules, it becomes more difficult to meet the timing closure conditions.

[0032] For example, level shifters are used to convert voltage levels when transmitting signals between different voltage domains. Level shifters ensure that the voltage levels of signals transmitted between different voltage domains match, thus avoiding signal distortion or circuit damage.

[0033] Since parts in different voltage domains may switch on and off at different times or be in different working states, isolation units are required to effectively isolate signals to ensure signal integrity and circuit safety when transmitting signals between different voltage domains.

[0034] Furthermore, in order to facilitate the design of the power network and the placement during power management, and to facilitate the subsequent physical layout and routing of the circuit (such as standard cell placement and clock tree design, etc.), the physical area of ​​the voltage domain is usually divided into relatively regular areas, such as the physical area of ​​the voltage domain can be divided into rectangles. However, for example, Figure 1B As shown, timing paths may exist within the voltage domain and between voltage domains. Therefore, the above-mentioned division of the physical area of ​​the voltage domain is not the optimal layout solution that meets the timing convergence conditions.

[0035] For example, a voltage domain includes multiple interactive modules, which have timing paths with multiple modules. Because these modules have timing paths with each module, dividing the voltage domain of these modules makes it more difficult to meet timing closure requirements.

[0036] In addition, current layout tools cannot effectively plan the layout of modules or standard cells in voltage domains in undetermined physical areas. Especially when dividing multiple interacting modules, engineers need to repeatedly adjust the voltage domain design based on the results of timing convergence tests. This makes the process of designing voltage domains with full consideration of timing impact very complicated.

[0037] At least one embodiment of the present disclosure provides a circuit layout method, which comprises obtaining, for a target circuit, a first standard cell layout that satisfies a first timing closure condition and is determined based on first voltage domain information; determining, for a plurality of standard cells in an object voltage domain whose physical area is not determined in the first standard cell layout, first voltage domain cluster information including at least one voltage domain cluster corresponding to the standard cells in the physical area of ​​the object voltage domain, and obtaining second voltage domain information based on the first voltage domain cluster information; in response to a second standard cell layout obtained based on the second voltage domain information not satisfying a second timing closure condition, re-determining new first voltage domain cluster information for the standard cells, and obtaining updated second voltage domain information based on the first voltage domain cluster information for updating the second standard cell layout; or in response to a second standard cell layout obtained based on the second voltage domain information satisfying a second timing closure condition, adopting the second standard cell layout for the target circuit.

[0038] In the circuit layout method of the above-mentioned embodiment of the present disclosure, by dividing the object voltage domain of the undetermined physical area into at least one voltage domain cluster, second voltage domain information including first voltage domain cluster information is obtained, and then a timing convergence test is performed, and iterations are performed until the second standard cell layout corresponding to the second voltage domain information meets the second timing convergence condition, so that the physical layout of the target circuit can fully consider the impact of timing, and the previous first voltage domain information is updated according to the first voltage domain cluster information to obtain the second voltage domain information for timing convergence test, so that the design process of the circuit layout is simplified and easy to implement.

[0039] The various embodiments of the present disclosure will be described below with reference to specific examples.

[0040] Figure 2 A schematic flow chart of a circuit layout method provided by at least one embodiment of the present disclosure is shown.

[0041] like Figure 2As shown, in some embodiments of the present disclosure, the circuit layout method includes step S30, step S31, and step S32 or step S33.

[0042] Step S30: For the target circuit, obtain a first standard cell layout that meets a first timing closure condition and is determined based on the first voltage domain information.

[0043] Step S31: For multiple standard cells in the object voltage domain whose physical area is not determined in the first standard cell layout, determine first voltage domain cluster information including at least one voltage domain cluster corresponding to the standard cells in the physical area of ​​the object voltage domain, and obtain second voltage domain information based on the first voltage domain cluster information.

[0044] Step S32: in response to the second standard cell layout obtained based on the second voltage domain information not meeting the second timing closure condition, re-determine new first voltage domain cluster information of the standard cell, and obtain updated second voltage domain information based on the first voltage domain cluster information for updating the second standard cell layout.

[0045] Step S33: In response to the second standard cell layout obtained based on the second voltage domain information meeting the second timing closure condition, the second standard cell layout is adopted for the target circuit.

[0046] A "target circuit" refers to a circuit for which a standard cell layout needs to be determined, such as an integrated circuit device under design. In a multi-level circuit design, a target circuit can refer to a circuit at a specific level. A "voltage domain" refers to circuit logic that shares a common power supply source or voltage range, representing the division of circuit logic. For example, a voltage domain can include multiple modules, and a module can include multiple standard cells. An "object voltage domain" is used as a description object to describe one of at least one voltage domain for which a voltage domain physical area (VoltageArea) is not specified in the first voltage domain information. A "power cluster" is a spatially contiguous physical area planned in the physical layout. For example, a voltage domain's corresponding power domain physical area can include one or more power domain clusters. A "standard cell" is a pre-designed basic logic functional unit with a uniform standard size on the physical layout. For example, a standard cell can include common logic gates (such as AND gates and OR gates), flip-flops, and memory cells. For example, the height of a standard cell is uniform, and the width of the standard cell can be determined based on the function and electrical characteristics of the corresponding standard cell.

[0047] For example, a definition file for defining a voltage domain may be read to obtain a first standard cell layout that satisfies a first timing closure condition and is determined based on the first voltage domain information.

[0048] For example, a Unified Power Format (UPF) file can be read. A UPF file describes the power consumption intent and strategy of a circuit design. A UPF file includes information such as voltage domain definitions, power control signal assignments, and power network control, guiding the implementation and verification of low-power designs. For example, UPF files can be read by layout tools such as EDA (Electronic Design Automation) software.

[0049] If the voltage domain physical range is not specified in the UPF file, the layout tool will not actually divide the voltage domain physical area. For example, after the layout tool reads the UPF file of the target circuit with the current level A, for the turn-off module A_OFF and other modules A_OTHER that require automatic voltage domain layout, the layout tool will arrange the turn-off module A_OFF and other modules A_OTHER as close together as possible according to its built-in layout rules to meet the timing convergence requirements of the target circuit. For example, the layout tool must use specific commands to divide the actual physical range of the voltage domain before the turn-off module A_OFF and other modules A_OTHER can be arranged according to the specified voltage domain physical area.

[0050] It can be seen from this that the layout tool cannot perform appropriate physical area division for the standard cells in the object voltage domain that does not have a specified voltage domain physical range. Therefore, in order to obtain better timing results after the layout tool EDA tool reads the UPF file, the voltage domain information in the UPF file is retained, that is, the voltage domain information in the first voltage domain information is retained in the first standard cell layout that meets the first timing convergence condition based on the first voltage domain information.

[0051] In some embodiments of the present disclosure, the object voltage domain includes at least one multi-interaction module, and the multi-interaction module has a timing path with multiple modules of the first standard cell layout.

[0052] Figure 3 An exemplary layout diagram of a physical area of ​​an object voltage domain including multiple interactive modules provided by at least one embodiment of the present disclosure is shown.

[0053] like Figure 3 As shown, the multiple modules include ordinary modules M1, M2 and M3 shown in the solid circle part, and multi-interaction modules Mt1, Mt2, Mt3 and Mt4 shown in the dotted circle part. Since the multi-interaction modules have timing paths with multiple modules of the first standard cell layout, that is, they communicate with multiple modules, in order to meet the first timing convergence condition, as shown in FIG. Figure 3As shown, the multiple interactive modules Mt1, Mt2, Mt3 and Mt4 are not gathered in the same range in terms of physical layout, that is, they are relatively dispersed in terms of physical layout. Therefore, it is difficult to control the multiple interactive modules as the same voltage domain, and they should be distributed in different voltage domains.

[0054] Therefore, for these multi-interactive modules with undetermined physical areas, multiple voltage domain clusters can be divided according to their dispersed locations in the first standard cell layout to enable separate power shutdown control. That is, corresponding voltage domain clusters (not shown) can be divided for the multi-interactive modules Mt1, Mt2, Mt3, and Mt4 at their corresponding dispersed locations.

[0055] For example, multiple interacting modules in Design for Testability (DFT) integrated circuits (ICs), such as the Embedded Deterministic Test (EDT) module for testing and the On-Chip Clock Controller (OCC) module for clock synchronization, operate only when the chip is in test mode and are not operational in functional mode. By distributing the logic for these multiple interacting modules, dividing voltage domain clusters at the corresponding locations, and implementing independent power shutdown control, the chip's power consumption in functional mode can be further reduced, thereby achieving optimal timing while further reducing chip power consumption.

[0056] Integrated circuits (ICs) that employ Design for Testability (DFT) incorporate specific structures and logic into the circuit design to make the chip easier to test during manufacturing and use. This improves test coverage, reduces test time and cost, and ensures high chip reliability. For example, these techniques can include ScanDesign, Built-in Self-Test (BIST), and Boundary Scan.

[0057] Embedded deterministic testing (EDT) is an advanced test technology in design for test (DFT). It can significantly reduce the number of test vectors and test time while maintaining high test coverage. For example, EDT can achieve efficient test data management and transmission by combining test vector compression and decompression technology with scan design.

[0058] The on-chip clock controller (OCC) module is a circuit logic integrated within the chip that manages and controls the generation, distribution, and adjustment of clock signals. It is an indispensable part of modern integrated circuit (IC) design. Especially in complex system-on-chip (SoC) designs, clock control is crucial to the performance, power consumption, and system reliability of the SoC.

[0059] When performing circuit layout, for a chip with multiple interactive modules, the object voltage domain including at least one multi-interactive module is divided at dispersed positions of the multi-interactive modules (such as timing-critical positions) to obtain multiple voltage domain clusters. This can fully consider the impact of timing to meet the timing convergence conditions, and because each voltage domain cluster can perform independent power shutdown control, it can further reduce the power consumption of the chip in functional mode.

[0060] It should be noted that the first standard cell layout may include multiple voltage domains with undetermined physical areas. For example, all voltage domains in the first standard cell layout have undetermined physical areas. For example, in the first standard cell layout, some voltage domains have determined physical areas, while other voltage domains have undetermined physical areas. The present disclosure does not limit the determination of the physical areas of the voltage domains of each voltage domain in the first standard cell.

[0061] In some embodiments of the present disclosure, the first standard cell layout includes a determined physical area of ​​a voltage domain, and the second standard cell layout includes the determined physical area in the first standard cell layout and at least one voltage domain cluster.

[0062] For example, the first voltage domain information may include the designation of the voltage domain physical area of ​​part of the voltage domain. For this part of the voltage domain with the determined physical area, there is no need to perform automatic layout, and the determined physical area of ​​the voltage domain can be retained in the first standard cell layout.

[0063] For example, for modules or standard cells in a voltage domain portion of an undetermined physical region, such as a turn-off module A_OFF, automatic layout can be performed according to steps S30 to S33 of the present disclosure. First voltage domain cluster information for at least one voltage domain cluster corresponding to the standard cells of the turn-off module A_OFF in the physical region of the voltage domain corresponding to the turn-off module A_OFF is determined. The first voltage domain information is updated based on the first voltage domain cluster information to obtain second voltage domain information, thereby determining the second standard cell layout. The "first timing closure condition" and the "second timing closure condition" can be the same timing closure condition or different timing closure conditions. For example, the timing closure condition can be the worst negative slack (WNS). In static timing analysis, WNS is an important metric for measuring whether timing requirements are met. It indicates the most severe timing violation in a design, namely, the maximum value at which data arrives later than the required time. For example, both the first and second timing closure conditions can be set to WNS = 0 (ns).

[0064] In some embodiments of the present disclosure, the above-mentioned circuit layout method further includes: adding an auxiliary network to the second standard cell layout based on the first voltage domain cluster information; and performing a timing convergence test on the second standard cell layout to determine whether the second standard cell layout meets the second timing convergence condition.

[0065] An "auxiliary network" includes a circuit logic network that assists standard cells divided into voltage domain clusters in implementing their functions. For example, it can be a power supply network. For example, the power supply network can include a power supply and a power switch. The power supply network can be implemented through multiple metal layers. For example, the bottom metal layer includes a power switch for connecting various voltage domains / voltage domain clusters, thereby achieving independent power control of each voltage domain / voltage domain cluster through the power switch. It should be noted that the auxiliary network can also include other circuits used to assist in function implementation or testing, and this disclosure does not limit the specific reference to the auxiliary network.

[0066] For example, in a multi-level circuit, for a target circuit whose current level is A, after obtaining the second standard cell layout, the power supply network can be added to the second standard cell layout, and then a timing convergence test based on the second timing convergence condition can be performed, so that the circuit layout of the target circuit determined by the present disclosure is closer to the actual situation and more credible.

[0067] Since the timing closure test is performed after the auxiliary network is added, the added auxiliary network may deteriorate the timing, which may require a long time and multiple rounds of iterations to determine the second standard cell layout that meets the second timing closure condition. Therefore, the first timing closure condition can be set to be stricter than the second timing closure condition.

[0068] For example, in some embodiments of the present disclosure, the most severe negative timing margin specified by the first timing closure condition is greater than the most severe negative timing margin specified by the second timing closure condition. For example, the first timing closure condition can be set to WNS=10 (ns), and the second timing closure condition can be set to WNS=0 (ns). By setting the first timing closure condition to be stricter than the second timing closure condition, a certain timing margin is reserved in the first standard cell layout, which can reduce the number of iterations for the second standard cell and obtain a circuit layout of the target circuit that meets the second timing closure condition. In particular, after adding the auxiliary network that is actually needed, it is possible to avoid excessive iteration time and rounds, thereby improving the efficiency of determining the circuit layout.

[0069] For example, for each module (including multiple interactive modules) of the object voltage domain whose physical area is not determined, a clustering algorithm can be used to perform clustering processing to divide the voltage domain into clusters.

[0070] In some embodiments of the present disclosure, an example of the above-mentioned step S31 includes: clustering the standard cells based on clustering parameters to obtain at least one cluster; determining at least one voltage domain cluster divided according to the at least one cluster, and determining first voltage domain cluster information according to the at least one voltage domain cluster.

[0071] For example, the clustering parameters include domain scope and minimum number of standard cells. Correspondingly, the circuit layout method further includes: in response to the number of standard cells included in the target domain scope being greater than or equal to the minimum number of standard cells, creating clusters for the standard cells in the target domain scope.

[0072] Here, the "target domain range" is determined based on the target standard cell of the standard cell, and the "target standard cell" is a standard cell that is a description target in the "target voltage domain".

[0073] For example, the clustering parameter domain range and the minimum number of standard units can be calculated based on the acquired setting parameters, or can also be directly set, and the present disclosure does not impose any restrictions on this.

[0074] For example, if the number of standard cells included in the object domain of the target standard cell (including the target standard cell) is greater than or equal to the minimum number of standard cells, the target standard cell can be regarded as a core object (CorePoints).

[0075] It should be noted that the present disclosure does not limit the specific clustering algorithm. For example, it can be a partition-based clustering algorithm, a density-based clustering algorithm, a hierarchy-based clustering algorithm, or a model-based clustering algorithm, and can be selected based on actual layout requirements. For example, the Gaussian Mixture Model (GMM) algorithm or the Spectral Clustering algorithm can be selected.

[0076] The following takes the density-based clustering algorithm DBSCAN (Density-Based Spatial Clustering of Applications with Noise) as an example for detailed description.

[0077] For example, before performing the DBSCAN algorithm, the following two setting parameters can be specified: the preset radius ε and the minimum number of standard cells MinCells.

[0078] The preset radius ε is used to determine the object domain range Nε(x,y) in the aforementioned clustering parameters based on the coordinate position (x,y) of the object standard unit. For example, the preset radius ε can be an initial value determined based on the process. The size of the preset radius ε can be determined based on the rectangular position occupied by a minimum standard unit in the process. For example, the rectangular position occupied by the minimum standard unit in the process is considered to be a site (generally measured in um in design). For example, the preset radius ε can be set to 20*site_width.

[0079] It should be noted that, because standard cells are typically small, their size is generally not considered. When determining the coordinate position of a standard cell, the coordinates of a fixed point within the physical area (cell box) of the standard cell can be selected as the coordinates of the standard cell. For example, the physical area of ​​a standard cell is typically rectangular, and the coordinates of the lower left corner, center point, or upper right corner of the physical area of ​​the standard cell can be selected as the coordinates of the standard cell. This disclosure does not impose any restrictions on this.

[0080] It should be noted that the present disclosure does not limit the value of the preset radius ε. The larger the preset radius ε, the fewer the number of voltage domain clusters ultimately planned. Although this is beneficial to the winding resources and area in the chip, it will lose a certain amount of timing.

[0081] The minimum number of standard cells MinCells can be directly used as the above-mentioned clustering parameter to indicate the minimum number of standard cells that the user expects the voltage domain cluster to contain, that is, clusters with less than this number within the domain will not be able to form a voltage domain cluster. For example, the minimum number of standard cells MinCells = 10, which means that at least 10 standard cells must be together to form a voltage domain cluster. The present disclosure does not limit the value of the minimum number of standard cells MinCells. It should be noted that the larger the value of the minimum number of standard cells MinCells, the more beneficial it is to the winding resources and area in the chip, but a certain amount of timing will be lost.

[0082] For example, when clustering is performed using a density-based clustering algorithm, the domain range can be determined based on the relationship between density directness, density reachability, and density connection in the density-based clustering algorithm.

[0083] For Directly Density-Reachable, for example, based on the coordinate position (x,y) of the target standard cell, density-reachable can indicate that the coordinate point (x1,y1) of a standard cell is within the range Nε(x,y)={dist((x1,y1),(x,y))≤ε} of the coordinate point (x,y) of the target standard cell. Furthermore, when the target standard cell is a core object, it can be said that the standard cell (x1,y1) is directly density-reachable from the target standard cell (x,y). In addition, considering that the routing cannot be a diagonal line during the back-end physical implementation, the algorithm for calculating the distance dist((x1,y1),(x,y)) can be calculated using the Manhattan distance calculation method, making the distance calculation more accurate.

[0084] For density-reachable, if there are two standard cells that are directly density-reachable to another standard cell, that is, although the density between the two standard cells is not directly reachable, the two standard cells can be called density-reachable.

[0085] For density-connected: If there is a standard cell (x, y) as a core object, so that any two standard cells are density-reachable with the core object (x, y), then the two standard cells are considered to be density-connected.

[0086] Figure 4 A schematic diagram of an example of a DBSCAN algorithm provided by at least one embodiment of the present disclosure is shown.

[0087] For example, Figure 4 As shown, the density of standard cell Cell 1 and standard cell Cell 2 is directly connected.

[0088] The density of standard cell Cell 3 and standard cell Cell 4 is directly reached, and the density of standard cell Cell 5 and standard cell Cell 4 is directly reached. Therefore, the density of standard cell Cell 3 and standard cell Cell 5 is reachable.

[0089] The density of standard cell Cell 6 and standard cell Cell 7 is reachable, and the density of standard cell Cell 8 and standard cell Cell 7 is reachable. Therefore, when standard cell Cell 7 is a core object, standard cell Cell 6 and standard cell Cell 8 are density-connected.

[0090] The standard cells Cell 9 have no connection relationship with the standard cells Cell 9, that is, non-density connection.

[0091] In some embodiments of the present disclosure, the circuit layout method further includes: traversing each target standard cell in each standard cell; in response to the identification state of the target standard cell being an unvisited state, determining the target domain range according to the target standard cell and a preset radius.

[0092] For example, before traversing each standard cell, the identification state of each standard cell may be set to the unvisited state, or the identification state of each standard cell before traversing may be set to the unvisited state by default.

[0093] The present disclosure does not limit the order of traversing the standard cells.

[0094] In some embodiments of the present disclosure, the circuit layout method further includes:

[0095] In response to the number of standard cells in the object domain range being greater than or equal to the minimum number of standard cells, the identification state of the standard cells in the object domain range is set to the visited state; or, in response to the number of standard cells in the object domain range being less than the minimum number of standard cells, the identification state of the standard cells in the object domain range is set to the discarded state.

[0096] Continue to refer Figure 4 For example, the minimum number of standard cells is set to be greater than 2. Since standard cell Cell 9 is not within the scope of the field, and the number of standard cells within the target field of standard cell Cell 9 is less than 3, the identification status of standard cell Cell 9 can be set to a discardable state.

[0097] The method for determining a voltage domain cluster is described below with reference to an exemplary flowchart.

[0098] Figure 5 An exemplary flowchart of determining a voltage domain cluster provided by at least one embodiment of the present disclosure is shown.

[0099] like Figure 5 As shown, for an object voltage domain whose physical area is not determined, a preset radius ε and a minimum number of standard cells MinCells may be obtained first (step 101 );

[0100] Then, the corresponding coordinates of all standard cells in the target voltage domain are obtained, and the identification states of all standard cells in the target voltage domain are set to the unvisited state (step 102);

[0101] Traversing each standard cell in the target voltage domain (step 103);

[0102] Determine whether the currently traversed object standard cell (x, y) is marked (step 104);

[0103] If so, determine whether the traversal is complete (step 109);

[0104] If not, the identification state of the target standard cell (x, y) is marked as the visited state, and the number of standard cells within the target domain range Nε(x, y) of the target standard cell (x, y) is obtained (step 105);

[0105] Determine whether the number of standard cells within the target area Nε(x,y) is greater than or equal to the minimum number of standard cells MinCells (step 106);

[0106] If not, the identification status of all standard cells within the target domain range Nε(x,y) is marked as discardable (step 107);

[0107] If so, a new cluster is created for all standard cells within the object domain range Nε(x,y), and the identification status of all standard cells within the object domain range Nε(x,y) is marked as visited (step 108);

[0108] Afterwards, it is determined whether the traversal is completed (step 109 ). If not, the process returns to step 103 to continue traversing other standard cells in the target voltage domain.

[0109] If so, all created clusters are returned, where the standard cells contained in each cluster constitute a voltage domain cluster.

[0110] After the above exemplary process, some discrete standard cells in the standard layout cells are still marked as discardable. Since their physical locations are relatively independent and far away from other standard cells, creating voltage domain clusters for these discrete standard cells separately will consume more winding resources. Therefore, without affecting the final timing closure test results, these discardable standard cells can be incorporated into the already formed clusters or voltage domain clusters based on their physical locations.

[0111] In some embodiments of the present disclosure, the circuit layout method further includes: based on the physical location of the standard cell identified as the discardable state and the at least one cluster, merging the discardable standard cell into a corresponding cluster in the at least one cluster to determine at least one voltage domain cluster.

[0112] Continue to refer Figure 4 For example, without affecting the timing, the discardable standard cell Cell 9 can be considered to be merged into the corresponding cluster where the standard cells Cell 6, Cell 7 and Cell 8 are located to form a voltage domain cluster.

[0113] After the voltage domain clusters are divided, the boundaries of the voltage domain clusters need to be determined. Considering that the divided voltage domain clusters are often irregular in shape, in order to further use layout tools for automated layout and subsequent timing convergence testing, the boundary information of the irregular voltage domain clusters needs to be determined.

[0114] In some embodiments of the present disclosure, the example of step S31 above further includes:

[0115] In response to completion of the division of at least one voltage domain cluster, initial boundary information of each voltage domain cluster in the at least one voltage domain cluster is determined based on a discrete boundary extraction algorithm; the initial boundary information of each voltage domain cluster is processed according to the boundary recognition requirements of the layout tool to determine first voltage domain cluster information.

[0116] The boundary recognition requirement of the layout tool is the requirement that the layout tool can recognize the boundary. Different layout tools may have different boundary recognition requirements. For example, the boundary recognition requirement of some layout tools is that they can only recognize right-angled edges.

[0117] For example, the first voltage domain cluster information includes boundary information of the voltage domain cluster.

[0118] For example, when determining the boundary, the coordinates of the corners of the voltage domain cluster can be determined first based on the standard cells included in the voltage domain cluster. For example, when the number of standard cells included in the voltage domain cluster is too small, the coordinates of the four corners of the physical area (Cell Box) of the standard cells can be selected as the boundary of the generated voltage domain cluster, thereby ensuring that at least two coordinates are included in the x-axis direction and the y-axis direction.

[0119] The discrete boundary extraction algorithm can be selected from a variety of algorithms, for example, a convex hull algorithm can be used.

[0120] For example, when the boundary shape of the voltage domain cluster is a convex shape, a convex hull algorithm or other similar discrete boundary extraction algorithms can be used.

[0121] However, since the boundary shape of the automatically generated voltage domain cluster is irregular, it cannot be guaranteed that the voltage domain cluster shape is an absolutely convex boundary point set. For example, the boundary shape of the voltage domain cluster may be an L-shape, a U-shape, or even a donut-shape. Therefore, for voltage domain cluster point sets with such special shapes, the convex hull algorithm cannot effectively extract their boundaries.

[0122] To effectively extract the boundaries of the voltage domain cluster, you can use the Delaunay triangulation algorithm, which supports concave polygon extraction, to extract the boundaries. Then, extract the boundaries after the Delaunay triangulation. The following uses the Delaunay triangulation algorithm as an example to explain the circuit layout method in detail.

[0123] Figure 6 FIG2 shows a schematic diagram of a Delaunay triangulation algorithm provided by at least one embodiment of the present disclosure. Figure 6 The complex shape shown in the figure is a triangle set formed by Delaunay triangulation of the boundary (shown by the dotted line), which is very close to the real boundary (shown by the solid line). Figure 6 It can be seen that even very complex shapes can be well approximated using the Delaunay triangulation algorithm, which can well extract the shape of the boundary.

[0124] The Delaunay triangulation algorithm is different from other triangulation algorithms. The Delaunay triangulation algorithm has the following characteristics: (1) maximizing the minimum angle property; (2) the empty circle property.

[0125] Maximize the minimum angle property, that is, the triangles generated by the Delaunay triangulation algorithm tend to avoid too small angles, thereby maximizing the minimum angle.

[0126] The empty circle property states that for every triangle in the triangulation, its circumcircle contains no other points.

[0127] Figure 7 A schematic diagram of the empty circle property of a Delaunay triangulation algorithm provided by at least one embodiment of the present disclosure is shown.

[0128] like Figure 7 As shown in (a) and (b) in the figure, the circumcircle associated with triangle V1V2V4 (also called triangle T1) and triangle V3V2V4 (also called triangle T2) is empty, that is, the circumcircle of triangle T1 does not contain any points. Such triangles are classified as the triangles used by the Delaunay triangulation algorithm.

[0129] like Figure 7As shown in (c) and (d) in the figure, the circumcircle of triangles V1', V2', and V4' (also called triangle T1') and V3', V2', and V4' (also called triangle T2') is not empty. This means that the circumcircle of triangle T1 includes both points V1' and V3'. This triangulation is not a Delaunay triangulation.

[0130] From this we can see that the empty circle property in Delaunay triangulation is of great significance. It can help avoid dividing long and thin triangles with poor shapes, thereby making the triangle shapes in the triangulation more uniform and close to regular triangles, further ensuring the stability of the results.

[0131] In some embodiments of the present disclosure, the above-mentioned circuit layout method also includes: for an object voltage domain cluster in at least one voltage domain cluster, calculating the triangulation of the object voltage domain cluster based on the Delaunay triangulation algorithm; extracting the edges in the triangulation of the object voltage domain cluster that are not shared with other triangles to determine the initial boundary information of the object voltage domain cluster.

[0132] The boundary information of the voltage domain cluster is extracted through Delaunay triangulation. The Delaunay triangulation can be calculated based on the coordinate set that determines the boundary information of the voltage domain cluster. For example, the mathematical operation of this step can be performed using the Delaunay package of the Python scipy.spatial library.

[0133] Then, all edges not shared with other triangles are extracted from the Delaunay triangulation. For example, all coordinates corresponding to edges not shared with other triangles can be extracted in a clockwise direction to form i boundary coordinate sets Boundary(i) as the initial boundary information, where i is a positive integer. Each set consists of a set of continuous voltage domain cluster boundary points. For most voltage domain clusters, there is only one boundary set. For example, in rare cases, such as a donut-shaped voltage domain cluster, there may be two boundary sets that constitute the voltage domain cluster boundary information.

[0134] If the layout tool (eg, EDA software) does not support creating physical regions using diagonal lines, then if the obtained boundary information of the voltage domain cluster contains boundaries formed by diagonal lines, the boundary set Boundary(i) needs to be converted into a right angle.

[0135] In some embodiments of the present disclosure, the circuit layout method further includes: performing right-angle conversion on the oblique line boundaries in each initial boundary information to determine the first voltage domain cluster information.

[0136] Figure 8 A schematic diagram of a right-angle conversion provided by at least one embodiment of the present disclosure is shown.

[0137] For example, the boundary coordinate sets of each voltage cluster can be traversed. For any boundary coordinate set Boundary(i), for example, Figure 8 The boundary coordinate set shown includes the coordinates of a, b, c, d, e, f, g, and h. The coordinate values ​​of the jth coordinate and the j+1th coordinate can be compared, where j is a positive integer. For example, the jth coordinate can be the coordinate of a, and the j+1th coordinate can be the coordinate of b; for example, the jth coordinate is (x j ,y j ), the j+1th coordinate is (x j+1 ,y j+1 ), if x j Not equal to x j+1 At the same time j Not equal to y j+1 Then you can add a coordinate (x j+1 ,y j ) or (x j ,y j+1 ). All boundary coordinates in the boundary coordinate set Boundary(i) are transformed into a boundary polygon coordinate set Boundary_Poly after rectangular transformation.

[0138] For the boundary polygon coordinate set Boundary_Poly, a real physical boundary of the voltage domain cluster can be created by using a command of a layout tool EDA, as boundary information of the voltage domain cluster.

[0139] For example, you can use the following commands with the layout tool:

[0140] create_voltage_area –power_domian Power_cluster -region Boundary_Poly, creates the real physical boundary of the voltage domain cluster for the boundary polygon coordinate set Boundary_Poly.

[0141] Therefore, the boundary information of the voltage domain cluster can be determined according to the boundary polygon coordinate set Boundary_Poly.

[0142] Afterwards, second voltage domain information is obtained based on the first voltage domain cluster information including boundary information of the voltage domain cluster, and a timing closure test is performed on the second standard cell layout obtained based on the second voltage domain information, iteration can be performed according to the result of the timing closure test.

[0143] For example, when applying the DBSCAN algorithm to divide voltage domain clusters, the two set parameters, the preset radius ε and the minimum number of standard cells MinCells, will affect the clustering parameters, thereby affecting the physical range of the voltage domain cluster and the number of divided voltage domain clusters. Therefore, when the result of the timing convergence test on the second standard cell layout is that the timing does not converge, the values ​​of the above two clustering parameters can be continuously reduced to re-determine the first voltage domain cluster information until the timing converges. For example, each iteration can reduce the values ​​of the initially selected preset radius ε and the minimum number of standard cells MinCells by 1 or 2 respectively, so as to divide more voltage domain clusters after re-clustering to optimize the timing.

[0144] The above iterative process may be performed until the final timing closure test result is timing convergence.

[0145] This iterative process is described in detail below based on an exemplary flow chart of a circuit layout.

[0146] Figure 9 An exemplary flow chart of a circuit layout provided by at least one embodiment of the present disclosure is shown.

[0147] First, a timing drive that satisfies a first timing closure condition is completed based on the first voltage domain information, and a first standard cell layout is determined (step 201 );

[0148] Then, according to the clustering parameters, for example, by using a density-based clustering algorithm, at least one cluster of standard cells of the target voltage domain whose physical area is not determined in the first standard cell layout is obtained, thereby determining at least one voltage domain cluster division according to the at least one cluster (step 202);

[0149] Then, the voltage domain cluster boundary is obtained based on a discrete point boundary extraction algorithm, thereby determining the first voltage domain cluster information (step 203);

[0150] Then, the first voltage domain cluster information is added to the first voltage domain information to obtain the second voltage domain information, and a timing closure test based on a second timing closure condition is performed based on the second standard cell layout obtained from the second voltage domain information (step 204);

[0151] Determine whether the second standard cell layout meets the second timing closure condition through a timing closure test (step 205 );

[0152] If the timing convergence is satisfied, the process ends; if the timing convergence is not satisfied, the clustering parameters are adjusted / set and the process returns to step 202 .

[0153] The following illustrates exemplary layout results after the circuit layout method of the present disclosure.

[0154] Figure 10An exemplary layout diagram of a voltage domain cluster divided by multiple interactive modules provided by at least one embodiment of the present disclosure is shown.

[0155] like Figure 10 As shown, the distributed logic of multiple interactive modules is divided into voltage domain clusters PC1, PC2, PC3, and PC4. Standard cell Z can be incorporated into existing voltage domain clusters, or remain separate, depending on their physical location, without affecting the timing closure test results.

[0156] For example, in Figure 5 In the exemplary voltage domain cluster determination process shown, standard cell Z can be regarded as a standard cell marked as a discardable state. The processing method for standard cells marked as discardable states is the same as described above in this disclosure and will not be repeated here.

[0157] Through the above-mentioned circuit layout method of the present invention, the timing-driven standard cell layout can be automatically completed, and it has a good layout effect for circuit layouts with high requirements for timing convergence conditions but low requirements for area and winding resources. The above-mentioned layout method of the present invention is not limited to a single and shape-symmetrical standard cell layout planning rule, and can plan an asymmetric standard cell layout.

[0158] Figure 11 A block diagram of a circuit layout device provided by at least one embodiment of the present disclosure is shown. Figure 11 As shown, the circuit layout device 100 includes an acquisition module 110 and a determination module 120 .

[0159] The acquisition module 110 is configured to acquire, for a target circuit, a first standard cell layout that meets a first timing closure condition and is determined based on the first voltage domain information.

[0160] The determination module 120 is configured to determine, for a plurality of standard cells in an object voltage domain whose physical area is not determined in the first standard cell layout, first voltage domain cluster information of at least one voltage domain cluster corresponding to the standard cells in the physical area of ​​the object voltage domain, and obtain second voltage domain information based on the first voltage domain cluster information.

[0161] The determination module 120 is further configured to, in response to the second standard cell layout obtained based on the second voltage domain information not satisfying the second timing closure condition, re-determine new first voltage domain cluster information of the standard cell, and obtain updated second voltage domain information based on the first voltage domain cluster information for updating the second standard cell layout; or, in response to the second standard cell layout obtained based on the second voltage domain information satisfying the second timing closure condition, adopt the second standard cell layout for the target circuit.

[0162] For example, the determination module 120 is further configured to cluster the standard cells based on the clustering parameters to obtain at least one cluster; determine at least one voltage domain cluster divided according to the at least one cluster, and determine the first voltage domain cluster information according to the at least one voltage domain cluster.

[0163] For example, clustering parameters include domain scope and minimum number of standard units.

[0164] For example, the determination module 120 is further configured to create clusters for the standard cells in the object domain range in response to the number of standard cells included in the object domain range being greater than or equal to the minimum number of standard cells, wherein the object domain range is determined based on the object standard cells of the standard cells.

[0165] For example, the determination module 120 is further configured to traverse each object standard cell in each standard cell; in response to the identification state of the object standard cell being an unvisited state, determine the object domain range according to the object standard cell and a preset radius.

[0166] For example, the determination module 120 is further configured to, in response to the number of standard cells in the object domain scope being greater than or equal to the minimum number of standard cells, set the identification status of the standard cells in the object domain scope to the visited state; or, in response to the number of standard cells in the object domain scope being less than the minimum number of standard cells, set the identification status of the standard cells in the object domain scope to the discarded state.

[0167] For example, the determination module 120 is further configured to merge the discardable standard cells into corresponding clusters in the at least one cluster based on the physical locations of the discardable standard cells and the at least one cluster, so as to determine at least one voltage domain cluster.

[0168] For example, clustering is performed based on a density-based clustering algorithm, and the domain scope is determined based on the density directness, density reachability, and density connection relationships in the density clustering algorithm.

[0169] For example, the determination module 120 is further configured to determine the initial boundary information of each voltage domain cluster in the at least one voltage domain cluster based on a discrete boundary extraction algorithm in response to completion of the division of at least one voltage domain cluster; and process the initial boundary information of each voltage domain cluster according to the boundary recognition requirements of the layout tool to determine the first voltage domain cluster information.

[0170] For example, the determination module 120 is further configured to perform right-angle conversion on the oblique line boundaries in each initial boundary information to determine the first voltage domain cluster information.

[0171] For example, the determination module 120 is further configured to calculate the triangulation of the object voltage domain cluster in at least one voltage domain cluster based on the Delaunay triangulation algorithm; and extract the edges in the triangulation of the object voltage domain cluster that are not shared with other triangles to determine the initial boundary information of the object voltage domain cluster.

[0172] For example, the object voltage domain includes at least one multi-interaction module, and the multi-interaction module has a timing path with a plurality of modules of the first standard cell layout.

[0173] For example, the first standard cell layout includes a determined physical area of ​​a voltage domain, and the second standard cell layout includes the determined physical area and at least one voltage domain cluster.

[0174] For example, the most severe negative timing margin specified by the first timing closure condition is greater than the most severe negative timing margin specified by the second timing closure condition.

[0175] For example, the determination module 120 is further configured to add an auxiliary network to the second standard cell layout based on the first voltage domain cluster information; and perform a timing closure test on the second standard cell layout to determine whether the second standard cell layout meets the second timing closure condition.

[0176] The technical effects of the circuit layout device of the above embodiment of the present disclosure are the same as the technical effects of the above circuit layout method, and therefore will not be described in detail.

[0177] Figure 12 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0178] At least one embodiment of the present disclosure further provides an electronic device, such as Figure 12 As shown, the electronic device 600 includes at least one memory 610 and at least one processor 620 .

[0179] The memory 610 is configured to store computer-executable instructions.

[0180] The processor 620 is configured to execute computer-executable instructions. When the computer-executable instructions are executed by at least one processor, the circuit layout method provided by any embodiment of the present disclosure is implemented.

[0181] The memory 610 may include, for example, a semiconductor memory unit, such as a dynamic random access memory (DRAM), a random access memory (RAM), or a static random access memory (SRAM), or any other memory with a storage function.

[0182] The processor 620 may be, for example, any processing circuit with processing capabilities implemented through hardware or firmware, such as a central processing unit (CPU) or a coprocessor, a microcontroller unit (MCU), or a digital signal processor (DSP). For example, the coprocessor may be an accelerator (e.g., a graphics accelerator or a digital signal processing unit), a graphics processing unit (GPU), a programmable logic array, or any other processor with instruction execution capabilities. The embodiments of the present disclosure do not limit the implementation of the at least one memory 610 and the at least one processor 620.

[0183] The technical effects of the electronic device of the above embodiment of the present disclosure are the same as the technical effects of the above circuit layout method, and therefore will not be described in detail.

[0184] Figure 13 A block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0185] The electronic devices in the embodiments of the present disclosure may include but are not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 13 The electronic device 1000 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0186] For example, reference Figure 13 In some examples, electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 into a random access memory (RAM) 1003. For example, processing device 1001 can execute the circuit layout method provided in any of the above-mentioned embodiments of the present disclosure. RAM 1003 also stores various programs and data required for the operation of the computer system. Processing device 1001, ROM 1002, and RAM 1003 are connected to each other via an internet network 1004. An input / output (I / O) interface 1005 is also connected to internet network 1004.

[0187] For example, the following components can be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 which can also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 can allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. Removable media 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 1010 as needed, so that the computer program read therefrom can be installed into the storage device 1008 as needed. Although Figure 13 The electronic device 1000 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0188] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0189] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, the circuit layout method provided by at least one embodiment of the present disclosure is implemented.

[0190] Figure 14 Schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. Figure 14 As shown, the non-transitory storage medium 900 can non-transitory store computer-executable instructions 910 , which, when executed by a computer, implement the circuit layout method provided by any embodiment of the present disclosure.

[0191] Regarding this disclosure, the following points need to be explained:

[0192] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0193] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0194] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A circuit layout method, comprising: For the target circuit, obtaining a first standard cell layout that satisfies a first timing closure condition and is determined based on the first voltage domain information; For a plurality of standard cells in a target voltage domain whose physical area is not determined in the first standard cell layout, determining first voltage domain cluster information of at least one voltage domain cluster corresponding to the standard cells in the physical area of ​​the target voltage domain, and obtaining second voltage domain information based on the first voltage domain cluster information; In response to a second standard cell layout obtained based on the second voltage domain information not meeting a second timing closure condition, re-determining new first voltage domain cluster information of the standard cell, and obtaining updated second voltage domain information based on the first voltage domain cluster information for updating the second standard cell layout; or In response to the second standard cell layout obtained based on the second voltage domain information satisfying the second timing closure condition, the second standard cell layout is adopted for the target circuit.

2. The circuit layout method according to claim 1, wherein: The determining of first voltage domain cluster information of at least one voltage domain cluster corresponding to the standard cell in the physical area of ​​the target voltage domain includes: Performing clustering processing on the standard units based on clustering parameters to obtain at least one cluster; The at least one voltage domain cluster divided is determined according to the at least one cluster, so as to determine the first voltage domain cluster information according to the at least one voltage domain cluster.

3. The circuit layout method according to claim 2, wherein: The clustering parameters include domain scope and minimum number of standard units; The step of clustering the standard units based on the clustering parameters to obtain at least one cluster includes: In response to the number of standard cells included in the target domain range being greater than or equal to the minimum number of standard cells, clusters are created for the standard cells in the target domain range, wherein the target domain range is determined based on the target standard cells of the standard cells.

4. The circuit layout method according to claim 3, wherein: The clustering process of the standard units based on the clustering parameters to obtain at least one cluster further includes: Traversing each target standard cell in the standard cells; In response to the identification state of the object standard unit being an unvisited state, the object area range is determined according to the object standard unit and a preset radius.

5. The circuit layout method according to claim 4, wherein: The clustering process of the standard units based on the clustering parameters to obtain at least one cluster further includes: In response to the number of standard cells in the target domain being greater than or equal to the minimum number of standard cells, setting the identification status of the standard cells in the target domain to an accessed status; or In response to the number of standard cells in the target domain being less than the minimum number of standard cells, the identification status of the standard cells in the target domain is set to a discardable state.

6. The circuit layout method according to claim 5, wherein: The determining of the at least one voltage domain cluster divided according to the at least one cluster comprises: Based on the physical location of the standard cell identified as the discardable state and the at least one cluster, the discardable standard cell is merged into a corresponding cluster in the at least one cluster to determine the at least one voltage domain cluster.

7. The circuit layout method according to claim 3, wherein: The clustering process is performed based on a density-based clustering algorithm. The domain range is determined based on the density directness, density reachability and density connection relationships in the density clustering algorithm.

8. The circuit layout method according to claim 2, wherein: The determining includes first voltage domain cluster information of at least one voltage domain cluster corresponding to the standard cell in the physical area of ​​the target voltage domain, further comprising: In response to the completion of the division of the at least one voltage domain cluster, determining initial boundary information of each voltage domain cluster in the at least one voltage domain cluster based on a discrete boundary extraction algorithm; The initial boundary information of each voltage domain cluster is processed respectively according to the boundary identification requirement of the layout tool to determine the first voltage domain cluster information.

9. The circuit layout method according to claim 8, wherein: The processing of the initial boundary information of each voltage domain cluster according to the boundary identification requirements of the layout tool includes: A right-angle conversion is performed on each oblique line boundary in the initial boundary information to determine the first voltage domain cluster information.

10. The circuit layout method according to claim 8, wherein: The determining the initial boundary information of each voltage domain cluster in the at least one voltage domain cluster based on a discrete boundary extraction algorithm includes: For a target voltage domain cluster in the at least one voltage domain cluster, calculating a triangulation of the target voltage domain cluster based on a Delaunay triangulation algorithm; Edges not shared with other triangles in the triangulation of the object voltage domain cluster are extracted to determine initial boundary information of the object voltage domain cluster.

11. The circuit layout method according to any one of claims 1 to 10, wherein: The object voltage domain includes at least one multi-interaction module, and the multi-interaction module has a timing path with multiple modules of the first standard cell layout.

12. The circuit layout method according to any one of claims 1 to 10, wherein: The first standard cell layout includes a determined physical area of ​​a voltage domain, The second standard cell layout includes the determined physical region and the at least one voltage domain cluster.

13. The circuit layout method according to any one of claims 1 to 10, wherein: The most severe negative timing margin specified by the first timing closure condition is greater than the most severe negative timing margin specified by the second timing closure condition.

14. The circuit layout method according to any one of claims 1 to 10, further comprising: adding an auxiliary network to the second standard cell layout based on the first voltage domain cluster information; A timing closure test is performed on the second standard cell layout to determine whether the second standard cell layout meets the second timing closure condition.

15. A circuit layout device comprising: An acquisition module is configured to acquire, for a target circuit, a first standard cell layout that satisfies a first timing closure condition and is determined based on the first voltage domain information; a determination module configured to determine, for a plurality of standard cells in a target voltage domain whose physical areas are not determined in the first standard cell layout, first voltage domain cluster information of at least one voltage domain cluster corresponding to the standard cells in the physical area of ​​the target voltage domain, and obtain second voltage domain information based on the first voltage domain cluster information; as well as In response to a second standard cell layout obtained based on the second voltage domain information not meeting a second timing closure condition, re-determining new first voltage domain cluster information of the standard cell, and obtaining updated second voltage domain information based on the first voltage domain cluster information for updating the second standard cell layout; or In response to the second standard cell layout obtained based on the second voltage domain information satisfying the second timing closure condition, the second standard cell layout is adopted for the target circuit.

16. An electronic device comprising: at least one memory configured to store computer-executable instructions; as well as At least one processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions implement the circuit layout method according to any one of claims 1 to 14 when executed by the at least one processor.

17. A non-transitory storage medium that non-transitory stores computer-executable instructions, wherein: When the computer-executable instructions are executed by at least one processor, the circuit layout method according to any one of claims 1 to 14 is implemented.

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