Wiring layout method based on reinforcement learning

Abstract

The invention relates to a wiring layout method based on reinforcement learning, which combines a macro-cell layout model and a congestion prediction model, and introduces a wiring evaluation mechanism in a layout stage, so as to improve the manufacturability and wiring success rate of chip design. The method specifically comprises the following steps: carrying out macro-cell layout by utilizing a layout model driven by reinforcement learning; performing congestion prediction on the layout result by using a congestion prediction model; extracting three types of features of a macro region, wiring density (RUDY) and pin density (Pin RUDY) after each layout iteration, normalizing the features, and combining the features into a three-channel feature map as the input of a congestion prediction model; and dynamically adjusting a reward function of reinforcement learning according to a prediction result, and guiding the layout model to avoid a high-congestion area. According to the method, the realizability of the layout scheme in the subsequent wiring stage can be remarkably improved, reworking is reduced, the design cost is reduced, and the method has high engineering practicability and expansibility.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation, and in particular relates to a routability layout method based on reinforcement learning. Background Art

[0002] As integrated circuit (IC) design becomes increasingly complex, layout optimization and routing become crucial steps, particularly in the design of modern high-performance computing chips. Traditional IC layout and routing methods rely on heuristic algorithms and rule-based approaches. While these methods can guarantee design manufacturability and performance to a certain extent, they often fail to effectively predict congested areas in the face of increasingly complex design requirements, leading to severe performance bottlenecks during the routing phase.

[0003] Existing deep reinforcement learning-based layout optimization algorithms often fail to fully consider routing congestion during the macrocell layout phase. In practical integrated circuit design, routing congestion is a key factor affecting circuit performance and manufacturability. Routing congestion occurs in areas where routing resources cannot meet routing requirements, leading to increased routing delays, decreased signal integrity, and even routing failures. Ignoring routing congestion can cause layout solutions generated by deep reinforcement learning to encounter problems during the subsequent detailed routing phase, failing to meet design requirements and even requiring upstream reconfiguration of the layout, extending the design cycle and increasing design costs.

[0004] To address the above issues, introducing routability analysis during the integrated circuit layout process has become one of the key ways to improve overall design quality. Routability refers to whether the subsequent routing stage can be completed smoothly under the current layout conditions and whether there is a risk of resource conflict or performance degradation. By introducing a congestion prediction mechanism during the layout stage, identifying potential congestion hotspots in advance, and optimizing the positions of macro cells, the routing failure rate and rework probability can be significantly reduced, and the layout quality and design convergence efficiency can be improved. Especially in high-density and high-complexity design scenarios, routability-driven layout optimization can not only alleviate the pressure on routing resources, but also improve timing convergence, reduce power consumption and area waste. Although there are several layout optimization methods that introduce routability information in the prior art, most of the existing methods rely on manually set heuristic rules and lack the ability to deeply model local spatial characteristics and routing requirement density. It is difficult to accurately respond to congestion hotspots in actual complex layout environments, and the generalization ability is limited.

[0005] Therefore, a new routability optimization method is urgently needed to overcome the shortcomings of the existing technology. Summary of the Invention

[0006] The present invention addresses the shortcomings of existing technologies by providing a routability layout method based on reinforcement learning. This method combines the adaptive optimization capabilities of reinforcement learning with congestion prediction models to proactively identify and avoid potential congested areas during the layout phase, thereby reducing conflicts during routing and improving overall design efficiency.

[0007] In order to solve the above problems, the present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention provides a routability layout method based on reinforcement learning, comprising the following steps:

[0009] S1. Build a layout model based on reinforcement learning, layout the macro cells of the chip, and obtain preliminary layout results;

[0010] S2. Acquire location information of the macro cell and extract layout features based on the location information of the macro cell, wherein the layout features include a macro region feature, a RUDY (Rectangular uniform wire density) feature, and a Pin RUDY (Pin RUDY) feature.

[0011] S3, preprocessing the layout features;

[0012] S4. Construct a congestion prediction model, input the preprocessed layout features, and obtain a prediction result of the layout congestion situation;

[0013] S5. Embed the congestion prediction model into the reinforcement learning-based layout model and update the layout results according to the prediction results;

[0014] S6. Repeat steps S2 to S5 until the layout model meets the convergence conditions and output the final layout result of the chip.

[0015] Furthermore, the congestion prediction model is a lightweight neural network model for predicting chip layout congestion; the model is based on a U-Net structure and includes an encoder and a decoder, wherein:

[0016] The encoder receives as input a three-channel feature map consisting of macro-region features, RUDY features, and Pin RUDY features to fully reflect the spatial distribution information of the layout data. It includes four cascaded downsampling modules, each consisting of a convolutional layer and a maximum pooling layer, which are used to gradually extract and compress the spatial information of the input feature map. At the end of the encoder, an Inception module is introduced, which extracts different features through multi-branch parallel convolution operations and concatenates the features of each branch output, thereby enhancing the diversity of feature representation and the model's ability to recognize local and global congestion patterns. The decoder includes four groups of upsampling modules connected in series, each of which includes an upsampling layer, a convolutional activation module, and a feature fusion layer. The convolutional activation module includes a convolutional layer and a Pre-ReLU activation function. Each upsampling module first performs an upsampling operation to gradually restore the spatial resolution of the feature map, then extracts high-level semantic information through a convolutional layer and a Pre-ReLU activation function, and performs feature fusion to integrate the corresponding layer features from the encoder. After all structures are cascaded, a layer of convolution operation is used to compress the multi-channel feature map into a single-channel output to generate the final congestion prediction map.

[0017] The congestion prediction model can effectively guide the timely prediction and optimization of congestion conditions during chip layout.

[0018] Furthermore, after the initial layout of the macro cell is completed, feature maps are extracted to represent the layout structure and routing requirements, including: Macro Region feature map, RUDY feature map, and Pin RUDY feature map. Each feature map is a two-dimensional matrix of 256×256.

[0019] Specifically, obtaining layout features includes the following steps:

[0020] S201: Obtain layout result information of all macro units, including the coordinates of the lower left corner of each macro unit and its size information.

[0021] S202: Based on the layout result information of the macro unit, first calculate the bounding box of each line net on the layout plane according to the position of the pin connected to it; based on the overlapping relationship between the bounding box and the grid, estimate the wiring resource requirements of the line net for the grid unit, and generate the RUDY feature map and the Pin RUDY feature map.

[0022] S203: Traverse all macro units, and mark the grid units occupied by them as 1 and the unoccupied areas as 0 according to their positions and sizes on the chip plane, thereby forming a Macro Region feature map.

[0023] Furthermore, the layout features are preprocessed including normalization and splicing, specifically including the following steps:

[0024] S301: Min-Max normalization is performed on the Macro Region feature map, RUDY feature map, and Pin RUDY feature map calculated in S2. The Min-Max normalization calculation formula is:

[0025]

[0026] in is the eigenvalue of a certain position in the original feature map to be normalized, is the maximum value among all the positions in the feature map. is the minimum value among all the positions in the feature map. is the normalized eigenvalue.

[0027] Specifically: For the Macro Region feature map, Is the mark value (0 or 1) of whether the pixel is occupied by the macro unit; for the RUDY feature, is the estimated value of the wire mesh routing density corresponding to the current pixel position; for the Pin RUDY feature, Provides an estimate of the pressure on the pin wiring at that location.

[0028] Through normalization operation, the value ranges of the three feature maps are ensured to be unified in the interval [0,1], which facilitates the unified processing and training of subsequent prediction models.

[0029] S302: The three normalized two-dimensional images are stitched together to form a three-channel image with an image size of , the splicing method is as follows:

[0030]

[0031] in, Indicates the Row, No. The first channel is the macro area occupancy map, the second channel is the wiring density map (RUDY), and the third channel is the pin density map (Pin RUDY). is the normalized macro-region feature, is the normalized RUDY feature, is the normalized Pin RUDY feature. It is the combined three-channel feature map.

[0032] Furthermore, step S4 includes the following steps:

[0033] S401: Input the three-channel feature map generated in step S3 into the loaded congestion prediction model and perform forward inference on the model to obtain a two-dimensional congestion map corresponding to the current layout. This map numerically represents the congestion level of each area on the layout plane, with higher values ​​indicating more limited routing resources.

[0034] S402: Counting the congestion index in the entire two-dimensional congestion distribution map as a performance evaluation index of the current layout solution in the congestion dimension, that is, predicting the total congestion amount.

[0035] Furthermore, step S5 includes the following steps:

[0036] S501: Embed the congestion prediction model into the layout model and dynamically adjust the reinforcement learning reward function based on the predicted total congestion: To guide the macrocell layout to evolve towards the direction of optimizing both wire length and congestion, a joint reward function that combines wire length and predicted congestion is constructed. The specific form is:

[0037]

[0038] in, is the congestion penalty coefficient, is the total congestion output by the congestion prediction model, This is a reward item based on line length optimization.

[0039] S502: Feed the updated comprehensive reward back into the reinforcement learning training process to guide the optimization of the placement strategy network. This reward design can guide the placement model to favor placing macrocells in low-congestion areas in subsequent iterations, thereby gradually optimizing the congestion distribution in the placement results and achieving a coordinated optimization of placement quality and routability.

[0040] In a second aspect, the present invention provides a chip layout system for implementing the reinforcement learning-based routability layout method, comprising the following modules:

[0041] The preliminary layout module performs preliminary layout of the chip's macro units;

[0042] The feature extraction module extracts the location information of the macro unit and obtains the layout features, and then performs preprocessing;

[0043] The layout adjustment module uses the layout model embedded with the congestion prediction model to process the pre-processed layout features and outputs the optimized layout.

[0044] In a third aspect, the present invention provides an electronic device, comprising a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the method.

[0045] In a fourth aspect, the present invention provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the method.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The routability-driven reinforcement learning layout optimization method proposed in this paper embeds a congestion prediction model into the layout decision process. By extracting real-time characteristics of space occupancy, wiring density, and pin distribution in the layout state, it constructs a three-channel routability feature map and uses a lightweight neural network model for congestion prediction. By promptly obtaining prediction results after each layout iteration and incorporating the predicted congestion level into the reward function of the reinforcement learning layout strategy as a dynamic penalty term, the layout model gradually avoids congested areas during the learning process, improving the routability of the layout solution.

[0048] This method introduces a routability metric with higher prediction accuracy during layout training and feeds the prediction results back into the reinforcement learning process, where they serve as an additional penalty term in reward function design. This guides the model to proactively avoid potentially congested areas, enabling a layout strategy that is friendly to back-end routing. This not only effectively improves the feasibility of layout results in the subsequent routing phase, reducing the risk of routing failures and rework, but also unifies wirelength optimization with congestion control, significantly enhancing the intelligence of the layout phase and overall design quality. Furthermore, because the congestion prediction model is decoupled from the layout strategy module, it possesses excellent versatility and scalability, adapting to integrated circuit design tasks of varying scales and types, and possessing broad engineering application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a flow chart of the reinforcement learning-based routability layout optimization method provided by the present invention.

[0050] Figure 2 This is a schematic diagram of the congestion prediction model structure provided by the present invention. DETAILED DESCRIPTION

[0051] The following is a further detailed description of the principles and features of the reinforcement learning routability layout optimization method proposed by the present invention in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often part of the actual structure. In particular, each drawing needs to show different focuses, and sometimes different proportions are used.

[0052] The present invention provides a method for optimizing routability layout based on reinforcement learning, the flow chart of which is as follows: Figure 1 As shown in the figure, the current layout result is first obtained based on the layout model, and feature processing is performed on it to extract RUDY, Pin RUDY, and macro region features. Subsequently, the extracted features are input into the pre-trained congestion prediction model to generate a corresponding congestion map. This congestion map is passed to the layout model as feedback information. The layout model adjusts the macro cell position based on the reinforcement learning strategy to reduce the congested area and optimize the line length. The above process is repeated in an iterative manner until the reinforcement learning model determines convergence. Finally, the optimized layout result is output and evaluated using evaluation indicators to achieve coordinated optimization of line length and congestion.

[0053] The specific embodiment of the present invention is described in detail below:

[0054] S1. Build a layout model based on reinforcement learning, layout the macro cells of the chip, and obtain preliminary layout results;

[0055] S2. Obtain the location information of the macro cell and extract layout features based on the location information of the macro cell, including macro region features, RUDY (Rectangular uniform wire density) features, and Pin RUDY (Rectangular uniform wire density) features.

[0056] S3, preprocessing the layout features;

[0057] S4. Construct a congestion prediction model, input the preprocessed layout features, and obtain a prediction result of the layout congestion situation;

[0058] S5. Embed the congestion prediction model into the reinforcement learning-based layout model constructed in step S1, and update the layout result according to the prediction result;

[0059] S6. Repeat steps S2 to S5. After each layout iteration of the layout model, obtain the feature map of the current layout and input it into the model to predict the congestion of the current layout.

[0060] Based on the congestion level predicted by the model, the reinforcement learning reward function is adjusted to guide the model to avoid high-congestion areas in subsequent layouts, thereby optimizing the congestion during the layout process until the layout model meets the convergence conditions and outputs the final layout results of the chip.

[0061] After the initial layout of the macro cell is completed, feature maps are extracted to represent the layout structure and routing requirements, including: Macro Region feature map, RUDY feature map, and Pin RUDY feature map. Each feature map is a two-dimensional matrix of 256×256.

[0062] (1) Macro Region feature map is a two-dimensional heat map, which aims to mark which locations in the chip layout area are occupied by macro cells. Its essence is to perform grid-based discretization on macro cells, dividing the chip canvas into A grid, where Represents the first two-dimensional grid Row, No. Column (i=1,2,…,w; j=1,2,…,h), generate a two-dimensional matrix; each pixel value in the generated two-dimensional matrix indicates whether the position is occupied by a macro unit. If it is an area covered by a macro unit, , if it is an area not covered by a macro cell, .That

[0063]

[0064] (2) The RUDY feature map is a two-dimensional grid map based on the geometric information of the net. Its purpose is to estimate the wiring pressure or wiring density at each location in the layout area by analyzing the size of the bounding box of the net connection area without performing actual wiring.

[0065] A net is a collection of pins that need to be connected to each other in a circuit, representing the propagation path of electrical signals.

[0066] A bounding box is the smallest rectangular area that encloses all pins of a net on the chip layout plane. Its purpose is to estimate the net's approximate impact range or routing requirement area.

[0067] Assume that there are multiple pins in the Net, and their position coordinates are:

[0068]

[0069] The bounding box is defined as:

[0070]

[0071]

[0072] The bounding box width and height are:

[0073]

[0074] This rectangular area is the bounding box of the wire mesh.

[0075] Based on the net and bounding box, RUDY can be further calculated. RUDY is used to estimate the required routing resource density for each area without actually routing. Its core principle is to proportionally map the area of ​​the net's bounding box to the grid cells it covers.

[0076] First calculate the overlapping area of ​​the line mesh k and the grid unit :

[0077]

[0078] in Indicates the maximum and minimum coordinate values ​​of the bounding box of the k-th net in the x direction; Indicates the starting and ending coordinates of the grid cell (i, j) in the x direction; Indicates the maximum and minimum coordinate values ​​of the bounding box of the k-th net in the y direction; Indicates the starting and ending coordinates of the grid cell (i, j) in the y direction.

[0079] Grid Cell The area is:

[0080]

[0081] The RUDY value is:

[0082]

[0083] in Indicates the width of the bounding box of the k-th line mesh (length in the x direction); Indicates the bounding box height (y-direction length) of the k-th line mesh.

[0084] (3) Pin RUDY feature map is a two-dimensional grid map constructed based on pin distribution density. It is mainly used to estimate the pin clustering in local areas during the chip layout stage, thereby assisting in identifying potential wiring congestion areas.

[0085] Similar to RUDY, Pin RUDY also estimates the pin density generated by each pin on the grid cell where it is located through the bounding box geometry information of the wire network without performing actual wiring.

[0086] During the calculation process, first determine the network k to which the pin belongs, and obtain the bounding box boundary information of the network:

[0087]

[0088] in Indicates the maximum and minimum coordinate values ​​of the bounding box of the k-th net in the x direction; Indicates the maximum and minimum coordinate values ​​of the bounding box of the k-th net in the y direction.

[0089] Then calculate the width and height of the bounding box as:

[0090]

[0091] in Indicates the width of the bounding box of the k-th line mesh (length in the x direction); Indicates the bounding box height (y-direction length) of the k-th line mesh.

[0092] Each pin is projected onto the grid cell where it is located When the network is added, the Pin RUDY value of the corresponding network is evenly weighted to the grid cell. The basic formula of Pin RUDY is as follows:

[0093]

[0094] Finally, the contributions of all pins are accumulated in a two-dimensional grid to form a continuous numerical two-dimensional Pin RUDY feature map.

[0095] This image can be compared with the RUDY feature map, macro region Figure 1 It serves as a three-channel image feature and is input into the congestion prediction model for congestion prediction.

[0096] The S2 comprises the following sub-steps:

[0097] S201: After completing a round of layout optimization, obtain layout result information of all macro units, including the coordinates of the lower left corner of each macro unit and its size information.

[0098] S202: Based on the layout result information of the macro unit, first calculate the bounding box of each line net on the layout plane according to the position of the pin connected to it; based on the overlapping relationship between the bounding box and the grid, estimate the wiring resource requirements of the line net for the grid unit, and generate the RUDY feature map and the Pin RUDY feature map.

[0099] S203: Traverse all macro units, and mark the grid units occupied by them as 1 and the unoccupied areas as 0 according to their positions and sizes on the chip plane, thereby forming a Macro Region feature map.

[0100] Optionally, in the reinforcement learning-based routability layout optimization method, the third step includes the following sub-steps:

[0101] S301: Min-Max normalization is performed on the feature maps such as Macro Region, RUDY, and Pin RUDY calculated in step S2. The Min-Max normalization calculation formula is:

[0102]

[0103] in is the eigenvalue of a certain position in the original feature map to be normalized, is the maximum value among all the positions in the feature map. is the minimum value among all the positions in the feature map. is the normalized eigenvalue.

[0104] Specifically: For the Macro Region feature map, Is the mark value (0 or 1) of whether the pixel is occupied by the macro unit; for the RUDY feature, is the estimated value of the wire mesh routing density corresponding to the current pixel position; for the Pin RUDY feature, Provides an estimate of the pressure on the pin wiring at that location.

[0105] Through normalization operation, the value ranges of the three feature maps are ensured to be unified in the interval [0,1], which facilitates the unified processing and training of subsequent prediction models.

[0106] S302: The three normalized two-dimensional images are stitched together to form a three-channel image with an image size of , the splicing method is as follows:

[0107]

[0108] in, Indicates the Row, No. The first channel is the macro area occupancy map, the second channel is the wiring density map (RUDY), and the third channel is the pin density map (Pin RUDY). It is the combined three-channel feature map.

[0109] In step S4, the architecture of the congestion prediction model is as follows Figure 2 shown.

[0110] Optionally, in the reinforcement learning-based routability layout optimization method, the fifth step includes the following sub-steps:

[0111] S501: Input the three-channel feature map generated in step S4 into the loaded congestion prediction model and perform forward inference on the model to obtain a two-dimensional congestion distribution map corresponding to the current layout. This prediction map numerically represents the congestion level of each area on the layout plane, with higher values ​​indicating more limited routing resources.

[0112] S502: Counting the congestion index in the entire predicted congestion graph as a performance evaluation index of the current layout solution in the congestion dimension, that is, predicting the total congestion amount.

[0113] S503: Dynamically adjust the reinforcement learning reward function based on the congestion prediction results. To guide the macrocell layout to evolve towards the direction of optimizing both wire length and congestion, a joint reward function that combines wire length and predicted congestion is constructed. The specific form is:

[0114]

[0115] in, is the congestion penalty coefficient, is the total congestion output by the congestion prediction model, This is a reward item based on line length optimization.

[0116] Further, is the congestion penalty coefficient, which is used to adjust the relative weight of the congestion penalty term in the comprehensive reward function. Specifically, due to Usually in level, and Usually in Level, in order to avoid the change of a dominant reward value due to inconsistent scale, it is necessary to set it reasonably To balance the two influences.

[0117] In this embodiment, The following strategy is used for the setting:

[0118] First, count the first 10 rounds and The value of the first ten rounds is used to calculate the average and The values ​​of are defined as and ,but The definition is as follows:

[0119]

[0120] This setting ensures that in the reward function, and The items are of a considerable order of magnitude, thus achieving a coordinated trade-off between connection optimization and congestion control during training, and improving layout quality and routability.

[0121] S505: Embed comprehensive rewards into the reinforcement learning training process to guide the optimization direction of the placement strategy network. This reward design can guide the placement model to place macrocells in low-congestion areas in subsequent iterations, thereby gradually optimizing the congestion distribution in the placement results and achieving coordinated optimization of placement quality and routability.

[0122] Furthermore, the general reinforcement learning convergence condition is usually defined as follows: when the agent's average cumulative reward reaches a certain threshold over several consecutive training rounds, or when the reward curve becomes stable (for example, the standard deviation of reward changes approaches zero), the policy is considered to have converged. Alternatively, some methods determine convergence by monitoring changes in the behavior policy network output or a downward trend in performance indicators (such as success rate and loss value).

[0123] In this embodiment, a comprehensive convergence determination method based on reward statistics and objective function indicator trends is proposed in combination with the characteristics of the layout optimization task. The specific definition is as follows:

[0124] The training results of the last 10 consecutive rounds are used as a sliding window. After each round of training, the comprehensive reward (Reward), half-perimeter line length index (HPWL) and total congestion prediction (Total Congestion) corresponding to the layout quality are recorded. If the reward value fluctuation stability is met, that is, the standard deviation of the reward in 10 consecutive rounds is lower than the set threshold, the reward value is stable. , the model is judged to have converged.

[0125] Table 1 compares the half-circle wire length and total congestion for eight benchmark circuits using two layout flows, one with and one without the congestion prediction module. The results show that integrating the congestion prediction module significantly reduces the total congestion of the circuits, and some circuits also see improvements in half-circle wire length, validating the effectiveness of this approach in improving layout routability.

[0126] Table 1

[0127]

[0128] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A routability layout method based on reinforcement learning, characterized in that: The method comprises the following steps: S1. Build a layout model based on reinforcement learning, layout the macro cells of the chip, and obtain preliminary layout results; S2. Acquire the location information of the macro cell and extract layout features, wherein the layout features include macro area features, wiring resource requirement indicator rectangular area line density features, and rectangular area pin line density map features; S3, preprocessing the layout features; S4. Construct a congestion prediction model, input the preprocessed layout features, and obtain a prediction result of the layout congestion situation; S5. Embed the congestion prediction model into the reinforcement learning-based layout model and update the layout results according to the prediction results; S6. Repeat steps S2 to S5 until the layout model meets the convergence conditions and output the final layout result of the chip.

2. The routability layout method based on reinforcement learning according to claim 1, characterized in that Step S2 includes the following steps: S201: Obtaining layout result information of all macro units, including the coordinates of the lower left corner of each macro unit and its size information; S202: Based on the layout result information of the macro cell, first, calculate the bounding box of each line net on the layout plane according to the position of the pins connected to it; estimate the wiring resource demand of the line net for the grid cell based on the overlapping relationship between the bounding box and the grid, and generate the wiring resource demand indicator rectangular area line density feature and rectangular area pin line density map feature; S203: Traverse all macro units, and based on their positions and sizes on the chip plane, mark the grid units they occupy as 1 and mark the unoccupied areas as 0, thereby forming macro region features.

3. The routability layout method based on reinforcement learning according to claim 1, characterized in that The preprocessing in step S3 includes normalization and splicing to obtain a three-channel feature map including the wiring resource requirement indicator rectangular area line density feature and the rectangular area pin line density map feature.

4. The routability layout method based on reinforcement learning according to claim 3, characterized in that The congestion prediction model is based on the U-Net structure, including an encoder and a decoder, where: The encoder consists of four cascaded downsampling modules. Each downsampling module consists of a convolutional layer and a maximum pooling layer. Each convolution layer is followed by a PReLU activation function. An Inception module is introduced at the end of the encoder to extract different features through multi-branch parallel convolution operations. The output of each branch is spliced ​​and input into the decoder. The decoder includes four groups of upsampling modules connected in series, each of which includes an upsampling layer, a convolutional activation module and a feature fusion layer. The convolutional activation module includes a convolutional layer and a PReLU activation function; after the last feature fusion, the prediction result is output.

5. The routability layout method based on reinforcement learning according to claim 4, characterized in that Step S4 includes the following steps: S401: Input the three-channel feature map into the loaded congestion prediction model, perform forward inference on the model, and obtain a two-dimensional congestion distribution map corresponding to the current layout; S402: Counting the congestion index in the entire two-dimensional congestion distribution map as a performance evaluation index of the current layout solution in the congestion dimension, that is, predicting the total congestion amount.

6. The routability layout method based on reinforcement learning according to claim 1, characterized in that Step S5 includes the following steps: S501: Embed the congestion prediction model into the layout model and dynamically adjust the reinforcement learning reward function based on the predicted total congestion: To guide the macrocell layout to evolve towards the direction of optimizing both wire length and congestion, a joint reward function that combines wire length and predicted congestion is constructed, expressed as: ； in, is the congestion penalty coefficient, is the total congestion output by the congestion prediction model, This is a reward item based on line length optimization; S502: Feedback the updated comprehensive reward to the reinforcement learning training process to guide the optimization direction of the layout strategy network.

7. A chip layout system implementing the reinforcement learning-based routability layout method according to any one of claims 1 to 6, characterized in that: Includes the following modules: The preliminary layout module performs preliminary layout of the chip's macro units; The feature extraction module extracts the location information of the macro unit and obtains the layout features, and then performs preprocessing; The layout adjustment module uses the layout model embedded with the congestion prediction model to process the pre-processed layout features and outputs the optimized layout.

8. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the method according to any one of claims 1 to 6.

9. A machine-readable storage medium, characterized in that The machine-readable storage medium stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the method according to any one of claims 1 to 6.

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