A method for digital backend full-process script design

Abstract

The application discloses a method for digital back-end whole-process script design, and relates to the field of digital integrated circuit design, which comprises the following steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file value_lib.tcl; generating a gate level netlist and a corresponding comprehensive report by using the library configuration file value_lib.tcl; generating the gate level netlist by make syn logic synthesis according to the behavior level netlist, and generating layout and routing data by make out; performing antenna inspection by make ant command, design rule inspection by make drc command, and comparison inspection between a layout and a schematic by make lvs command according to the layout and routing data; performing power consumption analysis according to the layout and routing data; and performing IR analysis according to parasitic parameters. The application improves the design efficiency in view of the low efficiency of the chip digital back-end design process in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital integrated circuit design, and particularly relates to a method for designing a digital back-end full-process script. BACKGROUND

[0002] With the continuous evolution of chip manufacturing processes, the complexity of chip design is continuously improved, especially at advanced process nodes, the integration and functional density of chips increase dramatically, which brings great challenges to digital back-end design.

[0003] At present, the mainstream digital back-end design process in the industry generally includes the stages of synthesis, layout and routing, physical verification, SIGNOFF, etc. In the synthesis stage, the behavior-level design needs to be converted into a gate-level netlist and logical optimization and mapping are performed; in the layout and routing stage, the layout and routing of standard cells are completed according to physical constraints and routing resources; in the physical verification stage, DRC / LVS / ANT rule checks are performed on the layout and routing results; in the SIGNOFF stage, STA / Power / IR analysis is performed to ensure the functionality, performance and reliability of the chip.

[0004] However, different designs use different technology library files and constraint files, resulting in poor compatibility and consistency of the synthesis results, which requires repeated manual processing and debugging, and is low in efficiency. SUMMARY

[0005] In view of the low efficiency of the chip digital back-end design process in the prior art, the present application provides a method for designing a digital back-end full-process script, which processes each link of the digital back-end design in a flowchart manner through script-driven mode, and generates a general standard cell technology library file through RTL design, technology library and constraint conditions, and at the same time establishes a unified interface for layout and routing, physical verification, power consumption analysis and IR analysis and other tasks, thereby improving the design efficiency.

[0006] The purpose of the present application is achieved by the following technical solutions.

[0007] The application provides a method for digital backend full-process script design, comprising: receiving an RTL behavior level netlist, a technology library file and a constraint file as input, and generating a library configuration file value_lib.tcl; generating a gate level netlist and a corresponding synthesis report by using the library configuration file value_lib.tcl; performing logic synthesis by make syn to generate a gate level netlist and layout and routing data according to the behavior level netlist; performing antenna inspection by make ant command, design rule inspection by make drc command and comparison inspection between a generated layout and a schematic by make lvs command according to the layout and routing data; and outputting a GDSII layout file by make out command according to the layout and routing data.

[0008] The RTL behavior level netlist (Register Transfer Level Design File) is a high-level description method of digital circuit design, which uses a hardware description language (such as Verilog, VHDL) to describe the structure and behavior of the circuit. The RTL behavior level netlist defines registers, combinational logic, sequential logic and data flow between them in an abstract way of register transfer level. The RTL behavior level netlist usually contains module definition, port declaration, register definition, combinational logic expression, sequential logic statement and the like, and describes the function and timing relationship of the circuit, which is the starting point of logic synthesis.

[0009] The technology library file (Technology Library File) is a file describing the characteristics and parameters of library units such as standard cells, I / O cells and memories under a specific process node. The technology library file contains the logical function, input and output port, timing parameter (such as delay, load), physical parameter (such as area, power consumption) and the like of the library unit, as well as the design rule and parasitic parameter model related to layout and routing. The technology library file is provided by a foundry and reflects the technical characteristics and limitations of a specific process node. Logic synthesis, layout and routing and the like need to rely on the technology library file to map the RTL design to actual physical devices and interconnections.

[0010] Constraint File: A text file that specifies design intent and requirements to guide optimization and implementation in logic synthesis, placement and routing, etc. Constraint file contains timing constraint, physical constraint, power constraint, etc. Timing constraint defines clock frequency, setup time, hold time, etc. of the circuit. Physical constraint defines size, pin location, layout area, etc. of the chip. Power constraint defines power budget, power domain partition, etc. of the chip. Constraint file is written in SDC (Synopsys Design Constraint), TCL (Tool Command Language), etc. and is refined and updated as the design flow proceeds.

[0011] Gate-level Netlist: A circuit description file generated after logic synthesis, which describes gate-level structure and connection relationship of the circuit. Gate-level netlist maps abstract structures in RTL design, such as registers and combinational logic, to actual standard cells (e.g. NAND gate, NOR gate, flip-flop, etc.) and interconnections (nets) in the technology library in the form of netlist. Gate-level netlist contains instantiation, port connection, hierarchy, etc. of each standard cell, reflecting logic function and structure of the circuit. Gate-level netlist is the input of subsequent steps such as placement and routing, static timing analysis, formal verification, etc. and is also an important basis for evaluating quality of logic synthesis.

[0012] Further, it further includes: performing power analysis according to the layout and routing data; performing IR analysis according to the parasitic parameters.

[0013] Further, the RTL behavioral-level netlist, the process library file and the constraint file are received as inputs to generate the library configuration file value_lib.tcl, including: receiving the RTL behavioral-level netlist, the process library file and the constraint file as inputs; wherein the RTL behavioral-level netlist describes the logic function and structure of the chip in Verilog or VHDL language; the process library file is used to define the physical characteristics and electrical characteristics of the standard cell; the constraint file is used to define the timing constraints and physical constraints of the design; using the RTL behavioral-level netlist, the process library file and the constraint file, the logic synthesis tool is used for synthesis to generate the behavioral-level netlist file value.v; wherein the logic synthesis tool reads the RTL behavioral-level netlist, combines the process library file and the constraint file, and converts the logic description of the behavioral level to the circuit description of the gate level to realize the conversion from the behavioral level to the gate level; according to the flow configuration file value.tcl, the library configuration file value_lib.tcl is generated by the flow. The library configuration file contains the cell information, the logic function and the timing constraint information of the process library.

[0014] The logic synthesis tool (Logic Synthesis Tool) is used to convert the RTL behavioral-level netlist into the behavioral-level netlist file value.v. The logic synthesis tool receives the RTL behavioral-level netlist, the process library file and the constraint file as inputs, and converts the logic description of the behavioral level to the circuit description of the gate level through a series of optimization and mapping algorithms. Specifically, the logic synthesis tool first performs syntax checking and elaboration on the RTL design to generate internal data structures and hierarchical relationships. Then, the logic synthesis tool performs high-level synthesis to convert the abstract structures such as registers, combinational logic, state machines, etc. in the RTL into basic logic units such as AND gates, OR gates, flip-flops, etc. Next, the logic synthesis tool combines the standard cell information provided by the process library file to perform mapping, optimization and restructuring on the generated logic circuit to meet the timing requirements and area requirements defined in the constraint file. Finally, the logic synthesis tool generates the behavioral-level netlist file value.v to describe the gate-level structure and connection relationship of the circuit. Common logic synthesis tools include Synopsys Design Compiler, Cadence RTL Compiler, Mentor Precision, etc. These tools provide rich command and script interfaces, support multiple HDL languages and constraint formats, and can realize automatic synthesis and optimization from RTL to gate level.

[0015] Library File Format Conversion Tool: A tool used to generate a library configuration file value_lib.tcl from the configuration in the Flow configuration file value.tcl. The Library File Format Conversion Tool takes a behavioral netlist file value.v as input, extracts the standard cell information from it, and generates a library configuration file value_lib.tcl in a specific library file format (e.g., Synopsys Liberty format). Specifically, the Library File Format Conversion Tool first reads the behavioral netlist file value.v, parses the module definitions, instantiation statements, and port connection information. Then, the Library File Format Conversion Tool iterates through each instance of a standard cell, extracts its logical function, input / output ports, timing parameters, and other attributes. Next, the Library File Format Conversion Tool organizes the extracted standard cell information into the.lib file format according to the syntax and structure of the Liberty format, including the library header information, cell definitions, pin definitions, timing definitions, and other contents. Finally, the Library File Format Conversion Tool generates the library configuration file value_lib.tcl as input for the subsequent steps.

[0016] Common library file formats include Synopsys Liberty, Cadence LEF / DEF, Verilog, and others. Different EDA tools and design flows may use different library file formats, so it is necessary to use corresponding library file format conversion tools for conversion and adaptation. Some EDA tools provide built-in library file format conversion functions, while others require the use of third-party conversion tools, such as Synopsys Library Compiler, Cadence Abstract Generator, and others.

[0017] Specifically, the goal of isochronous optimization is to balance the delays of different paths in the circuit, so that the delays of all paths are close to the clock period, thereby reducing clock skew and improving the speed and reliability of the circuit. Isochronous optimization mainly uses two techniques: logic restructuring and buffer insertion. Logic restructuring refers to adjusting and reorganizing the logical structure of the circuit to balance path delays. Specifically, logic restructuring is achieved through the following ways: identifying critical paths: through static timing analysis (STA), identify the critical paths in the circuit with the longest delay, the delay of these paths determines the highest speed of the circuit. Optimize critical paths: optimize the logic cells on the critical path, such as splitting complex logic cells into multiple simple logic cells to reduce the delay of individual logic cells; or adjust the number of logic stages on the critical path to reduce the number of logic stages and shorten the path delay. Balance non-critical paths: moderately delay balance non-critical paths to make their delays close to critical paths, avoiding excessive optimization of non-critical paths that introduces unnecessary area and power consumption overhead.

[0018] Buffer insertion refers to inserting buffers on long-delay interconnect lines to reduce the delay of interconnect lines. Specifically, buffer insertion is achieved through the following ways: calculating the optimal buffer size and location: according to the length, load and delay requirement of the interconnect line, calculate the optimal buffer size and insertion location, so that the delay of the interconnect line is minimized. Insert buffer: insert buffer at the selected location, the buffer can be an inverter or a non-inverter, which has the characteristics of strong driving force and small delay. Adjust the size of the buffer: according to the actual delay and load, adjust the size of the inserted buffer to further optimize the delay and area. Through logic restructuring and buffer insertion, isochronous optimization can effectively balance the delays of different paths in the circuit, reduce clock skew, and improve the speed and reliability of the circuit. At the same time, isochronous optimization will also introduce additional area and power consumption overhead, which needs to be balanced between performance and cost.

[0019] Logic optimization simplifies the logic circuit through Boolean simplification, constant propagation, and dead code elimination: The purpose of logic optimization is to simplify the logical structure of the circuit, reduce the number and complexity of logic units, and thus reduce the area and power consumption of the circuit. Logic optimization mainly uses three techniques: Boolean simplification, constant propagation, and dead code elimination. Boolean simplification refers to using simpler logic expressions to represent complex logic functions, reducing the number of logic units. Specifically, Boolean simplification is achieved through the following ways: Simplification of logical expressions: Using the equivalence transformation and absorption law, distribution law, and other theorems of Boolean algebra, complex logical expressions are simplified into simpler forms such as minimum term, maximum term, etc. Karnaugh map simplification: Karnaugh map (K-Map) is used to visually represent the logic function, and by merging adjacent cells, it is simplified into a simpler logic expression. Quine-McCluskey simplification: Using the Quine-McCluskey algorithm, the concept of prime implicant is used to systematically simplify Boolean functions to obtain the simplest form.

[0020] Constant propagation refers to propagating known constant inputs in the logic circuit, simplifying the logic units determined by constant inputs. Specifically, constant propagation is achieved through the following ways: Identification of constant inputs: Through analysis of input signals, constant inputs that are always 0 or always 1 are identified. Propagation of constant inputs: According to the function of the logic unit, the constant input is propagated to the next level of logic unit until it cannot be propagated further. Simplification of logic units: For logic units determined by constant inputs, according to their logic function, they are simplified into simpler forms such as constant 0, constant 1, or single-input buffer, etc. Dead code elimination refers to deleting unused logic units in the logic circuit, reducing the area and power consumption of the circuit. Specifically, dead code elimination is achieved through the following ways: Identification of dead code: Through analysis of the topological structure and connection relationship of the circuit, unused logic units such as dangling output ports, un-driven input ports, etc. are identified. Deletion of dead code: The identified dead code is deleted from the circuit, and the corresponding connection relationship is adjusted to ensure the correctness of the circuit. Iterative optimization: Dead code elimination may generate new dead code, so iterative execution of dead code elimination is needed until there is no dead code. Through Boolean simplification, constant propagation, and dead code elimination, logic optimization can effectively simplify the logic circuit, reduce the number and complexity of logic units, and reduce the area and power consumption of the circuit. At the same time, logic optimization may also introduce new timing problems such as delay mismatch, glitch, etc., which need to be combined with timing optimization for global trade-off and optimization.

[0021] Further, according to the behavior-level netlist, make syn performs logic synthesis to generate a gate-level netlist and generate layout and routing data, including: generating an MMMC file through the make mmmc command, used to define constraint information under different working modes and process angles; generating an initialization file through the make init command, used to initialize the environmental parameters of chip design; generating a floorplan according to physical design constraints through the make fp command, used to determine the physical size and position of the chip; wherein the physical design constraints include chip area, chip IO pin position and pre-layout macro cell position; performing standard cell layout and macro cell layout based on layout constraints through the make place command; wherein the standard cell includes NAND gate, NOR gate and flip-flop; the macro cell includes memory and PLL; performing clock tree synthesis according to clock constraints through the make cts command, to generate clock tree distribution scheme and buffer insertion scheme to balance the delay of the clock tree; performing routing based on routing resources and routing constraints through the make route command to connect standard cells and macro cells; and performing parasitic parameter extraction, static timing analysis on the routed design according to the optimization target through the make postopt command.

[0022] Specifically, modern EDA (Electronic Design Automation) tools, such as Synopsys ICC, Cadence Innovus, Mentor Nitro, etc., provide rich command interfaces for performing various design tasks and processes. These command interfaces are usually provided in the form of TCL (Tool Command Language) scripts, and designers can call these commands through the command line interface of the tool or script file to realize the automation of the design process. The make mmmc command: used to generate an MMMC (Multi-Mode Multi-Corner) file, usually corresponding to the set_multi_mode_constraint or write_mmmc_script command in the EDA tool, used to define constraint information under different working modes and process angles. The make init command: used to initialize the environmental parameters of chip design, usually corresponding to the init_design or source_initialize command in the EDA tool, used to load design files, set process libraries and constraint files, etc. The make fp command: used to generate a floorplan, usually corresponding to the floorplan or create_floorplan command in the EDA tool, used to determine the physical size, IO pin position and macro cell position of the chip, etc.

[0023] Further, according to the layout and routing data, antenna checking is performed through the make ant command, design rule checking is performed through the make drc command, and layout vs. schematic checking is performed through the make lvs command, including: according to the layout and routing data, antenna checking is performed through the make ant command using an antenna checking tool; wherein the antenna checking tool calculates the antenna ratio of each signal network by analyzing the metal wiring length, metal wiring area and connected transistor gate area in the layout and routing data, and compares the antenna ratio with a threshold value to obtain a violation network whose antenna ratio exceeds the threshold value, and generates an antenna checking report; according to the layout and routing data, design rule checking is performed through the make drc command using a design rule checking tool; wherein the design rule checking tool checks whether the layout and routing meet the minimum line width, minimum spacing, layer-to-layer wiring, wiring blockage and boundary extension by comparing the layout and routing data with the process design rules, and generates a design rule checking report. According to the layout and routing data, layout vs. schematic checking is performed through the make lvs command using a Layout vs. Schematic checking tool; wherein the Layout vs. Schematic checking tool extracts the device connection netlist in the layout and routing data and compares it with the generated gate-level netlist to check whether the device types, device quantities and device connection topologies of the two are consistent, and generates a Layout vs. Schematic checking report.

[0024] Further, the antenna checking tool includes at least one of Pegasus ARC, IC Validator ARC, Calibre Antenna Checker, Totem Antenna Checker and Quartz ARC; and the design rule checking tool includes at least one of Pegasus DRC, IC Validator DRC, Calibre DRC, Totem DRC, Quartz DRC and SKIPPER DRC.

[0025] Further, according to the layout and routing data, power consumption analysis is performed, including: according to the layout and routing data, parasitic parameter extraction is performed through the make starrc_step or make starrc command based on a parasitic parameter extraction tool; wherein the parasitic parameter extraction tool calculates the parasitic resistance and parasitic capacitance values of each segment of wiring according to the geometric parameters and process parameters of the wiring.

[0026] Specifically, make starrc_step: is a command used to generate configuration files and control files for parasitic parameter extraction, preparing for subsequent parasitic parameter extraction. The command will generate input files required by the STARRC tool according to the hierarchical structure of the design, the netlist structure and the process information, such as.STARRC_STEP_MAP files,.starrc_step.tcl files, etc. These files define the settings of the extraction, boundary conditions and output formats, etc. make starrc: is a command used to perform actual parasitic parameter extraction. The command will call the STARRC tool to analyze the layout and routing data according to the configuration files and control files generated by make starrc_step, and extract the parasitic resistance and parasitic capacitance values of each segment of the routing. The STARRC tool will consider the geometric parameters of the routing (such as length, width, spacing, etc.) and the process parameters (such as the resistivity of the metal layer, the dielectric constant of the dielectric layer, etc.), calculate the distributed RC values, and generate parasitic parameter files such as.spef files,.sbpf files, etc. for subsequent timing analysis and power consumption analysis. The difference between make starrc_step and make starrc is that the former is responsible for generating the configuration and control of extraction, and the latter is responsible for performing the actual extraction.

[0027] The PrimeTime static timing analysis tool is used to perform standard static timing analysis based on parasitic parameters by the make pt_step command, multi-mode multi-angle static timing analysis by the make pt_dmsa command, and generate a timing analysis report; wherein the standard static timing analysis calculates timing indicators of the data path delay, setup time, and hold time under typical process angles and typical working modes; the multi-mode multi-angle static timing analysis statistically calculates timing margin and violation number indicators of the data path under multiple process angles and multiple working modes; specifically, the standard static timing analysis (make pt_step) is performed under typical process angles (typical corner) and typical working modes (typical mode). The typical process angle refers to selecting representative process parameter combinations, such as a typical transistor speed, a typical interconnect resistance, and the like, reflecting the performance of devices and interconnections under normal process conditions. The typical working mode refers to selecting representative working conditions, such as a typical supply voltage, a typical temperature, and the like, reflecting the behavior of the circuit under normal use environment. Under the typical process angle and the typical working mode, the static timing analysis tool (such as PrimeTime) calculates timing indicators of the data path, such as path delay, setup time, hold time, and the like, and generates a timing report to evaluate whether the timing performance of the circuit meets the design requirements.

[0028] Multi-mode multi-corner static timing analysis (make pt_dmsa): is performed under multiple corners and multiple modes. Multiple corners refer to considering the extreme cases of process parameter variations, such as fast corner, slow corner, etc., reflecting the performance fluctuations of devices and interconnections under different process conditions. Multiple modes refer to considering the extreme cases of operating condition variations, such as maximum supply voltage, minimum supply voltage, maximum temperature, minimum temperature, etc., reflecting the behavior differences of circuits under different use environments. Under multiple corners and multiple modes, the static timing analysis tool will count indicators such as timing slack and violation count of data paths. Timing slack represents the difference between actual timing and required timing of data paths, positive value indicates that timing requirements are met, negative value indicates that timing requirements are violated. Violation count represents the number of paths that violate timing requirements. Multi-mode multi-corner analysis can comprehensively evaluate the timing performance of circuits under various extreme conditions, identify critical paths sensitive to process and environmental changes, and provide guidance for subsequent timing optimization.

[0029] Static power analysis (make ptpx): is performed on the basis of static timing analysis, using PrimeTime PX (PTPX) tool, according to information in the timing analysis report, such as circuit switching activity, signal transition, capacitance load, etc., to estimate the power consumption of the circuit. PTPX tool will consider various sources of power consumption, such as switching power, internal power, leakage power, etc., to generate detailed power analysis report (power report), providing statistical information and distribution of power consumption, such as total power consumption, average power consumption, maximum power consumption, power consumption contribution of each module, etc. Power analysis report can help designers evaluate the power consumption performance of the circuit, identify high power consumption modules and paths, and guide power optimization.

[0030] Timing ECO (Engineering Change Order) optimization is based on multi-mode multi-angle static timing analysis, aiming to correct timing violations and improve the timing performance of the circuit. ECO optimization tools (such as PrimeTime ECO) automatically or interactively insert buffers, adjust drive strength, etc. in the gate-level netlist to repair timing violation paths: specific optimization strategies include: buffer insertion: insert buffers on the timing critical path to reduce interconnection delay and improve signal transmission speed. Drive strength adjustment: increase or decrease the drive strength of the cell to match the load capacity and optimize the rise and fall time of the signal. Gate type replacement: replace cells on the timing critical path with higher performance gate types, such as replacing normal cells with low threshold voltage (low-Vt) cells. Clock tree optimization: adjust the structure and parameters of the clock tree to balance the delay of the clock path and reduce clock skew.

[0031] According to the timing analysis report, through the make ptpx command, use the PrimeTime static power consumption analysis tool to perform static power consumption analysis and generate a power consumption analysis report power report; according to the timing analysis report, through the make eco command, use the ECO optimization tool to debug and optimize the multi-mode multi-angle static timing analysis results and correct timing violations; wherein the ECO optimization tool inserts buffers, adjusts drive strength, and repairs timing violation paths in the netlist automatically or interactively until the timing under multi-mode multi-angle meets the requirements, and generates the final gate-level netlist.

[0032] Further, according to the parasitic parameters, IR analysis is performed, including: according to the parasitic parameters, a view file is generated through an IR analysis tool; wherein the view file contains the power network topology structure, parasitic parameters and pin information of the chip; when the chip is in a static state, static IR analysis is performed through the make static_ir command; wherein the static IR analysis evaluates the static IR performance of the power network by calculating the direct current voltage drop and average current density distribution of the power network; when the chip is in a dynamic working state, dynamic IR analysis is performed through the make dynamic_ir command; wherein the dynamic IR analysis obtains the flip information of the chip by reading the VCD waveform file or the SAIF flip activity file, and calculates the alternating current voltage drop and transient current density distribution of the power network combined with the flip information to evaluate the dynamic IR performance of the power network; according to the results of static IR analysis and dynamic IR analysis, an IR analysis report is generated.

[0033] Specifically, R is called Voltage Drop and Electro Migration. Where I represents electric current, R represents resistance. IR analysis tools (such as Voltus, RedHawk, etc.) will generate view files as input for IR analysis according to parasitic parameter files (such as SPEF, SBPF, etc.). The view file usually contains the following information: Power network topology: describes the hierarchy, connection relationship and physical attributes of the power network in the chip, such as the size, spacing, material of the power grid, power ring, power line, etc. Parasitic parameters: including the parasitic resistance and parasitic capacitance values of each wiring in the power network, these parameters determine the voltage drop and current distribution characteristics of the power network. Pin information: including the location, type, load and other attributes of the chip's power pins, ground pins, signal pins, etc. These information affect the distribution of power supply and load.

[0034] Static IR analysis (make static_ir): Static IR analysis is performed when the chip is in a static state, that is, the circuit is in a steady state without signal flipping and dynamic current. The purpose of static IR analysis is to evaluate the DC characteristics of the power network, that is, the spatial distribution of voltage drop (IR drop) and current density. The make static_ir command is the command to start static IR analysis, which will call the IR analysis tool, read the view file, and perform the following calculations: DC voltage drop: according to Ohm's law (V = IR), calculate the voltage drop of each node in the power network, that is, the difference between the power voltage and the actual voltage. The larger the voltage drop, the greater the impedance of the power network, the worse the power supply quality. Average current density: according to Kirchhoff's current law (KCL), calculate the average current density of each wiring in the power network, that is, the ratio of current intensity to wiring cross-sectional area. The greater the current density, the heavier the load of the wiring, the higher the risk of heat and reliability.

[0035] Dynamic IR analysis (make dynamic_ir): Dynamic IR analysis is performed when the chip is in dynamic operation, that is, considering the influence of signal flipping and dynamic current. The purpose of dynamic IR analysis is to evaluate the AC characteristics of the power network, that is, the time variation of voltage drop and current density. In dynamic IR analysis, the extraction of flip information is a key step, which provides the necessary input for calculating the AC voltage drop and transient current density. Flip information reflects the dynamic behavior of each signal in the circuit, that is, the change of signal value. IR analysis tool extracts flip information by reading VCD (Value Change Dump) waveform file or SAIF (Switching Activity Interchange Format) flip activity file. The specific steps of extracting flip information are as follows: parsing file format: IR analysis tool will first identify the format of input file (such as VCD or SAIF), and call the corresponding file parser to read the file content into memory and convert it into the tool's internal data structure. Build signal mapping: IR analysis tool will build a signal mapping table according to the signal definition and design hierarchy in the file, and map the signal name in the file to the actual node and network of the circuit. Extract flip information: IR analysis tool will traverse each time point or each signal in the file to extract the corresponding flip count, flip time, flip rate and other information, and store them in the internal data structure. Calculate flip statistics: IR analysis tool will calculate the statistics and calculation of the extracted flip information to get the total flip count, average flip rate, maximum flip frequency and other indicators of each signal, which are used for subsequent dynamic IR analysis. Correlation to power network: IR analysis tool will associate the extracted flip information to the corresponding nodes and networks of the power network as the input for calculating the AC voltage drop and transient current density. By extracting flip information, IR analysis tool can obtain the dynamic behavior characteristics of the circuit and convert them into dynamic excitation of the power network, so as to realize the calculation of AC voltage drop and transient current density and evaluate the dynamic IR performance of the power network.

[0036] Static IR analysis is suitable for evaluating the DC characteristics of the power network, such as the initial layout of the power trace, the position of the power pin, the structure of the power grid, etc., and is usually performed in the early stage of design to provide guidance for subsequent optimization. Dynamic IR analysis is suitable for evaluating the AC characteristics of the power network, such as the width of the power trace, the number and position of the power decoupling capacitor, the effect of clock gating and power down technology, etc., and is usually performed in the later stage of design to verify the power integrity finally.

[0037] Compared with the prior art, the application has the following advantages:

[0038] By introducing the generation of standard cell library, the RTL design, library file and constraint file are preprocessed to generate the library configuration file value_lib.tcl of flow, which solves the compatibility problem of different designs in the use of library. This standardized library processing method can greatly reduce the repeated work of subsequent synthesis, layout and routing, etc., and improve the design efficiency.

[0039] A two-stage synthesis strategy is adopted. First, the preliminary synthesis of gate-level netlist is performed based on the library configuration file value_lib.tcl of flow, and then the isochronous optimization and logic optimization are performed on the preliminary synthesized gate-level netlist to generate the optimized gate-level netlist. This phased optimization synthesis method can further improve the timing characteristics of the design, reduce timing violations and reduce the difficulty of timing convergence under the premise of ensuring the optimal design area.

[0040] An incremental physical design method is adopted to divide the layout and routing task into floorplan, placement, cts, routing, eco and other sub-steps, and the automation execution and interface docking of each step are realized through make command. This modular and incremental physical design process can make full use of the existing layout and routing results, focus on local optimization, accelerate the layout and routing convergence and shorten the physical design cycle.

[0041] A variety of physical verification tools and inspection methods are integrated to perform comprehensive quality inspection on the layout and routing results, including antenna effect inspection, design rule inspection, layout and schematic comparison, etc. This full-chain and multi-tool physical verification platform can automatically identify layout and routing defects and feedback to the designer for correction, ensuring the manufacturability of the design from the source and avoiding the risk of tape-out due to physical defects.

[0042] Static power analysis and dynamic power analysis are introduced to comprehensively evaluate the power characteristics of the chip. In static power analysis, the average power consumption of the chip and the power distribution of the critical path are calculated by extracting parasitic parameters and combining standard static timing analysis; in dynamic power analysis, the transient power consumption and peak power consumption of the chip are calculated by reading VCD waveforms or SAIF flip file and combining parasitic parameters. The power analysis results can guide the optimization of chip power consumption, such as inserting power gating in high power consumption area, optimizing clock tree, etc., to meet the power budget.

[0043] The static IR analysis and the dynamic IR analysis are introduced to comprehensively evaluate the power integrity of the chip. In the static IR analysis, the voltage drop and the current density distribution of the chip are calculated by solving the direct current equation of the power network, and the static IR violation is found out; in the dynamic IR analysis, the transient voltage drop and the transient current density of the chip are calculated by solving the dynamic equation of the power network through reading the signal flip information, and the dynamic IR violation is found out. The IR analysis result can guide the optimization of the power supply of the chip, for example, adjusting the power planning, increasing the power line width, inserting the decoupling capacitor and the like, so as to meet the IR constraint.

[0044] Various links of the digital back-end design are organically integrated to form a design platform based on the tcl script. The designer only needs to provide the input file (such as the RTL design, the process library and the SDC constraint) according to the specification, and the full-process design can be started by one key, which greatly reduces the workload and the skill requirement of the designer. Meanwhile, the design administrator can embed the design constraint into the full process through the customized tcl script, realize the automatic checking of the design specification, and reduce the human error. BRIEF DESCRIPTION OF DRAWINGS

[0045] The present application will be further described in the form of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same numbers represent the same structures, wherein:

[0046] Figure 1 is an exemplary flowchart of a method of a full-process script design of a digital back-end according to some embodiments of the present application;

[0047] Figure 2 is an exemplary flowchart of generating layout and routing data according to some embodiments of the present application;

[0048] Figure 3 is an exemplary flowchart of performing antenna checking according to some embodiments of the present application;

[0049] Figure 4 is an exemplary flowchart of performing power consumption analysis according to some embodiments of the present application;

[0050] Figure 5 is an exemplary flowchart of performing IR analysis according to some embodiments of the present application. DETAILED DESCRIPTION

[0051] The method and system provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0052] Figure 1is an exemplary flow chart of a method of a digital backend full flow script design according to some embodiments shown in the application, the application provides a method of a digital backend full flow script design, which takes improving the efficiency of chip digital backend design as the goal, realizes the full flow optimization from RTL level design to GDSII layout through introducing standardized interface, modularized architecture and automated flow. Including: receiving RTL behavior level netlist, process library file and constraint file as input, flow library configuration file value_lib.tcl; using flow library configuration file value_lib.tcl, generating gate level netlist and corresponding synthesis report; according to the behavior level netlist, make syn for logic synthesis to generate gate level netlist, generate layout and routing data; according to the layout and routing data, through make ant command for antenna inspection, through make drc command for design rule check, through make lvs command for generating layout and schematic comparison check; according to the layout and routing data, through make out command to output GDSII layout file; according to the layout and routing data, power consumption analysis; according to the parasitic parameter, IR analysis.

[0053] Receiving RTL behavior level netlist, process library file and constraint file as input, Flow library configuration file value_lib.tcl, receiving RTL behavior level netlist, process library file and constraint file as input. Among them, RTL behavior level netlist describes the logic function and structure of chip with Verilog or VHDL language, such as module division, interface definition, state machine description, etc.; process library file is used to define the physical characteristics (such as size, pin layout) and electrical characteristics (such as delay, driving strength) of standard cell; constraint file is used to define the timing constraints (such as clock frequency, setup and hold time) and physical constraints (such as area, power consumption, pin layout) of chip design. Using RTL behavior level netlist, process library file and constraint file, through logic synthesis tool (such as Design Compiler) for logic synthesis, generate behavior level netlist file value.v. Specifically, the logic synthesis tool first reads the RTL behavior level netlist, converts the high-level hardware description language in it into register transfer level (RTL) data flow description; then, combined with the standard cell information provided by the process library file and the constraint conditions provided by the constraint file, the behavior level data flow description is mapped to the gate level netlist, realizing the automatic conversion and optimization from behavior level to gate level.

[0054] The flow library configuration file value lib.tcl is generated by the make gen function in flow using the flow configuration file value.tcl. Specifically, the library file format conversion tool first reads the behavior-level netlist file value.v, extracts the logical function (e.g., NAND gate, NOR gate) of each standard cell, the input and output port (e.g., the direction and bit width of the signal line), and the timing parameter (e.g., delay, fanout) of each standard cell; and then converts the text syntax and data structure according to the Synopsys Liberty format (.lib) definition. The Liberty format is a commonly used library file format in the industry, which can be recognized and used by mainstream EDA tools. The standard cell library file value lib.tcl contains three types of key information: cell information of the process library, which defines the physical size, pin layout, and manufacturing level of each standard cell; pin information, which defines the input and output port, truth table, and logical expression of each standard cell; and timing constraint information, which defines the delay, fanout, setup time, and hold time of each standard cell.

[0055] Using the library configuration file value lib.tcl, a gate-level netlist and a corresponding synthesis report are generated, including generating a synthesis constraint file sdc file according to the flow library configuration file value lib.tcl in combination with timing constraints and physical constraints. The timing constraints define the clock frequency (e.g., 100 MHz), setup time (e.g., 0.2 ns), and hold time (e.g., 0.1 ns) of the chip, which are used to guide logic synthesis and optimization; the physical constraints define the area (e.g., 10 mm 2 ), power consumption (e.g., 500 mW), and pin position (e.g., IOring layout) of the chip, which are used to control the physical characteristics of the synthesis result. The synthesis constraint file stores the constraint information in the Synopsys Design Constraints (SDC) format.

[0056] Using a synthesis tool (e.g., Design Compiler), a logic synthesis is performed on the behavior-level netlist using the make syn command according to the synthesis constraint file sdc file, and an area-optimized gate-level netlist and a synthesis report are generated. Specifically, the synthesis tool first reads the behavior-level netlist file value.v, combines the gate-level components (e.g., NAND gate, flip-flop) therein with the constraint conditions (e.g., timing, area) provided by the synthesis constraint file, maps the gate-level netlist to the standard cells defined in the standard cell process library through a logic mapping algorithm, and performs optimization such as equivalent replacement and redundant logic deletion to generate a gate-level netlist with the smallest area. The synthesis report statistics the area (cell area), power consumption (power), and critical path timing (critical path timing) of the synthesized circuit.

[0057] The gate-level netlist is subjected to timing optimization and logic optimization to generate a further optimized gate-level netlist. In the timing optimization, the combinational logic on the critical path is adjusted through logic restructuring and buffer insertion to balance the path delay, reduce clock skew, and thus improve the timing performance of the circuit. In the logic optimization, the combinational logic is simplified through boolean minimization, constant propagation, and dead code elimination to remove redundant logic gates, thereby reducing the area and power consumption of the circuit.

[0058] Figure 2is an exemplary flowchart of generating layout routing data according to some embodiments of the present application, layout routing is performed according to a gate-level netlist Make out, layout routing data is generated, including: generating a Multi-Mode Multi-Corner (MMMC) file through a make_mmmc command, used to define constraint information under different working modes (such as normal mode, test mode) and process angles (such as typical, worst). The MMMC file contains library file links, process parameter settings and constraint condition settings under different conditions, providing a complete constraint model for subsequent layout routing. An initialization file is generated through a make_init command, used to initialize the environmental parameters of chip design, such as design library path, technology file path, layout hierarchy definition, etc. The initialization file ensures that the layout routing tool (such as ICC II) can correctly read the design data and technology file. A floorplan is generated according to physical design constraints through a make_fp command, used to determine the physical size (die size) and module location (module location) of the chip. Among them, the physical design constraints include the chip area (such as 10mm x 10mm), the chip IO pin position (such as arranged around), and the pre-layout macro unit position (such as SRAM placed in the center). The floorplan can be intuitively adjusted through an interactive graphical interface (GUI). Based on layout constraints, standard cell placement and macro placement are performed through a make_place command. Among them, the standard cell includes basic logic gates such as NAND gate, NOR gate, flip-flop (FF), etc.; the macro cell includes complex functional modules such as memory (SRAM), phase-locked loop (PLL), etc. The layout constraints define the spacing, alignment, orientation and other rules between cells. The layout engine solves the optimization problem based on the constraints to obtain a planar layout scheme. According to the clock constraints, clock tree synthesis (Clock Tree Synthesis) is performed through a make_cts command to generate a clock tree topology and buffer insertion scheme. Clock tree synthesis constructs a balanced clock tree through a recursive partitioning algorithm, and inserts buffers at the nodes and leaves of the clock tree to minimize clock skew. Based on routing resources and routing constraints, routing is performed through a make_route command to connect standard cells and macro cells. The routing resources define the physical characteristics of the routing layer (metallayer), such as line width, spacing, resistance and capacitance, etc.; the routing constraints define the length matching, antenna rule, current density, etc.The routing engine gets the routing topology and wire width assignment by solving a constraint-based maze algorithm. Through the make_postopt command, parasitic extraction and static timing analysis are performed on the routed design according to the optimization target. Parasitic extraction takes into account the resistance-capacitance effect of the routing and back annotates it into the gate-level netlist; static timing analysis takes the MMMC file as input and calculates the timing slack of the circuit under different process angles, identifies the violating path, and guides the optimization of placement and routing.

[0059] Figure 3 is an exemplary flowchart of performing antenna checking according to some embodiments of the present application. Through the make_ant command, the antenna checking tool (Antenna Checker) is used to perform antenna effect checking. The input data of the antenna effect checking is the post-layout and post-routing design data, including layout files (such as GDS, OASIS, etc.) and parasitic parameter files (such as SPEF, DSPF, etc.). The layout file contains the physical structure information of the chip, such as the geometric shape, position, and hierarchical relationship of the metal routing, etc.; the parasitic parameter file contains the electrical characteristic information of the metal routing, such as resistance, capacitance, and inductance, etc. The designer needs to generate layout and routing data that meets the process rules and design constraints through the layout and routing flow of the EDA tool.

[0060] The antenna checking tool is usually provided in the form of a plug-in of the EDA tool or a standalone software, and the designer needs to configure the parameters and options of the antenna checking tool according to the specific process requirements and design rules. The main configuration items include: process rules: define the geometric parameters of different metal layers, such as minimum width, minimum spacing, maximum length, etc., and the antenna ratio threshold under different scenarios. Design rules: define the layout constraints and connection rules of the functional units, power network, clock network, etc. of the chip. Checking rules: define the specific algorithm and standard of the antenna effect checking, such as the calculation formula of the antenna ratio, the judgment condition of the violating network, etc.

[0061] The designer starts the antenna checking tool by executing the make_ant command in the command line interface or script file of the EDA tool. The antenna checking tool automatically reads the layout file and the parasitic parameter file, and calculates the antenna ratio of each signal network according to the configured process rules, design rules and checking rules. The specific calculation process includes: extracting metal wiring: according to the geometric information in the layout file, extracting the metal wiring of each signal network, and calculating its length and area. Extracting transistors: according to the device information in the layout file, extracting the transistors connected by each signal network, and calculating the gate area. Calculate the antenna ratio: according to the formula of the antenna ratio, calculate the antenna ratio of each signal network, and compare it with the threshold value specified by the process. Common antenna ratio calculation formulas include: metal 1 antenna ratio = metal 1 area / gate area; metal 2 antenna ratio = (metal 1 area + metal 2 area) / gate area; metal 3 antenna ratio = (metal 1 area + metal 2 area + metal 3 area) / gate area;... Generate violation report: for the signal network whose antenna ratio exceeds the threshold value, the antenna checking tool generates a violation report, which identifies the name, location, antenna ratio and severity of the violation network and other information.

[0062] The designer understands the antenna effect risk in the design by checking the antenna checking report. The antenna checking report is usually presented in the form of text, table or graph, and contains the following contents: summary information of violation network: statistics of the number, type and distribution of violation networks in the design. Detailed information of violation network: list the name, location, connected device, antenna ratio and severity of each violation network. Visualization of violation network: identify the violation network in the layout editor with different colors or icons, which is convenient for the designer to locate and analyze. For the violation network found by the antenna checking, the designer needs to optimize the layout and wiring to eliminate or reduce the antenna effect. Common optimization methods include: inserting protection diode: insert a protection diode on the violation network to provide a discharge path to discharge the accumulated charge to the ground to avoid damaging the transistor gate oxide layer. Adjust the metal wiring: by changing the width, length and level of the metal wiring, reduce the area of the metal wiring, and thus reduce the antenna ratio. Adjust the device layout: by changing the position, direction and size of the transistor, increase the gate area, and thus reduce the antenna ratio. Split long signal network: for long signal networks that span multiple metal layers, insert a buffer or bridge resistor in the middle layer to split the long signal network into multiple short signal networks, and reduce the antenna ratio.

[0063] Design Rule Checking (DRC) is a process of verifying the design against the design rules. The input data for DRC is the layout data after placement and routing, usually including layout files such as GDS, OASIS, etc. The layout file contains the physical structure information of the chip, such as the geometry, position, and hierarchy of different routing layers. Designers need to generate layout data reflecting the final physical design through the placement and routing flow of EDA tools. Process design rules: define the geometric parameters and physical constraints of different routing layers, such as minimum line width, minimum spacing, interlayer routing rules, routing blocking rules, and boundary extension rules, etc. Process design rules are provided in specific file formats (such as Tech File, Calibre DRC Rule File, etc.) and need to be obtained from the process manufacturer or PDK (Process Design Kit). Check rules: define the specific algorithm and standard of design rule checking, such as the priority of rules, the area and hierarchy of checking, the marking method of violations, etc. Check rules can be customized and optimized according to the characteristics and requirements of the design. Check options: define the execution mode and output format of design rule checking, such as parallel processing, memory usage, output file format, etc.

[0064] Data preprocessing: perform preprocessing operations such as format conversion, data compression, and hierarchy extraction on layout data to improve checking efficiency and accuracy. Rule matching: use rule-based pattern matching algorithms to compare layout data with process design rules, quickly scan the entire chip layout, and find graphics and positions that violate design rules. Common pattern matching algorithms include scan line algorithm, region decomposition algorithm, and vectorization algorithm, etc. Error marking: for graphics that violate design rules, the design rule checking tool will generate error markers to identify the type, location, and severity of the violation. Error markers are usually presented in the form of different colors or icons in the layout editor, making it easy for designers to locate and analyze. Result output: the design rule checking tool will generate a design rule checking report (DRC Report) to summarize the results and statistical information of the checking. The report is usually output in the form of text, table, or graph, including the number, type, distribution, and detailed information of violations, etc.

[0065] By checking the design rule check report and violation markers, understand the design rule problems in the design. The design rule check report usually contains the following contents: violation summary information: statistics of the number, type and distribution of violations in the design, such as the total number of DRC violations, the number of violations of different rule types, etc. Detailed information of violations: list the location, level, rule type, severity and related graphics of each violation. Visualization of violations: identify violations in different colors or icons in the layout editor to facilitate designers to locate and analyze. Common repair methods include: manual repair: designers manually adjust the geometry in the layout according to the violation markers and design rule report, such as moving, resizing, deleting or adding graphics, etc. Automatic repair: use the automatic repair function provided by EDA tools, such as DRC Auto-Fix, layout optimization, etc., to automatically adjust the layout to eliminate violations. Automatic repair is usually based on pre-defined repair rules and heuristic algorithms, which can quickly repair simple violations and reduce the workload of manual repair. Design rule waiver(DRC Waiver): for some special design situations, such as analog circuits, custom circuits, etc., designers can apply for design rule waiver to allow violation of some design rules in specific areas or conditions. Design rule waiver needs to be audited and approved, and special processing is needed in design rule check.

[0066] Through the make_lvs command, use the Layout vs. Schematic(LVS) check tool to check the consistency of the layout and schematic. The input data of LVS check includes layout routing data and gate-level netlist. Layout routing data is usually provided in GDS, OASIS, etc. Layout file, contains the physical structure information of the chip, such as the layout of the device, the geometry and level relationship of the routing, etc. Gate-level netlist is usually provided in SPICE or Verilog format, describes the logical function and device connection relationship of the circuit, which is the schematic representation of circuit design. Gate-level netlist can be generated by logic synthesis or manually written.

[0067] The LVS checking tool is usually provided in the form of a plug-in of an EDA tool or a standalone software. The designer needs to configure the parameters and options of the LVS checking tool according to the specific process requirements and design constraints. The main configuration items include: process file: defining the physical parameters and extraction rules of different device types, such as the geometric parameters and parasitic parameter extraction methods of MOS tubes, resistors, capacitors, etc. The process file is usually provided in the format of Tech File, Calibre LVS Rule File, etc., and needs to be obtained from the process manufacturer or PDK (Process Design Kit). Mapping file: defining the correspondence between layout devices and gate-level devices, such as the mapping relationship between the geometric parameters of MOS tubes in the layout and the electrical parameters of MOS tubes in the gate-level netlist. The mapping file is usually provided in the format of mapping file or layer map file, etc., and needs to be configured according to the device types and naming conventions of the design. Comparison options: defining the comparison method and tolerance of LVS checking, such as the comparison tolerance of device parameters, the normalization method of netlist, the processing method of black box, etc.

[0068] The LVS checking tool is started by executing the make_lvs command in the command line interface or script file of the EDA tool. The LVS checking tool automatically reads the layout file, gate-level netlist, and configuration file, and performs consistency checking according to the configured process file, mapping file, and comparison options. The specific checking process includes: layout extraction: according to the layout file and process file, the device, network, and connection information in the layout are extracted, and a layout extraction netlist is generated. The layout extraction process identifies the device geometry in the layout and calculates the electrical parameters of the device, such as the W / L ratio of the MOS tube, the resistance value of the resistor, etc., according to the extraction rules in the process file. Netlist preprocessing: the layout extraction netlist and the gate-level netlist are preprocessed, such as removing redundant devices and networks, merging equivalent devices and networks, renaming matching devices and networks, etc., to facilitate subsequent comparison. Topology comparison: using normalization and isomorphic matching algorithms, the topology structures of the layout extraction netlist and the gate-level netlist are compared to check whether their device types, device quantities, and connection relationships match. The topology comparison process considers the direction, symmetry, and equivalence of the devices, as well as the hierarchical structure and modular organization of the netlist. Parameter comparison: for the topologically matched devices, further compare whether their electrical parameters are within the specified tolerance range, i.e., check whether the device parameters of the layout extraction match the device parameters of the gate-level netlist. The parameter comparison process considers the influence of factors such as process corner, environmental conditions, and test conditions. Result output: the LVS checking tool generates an LVS report, which summarizes the comparison results and statistical information. The report is usually output in the form of text, table, or graph, including the summary of the comparison results, the list of mismatched devices and networks, and the visualization of the layout and schematic.

[0069] Analyzing LVS checking results: comparison result summary: statistics of the number of matched and mismatched devices, the number of networks, and the number of connections in the layout and schematic, giving an overall evaluation of consistency checking. Mismatched device and network list: list the inconsistent devices and networks found in topology comparison or parameter comparison, and give the specific reasons for mismatch, such as different device types, device parameters beyond tolerance, missing connections, etc. Visualization of layout and schematic: in the layout editor and schematic editor, mismatched devices and networks are identified with different colors or icons, making it easy for designers to locate problems.

[0070] Repair LVS mismatch: For the mismatch found by LVS check, the designer needs to analyze the reason and repair the layout or schematic to ensure the consistency of the two. Common mismatch reasons and repair methods include: layout error: the device placement and wiring connection in the layout are inconsistent with the schematic, the layout file needs to be modified, such as adjusting the device position, modifying the wiring direction, etc. Schematic error: the device and network in the schematic are inconsistent with the design intention, the gate-level netlist needs to be modified, such as adding missing devices, deleting redundant connections, etc. Naming inconsistency: the device and network naming in the layout and schematic are inconsistent, the naming rules or mapping file needs to be modified to unify the naming conventions of the two. Parameter matching: the device parameters extracted by the layout are inconsistent with the device parameters in the schematic, the geometric parameters of the device or the extraction rules need to be adjusted, such as adjusting the W / L ratio of MOS tube, modifying the layout of resistor, etc.

[0071] According to the layout and routing data, the GDSII layout file is output by the make_out command to complete the digital back-end design, including the following steps: after the layout and routing data are ensured to meet the design rules, antenna rules and LVS consistency requirements through physical verification, the layout export tool (Layout Exporter) is called by the make_out command to convert the layout and routing data into a GDSII format layout file. The layout export tool first reads the layout and routing database (such as DEF / LEF format), extracts the geometry, connectivity and hierarchy information therein. The geometry information defines the geometric elements such as polygons, paths, texts, etc. in the layout; the connectivity information defines the topological elements such as nets, pins, vias, etc. in the layout; the hierarchy information defines the logical elements such as cells, arrays, blocks, etc. in the layout. Then, the layout export tool encodes the extracted geometry, connectivity and hierarchy information into binary records according to the GDSII stream format. The GDSII stream format consists of Header Record, Library Record, Structure Record, Element Record and Tail Record, etc. and adopts the encoding mode of Tag-Length-Value. Each record starts with a specific tag, followed by the data length and the actual data value. The layout export tool maps the content of the layout and routing database to the corresponding GDSII records and arranges the records in the specified order. During the encoding process, the layout export tool converts the abstract information such as layer name, wiring rule, etc. in the layout and routing database into specific information such as layer number, data type, etc. in the GDSII file according to the mapping table provided by the process design kit. Different processes may use different GDSII layer numbers and naming conventions. The layout export tool also supports custom GDSII encoding options such as resolution, unit, compression, etc. to meet the requirements of different customers. Finally, the layout export tool writes the encoded GDSII records into a file to generate a complete GDSII layout file. The GDSII layout file is stored in ASCII or binary format and the extension is usually.gds or.gdsii.GDSII layout file is a common layout exchange format in the industry, which can be directly transmitted to chip manufacturers (such as TSMC, GlobalFoundries) for producing photomask and wafer. GDSII layout file can also be imported into other EDA tools for subsequent layout verification and manufacturability analysis. The make_out command converts the layout and routing database into a GDSII layout file through a layout output tool, realizing the final deliverable of digital back-end design. GDSII layout file is an important interface between digital back-end design and chip manufacturing, and its quality directly affects the yield and reliability of the chip.

[0072] In addition, the method also integrates power consumption analysis and IR analysis functions as an important supplement to digital back-end design:

[0073] Figure 4 is an exemplary flowchart for power consumption analysis according to some embodiments of the present application. According to the layout and routing data, the parasitic parameter extraction tool (Parasitic Extraction Tool) such as Star-RCXT, Calibre xRC, etc. is called through make_starrc_step or make_starrc command to extract the parasitic parameters of the wiring, including parasitic resistance and parasitic capacitance, according to the layout and routing data. The parasitic parameter extraction tool calculates the parasitic resistance and parasitic capacitance value of each wiring according to the geometric parameters (such as line width, line length) and process parameters (such as metal resistivity, dielectric constant) of the wiring, and generates a parasitic parameter model file (such as SPEF, DSPF format). Parasitic parameters reflect the electrical characteristics of the wiring and are an important input for timing analysis and power consumption analysis.

[0074] Using PrimeTime static timing analysis tool, based on gate-level netlist and parasitic parameters, standard static timing analysis (Standard STA) is performed by make_pt_step command, multi-mode multi-corner static timing analysis (Multi-Mode Multi-Corner STA) is performed by make_pt_dmsa command, and timing report is generated. Standard static timing analysis calculates timing indexes such as delay, setup time, hold time of data path under typical corner and typical mode, which are used to evaluate the performance of circuit. Multi-mode multi-corner static timing analysis calculates timing indexes such as timing slack and violation count of data path under multiple corners (e.g. worst, best) and multiple modes (e.g. high voltage, low voltage), which are used to evaluate the robustness of circuit.

[0075] According to the timing report, static power analysis is performed by make_ptpx command using PrimeTime static power analysis tool, power report is generated. Static power analysis calculates power indexes such as dynamic power, static power, peak power of circuit based on gate-level netlist, parasitic parameters and switching activity, and analyzes the time and space distribution of power. Power report provides guidance for low power design of chip.

[0076] According to the timing analysis report, through the make_eco command, the multi-mode multi-angle static timing analysis results are debugged and optimized using the ECO optimization tool (Engineering Change Order Tool), and timing violations are corrected. The ECO optimization tool automatically or interactively inserts buffers, adjusts driving strength, adjusts load capacitance, etc. in the gate-level netlist to fix timing violation paths until the timing indicators under multi-mode multi-angle meet the design constraints, and generates the final gate-level netlist. The ECO optimization process usually needs multiple iterations until the timing converges. The power analysis is based on the layout and routing data, and through the steps of parasitic parameter extraction, static timing analysis, static power analysis, etc. to evaluate the performance, power consumption and robustness of the circuit, and to achieve timing convergence through ECO optimization. Power analysis runs through the whole process of digital back-end design, and is closely integrated with layout and routing, physical verification, forming a closed-loop feedback and continuous optimization. Through the make command, the corresponding EDA tool can be automatically called to execute each analysis step and generate a standard analysis report. Power analysis is crucial to the quality and cost of the chip, and designers need to weigh multiple targets such as area, timing, power, etc. and constantly adjust and optimize the design to achieve the optimal design scheme.

[0077] Figure 5 is an exemplary flowchart of performing IR analysis according to some embodiments of the present application, and the IR analysis (IR Analysis) is performed according to the parasitic parameters, including the following steps: generating a view file through an IR analysis tool according to the parasitic parameters, first, the IR analysis tool reads the parasitic parameter file, such as SPEF (Standard Parasitic Exchange Format) or DSPF (Detailed Standard Parasitic Format). The parasitic parameter file is generated by a parasitic parameter extraction tool and contains the parasitic parameter information of the resistance, capacitance and inductance of the chip layout. The IR analysis tool parses the parasitic parameter file and extracts the resistance and inductance values for subsequent IR analysis.

[0078] Then, the IR analysis tool reads the layout routing data of the chip, such as DEF (Design Exchange Format) or LEF / DEF (Library Exchange Format / Design Exchange Format) format. The layout routing data describes the physical design of the chip, including the routing topology of the power network, the pin location, and other geometric information. The IR analysis tool analyzes the layout routing data, identifies the structure of the power network, such as the power ring, power plane, power strap, and extracts the pin information, such as the coordinate, layer, clearance, and other attributes. Then, the IR analysis tool matches and associates the parasitic parameters with the layout routing data, generating the power network model of the chip. The IR analysis tool maps the resistance and inductance values in the parasitic parameter file to the corresponding line segments in the layout routing data through a geometric matching algorithm, obtaining the power network topology structure with parasitic parameters. The power network model is represented in the form of a graph, where the node represents the pin, the edge represents the routing, and the weight represents the parasitic parameter.

[0079] Finally, the IR analysis tool converts the power network model into a view file in a specific format, such as Milkyway, OpenAccess, etc. The view file is stored in ASCII or binary format, and follows the standard interface specification of EDA tools. The view file contains complete information of the chip power network, such as topology structure, parasitic parameters, pin attributes, etc., which can be read and processed by other EDA tools, such as layout routing tools, timing analysis tools, etc. The generation of the view file needs to be consistent with the layout routing, ensuring that the power network model matches the actual routing.

[0080] The IR analysis tool usually provides flexible configuration options and script interfaces, allowing users to customize the generation parameters of the view file, such as precision, unit, filter, etc., to meet different design requirements and tool requirements. Users can modify the configuration file or write scripts to control the generation process of the view file, such as selecting specific layers, setting threshold conditions, merging repeated elements, etc., to optimize the quality and efficiency of the view file.

[0081] When the chip is in a static state, the steps of static IR analysis are performed by the make_static_ir command: First, by the make_static_ir command, the IR analysis tool is called to load the previously generated view file. The view file contains the topology of the chip power network, parasitic parameters, and pin information, and is the basic data for static IR analysis. The IR analysis tool reads the view file and constructs the matrix equation of the power network, where the rows and columns of the matrix correspond to the nodes of the power network, and the elements of the matrix correspond to the resistance values between the nodes. Then, the IR analysis tool sets the boundary conditions and load conditions of the static IR analysis. The boundary conditions specify the voltage values of the power supply and ground nodes of the power network, such as VDD = 1.0V, VSS = 0V, etc. The load conditions specify the current consumption distribution of the power network, i.e. the static current value of each pin. The static current value can be obtained by design specification, power estimation, etc., reflecting the static power consumption characteristics of the chip.

[0082] Next, the IR analysis tool solves the DC voltage drop and average current density distribution of the power network. Based on the modified nodal analysis (MNA) algorithm, the IR analysis tool calculates the voltage and current values of each node in the power network. The DC voltage drop refers to the voltage difference between the power supply node and the load node, reflecting the IR drop of the power network. The average current density refers to the average current intensity per unit area, reflecting the current distribution of the power network. The IR analysis tool solves the matrix equation by iteration to obtain the converged voltage and current values, and saves the results in memory or file. Then, the IR analysis tool post-processes and analyzes the DC voltage drop and average current density. The IR analysis tool extracts key IR performance indicators such as maximum IR drop, minimum voltage level, maximum current density, etc., and compares them with design constraints to identify IR violations that exceed the threshold. The IR analysis tool also generates intuitive visual results such as voltage drop heatmaps, current density vector maps, etc., to help designers intuitively understand the IR distribution.

[0083] Finally, the IR analysis tool generates a static IR analysis report, which summarizes the IR performance metrics and violation information, and provides optimization suggestions and repair guidance. The static IR analysis report is presented in the form of tables, charts, and other forms, which facilitates designers to quickly locate and solve IR problems. Common optimization methods include increasing the metal width of the power network, increasing the power via, adjusting the pin location, etc., to reduce resistance and balance current density. Designers can iterate and optimize the power network according to the static IR analysis report until the IR performance requirements are met.

[0084] When the chip is in a dynamic working state, the steps of dynamic IR analysis through the make_dynamic_ir command are as follows: First, through the make_dynamic_ir command, the IR analysis tool is called to load the previously generated view file and flip activity file. The view file provides static information of the power network, while the flip activity file provides dynamic flip information of the pins. The flip activity file can be in VCD (Value Change Dump) format or SAIF (Switching Activity Interchange Format), which records the number of flips and flip times of each pin at different time points. The IR analysis tool reads the view file and flip activity file, extracts the topology of the power network, parasitic parameters, and flip activity data.

[0085] Then, the IR analysis tool performs preprocessing and mapping of the flip activity. The IR analysis tool parses and filters the flip activity file to extract the pin flip information related to the power network. The IR analysis tool maps the flip activity data to the corresponding pins of the power network to obtain the dynamic current waveform of each pin. The dynamic current waveform reflects the instantaneous current consumption of the pin at different time points, taking into account the number of flips and flip times. The IR analysis tool also performs time alignment and interpolation processing to ensure that the dynamic current waveform matches the time step of the power network.

[0086] Next, the IR analysis tool sets up the boundary conditions and simulation parameters for dynamic IR analysis. Similar to static IR analysis, dynamic IR analysis also requires specifying the voltage values of the power and ground nodes of the power network. In addition, dynamic IR analysis also needs to set up parameters such as the time range, time step, convergence criteria, etc. to control the accuracy and efficiency of the simulation. The IR analysis tool also supports multi-threading and distributed simulation to accelerate the dynamic IR analysis of large-scale power networks.

[0087] Then, the IR analysis tool performs dynamic IR simulation to calculate the AC voltage drop and transient current density distribution of the power network. Based on the matrix equation and dynamic current waveform of the power network, the IR analysis tool uses transient simulation algorithms such as implicit Euler method, trapezoidal method, etc. to solve the node voltage and branch current of the power network at different time points. The AC voltage drop refers to the dynamic voltage difference between the power node and the load node, reflecting the transient IR drop of the power network. The transient current density refers to the dynamic current intensity per unit area, reflecting the dynamic current distribution of the power network. The IR analysis tool solves the matrix equation by iteration to obtain the converged voltage waveform and current waveform, and saves the results in memory or file.

[0088] Next, the IR analysis tool post-processes and analyzes the dynamic IR simulation results. The IR analysis tool extracts key dynamic IR performance indicators such as peak IR drop, minimum voltage amplitude, maximum transient current density, average dynamic power, etc. and compares them with design constraints to identify dynamic IR violations that exceed thresholds. The IR analysis tool also generates visual results of dynamic IR such as voltage waveform plot, current density animation, etc. to help designers intuitively understand the dynamic IR behavior.

[0089] Finally, the IR analysis tool generates a dynamic IR analysis report, which summarizes dynamic IR performance metrics, violation information, and optimization suggestions. The dynamic IR analysis report is presented in various forms such as tables, waveforms, animations, etc., making it easy for designers to comprehensively evaluate the dynamic IR characteristics of the power network. Common optimization methods include adjusting the topology of the power network, adding decoupling capacitors, balancing the activity distribution, etc., to suppress transient noise and reduce dynamic IR voltage drop. Designers can iterate and optimize the dynamic behavior of the power network and chip based on the dynamic IR analysis report until the dynamic IR performance requirements are met.

[0090] Based on the results of static IR analysis and dynamic IR analysis, the IR analysis tool generates an IR analysis report (IR Analysis Report). The IR analysis report presents the IR performance metrics of the power network in the form of text, charts, etc., such as maximum IR voltage drop, maximum current density, minimum voltage amplitude, etc., and identifies the location and severity of IR violations. The IR analysis report also provides intuitive visualizations such as voltage drop heatmaps, current density vector maps, etc., to help designers quickly locate and fix IR problems.

[0091] IR analysis is based on parasitic parameters and flip information, and through static IR analysis and dynamic IR analysis, it evaluates the IR performance of the chip power network, including key indicators such as DC voltage drop, AC voltage drop, current density distribution, etc., and generates an IR analysis report. IR analysis is closely related to power analysis, and together they ensure the low power consumption and reliability of the chip. Through the make command, the IR analysis tool can be automatically called to execute the IR analysis process and generate standardized analysis results. IR analysis is crucial to the design and optimization of the power network, and multiple factors such as chip functionality, layout, process, etc. need to be considered to balance IR performance and cost, ultimately achieving stable and reliable power supply. IR analysis runs throughout the entire digital back-end design process and is closely integrated with layout, routing, power analysis, etc., forming a closed-loop feedback and continuous optimization.

Claims

1. A method for digital backend full flow script design, characterized in that, Comprise: Receive RTL behavioral level netlist, library file and constraint file as input, generate library configuration file value_lib.tcl; Using library configuration file value_lib.tcl, generate gate level netlist through make syn to perform logic synthesis and generate corresponding synthesis report; According to the behavioral level netlist, make syn to perform logic synthesis to generate gate level netlist, generate layout and routing data; According to the layout and routing data, through make ant command to perform antenna inspection, through make drc command to perform design rule check, through make lvs command to perform layout and schematic comparison check; According to the layout and routing data, through make out command to output GDSII layout file; According to the layout and routing data, perform power consumption analysis; According to the parasitic parameters, perform IR analysis.

2. The method of claim 1, wherein the digital back-end full-process script design method comprises: Generating library configuration file value_lib.tcl, comprising: Receiving RTL behavioral level netlist, library file and constraint file as input; wherein the RTL behavioral level netlist describes the logic function and structure of the chip using Verilog or VHDL language; the library file is used to define the physical characteristics and electrical characteristics of the standard cell; the constraint file is used to define the timing constraints and physical constraints of the design; Using RTL behavioral level netlist, library file and constraint file, through logic synthesis tool to perform synthesis, generate behavioral level netlist file value.v; wherein the logic synthesis tool converts the behavioral level logic description into gate level circuit description by reading the RTL behavioral level netlist, combining the library file and the constraint file, to realize the conversion from behavioral level to gate level; Using flow configuration file value.tcl, through library file format conversion tool, generate library configuration file value_lib.tcl; wherein the library file format conversion tool generates flow library configuration file value_lib.tcl by reading flow configuration file value.tcl according to format segmentation view to generate library configuration file value_lib.tcl; standard cell library file value_lib.tcl contains cell information, logic function information and timing constraint information of the process library.

3. The method of claim 2, wherein the digital back-end full-process script design method comprises: Generating gate level netlist Make syn and corresponding synthesis report, comprising: According to the flow library configuration file value_lib.tcl, combining timing constraints and physical constraints, generate synthesis constraint file make syn; wherein the timing constraints define the clock frequency, setup time and hold time; the physical constraints define the area, power consumption and pin position of the chip; Using the synthesis tool, according to the synthesis constraint file, the generated behavior-level netlist file value.v is logically synthesized to generate a gate-level netlist and a synthesis report syn report; wherein, the synthesis tool reads the behavior-level netlist file value.v and the synthesis constraint file make syn to perform logical synthesis to map the behavior-level netlist into an area-optimal gate-level netlist according to a standard cell library; the synthesis report syn report includes area, power consumption and timing; The gate-level netlist is subjected to isochronous optimization and logical optimization to generate a gate-level netlist; wherein, the isochronous optimization balances path delay and reduces clock skew through logical restructuring and buffer insertion; the logical optimization simplifies the logic circuit through Boolean simplification, constant propagation and dead code elimination.

4. The method of claim 3, wherein: layout and routing data is generated, including: an MMMC file is generated by a make mmmc command, used to define constraint information under different working modes and process angles; an initialization file is generated by a make init command, used to initialize environment parameters of the chip design; a floorplan is generated by a make fp command according to physical design constraints, used to determine the physical size and position of the chip; wherein, the physical design constraints include chip area, chip IO pin position and pre-layout macro cell position; standard cell layout and macro cell layout are performed based on layout constraints by a make place command; wherein, the standard cells include NAND gates, NOR gates and flip-flops; the macro cells include memories and PLLs; a clock tree synthesis is performed according to clock constraints by a make cts command to generate a clock tree distribution scheme and a buffer insertion scheme to balance the delay of the clock tree; routing is performed based on routing resources and routing constraints by a make route command to connect the standard cells and the macro cells; parasitic parameter extraction and static timing analysis are performed on the routed design according to optimization targets by a make postopt command.

5. The method of claim 4, wherein: antenna checking is performed by a make ant command, design rule checking is performed by a make drc command, and generated layout versus schematic checking is performed by a make lvs command according to the layout and routing data, including: antenna effect checking is performed by an antenna checking tool using the make ant command according to the layout and routing data; wherein, the antenna checking tool calculates the antenna ratio of each signal network by analyzing the metal routing length, metal routing area and connected transistor gate area in the layout and routing data, compares the antenna ratio with a threshold value, obtains the violation network whose antenna ratio exceeds the threshold value, and generates an antenna checking report.

6. The method of claim 5, wherein: According to the layout and routing data, a design rule check is performed by a make drc command using a design rule check tool; wherein the design rule check tool checks whether the layout and routing meet minimum line width, minimum spacing, layer-to-layer routing, routing blockage and boundary extension by comparing the layout and routing data with process design rules, and generates a design rule check report.

7. The method of claim 6, wherein: According to the layout and routing data, a layout vs. schematic check is performed by a make lvs command using a Layout vs. Schematic check tool; wherein the Layout vs. Schematic check tool checks whether the device types, device quantities and device connection topologies of the layout and routing data and the generated gate-level netlist are consistent by comparing the device connection netlist in the layout and routing data with the generated gate-level netlist, and generates a Layout vs. Schematic check report.

8. The method of any one of claims 5 to 7, wherein: the antenna check tool comprises at least one of Pegasus ARC, IC Validator ARC, Calibre Antenna Checker, Totem Antenna Checker and Quartz ARC; the design rule check tool comprises at least one of Pegasus DRC, IC Validator DRC, Calibre DRC, Totem DRC, Quartz DRC and SKIPPER DRC.

9. The method of claim 8, wherein: According to the layout and routing data, power consumption analysis is performed, including: According to the layout and routing data, parasitic parameters of the routing including parasitic resistance and parasitic capacitance are extracted by a make starrc_step or make starrc command based on a parasitic parameter extraction tool; wherein the parasitic parameter extraction tool calculates the parasitic resistance and parasitic capacitance values of each segment of the routing according to the geometric parameters and process parameters of the routing; a PrimeTime static timing analysis tool is used to perform standard static timing analysis and multi-mode multi-angle static timing analysis based on the parasitic parameters by make pt_step and make pt_dmsa commands, and generate a timing analysis report; wherein the standard static timing analysis calculates timing indicators of delay, setup time and hold time of the data path under typical process angles and typical working modes; the multi-mode multi-angle static timing analysis calculates timing indicators of timing margin and violation number of the data path under multiple process angles and multiple working modes; According to the timing analysis report, static power consumption analysis is performed by a make ptpx command using a PrimeTime static power consumption analysis tool, and a power consumption analysis report power report is generated. According to the timing analysis report, through the make eco command, the multi-mode multi-angle static timing analysis result is debugged and optimized by using the ECO optimization tool, and the timing violation is corrected; wherein, the ECO optimization tool inserts a buffer in the netlist, adjusts the driving strength, and repairs the timing violation path in an automatic or interactive manner until the timing under the multi-mode multi-angle meets the requirements, and finally generates a gate-level netlist.

10. The method of claim 9, wherein the digital back-end full-flow scripting design is characterized by: According to the parasitic parameters, IR analysis is performed, including: According to the parasitic parameters, a view file is generated by an IR analysis tool; wherein, the view file contains the power network topology structure, the parasitic parameters and the pin information of the chip; When the chip is in a static state, static IR analysis is performed through the make static_ir command; wherein, the static IR analysis evaluates the static IR performance of the power network by calculating the direct current voltage drop and the average current density distribution of the power network; When the chip is in a dynamic working state, dynamic IR analysis is performed through the make dynamic_ir command; wherein, the dynamic IR analysis obtains the flip information of the chip by reading the VCD waveform file or the SAIF flip activity file, and calculates the alternating current voltage drop and the transient current density distribution of the power network in combination with the flip information, to evaluate the dynamic IR performance of the power network; According to the results of the static IR analysis and the dynamic IR analysis, an IR analysis report is generated.

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