Sensitive amplifier and memory

Abstract

The invention provides a sensitive amplifier and a memory, and relates to the technical field of integrated circuit design. The sensitive amplifier comprises a tail current source, an automatic clamping circuit, a differential pair, an inverter and a latch, wherein the automatic clamping circuit is used for clamping the potential of a first output end or a second output end of a differential pair at a preset potential in a working stage according to a first voltage signal input by a bit line of the memory and a second voltage signal input by an anti-phase line of the memory; the first control end and the second control end of the differential pair are electrically connected with the bit line and the anti-phase line of the memory respectively, so that the potential of the first output end or the second output end of the differential pair can be clamped at the preset potential in the working stage, and recharging can be carried out based on the preset potential in the pre-charging stage. The dynamic power consumption of the sensitive amplifier is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a sensitive amplifier and a memory. Background Art

[0002] Static Random Access Memory (SRAM), as a core component of cache, is widely used in CPUs, GPUs, AI accelerators, and IoT devices. The sense amplifier is a key module in the SRAM read path, responsible for quickly amplifying the tiny voltage difference (usually tens of millivolts) on the memory cell bit line to a logic level.

[0003] In the prior art, during operation, a sense amplifier uses the read voltages on the bit line (BL) and the inverted bit line (BLB) in the SRAM memory array as input signals. The sense amplifier amplifies the voltages, amplifying the higher voltage to "1" and the lower voltage to "0," thereby realizing SRAM read signal judgment.

[0004] However, in existing sensitive amplifiers, each pre-charging stage requires charging its internal nodes from 0 potential to a specified potential. Therefore, existing sensitive amplifiers have the problem of high power consumption during the pre-charging stage. In particular, when the memory of the static random access memory is larger or the reading frequency is higher, the power consumption of this part will also increase. Summary of the Invention

[0005] The purpose of this application is to address the deficiencies in the above-mentioned prior art and provide a sense amplifier and a memory, which can reduce the dynamic power consumption of the sense amplifier.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows: In a first aspect, the present invention provides a sense amplifier, comprising: a tail current source, an automatic clamping circuit, a differential pair, an inverter, and a latch; The control end of the tail current source is electrically connected to the enable end of the sense amplifier of the memory, the input end is grounded, and the output end is electrically connected to the first input end and the second input end of the automatic clamping circuit respectively; The first control terminal of the automatic clamping circuit is electrically connected to the second output terminal of the differential pair and the second input terminal of the latch, respectively; the second control terminal of the automatic clamping circuit is electrically connected to the first output terminal of the differential pair and the first input terminal of the latch, respectively; the first output terminal of the automatic clamping circuit is electrically connected to the first input terminal of the differential pair, and the second output terminal of the automatic clamping circuit is electrically connected to the second input terminal of the differential pair; the automatic clamping circuit is configured to clamp the potential of the first output terminal or the second output terminal of the differential pair at a preset potential according to a first voltage signal inputted from a bit line of the memory and a second voltage signal inputted from an inverted bit line of the memory during an operation phase; The first control end of the differential pair is electrically connected to the bit line of the memory, and the second control end is electrically connected to the inverted bit line of the memory, and the bit line and the inverted bit line form a pair of differential signal lines; The first control terminal and the second control terminal of the latch are respectively electrically connected to the sense amplifier enable terminal of the memory, the first output terminal is electrically connected to the first inverting input terminal of the inverter, the second output terminal is electrically connected to the second inverting input terminal of the inverter, and the third input terminal is connected to a preset DC power supply.

[0007] In an optional embodiment, when the sense amplifier enable terminal of the memory is a low-level signal, the sense amplifier is in a pre-charging stage, and the potentials of the first output terminal and the second output terminal of the differential pair are raised to a preset potential; When the enable terminal of the sensitive amplifier of the memory is a high-level signal, the sensitive amplifier is in the working stage. If the first voltage signal of the bit line input is greater than the second voltage signal of the inverting bit line input, the automatic clamping circuit is used to clamp the potential of the second output terminal of the differential pair at a first preset potential; if the first voltage signal of the bit line input is less than the second voltage signal of the inverting bit line input, the automatic clamping circuit is used to clamp the potential of the first output terminal of the differential pair at a second preset potential.

[0008] In an optional embodiment, the automatic clamping circuit includes: a fifth NMOS transistor and a sixth NMOS transistor, wherein the gate of the fifth NMOS transistor is electrically connected to the second output terminal of the differential pair and the second input terminal of the latch, respectively; the drain of the fifth NMOS transistor is electrically connected to the second input terminal of the differential pair; and the source of the fifth NMOS transistor is electrically connected to the output terminal of the tail current source; The gate of the sixth NMOS tube is electrically connected to the first output end of the differential pair and the first input end of the latch respectively, the drain of the sixth NMOS tube is electrically connected to the first input end of the differential pair, and the source of the sixth NMOS tube is electrically connected to the output end of the tail current source.

[0009] In an optional embodiment, the latch includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all preset with a DC power supply, the gates of the first PMOS transistor and the fourth PMOS transistor are respectively electrically connected to the enable terminal of the sense amplifier of the memory, and the drain of the first PMOS transistor is respectively electrically connected to the drain of the second PMOS transistor, the gate of the third PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the first inverting input terminal of the inverter; The gate of the second PMOS transistor is electrically connected to the gate of the first NMOS transistor, the drain of the first NMOS transistor, the drain of the third PMOS transistor, the drain of the fourth PMOS transistor, and the second inverting input terminal of the inverter respectively; The source of the first NMOS transistor is electrically connected to the first output end of the differential pair and the second control end of the automatic clamping circuit respectively, and the source of the second NMOS transistor is electrically connected to the second output end of the differential pair and the first control end of the automatic clamping circuit respectively.

[0010] In an optional embodiment, the differential pair includes: a third NMOS transistor and a fourth NMOS transistor, the gate of the third NMOS transistor is electrically connected to the bit line of the memory, the source of the third NMOS transistor is electrically connected to the first output end of the automatic clamping circuit, and the drain of the third NMOS transistor is electrically connected to the first input end of the latch; the gate of the fourth NMOS transistor is electrically connected to the inverting bit line of the memory, the source of the fourth NMOS transistor is electrically connected to the second output end of the automatic clamping circuit, and the drain of the fourth NMOS transistor is electrically connected to the second input end of the latch.

[0011] In an optional embodiment, the inverter is a preset threshold inverter, the conduction threshold of the preset threshold inverter is greater than a preset threshold voltage, and the preset threshold inverter includes a first preset threshold inverter and a second preset threshold inverter.

[0012] In an optional embodiment, the inverting input terminal of the first preset threshold inverter is electrically connected to the first output terminal of the latch, and the inverting input terminal of the second preset threshold inverter is electrically connected to the second output terminal of the latch.

[0013] In an optional embodiment, the tail current source includes: a seventh NMOS tube, the gate of the seventh NMOS tube is electrically connected to the enable terminal of the sensitive amplifier of the memory, the source of the seventh NMOS tube is grounded, and the drain of the seventh NMOS tube is electrically connected to the first input terminal and the second input terminal of the automatic clamping circuit respectively.

[0014] In a second aspect, the present invention provides a memory, comprising the sense amplifier as described in any one of the aforementioned embodiments.

[0015] In an optional embodiment, the memory includes at least one of the following: a dynamic random access memory and a static random access memory.

[0016] The beneficial effects of this application are: The sense amplifier and memory provided in the embodiments of the present application include: a tail current source, an automatic clamping circuit, a differential pair, an inverter, and a latch; wherein the control end of the tail current source is electrically connected to the sense amplifier enable end of the memory, the input end is grounded, and the output end is electrically connected to the first input end and the second input end of the automatic clamping circuit respectively; the first control end of the automatic clamping circuit is electrically connected to the second output end of the differential pair and the second input end of the latch respectively, the second control end of the automatic clamping circuit is electrically connected to the first output end of the differential pair and the first input end of the latch respectively, the first output end of the automatic clamping circuit is electrically connected to the first input end of the differential pair, and the second output end of the automatic clamping circuit is electrically connected to the second input end of the differential pair; the automatic clamping circuit is used to, in the working stage, clamp the first bit line of the differential pair according to the first voltage signal input to the memory bit line and the second voltage signal input to the inverted bit line of the memory. The potential of one output terminal or the second output terminal is clamped at a preset potential; the first control terminal of the differential pair is electrically connected to the bit line of the memory, and the second control terminal is electrically connected to the inverted bit line of the memory, and the bit line and the inverted bit line form a pair of differential signal lines; the first control terminal and the second control terminal of the latch are respectively electrically connected to the enable terminal of the sensitive amplifier of the memory, the first output terminal is electrically connected to the first inverting input terminal of the inverter, the second output terminal is electrically connected to the second inverting input terminal of the inverter, and the third input terminal is connected to a preset DC power supply. This achieves that in the working stage, the potential of the first output terminal or the second output terminal of the differential pair can be clamped at the preset potential according to the differential voltage signal output by the differential pair, so as to prevent the potential of the first output terminal and the second output terminal of the differential pair from continuously dropping to a lower potential. Furthermore, in the pre-charging stage, the sensitive amplifier can be recharged based on the clamped preset potential, thereby reducing the dynamic power consumption of the sensitive amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of a circuit module of a sensitive amplifier provided in this application; Figure 2 A schematic diagram of the circuit structure of a sensitive amplifier provided in this application; Figure 3 A schematic diagram of the circuit structure of another sensitive amplifier provided in this application; Figure 4 A circuit timing diagram of a sense amplifier provided in this application; Figure 5 A schematic diagram of a memory module provided in this application. DETAILED DESCRIPTION

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0021] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0022] The sense amplifier is a key module in the SRAM read path, responsible for quickly amplifying the tiny voltage difference (typically tens of millivolts) on the memory cell's bit line to a logic level. However, as process nodes advance to nanometer levels (e.g., below 7nm) and memory density increases, the power consumption of the sense amplifier becomes increasingly prominent.

[0023] In related technologies, during operation, the sense amplifier primarily uses the read voltages on the BL and BLB pins in the SRAM memory array as input signals. The sense amplifier amplifies the voltage, converting higher voltages to "1" and lower voltages to "0," thereby determining the SRAM read signal. During the precharge phase, the sense amplifier charges all internal nodes to VDD, including both the "1" and "0" voltages during operation. Therefore, each read operation involves a charging process from "0" voltage to VDD. The larger the memory capacity or the higher the read frequency, the higher the power consumption of this component, resulting in increased energy requirements for the memory.

[0024] In view of this, an embodiment of the present application provides a sensitive amplifier, which includes an automatic clamping circuit 102. When the sensitive amplifier is in the working stage, the potential of the first output end or the second output end of the differential pair 103 can be clamped at a preset potential based on a first voltage signal input to the bit line of the memory and a second voltage signal input to the inverted bit line of the memory. Then, in the pre-charging stage, the sensitive amplifier can be recharged based on the clamped preset potential, thereby reducing the dynamic power consumption of the sensitive amplifier.

[0025] Figure 1 This is a circuit module diagram of a sensitive amplifier provided in this application. Figure 1 As shown, the sense amplifier includes a tail current source 101 , an automatic clamping circuit 102 , a differential pair 103 , an inverter 104 and a latch 105 .

[0026] The control terminal of the tail current source 101 is electrically connected to the sense amplifier enable terminal SAEN of the memory, the input terminal is grounded, and the output terminal is electrically connected to the first input terminal and the second input terminal of the automatic clamping circuit 102 respectively; The first control end of the automatic clamping circuit 102 is electrically connected to the second output end of the differential pair 103 and the second input end of the latch 105, respectively. The second control end of the automatic clamping circuit 102 is electrically connected to the first output end of the differential pair 103 and the first input end of the latch 105, respectively. The first output end of the automatic clamping circuit 102 is electrically connected to the first input end of the differential pair 103, and the second output end of the automatic clamping circuit 102 is electrically connected to the second input end of the differential pair 103. The automatic clamping circuit 102 is used to clamp the potential of the first output end or the second output end of the differential pair 103 at a preset potential according to a first voltage signal inputted by a bit line of the memory and a second voltage signal inputted by an inverted bit line of the memory during the working phase.

[0027] A first control terminal of the differential pair 103 is electrically connected to a bit line of the memory, and a second control terminal is electrically connected to an inverted bit line of the memory. The bit line and the inverted bit line form a pair of differential signal lines.

[0028] The first control terminal and the second control terminal of the latch 105 are respectively electrically connected to the sensitive amplifier enable terminal SAEN of the memory, the first output terminal is electrically connected to the first inverting input terminal of the inverter 104, the second output terminal is electrically connected to the second inverting input terminal of the inverter 104, and the third input terminal is connected to a preset DC power supply.

[0029] Optionally, the inverter 104 may be a standard inverter, wherein the standard inverter may be formed of a standard NMOS transistor and a standard PMOS transistor to form a complementary symmetrical transistor structure.

[0030] Among them, the sense amplifier is a key circuit in the memory system for detecting and amplifying weak signals of the bit line. Its working process can be divided into a pre-charging stage and a working stage, wherein the working stage is located after the pre-charging stage.

[0031] The working principle of the sense amplifier is as follows: in the pre-charge phase, the sense amplifier is mainly used to pre-charge the potentials of the first output terminal and the second output terminal of the differential pair 103 to the initial voltage level, providing a stable reference baseline for subsequent data reading, while eliminating the residual signal influence of the previous operation; in the working phase, when the bit line (Bit Line, BL) and the inverted bit line (Bit Line Bar, BLB) of the memory have a slight difference due to the stored data, the sense amplifier detects this difference and amplifies it to a standard logic level to complete the data reading.

[0032] The tail current source 101 is used to provide a preset DC power supply; the differential pair 103 is used to convert a first voltage signal inputted from a bit line and a second voltage signal inputted from an inverted bit line into a differential voltage signal.

[0033] Latch 105 is used to latch the output to inverter 104 when the potential values ​​of the first output terminal and the second output terminal of the latch 105 are stable; inverter 104 is used to output a first level signal corresponding to the first voltage signal and a second level signal corresponding to the second voltage signal according to the potential values ​​of the first output terminal and the second output terminal of the latch 105.

[0034] In conjunction with the differential pair 103, the automatic clamping circuit 102 is used to clamp the potential of the first output terminal or the second output terminal of the differential pair 103 at a preset potential according to the differential voltage signal output by the differential pair 103 during the working phase, so as to prevent the potential of the first output terminal and the second output terminal of the differential pair 103 from continuously dropping to a lower potential. Then, in the pre-charging phase, the sensitive amplifier can be recharged based on the clamped preset potential, thereby reducing the dynamic power consumption of the sensitive amplifier.

[0035] In summary, an embodiment of the present application provides a sensitive amplifier circuit, comprising: a tail current source, an automatic clamping circuit, a differential pair, an inverter, and a latch; wherein the control end of the tail current source is electrically connected to the sensitive amplifier enable end of the memory, the input end is grounded, and the output end is electrically connected to the first input end and the second input end of the automatic clamping circuit respectively; the first control end of the automatic clamping circuit is electrically connected to the second output end of the differential pair and the second input end of the latch respectively, the second control end of the automatic clamping circuit is electrically connected to the first output end of the differential pair and the first input end of the latch respectively, the first output end of the automatic clamping circuit is electrically connected to the first input end of the differential pair, and the second output end of the automatic clamping circuit is electrically connected to the second input end of the differential pair; the automatic clamping circuit is used to, in a working stage, clamp the first bit line of the differential pair according to a first voltage signal input to the memory bit line and a second voltage signal input to the inverted bit line of the memory. The potential of one output terminal or the second output terminal is clamped at a preset potential; the first control terminal of the differential pair is electrically connected to the bit line of the memory, and the second control terminal is electrically connected to the inverted bit line of the memory, and the bit line and the inverted bit line form a pair of differential signal lines; the first control terminal and the second control terminal of the latch are respectively electrically connected to the enable terminal of the sensitive amplifier of the memory, the first output terminal is electrically connected to the first inverting input terminal of the inverter, the second output terminal is electrically connected to the second inverting input terminal of the inverter, and the third input terminal is connected to a preset DC power supply. This achieves that in the working stage, the potential of the first output terminal or the second output terminal of the differential pair can be clamped at the preset potential according to the differential voltage signal output by the differential pair, so as to prevent the potential of the first output terminal and the second output terminal of the differential pair from continuously dropping to a lower potential. Furthermore, in the pre-charging stage, the sensitive amplifier can be recharged based on the clamped preset potential, thereby reducing the dynamic power consumption of the sensitive amplifier.

[0036] In an optional embodiment, when the sense amplifier enable terminal SAEN of the memory is a low-level signal, the sense amplifier is in a pre-charging stage, and the potentials of the first output terminal and the second output terminal of the differential pair 103 are raised to a preset potential.

[0037] When the sense amplifier enable terminal SAEN of the memory is a high-level signal, the sense amplifier is in the working stage. If the first voltage signal of the bit line input is greater than the second voltage signal of the inverting bit line input, the automatic clamping circuit 102 is used to clamp the potential of the second output terminal of the differential pair 103 at the first preset potential; if the first voltage signal of the bit line input is less than the second voltage signal of the inverting bit line input, the automatic clamping circuit 102 is used to clamp the potential of the first output terminal of the differential pair 103 at the second preset potential.

[0038] Among them, if the sensitive amplifier enable terminal SAEN of the memory is a low-level signal, it can be determined that the sensitive amplifier is in the pre-charging stage. At this time, the first output terminal and the second output terminal of the differential pair 103 can be charged through the preset DC power supply connected to the latch 105 to charge the potential of the first output terminal and the second output terminal of the differential pair 103 to the preset potential.

[0039] If the sense amplifier enable terminal SAEN of the memory is a high-level signal, it indicates that the memory is performing a read operation, and it can be determined that the sense amplifier is in the working stage. Furthermore, if the first voltage signal of the bit line input of the memory is greater than the second voltage signal of the inverting bit line input (that is, the BL potential is higher than the BLB potential), then at this time, the potential of the second output terminal of the differential pair 103 can be clamped at the first preset potential by the automatic clamping circuit 102 to prevent the potential of the second output terminal of the differential pair 103 from continuously dropping to a lower potential; and if the first voltage signal of the bit line input of the memory is less than the second voltage signal of the inverting bit line input (that is, the BL potential is lower than the BLB potential), then at this time, the potential of the first output terminal of the differential pair 103 can be clamped at the first preset potential by the automatic clamping circuit 102 to prevent the potential of the first output terminal of the differential pair 103 from continuously dropping to a lower potential.

[0040] By applying the embodiments of the present application, it is achieved that when the first voltage signal is greater than the second voltage signal, the potential of the second output end of the differential pair 103 can be clamped at the first preset potential through the automatic clamping circuit 102; when the first voltage signal is less than the second voltage signal, the potential of the first output end of the differential pair 103 can be clamped at the second preset potential through the automatic clamping circuit 102, ensuring that the potential clamping function can be implemented by the automatic clamping circuit 102 when the memory reads various types of data, thereby reducing the dynamic power consumption of the sensitive amplifier and improving the applicability of the sensitive amplifier.

[0041] Figure 2 This is a schematic diagram of the circuit structure of a sensitive amplifier provided by this application. In an optional embodiment, as Figure 2 As shown, in an optional embodiment, the differential pair 103 includes: a third NMOS transistor NM3 and a fourth NMOS transistor NM4, the gate of the third NMOS transistor NM3 is electrically connected to the bit line of the memory, the source of the third NMOS transistor NM3 is electrically connected to the first output terminal of the automatic clamping circuit 102, and the drain of the third NMOS transistor NM3 is electrically connected to the first input terminal of the latch 105; the gate of the fourth NMOS transistor NM4 is electrically connected to the inverting bit line of the memory, the source of the fourth NMOS transistor NM4 is electrically connected to the second output terminal of the automatic clamping circuit 102, and the drain of the fourth NMOS transistor NM4 is electrically connected to the second input terminal of the latch 105.

[0042] The differential pair 103 can be configured based on multiple NMOS transistors, such as Figure 2 As shown, the differential pair 103 may include a third NMOS transistor NM3 and a fourth NMOS transistor NM4, a total of two NMOS transistors. When the sense amplifier enable terminal of the memory is a low-level signal, the sense amplifier is in a pre-charging stage. At this time, the potentials of the first output terminal and the second output terminal of the differential pair 103 can be charged to a preset potential through a preset DC power supply connected to the latch 105. Optionally, the preset potential can be a power supply voltage of a preset DC power supply.

[0043] It should be noted that the setting of the differential pair 103 is not limited to this. According to the actual application scenario, the differential pair 103 can also be set to include multiple PMOS tubes, or to include multiple PMOS tubes and multiple NMOS tubes. This is not limited here and can be flexibly set according to the actual application scenario.

[0044] like Figure 2 As shown, the automatic clamping circuit 102 includes: a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6, wherein the gate of the fifth NMOS transistor NM5 is electrically connected to the second output terminal of the differential pair 103 and the second input terminal of the latch 105, respectively; the drain of the fifth NMOS transistor NM5 is electrically connected to the second input terminal of the differential pair 103; and the source of the fifth NMOS transistor NM5 is electrically connected to the output terminal of the tail current source 101; The gate of the sixth NMOS transistor NM6 is electrically connected to the first output terminal of the differential pair 103 and the first input terminal of the latch 105 respectively, the drain of the sixth NMOS transistor NM6 is electrically connected to the first input terminal of the differential pair 103, and the source of the sixth NMOS transistor NM6 is electrically connected to the output terminal of the tail current source 101.

[0045] In an optional embodiment, the tail current source 101 includes: a seventh NMOS transistor NM7, the gate of the seventh NMOS transistor NM7 is electrically connected to the sense amplifier enable terminal of the memory, the source of the seventh NMOS transistor NM7 is grounded, and the drain of the seventh NMOS transistor NM7 is electrically connected to the first input terminal and the second input terminal of the automatic clamping circuit 102 respectively.

[0046] The operating principle of the automatic clamping circuit 102 is as follows: when the enable terminal of the memory's sense amplifier is a high-level signal, the sense amplifier is in the operating stage. At this time, the seventh NMOS transistor NM7 is turned on, and a discharge loop is provided for the circuit via the tail current source 101. When the first voltage signal input to the bit line is less than the second voltage signal input to the inverted bit line (i.e., the BLB potential is greater than the BL potential), the charge discharge rate of the second output terminal CB1 of the differential pair 103 will be greater than the charge discharge rate CT1 of the first output terminal of the differential pair 103, causing the potential of the second output terminal CB1 of the differential pair 103 to be less than the potential of the first output terminal CT1 of the differential pair 103.

[0047] Furthermore, since the second output terminal CB1 of the differential pair 103 is connected to the gate of the fifth NMOS transistor NM5, and the first output terminal CT1 of the differential pair 103 is connected to the gate of the sixth NMOS transistor NM6, the potential of the second output terminal CB1 of the differential pair 103 is lower than the potential of the first output terminal CT1 of the differential pair 103. This will cause the conduction degree of the fifth NMOS transistor NM5 to be lower than the conduction degree of the sixth NMOS transistor NM6, thereby further amplifying the potential drop speed of the second output terminal CB1 of the differential pair 103.

[0048] When the potential at the second output terminal CB1 of the differential pair 103 drops below the threshold voltage of the fifth NMOS transistor NM5, the fifth NMOS transistor NM5 is turned off, and the first output terminal CT1 of the differential pair 103 is clamped to the potential corresponding to the turn-off state of the fifth NMOS transistor NM5. The second output terminal CB1 of the differential pair 103 continues to discharge. The preset DC power supply connected through the latch 105 can continuously act on the first output terminal CT1 of the differential pair 103, thereby causing the potential of the first output terminal CT1 of the differential pair 103 to begin to rise. After rising to approximately equal the potential of the first output terminal of the latch 105, it begins to stabilize. At this time, the potential of the first output terminal CT1 of the differential pair 103 will be greater than the threshold voltage of the sixth NMOS transistor NM6. Therefore, the sixth NMOS transistor NM6 will remain in the on state, and the second output terminal CB1 of the differential pair 103 will continue to discharge to a lower potential.

[0049] Figure 3 This is a schematic diagram of the circuit structure of another sensitive amplifier provided in this application. Figure 4 This is a circuit timing diagram of a sense amplifier provided in this application. In an optional embodiment, as Figure 3 As shown, the latch 105 includes a first PMOS transistor PM1 , a second PMOS transistor PM2 , a third PMOS transistor PM3 , a fourth PMOS transistor PM4 , a first NMOS transistor NM1 , and a second NMOS transistor NM2 .

[0050] The sources of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 are all connected to a preset DC power supply. The gates of the first PMOS transistor PM1 and the fourth PMOS transistor PM4 are respectively electrically connected to the enable terminal of the sense amplifier of the memory. The drain of the first PMOS transistor PM1 is respectively electrically connected to the drain of the second PMOS transistor PM2, the gate of the third PMOS transistor PM3, the drain of the first NMOS transistor PM1, the gate of the second NMOS transistor NM2, and the first inverting input terminal of the inverter 104.

[0051] The gate of the second PMOS transistor PM2 is electrically connected to the gate of the first NMOS transistor NM1 , the drain of the second NMOS transistor NM2 , the drain of the third PMOS transistor PM3 , the drain of the fourth PMOS transistor NM4 , and the second inverting input terminal of the inverter 104 .

[0052] The source of the first NMOS transistor NM1 is electrically connected to the first output terminal of the differential pair 103 and the second control terminal of the automatic clamping circuit 102 . The source of the second NMOS transistor NM2 is electrically connected to the second output terminal of the differential pair 103 and the first control terminal of the automatic clamping circuit 102 .

[0053] In conjunction with the above circuit, when the sensor is in the initial pre-charging stage, the operating principle of the latch 105 is as follows: the memory's sense amplifier enable terminal SAEN signal is at a low voltage, the seventh NMOS transistor NM7 is turned off, and in the initial stage, the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 are turned on. The conduction of the first PMOS transistor PM1 and the fourth PMOS transistor PM4 raises the potential of the first inverting input terminal XT1 and the second inverting input terminal XB1 of the inverter 104. When the potential of the first inverting input terminal XT1 rises to the threshold voltage of the second PMOS transistor PM2, the second PMOS transistor PM2 is turned off. When the potential of the second inverting input terminal XB1 rises to the threshold voltage of the third PMOS transistor PM3, the third PMOS transistor PM3 is turned off.

[0054] When the potential of the first inverting input terminal XT1 is continuously raised, the first preset threshold inverter will be pulled down to a lower potential. When the potential of the second inverting input terminal XB1 is continuously raised, the second preset threshold inverter will be pulled down to a lower potential.

[0055] Furthermore, when the potential of the first inverting input terminal XT1 is continuously raised to a value greater than the threshold voltage of the first NMOS transistor NM1, the first NMOS transistor NM1 is turned on, and at this time, charge is transferred to the source of the first NMOS transistor NM1 (i.e., the first output terminal of the differential pair 103), and the first output terminal of the differential pair 103 is raised to a preset potential; when the potential of the second inverting input terminal XB1 is continuously raised to a value greater than the threshold voltage of the second NMOS transistor NM2, the second NMOS transistor NM2 is turned on, and at this time, charge is transferred to the source of the second NMOS transistor NM2 (i.e., the second output terminal of the differential pair 103), and the second output terminal of the differential pair 103 is raised to a preset potential.

[0056] In addition, when the sensor is in the working stage, the working principle of the latch 105 is as follows: the memory sense amplifier enable terminal SAEN signal is high potential, if the first voltage signal of the bit line input is less than the second voltage signal of the inverted bit line input, such as Figure 4 As shown, at time t1, the potential value of BLB is 750 mV, and the potential value of BL is 720 mV, that is, the potential of BLB is greater than the potential of BL. Time t2 is a working moment in the working stage in which the potential of BLB is less than the potential of BL.

[0057] Based on the above description, when the sense amplifier enable terminal SAEN of the memory is a low-level signal, the sense amplifier is in the precharge stage, and there is no voltage difference between the first voltage signal BL input to the bit line of the memory and the second voltage signal BLB input to the inverting bit line of the memory, since the first PMOS transistor PM1 and the fourth PMOS transistor PM4 are turned on, the first inverting input terminal XT1 and the second inverting input terminal XB1 are both precharged to the power supply voltage, the conduction capabilities of NM1 and NM2 are the same, and therefore CT1 and CB1 are also the same.

[0058] Furthermore, when the first voltage signal BL input to the memory's bit line is less than the second voltage signal BLB input to the memory's inverting bit line, a voltage difference exists between BL and BLB, and the memory's sense amplifier enable terminal SAEN is a low-level signal. Then, the voltage at the first inverting input terminal XT1 is equal to the voltage at the second inverting input terminal XB1. At this time, since the VGS of the third NMOS transistor NM3 is less than 0 (VGS is the Gate terminal voltage minus the Source terminal voltage), NM3 is in a cut-off state, while the VGS of NM4 is greater than 0 and less than its corresponding threshold voltage, and NM4 is in a leakage state. Therefore, since NM3 is cut off, the first inverting input terminal XT1 continues to charge CT1, and the potential of CT1 is higher than CB1.

[0059] To better understand the present application, the following description is made in conjunction with a specific timing diagram. When the sense amplifier enable terminal SAEN of the memory is a high-level signal, the sense amplifier is in the working phase, wherein the working phase can be divided into a pre-working phase and a stable phase, wherein the stable phase is located after the pre-working phase.

[0060] In the pre-operation phase, the first PMOS transistor PM1 and the fourth PMOS transistor PM4 are turned off. Since the potential of the first inverting input terminal XT1 has not dropped to the turn-on voltage of the third PMOS transistor PM3, and since the potential of the second inverting input terminal XB1 has not dropped to the turn-on voltage of the second PMOS transistor PM2, the second PMOS transistor PM2 and the third PMOS transistor PM3 are both turned off. At this time, the first inverting input terminal XT1 and the second inverting input terminal XB1 are temporarily in an inactive state. Moreover, since the first NMOS transistor NM1 and the second NMOS transistor NM2 have the same conduction capability and are in a weak conduction state in the initial phase, the potential drop rate of the first drain CT1 of the differential pair 103 is much faster than the potential drop rate of the second drain CB1 of the differential pair 103. As a result, when NM5 is turned off, the potential of the first inverting input terminal XT1 reaches the threshold voltage of the second PMOS transistor PM2 and the third PMOS transistor PM3 before the second inverting input terminal XB1, as shown in FIG. Figure 4 As shown, at time t1, the potential of the first inverting input terminal XT1 is 294.9 mV, and the potential of the second inverting input terminal XB1 is 573.0 mV. The potential of the first inverting input terminal XT1 is less than the potential of the second inverting input terminal XB1. The threshold voltage of the second PMOS transistor PM2 is equal to the threshold voltage of the third PMOS transistor PM3. The third PMOS transistor PM3 is turned on before the second PMOS transistor PM2.

[0061] In addition, because the potential of the first inverting input terminal XT1 falls below the threshold voltages of the first NMOS transistor NM1 and the second NMOS transistor NM2 before the potential of the second inverting input terminal XB1, the second NMOS transistor NM2 is turned off before the first NMOS transistor NM1. Furthermore, the threshold voltage of the first NMOS transistor NM1 is equal to the threshold voltage of the second NMOS transistor NM2. Therefore, the potential of the second inverting input terminal XB1 is pulled up to a relatively high level (for example, 573 mV) and then enters a stable phase.

[0062] In the stable phase, the potential of the second inverting input terminal XB1 will be greater than the threshold of the inverter 104, the second inverting output terminal of the inverter 104 will output a logic level 0, and the first inverting output terminal of the inverter 104 will output a logic level 1. Figure 4 As shown, at time t1, the potential value of BLBO is 737.1 mV, which corresponds to a logic level 1, and the potential value of BLO is 1.37 mV, which corresponds to a logic level 0.

[0063] It can be seen that, by applying the embodiment of the present application, when BLB is greater than BL, the first inverting output terminal of the inverter 104 will output a logic level 1, and the second inverting output terminal of the inverter 104 will output a logic level 0; wherein, when BLB is less than BL, referring to the above working principle, it can be seen that the first inverting output terminal of the inverter 104 will output a logic level 0, and the second inverting output terminal of the inverter 104 will output a logic level 1.

[0064] like Figure 4 As shown, it should also be noted that, if the current working stage is completed, the sense amplifier will enter the next pre-charging cycle, the potential of the first output terminal CT1 of the differential pair 103 is increased from 294mV to the power supply voltage of the preset DC power supply, the potential of the second output terminal CB1 of the differential pair 103 is increased from 61.6mV to the power supply voltage of the preset DC power supply, the potential of the first inverting input terminal XT1 is increased from 294.9mV to the power supply voltage of the preset DC power supply, and the potential of the second inverting input terminal XB1 is increased from 573.0mV to the power supply voltage of the preset DC power supply. Compared with the prior art, a certain amount of charge can be retained to avoid complete discharge in the working stage, so that charging can be performed based on the currently retained potential in the next pre-charging stage, which can effectively reduce the power consumption of the sense amplifier.

[0065] It should be noted that if Figure 4 As shown, time t2 is the time point corresponding to the working cycle when the BLB potential is greater than the BL potential. For the description of time t2, please refer to the relevant content of time t1 above, which will not be repeated here.

[0066] In an optional embodiment, the inverter 104 is a preset threshold inverter, the on-threshold of which is greater than a preset threshold voltage, and the preset threshold inverter includes a first preset threshold inverter HVT-INV1 and a second preset threshold inverter HVT-INV2.

[0067] Among them, the preset threshold inverter 104 can be a high threshold inverter. Compared with the standard inverter, the standard inverter refers to a transistor structure formed by a standard NMOS tube and a standard PMOS tube to form a complementary symmetrical structure, while the high threshold inverter is also composed of a high threshold NMOS tube (N-HVT) and a high threshold PMOS tube (P-HVT) to form an inverter 104 with a complementary symmetrical structure.

[0068] like Figure 3 As shown, the high threshold inverter may include: a first preset threshold inverter (ie, a first high threshold inverter HVT-INV1) and a second preset threshold inverter (ie, a second high threshold inverter HVT-INV2).

[0069] Based on the above analysis, it can be understood that by configuring the inverter 104 as a high-threshold inverter, when the potential at the first inverting input terminal XT1 drops, the high-threshold PMOS transistor in the first preset threshold inverter will turn on before the third PMOS transistor PM3, causing the first inverting output terminal to output a logic level 1, and correspondingly, the second inverting output terminal to output a logic level 0. Compared to the conventional method of using a standard inverter 104 as an output flipping circuit, by configuring the high-threshold inverter as the output flipping circuit, the threshold voltage of the high-threshold PMOS transistor within the high-threshold inverter is lower than the threshold voltage of the standard PMOS transistor in the standard-threshold inverter 104. Therefore, the high-threshold inverter can output an inverted signal when the potentials at the first inverting input terminal XT1 and the second inverting input terminal XB1 drop even lower, thereby avoiding inverted output caused by insufficient potentials at the first inverting input terminal XT1 and the second inverting input terminal XB1. This, in turn, prevents a reduction in the output margin of the sense amplifier, thereby improving the read accuracy of the sense amplifier.

[0070] In an optional embodiment, the inverting input terminal of the first preset threshold inverter is electrically connected to the first output terminal of the latch 105 , and the inverting input terminal of the second preset threshold inverter is electrically connected to the second output terminal of the latch 105 .

[0071] Refer to the above Figure 3 As shown, the inverting input terminal of the first preset threshold inverter is electrically connected to the first output terminal of the latch 105 (that is, the drain of the first NMOS tube NM1), and the inverting input terminal of the second preset threshold inverter is electrically connected to the second output terminal of the latch 105 (that is, the drain of the second NMOS tube NM2).

[0072] It should be noted that the present application does not limit the specific setting method of the above-mentioned tail current source 101, automatic clamping circuit 102, differential pair 103, inverter 104 and latch 105. According to the actual application scenario, for each module, according to the actual application scenario, some or all of the PMOS tubes can be replaced by NMOS tubes, or some or all of the NMOS tubes can be replaced by PMOS tubes. This is not limited here and can be flexibly set according to the actual application scenario.

[0073] Figure 5 This is a module diagram of a memory provided by this application. Figure 5 As shown, the memory 200 may include the sense amplifier 100 as described in the above embodiment.

[0074] In an optional implementation, the memory 200 includes at least one of the following: a dynamic random access memory (DRAM) and a static random access memory (SRAM).

[0075] Of course, it should be noted that the present application does not limit the specific type of memory. Depending on the actual application scenario, it can also be other types of memory including a sense amplifier.

[0076] By applying the embodiments of the present application, it is achieved that when the first voltage signal is greater than the second voltage signal, the potential of the second output end of the differential pair can be clamped at the first preset potential through the automatic clamping circuit; when the first voltage signal is less than the second voltage signal, the potential of the first output end of the differential pair can be clamped at the second preset potential through the automatic clamping circuit, ensuring that the memory can implement the potential clamping function through the automatic clamping circuit when reading various types of data, reducing the dynamic power consumption of the sensitive amplifier, and thereby reducing the reading energy consumption of the memory.

[0077] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element. The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A sensitive amplifier, characterized in that: The sensitive amplifier includes: a tail current source, an automatic clamping circuit, a differential pair, an inverter and a latch; The control end of the tail current source is electrically connected to the enable end of the sense amplifier of the memory, the input end is grounded, and the output end is electrically connected to the first input end and the second input end of the automatic clamping circuit respectively; The first control terminal of the automatic clamping circuit is electrically connected to the second output terminal of the differential pair and the second input terminal of the latch, respectively; the second control terminal of the automatic clamping circuit is electrically connected to the first output terminal of the differential pair and the first input terminal of the latch, respectively; the first output terminal of the automatic clamping circuit is electrically connected to the first input terminal of the differential pair, and the second output terminal of the automatic clamping circuit is electrically connected to the second input terminal of the differential pair; the automatic clamping circuit is configured to clamp the potential of the first output terminal or the second output terminal of the differential pair at a preset potential according to a first voltage signal inputted from a bit line of the memory and a second voltage signal inputted from an inverted bit line of the memory during an operation phase; The first control end of the differential pair is electrically connected to the bit line of the memory, and the second control end is electrically connected to the inverted bit line of the memory, and the bit line and the inverted bit line form a pair of differential signal lines; The first control terminal and the second control terminal of the latch are respectively electrically connected to the sense amplifier enable terminal of the memory, the first output terminal is electrically connected to the first inverting input terminal of the inverter, the second output terminal is electrically connected to the second inverting input terminal of the inverter, and the third input terminal is connected to a preset DC power supply.

2. The sense amplifier according to claim 1, wherein: When the sense amplifier enable terminal of the memory is a low-level signal, the sense amplifier is in a pre-charging stage, and the potentials of the first output terminal and the second output terminal of the differential pair are raised to a preset potential; When the sense amplifier enable terminal of the memory is a high-level signal, the sense amplifier is in a working stage, and if the first voltage signal input to the bit line is greater than the second voltage signal input to the inverted bit line, the automatic clamping circuit is used to clamp the potential of the second output terminal of the differential pair to a first preset potential; If the first voltage signal inputted by the bit line is less than the second voltage signal inputted by the inverted bit line, the automatic clamping circuit is configured to clamp the potential of the first output terminal of the differential pair to a second preset potential.

3. The sense amplifier according to claim 1, wherein: The automatic clamping circuit includes: a fifth NMOS transistor and a sixth NMOS transistor, wherein the gate of the fifth NMOS transistor is electrically connected to the second output terminal of the differential pair and the second input terminal of the latch, respectively; the drain of the fifth NMOS transistor is electrically connected to the second input terminal of the differential pair; and the source of the fifth NMOS transistor is electrically connected to the output terminal of the tail current source; The gate of the sixth NMOS tube is electrically connected to the first output end of the differential pair and the first input end of the latch respectively, the drain of the sixth NMOS tube is electrically connected to the first input end of the differential pair, and the source of the sixth NMOS tube is electrically connected to the output end of the tail current source.

4. The sense amplifier according to claim 1, wherein: The latch includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor and a second NMOS transistor; The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all preset with a DC power supply, the gates of the first PMOS transistor and the fourth PMOS transistor are respectively electrically connected to the enable terminal of the sense amplifier of the memory, and the drain of the first PMOS transistor is respectively electrically connected to the drain of the second PMOS transistor, the gate of the third PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the first inverting input terminal of the inverter; The gate of the second PMOS transistor is electrically connected to the gate of the first NMOS transistor, the drain of the first NMOS transistor, the drain of the third PMOS transistor, the drain of the fourth PMOS transistor, and the second inverting input terminal of the inverter respectively; The source of the first NMOS transistor is electrically connected to the first output end of the differential pair and the second control end of the automatic clamping circuit respectively, and the source of the second NMOS transistor is electrically connected to the second output end of the differential pair and the first control end of the automatic clamping circuit respectively.

5. The sense amplifier according to claim 1, wherein: The differential pair includes: a third NMOS transistor and a fourth NMOS transistor, the gate of the third NMOS transistor is electrically connected to the bit line of the memory, the source of the third NMOS transistor is electrically connected to the first output end of the automatic clamping circuit, and the drain of the third NMOS transistor is electrically connected to the first input end of the latch; the gate of the fourth NMOS transistor is electrically connected to the inverting bit line of the memory, the source of the fourth NMOS transistor is electrically connected to the second output end of the automatic clamping circuit, and the drain of the fourth NMOS transistor is electrically connected to the second input end of the latch.

6. The sense amplifier according to claim 1, wherein: The inverter is a preset threshold inverter, a conduction threshold of the preset threshold inverter is greater than a preset threshold voltage, and the preset threshold inverter includes a first preset threshold inverter and a second preset threshold inverter.

7. The sense amplifier according to claim 6, wherein: The inverting input terminal of the first preset threshold inverter is electrically connected to the first output terminal of the latch, and the inverting input terminal of the second preset threshold inverter is electrically connected to the second output terminal of the latch.

8. The sense amplifier according to any one of claims 1 to 7, wherein: The tail current source includes: a seventh NMOS transistor, the gate of the seventh NMOS transistor is electrically connected to the enable terminal of the sense amplifier of the memory, the source of the seventh NMOS transistor is grounded, and the drain of the seventh NMOS transistor is electrically connected to the first input terminal and the second input terminal of the automatic clamping circuit respectively.

9. A memory, characterized in that: The memory comprises the sense amplifier according to any one of claims 1-8.

10. The memory according to claim 9, wherein: The memory includes at least one of the following: a dynamic random access memory and a static random access memory.

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