Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises a substrate and a stacking structure, and the stacking structure comprises a first layer and a second layer which are alternately stacked; a limiting structure is formed, so that a plurality of sub-stacking structures arranged at intervals in the first horizontal direction are defined in the stacking structure, the limiting structure comprises conductive wires, isolation wires and isolation wall structures, the conductive wires and the first layer are arranged on the same layer, the isolation wires and the second layer are arranged on the same layer, and the isolation wall structures penetrate through the stacking structure to make contact with the substrate; each sub-stacking structure is surrounded by a conductive wire, an isolation wire and an isolation wall structure; processing the plurality of sub-stack structures by wet etching to form a plurality of contact holes with different depths; a plurality of conductive step structures are formed in a plurality of contact holes, and one conductive step structure is correspondingly and electrically connected with one conductive wire, so that the positioning accuracy of the conductive step structures can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] A memory cell is actually a type of sequential logic circuit and can be divided into read-only memory (ROM) and random access memory (RAM) according to the type of memory used.

[0003] The integration level of semiconductor devices is an important factor in determining product prices. In order to achieve excellent performance and low prices, semiconductor devices are developing towards higher integration levels. However, as the integration level increases, the etching process becomes more difficult and the etching accuracy decreases.

[0004] Therefore, it is necessary to provide a method for manufacturing a semiconductor structure to improve the accuracy of etching, thereby improving the reliability of the formed conductive step structure. Summary of the Invention

[0005] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure, which can at least improve the reliability of the formed semiconductor structure.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a base, the base comprising a substrate and a stacking structure located on the substrate, the stacking structure comprising a first layer and a second layer stacked alternately, the second layer being a dielectric layer; forming a limiting structure to define a plurality of sub-stacked structures spaced apart along a first horizontal direction in the stacking structure, the limiting structure comprising a conductive line and an isolation line stacked alternately, and an isolation wall structure, the conductive line being arranged in the same layer as the first layer, the isolation line being arranged in the same layer as the second layer, the isolation wall structure passing through the stacking structure and contacting the substrate, each of the sub-stacked structures being surrounded by the conductive line, the isolation line and the isolation wall structure; wet etching the plurality of sub-stacked structures to form a plurality of contact holes with different depths; forming a plurality of conductive step structures in the plurality of contact holes, one of the conductive step structures being electrically connected to one of the conductive lines accordingly.

[0007] In some embodiments, forming the defining structure includes: etching the stacked structure to form a first vertical opening, the first vertical opening including a first vertical sub-opening extending along the first horizontal direction and a plurality of second vertical sub-openings extending along the second horizontal direction, the plurality of second vertical sub-openings being located on the same side of the first vertical sub-opening and each being connected to the first vertical sub-opening; forming the isolation wall structure in the first vertical opening, the isolation wall structure including a first isolation wall located in the first vertical sub-opening and a plurality of second isolation walls located in the plurality of second vertical sub-openings; forming a second vertical opening on a side of the plurality of second isolation walls away from the first isolation wall; laterally etching the second layer from the second vertical opening to form a first horizontal opening, the first horizontal opening exposing the side walls of the plurality of second isolation walls; forming the isolation line in the first horizontal opening; laterally etching the first layer along the second vertical opening to form a second horizontal opening, the second horizontal opening exposing the side walls of the plurality of second isolation walls; and forming the conductive line in the second horizontal opening.

[0008] In some embodiments, the multiple sub-stack structures are processed by wet etching to form multiple contact holes with different depths, including: removing several first layers and several second layers in the multiple sub-stack structures by wet etching to form multiple initial holes with different depths, each of the initial holes exposing the top surface of one of the first layers as the target layer; forming an isolation layer on the sidewalls of the multiple initial holes; removing the target layer exposed by the multiple initial holes by wet etching to expose the conductive wires arranged in the same layer as the target layer, the space in each initial hole not filled by the isolation layer and the space left after the target layer is removed together form one contact hole.

[0009] In some embodiments, the material of the isolation layer is the same as the material of the second layer.

[0010] In some embodiments, the isolation line is made of the same material as the isolation wall structure.

[0011] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a semiconductor structure, comprising: a substrate; a defining structure located on the substrate, defining a plurality of regions arranged at intervals along a first horizontal direction on the substrate, the defining structure comprising a line stacking structure and an isolation wall structure, the line stacking structure comprising alternatingly stacked conductive lines and isolation lines, the bottom surface of the isolation wall structure being in contact with the substrate, and each of the regions being surrounded by the line stacking structure and the isolation wall structure; a plurality of stacking substructures, respectively located in the plurality of regions, at least two of the stacking substructures comprising at least one stacking structure and a conductive step structure, the number of the stacking structures in the plurality of stacking substructures being different, and the conductive step structure in one of the stacking substructures being electrically connected to the conductive line in one of the line stacking structures.

[0012] In some embodiments, the isolation wall structure includes a first isolation wall extending along the first horizontal direction and a plurality of second isolation walls extending along the second horizontal direction, wherein the plurality of second isolation walls are located on the same side of the first isolation wall and are each connected to the first isolation wall; the line stacking structure is located on the side of the plurality of second isolation walls away from the first isolation wall.

[0013] In some embodiments, each of the first isolation walls is used to define two columns of areas located on both sides thereof.

[0014] In some embodiments, the method further includes: a plurality of isolation layers respectively located in the plurality of regions, each of the isolation layers surrounding a sidewall of a corresponding conductive step structure.

[0015] In some embodiments, the conductive lines and the isolation lines in the line stacking structures are both ring-shaped, and each of the line stacking structures is used to define two columns of regions located on both sides thereof.

[0016] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: first, before forming the conductive step structure, the stacking structure is first divided into a plurality of spaced-apart sub-stacking structures by a limiting structure. In this way, the sub-stacking structures to be etched are defined in advance, so that they can be completed by wet etching in the subsequent process of forming the conductive step structure. Moreover, since the reagents used in the limited wet etching of the limited structure will not flow arbitrarily, the precision and accuracy of the wet etching process are improved, thereby improving the reliability of the formed conductive step structure. On the other hand, before forming the conductive step structure, a conductive line is also formed, and the conductive line can be used as a local bit line to realize signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figures 1 to 10 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] As known from the background art, currently, dry etching is usually used to form contact holes. However, with the miniaturization of semiconductor structures, the aspect ratio of the contact holes increases, and dry etching cannot effectively complete the formation of contact holes.

[0020] In the embodiment of the present disclosure, before forming the conductive step structure, the stacking structure is first divided into a plurality of spaced-apart sub-stacking structures by means of a limiting structure. In this way, the sub-stacking structures to be etched are defined in advance so that they can be completed by wet etching in the subsequent process of forming the conductive step structure. Moreover, since the reagents used in the limited wet etching of the limited structure will not flow arbitrarily, the precision and accuracy of the wet etching process are improved, thereby improving the reliability of the formed conductive step structure. On the other hand, before forming the conductive step structure, a conductive line is also formed, and the conductive line can be used as a local bit line to realize signal transmission.

[0021] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are used solely to distinguish between different objects and should not be understood to indicate or imply relative importance or to implicitly specify the quantity, specific order, or primary and secondary relationship of the technical features indicated. In the description of the embodiments of the present disclosure, "plurality" means more than two, unless otherwise specifically defined.

[0022] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0023] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0024] In the description of the embodiments of the present disclosure, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0025] In the description of the embodiments of the present disclosure, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the embodiments of the present disclosure.

[0026] In the description of the embodiments of the present disclosure, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and they can refer to internal connectivity between two components or interaction between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present disclosure based on specific circumstances.

[0027] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of ​​the layers are exaggerated for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of the other component, or a third component can be present between the two components. Conversely, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0028] In the description of the embodiments of the present disclosure, when a component is referred to as "including" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component can be present between them. In addition, when a component such as a layer, film, region, or plate is "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located between them.

[0029] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0030] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0031] refer to Figures 1 to 10 , Figures 1 to 10 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0032] In some embodiments, a method for manufacturing a semiconductor structure may include providing a substrate 100 , wherein the substrate 100 includes a substrate 110 and a stacked structure 120 located on the substrate 110 , wherein the stacked structure 120 includes a first layer 130 and a second layer 140 alternately stacked, and the second layer 140 is a dielectric layer.

[0033] A method for manufacturing a semiconductor structure may include: forming a limiting structure 101 to limit a plurality of sub-stack structures 102 arranged at intervals along a first horizontal direction X in a stack structure 120, wherein the limiting structure 101 includes alternatingly stacked conductive lines 111 and isolation lines 121, and an isolation wall structure 131, wherein the conductive lines 111 are arranged on the same layer as the first layer 130, and the isolation lines 121 are arranged on the same layer as the second layer 140, and the isolation wall structure 131 penetrates the stack structure 120 and contacts the substrate 110, and each sub-stack structure 102 is surrounded by the conductive lines 111, the isolation lines 121, and the isolation wall structure 131.

[0034] The method for manufacturing the semiconductor structure may include: performing wet etching on the plurality of sub-stack structures 102 to form a plurality of contact holes 103 with different depths.

[0035] The method for manufacturing the semiconductor structure may include: forming a plurality of conductive step structures 104 in the plurality of contact holes 103 , wherein each conductive step structure 104 is electrically connected to a corresponding conductive line 111 .

[0036] In the embodiment of the present disclosure, before forming the conductive step structure 104, the stacking structure 120 is first divided into a plurality of spaced-apart sub-stacking structures 102 by means of a limiting structure 101. In this way, the sub-stacking structure 102 to be etched is defined in advance so that it can be completed by wet etching in the subsequent process of forming the conductive step structure 104. Moreover, since the reagents used in the limited wet etching of the limiting structure 101 will not flow arbitrarily, the precision and accuracy of the wet etching process are improved, thereby improving the reliability of the formed conductive step structure 104. On the other hand, before forming the conductive step structure 104, a conductive line 111 is also formed, and the conductive line 111 can realize the transmission of electrical signals together with the conductive step structure 104.

[0037] refer to Figure 1 , providing a substrate, and forming a stacked structure on the substrate.

[0038] In some embodiments, before forming the stacking structure 120, a barrier layer 150 is formed on the surface of the substrate 110. The barrier layer 150 separates the substrate 110 and the stacking structure 120, thereby preventing the substrate 110 from being damaged during the subsequent etching of the stacking structure 120, thereby improving the reliability of the formed semiconductor structure.

[0039] In some embodiments, the material of substrate 110 may include a semiconductor material, such as, but not limited to, silicon, and may also include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, gallium arsenic phosphide, gallium indium phosphide, gallium in arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 110 may also be a silicon-on-insulator structure.

[0040] The material of the first layer 130 of the stacked structure 120 can be the same as that of the substrate 110 , both of which can be semiconductor materials. The material of the second layer 140 can be silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0041] In some embodiments, a mask layer 105 is formed on the top surface of the stack structure 120 . The mask layer 105 has a first opening 115 therein. The stack structure 120 can be subsequently etched using the mask layer 105 as a mask.

[0042] refer to Figure 2, etching the stacked structure.

[0043] In some embodiments, the stacked structure 120 is etched to form a first vertical opening 106, which includes a first vertical sub-opening 116 extending along a first horizontal direction X and a plurality of second vertical sub-openings 126 extending along a second horizontal direction Y. The plurality of second vertical sub-openings 126 are located on the same side of the first vertical sub-opening 116 and are each connected to the first vertical sub-opening 116.

[0044] In some embodiments, the first vertical opening 106 can etch all the stacked structures 120 to expose the surface of the substrate 110. An insulating layer is formed before the stacked structure 120 is formed. The first vertical opening 106 can etch all the stacked structures 120 to expose the surface of the insulating layer. Etching all the stacked structures 120 can provide a process basis for the subsequent formation of contact holes 103 of different depths.

[0045] In some embodiments, a plurality of third vertical sub-openings 136 extending along the second horizontal direction Y are also formed during the process of forming the first vertical opening 106. The third vertical sub-openings 136 can be located on another layer of the first vertical sub-opening 116 away from the second vertical sub-opening 126, and the third vertical sub-openings 136 and the second vertical sub-openings 126 are arranged in the same row along the second horizontal direction Y. The first vertical sub-opening 116, the second vertical sub-opening 126 and the third vertical sub-opening 136 constitute a plurality of interconnected H-shaped portions.

[0046] After the first vertical opening 106 is formed, the mask layer 105 may be removed.

[0047] refer to Figures 3 to 7 , forming a separation wall structure, wherein, Figure 3 For an embodiment of the present disclosure Figure 2 The initial isolation wall structure is formed on the basis of Figure 4 For an embodiment of the present disclosure Figure 3 A second vertical opening is formed on the basis of Figure 5 For an embodiment of the present disclosure Figure 4 The limiting structure is formed on the basis of Figure 6 A top view provided in accordance with an embodiment of the present disclosure is shown. Figure 7 For an embodiment of the present disclosure Figure 5 A separation wall structure is formed on the basis of

[0048] Combined with reference Figure 2 and references Figure 3In some embodiments, the initial isolation wall structure 1310 includes a first isolation wall 1311 located in the first vertical sub-opening 116 and a plurality of second isolation walls 1312 located in the plurality of second vertical sub-openings 126. The first isolation wall 1311 and the second isolation wall 1312 constitute the three side walls of the defining structure 101, thereby providing a process basis for the subsequent formation of the sub-stack structure 102.

[0049] In some embodiments, the first vertical opening 106 also includes a third vertical sub-opening 136, and the initial isolation wall structure 1310 also includes a third isolation wall 1313. The third isolation wall 1313 and the first isolation wall 1311 can also form three side walls of the defining structure 101, and the defining structure 101 formed by the third isolation wall 1313 and the first isolation wall 1311 and the defining structure 101 formed by the second isolation wall 1312 and the first isolation wall 1311 share the first isolation wall 1311. Therefore, more isolation wall structures can be formed in the same process steps, thereby improving the efficiency of the semiconductor structure manufacturing method.

[0050] refer to Figures 4 to 6 In some embodiments, a second vertical opening 107 is formed on a side of the plurality of second isolation walls 1312 away from the first isolation wall 1311; the second layer 140 is laterally etched from the second vertical opening 107 to form a first horizontal opening (not shown), which exposes the sidewalls of the plurality of second isolation walls 1312; an isolation line 121 is formed in the first horizontal opening; the first layer 130 is laterally etched along the second vertical opening 107 to form a second horizontal opening (not shown), which exposes the sidewalls of the plurality of second isolation walls 1312; and a conductive line 111 is formed in the second horizontal opening. The formation of the second vertical opening 107 provides a process foundation for etching the first and second horizontal openings, which in turn provides a process foundation for forming the isolation line 121 and the conductive line 111. By cooperating with the isolation line 121, the conductive line 111, the first isolation wall 1311 and the second isolation wall 1312, the stacking structure 120 can be enclosed into a plurality of spaced-apart sub-stack structures 102, so that the etching reagent will not flow to other areas during the subsequent etching of the sub-stack structure 102, thereby achieving the controllable size of the contact hole 103 formed by etching.

[0051] In some embodiments, a third isolation wall 1313 is also formed. In the process of forming the first horizontal opening, a portion of the second layer 140 is also etched along the direction of the second vertical opening 107 toward the third isolation wall 1313 to form a third horizontal opening (not shown). The third horizontal opening exposes the side wall of the third isolation wall 1313, and an isolation line 121 is also formed in the third horizontal opening. In the process of forming the second horizontal opening, a portion of the first layer 130 is also etched along the direction of the second vertical opening 107 toward the third isolation wall 1313 to form a fourth horizontal opening (not shown). The fourth horizontal opening exposes the side wall of the third isolation wall 1313, and in the process of forming the conductive line 111, a conductive line 111 is also formed in the fourth horizontal opening.

[0052] The stacking structure 120 can also be divided into a plurality of spaced-apart sub-stack structures 102 by combining the isolation line 121, the conductive line 111, the first isolation wall 1311 and the third isolation wall 1313, so that more isolation wall structures can be formed in the same process steps, thereby improving the efficiency of the semiconductor structure manufacturing method.

[0053] It can be understood that the first horizontal opening, the second horizontal opening, the third horizontal opening and the fourth horizontal opening are not shown in the figure. The position of the isolation line 121 in the figure corresponds to the position of the first horizontal opening or the third horizontal opening, and the position of the conductive line 111 in the figure corresponds to the position of the second horizontal opening or the fourth horizontal opening.

[0054] In some embodiments, during the process of forming the isolation line 121, part of the material of the isolation line 121 will also fill the second vertical opening 107. Therefore, before forming the second horizontal opening, the isolation line 121 located in the second vertical opening 107 will also be etched so that the isolation line 121 is only located in the first horizontal opening.

[0055] In some embodiments, the material of the isolation line 121 is the same as the material of the initial isolation wall structure 1310. By setting the isolation line 121 to be the same as the material of the initial isolation wall structure 1310, the number of materials required in the semiconductor structure manufacturing method can be reduced, and the adhesion of the isolation line 121 material can be facilitated, thereby improving the reliability of the formed isolation line 121.

[0056] In some embodiments, during the process of forming the conductive line 111, part of the material of the conductive line 111 will also fill the second vertical opening 107. Therefore, after the conductive line 111 is formed, the conductive line 111 located in the second vertical opening 107 will be etched so that the conductive line 111 is only located in the second horizontal opening.

[0057] In some embodiments, the conductive line 111 may be made of a conductive material such as metal (eg, tungsten) or a metal semiconductor compound (eg, titanium nitride).

[0058] In some embodiments, after the conductive line 111 is formed, a fourth isolation wall 141 is further formed, and the fourth isolation wall 141 completely fills the second vertical opening 107 .

[0059] refer to Figure 7 , a portion of the initial isolation wall structure 1310 is etched to form an isolation wall structure 131, wherein the initial isolation wall structure 1310 on the top surface of the second layer can be removed by grinding, and the remaining initial isolation wall structure 1310 serves as the isolation wall structure 131.

[0060] refer to Figure 8 and Figure 9 , forming a contact hole, wherein, Figure 8 For an embodiment of the present disclosure Figure 7 An isolation layer and contact holes are formed on the basis of Figure 9 For the Figure 8 Cross-section view in the MM1 direction.

[0061] In some embodiments, wet etching is performed on the plurality of sub-stack structures 102 to form a plurality of contact holes 103 having different depths. This includes removing a plurality of first layers 130 and a plurality of second layers 140 in the plurality of sub-stack structures 102 using wet etching to form a plurality of initial holes having different depths, each initial hole exposing the top surface of one of the first layers 130 serving as the target layer. By forming the plurality of initial holes having different depths, it is possible to control the contact between the conductive step structure 104 and different conductive lines 111 during the subsequent formation of the conductive step structure 104, thereby enabling signal transmission between different layers.

[0062] In some embodiments, the method for forming a plurality of initial holes having different depths includes: forming a plurality of second mask layers (not shown) arranged along a first horizontal direction X, with at least one sub-stack structure 102 spaced between two adjacent second mask layers, and etching the exposed m first layers 130 and m second layers 140 of the sub-stack structure 102 using the second mask layer as a mask; removing the second mask layer; forming a third mask layer arranged along a second horizontal direction Y, with at least one sub-stack structure 102 spaced between two adjacent third mask layers, and using the third mask layer as a mask. The mask layer is used as a mask to etch the n first layers 130 and the n second layers 140 of the sub-stacked structure 102 exposed; the third mask layer is removed; a fourth mask layer is formed, the fourth mask layer covers the multiple sub-stacked structures 102 arranged continuously along the first horizontal direction X and the second horizontal direction Y, and the i first layers 130 and the i second layers 140 of the exposed sub-stacked structure 102 are etched using the fourth mask layer as a mask; the fourth mask layer is removed; and each sub-stacked structure 102 is etched to form a plurality of initial holes with different depths, where m, n and i are positive integers.

[0063] In other words, the sub-stack structure 102 of the initial thickness can be etched by at least three mask etchings. Since the sub-stack structure 102 at some positions is repeatedly etched during the three mask etching processes, and sub-stack structures 102 with different thicknesses are formed in advance during the last whole-surface etching process, in the subsequent etching process, it is only necessary to control the etching thickness of different sub-stack structures 102 to be the same, and finally initial holes with different depths are formed.

[0064] In some embodiments, the sub-stack structures 102 arranged along the first horizontal direction X are respectively defined as the first row of sub-stack structures, the second row of sub-stack structures, the third row of sub-stack structures to the sixth row of sub-stack structures, and the sub-stack structures 102 arranged along the second horizontal direction Y are defined as the first column of sub-stack structures, the second column of sub-stack structures to the sixth column of sub-stack structures. The formed second mask layer can cover the first row of sub-stack structures, the third row of sub-stack structures, and the fifth row of sub-stack structures. Then, an etching process is performed to etch the m first layers 130 and the m second layers 140 of the exposed sub-stack structures 102. Then, the formed third mask layer can cover The first column of sub-stack structures, the third column of sub-stack structures and the fifth column of sub-stack structures are covered, and then the n first layers 130 and the n second layers 140 of the exposed sub-stack structures 102 are etched. Finally, the formed fourth mask layer can cover the fourth row of sub-stack structures to the sixth row of sub-stack structures, and then the i first layers 130 and the i second layers 140 of the exposed sub-stack structures 102 are etched. In this way, since different etching processes will etch the same sub-stack structure 102, remaining sub-stack structures 102 with different heights will be formed, and finally, a plurality of contact holes 103 with different depths will be formed during the wet etching process.

[0065] It can be understood that during the wet etching process, the first layer 130 of the remaining sub-stack structure 102 is used as an etch stop layer. Therefore, the first layer 130 of the remaining sub-stack structure 102 is used as a target layer.

[0066] It can be understood that, during the wet etching process, the first layer 130 serves as an etch stop layer for the second layer 140 thereon, and the second layer 140 serves as an etch stop layer for the first layer 130 thereon.

[0067] In some embodiments, an isolation layer 108 is formed on the sidewalls of the multiple initial holes; wet etching is used to remove the target layer exposed by the multiple initial holes to expose the conductive line 111 arranged in the same layer as the target layer, and the space in each initial hole not filled by the isolation layer 108 and the space left after the target layer is removed together form a contact hole 103.

[0068] By forming an isolation layer 108 on the side wall of the initial hole, the insulation between the conductive step structure 104 and the conductive line 111 can be improved when the conductive step structure 104 is subsequently formed, thereby avoiding electrical connection between the conductive step structure 104 and the conductive line 111 that does not need to be electrically connected. By forming the isolation layer 108, damage to the limiting structure 101 can also be avoided during the subsequent etching of the target layer, thereby improving the reliability of the formed semiconductor structure.

[0069] After forming the isolation layer 108 , the conductive line 111 is exposed by removing the target layer so that the subsequently formed conductive step can contact and connect with the conductive line 111 , thereby completing signal transmission through the contact between the conductive step and the conductive line 111 .

[0070] In some embodiments, the material of the isolation layer 108 is the same as the material of the second layer 140. By setting the material of the isolation layer 108 to be the same as the material of the second layer 140, the types of materials in the manufacturing method of the semiconductor structure can also be reduced. When there is etching residue in the etched sub-stack structure 102, it is convenient for the isolation layer 108 to grow. At the same time, the isolation layer 108 can also cover the entire side wall to prevent the etching residue from affecting the subsequently formed conductive step structure 104.

[0071] It should be noted that Figure 9 The cross-sectional view shown in the figure is to illustrate that when forming the contact hole 103, a plurality of contact holes 103 with different depths can be formed by controlling the process. Figure 8 The stereograms shown do not correspond exactly. Figure 9 Just along Figure 8 Schematic cross-sectional view in the MM1 direction.

[0072] refer to Figure 10 , forming a conductive step structure.

[0073] In some embodiments, the conductive line 111 serves as a signal transmission line, and the semiconductor structure further includes a plurality of common bit lines (or common word lines) stacked vertically. The plurality of common bit lines (or common word lines) are respectively coupled to the plurality of vertically stacked signal transmission lines, so that the common word lines (or common bit lines) can exchange electrical signals with peripheral circuits through corresponding signal transmission lines and conductive step structures. A selection transistor can also be set between the signal transmission line and the common bit line (or common word line). By controlling whether the selection transistor is turned on, whether the corresponding common bit line (or common word line) and the signal transmission line are turned on can be selected, thereby selecting the corresponding common bit line (or common word line).

[0074] In the embodiment of the present disclosure, before forming the conductive step structure 104, the stacking structure 120 is first divided into a plurality of spaced-apart sub-stack structures 102 by means of a limiting structure 101. In this way, the sub-stack structures 102 to be etched are defined in advance so that they can be completed by wet etching in the subsequent process of forming the conductive step structure 104. Moreover, since the reagents used in the limited wet etching of the limiting structure 101 will not flow arbitrarily, the precision and accuracy of the wet etching process are improved, thereby improving the reliability of the formed conductive step structure 104. On the other hand, before forming the conductive step structure 104, a conductive line 111 is also formed, and the conductive line 111 can be used as a local bit line to realize signal transmission.

[0075] Another embodiment of the present disclosure further provides a semiconductor structure, which can be formed by the manufacturing method of the semiconductor structure in some or all of the above-mentioned embodiments. The semiconductor structure provided by one embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the parts that are the same or corresponding to those in the above-mentioned embodiments can refer to the above-mentioned embodiments and will not be repeated below.

[0076] refer to Figure 10 In some embodiments, the semiconductor structure may include: a substrate 110 .

[0077] The semiconductor structure may further include: a defining structure 101 located on the substrate 110, defining a plurality of regions spaced apart along the first horizontal direction X on the substrate 110, the defining structure 101 including a wire stacking structure 151 and an isolation wall structure 131, the wire stacking structure 151 including alternatingly stacked conductive wires 111 and isolation wires 121, the bottom surface of the isolation wall structure 131 in contact with the substrate 110, and each region being surrounded by the wire stacking structure 151 and the isolation wall structure 131.

[0078] The semiconductor structure may also include: multiple stacked substructures, respectively located in multiple regions, at least two stacked substructures include at least one stacked structure 120 and a conductive step structure 104, the number of stacked structures 120 in the multiple stacked substructures is different, and the conductive step structure 104 in a stacked substructure is electrically connected to the conductive line 111 in a line stacking structure 151.

[0079] By defining the structure 101 to enclose a space for accommodating the conductive step structure 104, the formation of the conductive step structure 104 is facilitated, and the reliability of isolation between different conductive step structures 104 can be improved. At the same time, a conductive step structure 104 is electrically connected to a conductive line 111 to achieve signal transmission.

[0080] In some embodiments, the isolation wall structure 131 includes a first isolation wall 1311 extending along a first horizontal direction X and a plurality of second isolation walls 1312 extending along a second horizontal direction Y. The plurality of second isolation walls 1312 are located on the same side of the first isolation wall 1311 and are each connected to the first isolation wall 1311. In other words, the first isolation wall 1311 and the second isolation wall 1312 constitute the three sidewalls defining the structure 101, and the line stacking structure 151 constitutes the last sidewall of the isolation wall structure 131. While isolating the different conductive step structures 104 through the isolation wall structure 131, the conductive step structures 104 are electrically connected to the conductive lines 111, thereby enabling signal transmission through the conductive step structures 104.

[0081] It can be understood that since the isolation wall structure 131 includes the first isolation wall 1311 extending in the first horizontal direction X, the isolation wall structure 131 separates the conductive step structure 104 along the second horizontal direction Y. Therefore, only one row of conductive step structures 104 arranged along the first horizontal direction X is provided on one side of a conductive line 111 along the second horizontal direction Y.

[0082] In some embodiments, each first isolation wall 1311 is used to define two columns of regions located on either side thereof. Furthermore, a second isolation wall 1312 is located on one side of the first isolation wall 1311, and a third isolation wall 1313 is located on the other side of the second isolation wall 1312. A first isolation wall 1311, together with the second isolation wall 1312 and the third isolation wall 1313, forms a two-sided defining structure 101. Using a first isolation wall 1311 to define the regions located on either side thereof can improve the efficiency and integration of the semiconductor structure manufacturing method.

[0083] In some embodiments, the semiconductor structure may further include: a plurality of isolation layers 108, respectively located in the plurality of regions, each isolation layer 108 surrounding the sidewall of a corresponding conductive step structure 104. The isolation layers 108 further separate the conductive step structures 104. Furthermore, the provision of the isolation layers 108 may prevent the conductive step structures 104 from being electrically connected to multiple conductive lines 111 simultaneously, thereby improving the reliability of the semiconductor structure.

[0084] In some embodiments, the conductive lines 111 and isolation lines 121 in the wire stacking structures 151 are both ring-shaped, and each wire stacking structure 151 is used to define two columns of regions located on either side thereof. In other words, the ring-shaped wire stacking structures 151 simultaneously serve as the sidewalls of two defining structures 101, which can also improve the efficiency and integration of the semiconductor structure manufacturing method.

[0085] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a stacked structure located on the substrate, the stacked structure comprising a first layer and a second layer alternately stacked, the second layer being a dielectric layer; forming a defining structure to define a plurality of sub-stack structures spaced apart along a first horizontal direction in the stack structure, the defining structure comprising alternating conductive lines and isolation lines, and an isolation wall structure, wherein the conductive lines are disposed in the same layer as the first layer, the isolation lines are disposed in the same layer as the second layer, and the isolation wall structure penetrates the stack structure and contacts the substrate, and each sub-stack structure is surrounded by the conductive lines, the isolation lines, and the isolation wall structure; Processing the plurality of sub-stack structures by wet etching to form a plurality of contact holes with different depths; A plurality of conductive step structures are formed in the plurality of contact holes, and one of the conductive step structures is electrically connected to one of the conductive lines.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Forming the defining structure includes: etching the stacked structure to form a first vertical opening, the first vertical opening including a first vertical sub-opening extending along the first horizontal direction and a plurality of second vertical sub-openings extending along a second horizontal direction, the plurality of second vertical sub-openings being located on the same side of the first vertical sub-opening and each communicating with the first vertical sub-opening; forming the isolation wall structure in the first vertical opening, the isolation wall structure comprising a first isolation wall located in the first vertical sub-opening and a plurality of second isolation walls located in the plurality of second vertical sub-openings; forming a second vertical opening on one side of the plurality of second isolation walls away from the first isolation wall; etching the second layer laterally from the second vertical opening to form a first horizontal opening, wherein the first horizontal opening exposes sidewalls of the plurality of second isolation walls; forming the isolation line in the first horizontal opening; etching the first layer laterally along the second vertical opening to form a second horizontal opening, wherein the second horizontal opening exposes sidewalls of the plurality of second isolation walls; The conductive line is formed in the second horizontal opening.

3. The method for manufacturing a semiconductor structure according to claim 1 or 2, wherein: The plurality of sub-stack structures are processed by wet etching to form a plurality of contact holes with different depths, comprising: removing the plurality of first layers and the plurality of second layers in the plurality of sub-stack structures by wet etching to form a plurality of initial holes with different depths, each of the initial holes exposing a top surface of one of the first layers serving as a target layer; forming an isolation layer on sidewalls of the plurality of initial holes; The target layer exposed by the multiple initial holes is removed by wet etching to expose the conductive wires arranged in the same layer as the target layer. The space in each initial hole not filled by the isolation layer and the space left after the target layer is removed together form a contact hole.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The material of the isolation layer is the same as that of the second layer.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of the isolation line is the same as that of the isolation wall structure.

6. A semiconductor structure, characterized in that include: substrate; a defining structure located on the substrate, defining a plurality of regions spaced apart along a first horizontal direction on the substrate, the defining structure comprising a wire stacking structure and an isolation wall structure, the wire stacking structure comprising alternatingly stacked conductive wires and isolation wires, the bottom surface of the isolation wall structure being in contact with the substrate, and each of the regions being surrounded by the wire stacking structure and the isolation wall structure; Multiple stacked substructures are respectively located in the multiple areas, at least two of the stacked substructures include at least one stacking structure and a conductive step structure, the number of the stacking structures in the multiple stacked substructures is different, and the conductive step structure in one of the stacked substructures is electrically connected to the conductive line in one of the line stacking structures.

7. The semiconductor structure according to claim 6, wherein: The isolation wall structure includes a first isolation wall extending along the first horizontal direction and a plurality of second isolation walls extending along a second horizontal direction, wherein the plurality of second isolation walls are located on the same side of the first isolation wall and are each connected to the first isolation wall; The line stack structure is located on a side of the plurality of second isolation walls away from the first isolation wall.

8. The semiconductor structure according to claim 7, wherein: Each of the first isolation walls is used to define two columns of areas located on both sides thereof.

9. The semiconductor structure according to claim 6, wherein: Also includes: A plurality of isolation layers are respectively located in the plurality of regions, and each of the isolation layers surrounds a sidewall of a corresponding conductive step structure.

10. The semiconductor structure according to claim 6, wherein: The conductive lines and the isolation lines in the line stacking structure are both ring-shaped, and each line stacking structure is used to define two columns of regions located on both sides thereof.

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