Multi-DBC packaging structure and packaging method of WLCSP chip

Abstract

This invention discloses a multi-DBC packaging structure and packaging method for WLCSP chips, belonging to the field of chip packaging technology. It solves the problem of long heat conduction paths and high overall thermal resistance in existing heat dissipation packaging structures, which limit the overall heat dissipation capacity of the chip. The method includes depositing dielectric layers on the wafer within the wafer disk, mounting metal bumps in an array on the wafer surface pads to create a low thermal resistance DBC packaging architecture; using DBC flip-chip technology to flip-chip interconnect the WLCSP chip and the DBC packaging architecture; placing the packaged individual WLCSP chip in a molding machine mold, and using a trimming machine to remove excess structural copper to form the finished WLCSP chip. In this invention, the flip-chip interconnection of the WLCSP chip and the DBC packaging architecture based on the DBC flip-chip technology ensures more effective heat conduction from the chip to the outside. Utilizing the high thermal conductivity and high insulation characteristics of the DBC packaging frame, high-reliability chip packaging is achieved, and chip stability is improved.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically relating to the multi-DBC packaging structure and packaging method of WLCSP chips. Background Technology

[0002] With the rapid development of microelectronics technology, the integration and power density of chips are constantly increasing, placing higher demands on the heat dissipation performance, reliability, and flexibility of chip packaging. However, traditional chip packaging structures are gradually revealing their limitations in terms of heat dissipation efficiency and application adaptability, making it difficult to meet the needs of modern high-power, high-frequency, and high-voltage systems.

[0003] Traditional chip packaging structures mainly use a single-layer DBC (direct copper bonding) substrate. Heat dissipation and electrical connection are achieved by mounting the chip on the single-layer DBC substrate. However, this single-layer structure has the following problems: limited heat dissipation efficiency, difficulty in withstanding large currents and heat, and easy to cause packaging failure.

[0004] Chinese patent CN119008553B discloses a chip heat dissipation packaging structure and a method for fabricating the chip heat dissipation packaging structure. The chip heat dissipation packaging structure includes a substrate, a packaged chip, a thermally conductive material layer, and a first heat dissipation cap. The packaged chip is mounted on the substrate. The thermally conductive material layer is disposed on the side of the packaged chip away from the substrate. The first heat dissipation cap is disposed on the substrate and covers the packaged chip, with at least a portion of the first heat dissipation cap located on the side of the thermally conductive material layer away from the substrate. Multiple first heat dissipation bumps are provided on the side of the first heat dissipation cap closest to the substrate, and these bumps are all connected to the surface of the packaged chip facing away from the substrate. The thermally conductive material layer is connected to the first heat dissipation cap. However, existing heat dissipation packaging structures form a heat conduction path through the cooperation of the thermally conductive material layer and the heat dissipation cap bumps. This results in a long heat conduction path and high overall thermal resistance, further limiting the overall heat dissipation capacity of the chip. To address these issues, we propose a multi-DBC packaging structure and packaging method for WLCSP (Wafer-Level Chip Scale Package) chips. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing a multi-DBC packaging structure and packaging method for WLCSP chips. This solves the problem that existing heat dissipation packaging structures form a long heat conduction path through the cooperation of a thermally conductive material layer and heat sink bumps, resulting in a large overall thermal resistance and further limiting the overall heat dissipation capacity of the chip.

[0006] This invention is implemented as follows: a multi-DBC packaging method for WLCSP chips, the method comprising:

[0007] The wafer disk is treated with deionized water and ultrasonic cleaning to remove particulate contaminants from the wafer disk surface. Dielectric layer deposition is performed on the wafers inside the wafer disk, followed by UBM layer (bottom metallization layer) deposition. Metal bumps are installed on the wafer surface in an array of pads to obtain the pre-treated WLCSP chip.

[0008] Based on the WLCSP chip type, the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer is preset. The thermally conductive ceramic layer and the thermally conductive copper layer are alternately deposited on the packaging substrate. Vertical through holes are made in the DBC packaging architecture by laser drilling technology to create a DBC packaging architecture with a low thermal resistance path.

[0009] The pre-processed WLCSP chip is inverted, and the WLCSP chip and DBC packaging architecture are flip-chip interconnected using the DBC flip-chip process. Solder paste is printed on the surface of the packaging substrate, and the heat dissipation frame is fastened to the outside of the packaging substrate. The WLCSP chip is completed by welding in a vacuum eutectic furnace. The wafer-level WLCSP chip is cut into individual WLCSP chips using laser cutting.

[0010] The packaged single WLCSP chip is placed in the mold of the molding machine, and high-temperature resistant thermally conductive material is injected into the mold. After the mold is opened and cooled, the excess structural copper is removed by the trimming machine to form the finished WLCSP chip. The finished WLCSP chip is subjected to electrical testing, and qualified finished WLCSP chips are selected.

[0011] Preferably, the method for mounting metal bumps in an array of pads on the wafer surface includes:

[0012] The type of metal bump is determined based on the wafer type. The metal bumps include tin-lead bumps, lead-free bumps, and copper pillar bumps. The dimensional deviation of the metal bumps is detected by a laser thickness gauge, and the surface defect rate of the metal bumps is analyzed by scanning electron microscopy.

[0013] Oxygen plasma is used to perform plasma cleaning on the pads on the wafer surface. A robotic arm picks up metal bumps from the bump conveyor belt and aligns the metal bumps with the pads using a CCD camera (a digital imaging device based on a charge-coupled device image sensor).

[0014] The laser bonding machine bonds metal bumps to pads according to the material type of the metal bumps, evaluates the reliability of the metal bump interconnect based on the modal synthesis method, and adjusts the thickness of the nano silver paste of the metal bumps based on the reliability evaluation results.

[0015] Preferably, the method for reliability assessment of metal bump interconnects based on modal synthesis includes:

[0016] Obtain the wafer surface pad size parameters and bump distribution coordinate parameters. The 3D visualization tool constructs a 3D model of the bumps based on the wafer surface pad size parameters and bump distribution coordinate parameters. The 3D model of the bumps includes the wafer, pads and metal bumps.

[0017] Accelerated thermal cycling tests were conducted on simulated wafers to accelerate the fatigue failure of metal bumps. The fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness of the metal bumps were statistically analyzed. Based on the fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness of the bumps, index failure curves were obtained. The indexes were normalized to obtain normalized failure curves.

[0018] Modal analysis is performed on the normalized failure curve based on the modal synthesis method. Modal analysis is performed on the substructure associated with the metal bump to obtain the substructure modal failure probability. The substructure modal failure probabilities are linearly weighted and combined to obtain the comprehensive failure probability of the metal bump.

[0019] Determine whether the overall failure probability of the metal bump exceeds a preset probability threshold. If the overall failure probability of the metal bump exceeds the preset probability threshold, locate the metal bump as a failed bump.

[0020] The failure bumps in the 3D model of the bumps are obtained and marked. The thickness of the metal bump nano-silver paste is adjusted based on the comprehensive failure probability corresponding to the failure bumps, and the marked failure bumps and the thickness of the metal bump nano-silver paste are fed back.

[0021] The adjusted thickness of the metal bump nano-silver paste is calculated using the following formula:

[0022]

[0023]

[0024]

[0025] in, This indicates the adjusted thickness of the nano-silver paste used to create the metal bumps. The initial thickness of the bumped nano-silver paste. These are the overall failure probability and the preset probability threshold, respectively. Sub-modes Substructure weighting coefficients and substructure modal failure probabilities. They represent sub-modes respectively. The fatigue life and shape parameters, with the shape parameter being a key parameter describing the morphological characteristics of the probability distribution. For sub-mode Quantity, This represents the sensitivity coefficient.

[0026] Preferably, the method for presetting the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer based on the WLCSP chip type includes:

[0027] Identify the WLCSP chip type, determine the chip junction temperature requirement, chip power consumption, and maximum ambient temperature based on the WLCSP chip type, and calculate the chip's maximum thermal resistance using the chip junction temperature requirement, chip power consumption, and maximum ambient temperature.

[0028] Using the chip's maximum thermal resistance as a constraint, at least one combination of thickness ratios for thermally conductive ceramic layers and thermally conductive copper layers is simulated based on ANSYS Icepak (a high-precision professional simulation software for electronic thermal management analysis).

[0029] Load at least one set of thickness ratio combinations, preset the maximum skin depth, determine the thickness range of the thermally conductive copper layer based on the maximum skin depth, and filter the thickness ratio combinations that meet the maximum skin depth based on the thickness range of the thermally conductive copper layer.

[0030] A DBC thermal resistance model is established based on the maximum thermal resistance, coefficient of thermal expansion, and maximum current carrying capacity. The overall thermal resistance of the DBC thermal resistance model is calculated using the thickness ratio combination that meets the maximum skin depth as variables. The thickness ratio combination with the minimum overall thermal resistance is taken as the optimal thickness ratio combination.

[0031] Preferably, the method for fabricating a low thermal resistance path DBC packaging architecture includes:

[0032] Obtain the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer, cut the packaging substrate to the target size, and polish the surface of the packaging substrate.

[0033] A thermally conductive copper layer and a thermally conductive ceramic layer are deposited on a substrate using magnetron sputtering. The thermally conductive copper layer and the thermally conductive ceramic layer are then bonded alternately under high temperature and high pressure to fabricate the target circuit pattern on the thermally conductive copper layer.

[0034] Vertical vias are fabricated within the DBC packaging architecture using laser drilling technology, and temperature sensors are embedded within these vias to create a DBC packaging architecture with a low thermal resistance path.

[0035] Preferably, the method for flip-chip interconnection of WLCSP chips and DBC package architecture using DBC flip-chip technology includes:

[0036] A robotic arm is used to grip the DBC package holder, the WLCSP chip is inverted, and a CCD camera is used to align the WLCSP chip and the DBC package architecture.

[0037] The thermally conductive copper layer on the top of the DBC package holder was micro-etched, and nano silver paste was printed on the micro-etched thermally conductive copper layer on the top of the DBC package holder.

[0038] The aligned WLCSP chip and DBC package architecture are flip-chip aligned and thermo-bonded at 280-340℃ and 3.5MPa pressure. The thermo-bonded WLCSP chip and DBC package architecture are then reflow soldered to complete the flip-chip interconnect of the WLCSP chip and DBC package architecture.

[0039] Preferably, when printing nano-silver paste on the thermally conductive copper layer on the top of the micro-etched DBC package frame, the copper layer interconnection point corresponding to the failure bump in the thermally conductive copper layer on the top of the DBC package frame is identified, the marked failure bump and the thickness of the nano-silver paste on the metal bump are obtained, and the thickness of the nano-silver paste on the metal bump of the copper layer interconnection point is adjusted based on the marked failure bump.

[0040] Preferably, when performing electrical tests on the finished WLCSP chip, the test items include insulation test, electrostatic discharge test, leakage current test under drain-source voltage, switching test, reverse recovery time test, resistance over-limit test, and DC parameter test.

[0041] On the other hand, the present invention also provides a multi-DBC packaging structure for WLCSP chips, the multi-DBC packaging structure for WLCSP chips comprising:

[0042] The package includes a substrate, a DBC packaging architecture, and a heat dissipation frame. The substrate and the heat dissipation frame are soldered together using large pads. The DBC packaging architecture is bonded to the substrate. The WLCSP chip is bonded to the top of the DBC packaging architecture, and the chip electrodes are electrically connected to the bottom layer of the DBC packaging architecture through conductive vias.

[0043] Preferably, the DBC packaging architecture includes a thermally conductive copper layer and a thermally conductive ceramic layer, with at least one thermally conductive copper layer and a thermally conductive ceramic layer respectively, and the thermally conductive copper layer and the thermally conductive ceramic layer are alternately arranged. The DBC packaging architecture also includes at least one set of vertical through holes penetrating the thermally conductive copper layer and the thermally conductive ceramic layer, and bonding wires are arranged in the vertical through holes.

[0044] Compared with the prior art, the embodiments of this application have the following main advantages:

[0045] In this embodiment of the invention, by fabricating a DBC packaging architecture with a low thermal resistance path and performing flip-chip interconnection between the WLCSP chip and the DBC packaging architecture based on the DBC flip-chip process, the heat generated by the chip is more effectively conducted to the outside. By utilizing the high thermal conductivity and high insulation characteristics of the DBC packaging frame, a highly reliable chip package is achieved, reducing the chip's operating temperature and thus improving the chip's stability and reliability.

[0046] In this embodiment of the invention, considering that long-term thermal cycling can cause creep strain inside the solder joints, when the strain exceeds the fatigue limit of the interconnect bonding alloy, microcracks will appear on the metal bumps and gradually propagate, eventually leading to failure. To avoid chip damage caused by metal bump failure during flip-chip interconnection of WLCSP chips and DBC packaging architectures, this embodiment of the invention provides a method for reliability assessment of metal bump interconnects based on modal synthesis. Through high-temperature-low-temperature rapid cycling, fatigue failure of metal bumps can be accelerated, thereby obtaining long-term failure data in a short time. Furthermore, by performing modal analysis on the normalized failure curves, the failure probability of the substructure modes associated with the metal bumps can be obtained, thus accurately reflecting the failure risk of the bumps under different operating conditions. By identifying high-risk bumps early and adjusting the thickness of the nano-silver paste on the metal bumps, failure can be effectively avoided while improving the reliability consistency of batch products. Ultimately, this effectively reduces the failure rate of chip packaging.

[0047] This invention provides a method for presetting the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer based on the WLCSP chip type. By identifying the WLCSP chip type and determining its junction temperature requirements, power consumption, and maximum ambient temperature, the maximum thermal resistance requirement of the chip can be accurately calculated. This ensures that the thickness ratio design meets the heat dissipation requirements of a specific chip, avoiding performance degradation or damage due to insufficient heat dissipation. Furthermore, by establishing a DBC thermal resistance model and using the thickness ratio combination that conforms to the maximum skin depth as variables, the overall thermal resistance can be accurately calculated. This helps to find the optimal thickness ratio combination. By optimizing the thickness ratio, the heat dissipation performance of the package can be improved, thereby improving the chip's reliability and performance, and extending its lifespan.

[0048] In this embodiment of the invention, a method for fabricating a low thermal resistance path DBC packaging architecture is provided. The DBC packaging architecture adopts a low thermal resistance design and effectively solves the problems of interface peeling and solder joint fatigue caused by CTE mismatch (thermal expansion mismatch) in traditional packaging through the alternating stacked structure of copper and ceramic layers and the optimization of thickness ratio. Moreover, the DBC packaging architecture can flexibly adapt to different types of WLCSP chips. Attached Figure Description

[0049] Figure 1 This is a schematic diagram illustrating the implementation process of the multi-DBC packaging method for WLCSP chips provided by the present invention.

[0050] Figure 2 A schematic diagram of the finished WLCSP chip structure in an embodiment of the present invention is shown.

[0051] Figure 3 This is a three-dimensional structural diagram of the multi-DBC packaging structure of the WLCSP chip provided by the present invention.

[0052] Figure 4This is a top view of the multi-DBC packaging structure of the WLCSP chip provided by the present invention.

[0053] Figure 5 A schematic diagram of the module circuit of the DBC encapsulation architecture is shown.

[0054] Figure 6 This diagram illustrates the arrangement of the thermally conductive copper layer and thermally conductive ceramic layer in the DBC packaging architecture.

[0055] In the diagram: 1-molded housing, 2-packaging substrate, 3-heat dissipation frame, 4-DBC packaging architecture, 41-thermal conductive copper layer, 42-thermal conductive ceramic layer, 43-vertical through hole. Detailed Implementation

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0057] Existing heat dissipation packaging structures form heat conduction paths through the combination of thermally conductive material layers and heat sink bumps. These paths are lengthy and have high overall thermal resistance, further limiting the chip's overall heat dissipation capacity. To address these issues, we propose a multi-DBC packaging structure and method for WLCSP chips. The method includes depositing dielectric layers on the wafer within the wafer disk, followed by UBM layer deposition, and mounting metal bumps in an array on the wafer surface to obtain a pre-processed WLCSP chip. The thicknesses of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 are preset based on the WLCSP chip type. In this embodiment of the invention, a low thermal resistance path DBC packaging architecture 4 is fabricated by alternately depositing thermally conductive ceramic layers 42 and thermally conductive copper layers 41 on the packaging substrate 2. The WLCSP chip and the DBC packaging architecture 4 are flip-chip interconnected using a DBC flip-chip process. The wafer-level WLCSP chip is then diced into individual WLCSP chips using laser cutting. The packaged individual WLCSP chips are placed in a mold of a molding machine, and excess structural copper is removed using a trimming machine to form finished WLCSP chips. Electrical testing is performed on the finished WLCSP chips, and qualified finished WLCSP chips are selected. In this embodiment of the invention, by fabricating a low thermal resistance path DBC packaging architecture 4 and flip-chip interconnecting the WLCSP chip and the DBC packaging architecture 4 using a DBC flip-chip process, the heat generated by the chip is more effectively conducted to the outside. Utilizing the high thermal conductivity and high insulation characteristics of the DBC packaging frame, high-reliability chip packaging is achieved, reducing the chip's operating temperature and thus improving the chip's stability and reliability.

[0058] This invention provides a multi-DBC packaging method for WLCSP chips. Figure 1 This diagram illustrates the implementation flow of a multi-DBC packaging method for a WLCSP chip. The multi-DBC packaging method for the WLCSP chip specifically includes:

[0059] S10, the wafer disk is cleaned with deionized water and ultrasonic cleaning to remove particulate contaminants from the wafer disk surface. Dielectric layer deposition is performed on the wafers in the wafer disk, followed by UBM layer deposition. Metal bumps are installed on the wafer surface in an array of pads to obtain the pre-processed WLCSP chip.

[0060] It should be noted that when using deionized water combined with ultrasonic cleaning to clean the wafer disk, a plasma cleaner can also be used to activate and clean the wafer inside the disk. The cleaning power of the plasma cleaner can be 100-250W, the processing temperature is 20-40℃, and the processing time is 20-60s. Additionally, the WLCSP chip also has a metal redistribution layer.

[0061] S20, based on the WLCSP chip type, the thickness ratio of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 is preset, and the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 are alternately deposited on the packaging substrate 2. Vertical through holes 43 are made in the DBC packaging architecture 4 by laser drilling technology to create a DBC packaging architecture 4 with a low thermal resistance path.

[0062] S30, the pre-processed WLCSP chip is inverted, and the WLCSP chip and DBC packaging architecture 4 are flip-chip interconnected using DBC flip-chip process. Solder paste is printed on the surface of the packaging substrate 2, and the heat dissipation frame 3 is fastened to the outside of the packaging substrate 2. The WLCSP chip is completed by welding in a vacuum eutectic furnace. The wafer-level WLCSP chip is cut into individual WLCSP chips using laser cutting.

[0063] S40: The packaged single WLCSP chip is placed in the mold of the molding machine. High-temperature resistant and thermally conductive material is injected into the mold. After mold opening and cooling treatment, the plastic casing 1 encapsulates the WLCSP chip and the DBC packaging structure 4. Excess structural copper is removed using a trimming machine to form the finished WLCSP chip. Electrical tests are performed on the finished WLCSP chip to screen out qualified finished WLCSP chips. Figure 2 The diagram shows a schematic of the finished WLCSP chip structure in an embodiment of the present invention. The finished WLCSP chip is subjected to electrical testing at least 3 times, and the batch size of the tested chips is 600-900 sets. After electrical testing of the finished WLCSP chips, the WLCSP chips packaged using the multi-DBC packaging method provided in this embodiment of the present invention have a test pass rate of over 98%.

[0064] In this embodiment, when performing electrical tests on the finished WLCSP chip, the test equipment includes a probe station, a flying probe tester, and a vector network analyzer. The test items include, but are not limited to, insulation test, electrostatic discharge test (EAS), leakage current test under drain-source voltage (DVDS), switching test (SW), reverse recovery time test (TRR), resistance over-limit test (RG), and DC parameter test (DC).

[0065] This invention provides a method for mounting metal bumps on a wafer surface using an array of pads. The method specifically includes:

[0066] S101. The type of metal bump is determined based on the wafer type. The metal bump includes, but is not limited to, tin-lead bump, lead-free bump, and copper pillar bump. The size deviation of the metal bump is detected by a laser thickness gauge. The size deviation is <3μm. The surface defect rate of the metal bump is analyzed by scanning electron microscopy. The surface defect rate is ≤5%, thereby avoiding short circuits during bonding or soldering.

[0067] S102 uses oxygen plasma to perform plasma cleaning on the wafer surface pads. A robotic arm picks up metal bumps from the bump conveyor belt and a CCD camera aligns the metal bumps with the pads.

[0068] S103, the laser bonding machine bonds metal bumps to pads according to the material type of the metal bumps. The bonding pressure can be 3-5 MPa. The reliability of the metal bump interconnect is evaluated based on the modal synthesis method, and the thickness of the nano-silver paste on the metal bumps is adjusted based on the reliability evaluation results.

[0069] In this embodiment, the reliability assessment of metal bump interconnects is based on modal synthesis. The goal is to identify the potential failure risks of bumps under stress such as thermal cycling, mechanical vibration, and temperature shock, thereby ensuring the stability and lifespan of the packaged WLCSP chip. It should be noted that nano silver paste is a conductive paste formed by dispersing nano-sized silver particles in organic or inorganic solvents. Due to its unique nano-effect, it has characteristics such as high conductivity, low resistivity, good adhesion, high temperature resistance, and chemical corrosion resistance. In this embodiment, nano silver paste is used to replace conventional solder or metal plating, which can reduce the line resistance of the WLCSP chip, achieve high-resolution printing and high thermal conductivity, and improve the overall heat dissipation performance of the WLCSP chip.

[0070] Considering that long-term thermal cycling can cause creep strain inside the solder joints, when the strain exceeds the fatigue limit of the interconnect bonding alloy, microcracks will appear on the metal bumps and gradually propagate, eventually leading to failure. To avoid chip damage due to metal bump failure during flip-chip interconnection of WLCSP chips and DBC package architecture 4, this invention provides a method for reliability assessment of metal bump interconnects based on modal synthesis. This method specifically includes:

[0071] S1031, obtain the wafer surface pad size parameters and bump distribution coordinate parameters. The 3D visualization tool constructs a 3D model of the bumps based on the wafer surface pad size parameters and bump distribution coordinate parameters. The 3D model of the bumps includes the wafer, pads and metal bumps. By constructing the 3D model of the bumps, the geometric relationship between the wafer, pads and bumps can be realistically reproduced, providing accurate geometric input for subsequent simulation analysis and avoiding the "idealization" error of traditional 2D analysis.

[0072] S1032 simulates accelerated thermal cycling testing of wafers. The number of accelerated thermal cycling tests can be 1000-1500 cycles, with a temperature cycling range of -40℃ to 150℃, accelerating the fatigue failure of metal bumps. The fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness of the metal bumps are statistically analyzed. Failure curves are obtained by mapping these parameters based on the fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness. The parameters are then normalized to obtain normalized failure curves. It should be noted that the fatigue failure time of the metal bumps reflects their resistance to thermal cycling, the cumulative creep strain reflects the degree of plastic deformation, and the fracture toughness reflects the interconnect's resistance to crack propagation. Normalization of the parameters eliminates the influence of differences in testing equipment and environment, making the data more universal.

[0073] S1033, Modal analysis is performed on the normalized failure curve based on the modal synthesis method, and the modal analysis is performed on the substructure associated with the metal bump to obtain the substructure modal failure probability. The substructure modal failure probabilities are linearly weighted and combined to obtain the comprehensive failure probability of the metal bump.

[0074] In this embodiment of the invention, the substructures include, but are not limited to, printed silver paste layer, chip, thermally conductive copper layer 41, etc., and their failure probabilities are evaluated separately, thus avoiding the ambiguity of "overall evaluation".

[0075] S1034, determine whether the overall failure probability of the metal bump exceeds a preset probability threshold, wherein the preset probability threshold can be set to 50-60%;

[0076] S1035, if the overall failure probability of a metal bump exceeds a preset probability threshold, the metal bump is identified as a failed bump.

[0077] If the overall failure probability of the metal bump does not exceed the preset probability threshold, the current metal bump is determined to be a normal bump.

[0078] S1036, obtain the failed bumps in the 3D model of the bumps and mark the failed bumps, adjust the thickness of the metal bump nano-silver paste based on the comprehensive failure probability corresponding to the failed bumps, and feed back the marked failed bumps and the thickness of the metal bump nano-silver paste.

[0079] In this embodiment, the adjusted thickness of the metal bump nano-silver paste is calculated using the following formula:

[0080]

[0081]

[0082]

[0083] in, This indicates the adjusted thickness of the nano-silver paste used to create the metal bumps. The initial thickness of the bumped nano-silver paste. These are the overall failure probability and the preset probability threshold, respectively. Sub-modes Substructure weighting coefficients and substructure modal failure probabilities. They represent sub-modes respectively. The fatigue life and shape parameters, with the shape parameter being a key parameter describing the morphological characteristics of the probability distribution. For sub-mode Quantity, This represents the sensitivity coefficient.

[0084] In this embodiment of the invention, considering that long-term thermal cycling can cause creep strain inside the solder joints, when the strain exceeds the fatigue limit of the interconnect bonding alloy, microcracks will appear on the metal bumps and gradually propagate, eventually leading to failure. To avoid chip damage caused by metal bump failure during flip-chip interconnection of WLCSP chips and DBC packaging architecture 4, this embodiment of the invention provides a method for reliability assessment of metal bump interconnects based on modal synthesis. Through high-temperature-low-temperature rapid cycling, the fatigue failure of metal bumps can be accelerated, thereby obtaining failure data from long-term use in a short time. Furthermore, by performing modal analysis on the normalized failure curves, the failure probability of the substructure modes associated with the metal bumps can be obtained, thus accurately reflecting the failure risk of the bumps under different operating conditions. By identifying high-risk bumps early and adjusting the thickness of the nano-silver paste on the metal bumps, failure can be effectively avoided while improving the reliability consistency of batch products. Ultimately, this effectively reduces the failure rate of chip packaging.

[0085] In WLCSP (Wafer-Level Chip Scale Package) chip packaging, the thickness ratio of the thermally conductive ceramic layer 42 to the thermally conductive copper layer 41 directly affects the package's thermal resistance, heat dissipation efficiency, and long-term reliability. However, in traditional packaging designs, the thicknesses of the ceramic and copper layers are often chosen empirically, leading to problems such as excessively high thermal resistance, insufficient heat dissipation efficiency, or CTE mismatch, resulting in excessive chip junction temperature and affecting chip operational stability. Therefore, this invention provides a method for presetting the thickness ratio of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 based on the WLCSP chip type. This method specifically includes:

[0086] S201 identifies the WLCSP chip type, determines the chip junction temperature requirement, chip power consumption, and maximum ambient temperature based on the WLCSP chip type, and calculates the chip's maximum thermal resistance using the chip junction temperature requirement, chip power consumption, and maximum ambient temperature. The WLCSP chip types include high-power, high-frequency, and low-power types, and the formula for calculating the chip's maximum thermal resistance is as follows:

[0087]

[0088]

[0089] in, Indicates the chip's maximum thermal resistance. For chip power consumption, For the chip's operating temperature difference, These are the junction temperature requirement and the maximum ambient temperature, respectively. In this embodiment, the upper limit of thermal resistance is deduced from the junction temperature requirement to avoid the risk of exceeding the junction temperature limit due to excessive thermal resistance.

[0090] S202, with the maximum thermal resistance of the chip as a constraint, at least one combination of the thickness ratio of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 is simulated based on ANSYS Icepak. In this embodiment, with the maximum thermal resistance of the chip as a constraint, when simulating based on ANSYS Icepak, multiple dimensions of indicators such as thermal resistance, skin effect, and CTE mismatch are simulated and evaluated simultaneously. Thus, with the maximum thermal resistance of the chip as a constraint, candidate combinations with better overall performance can be initially screened.

[0091] S203, load at least one set of thickness ratio combinations, preset the maximum skin depth, determine the thickness range of the thermally conductive copper layer 41 based on the maximum skin depth, and filter the thickness ratio combinations that meet the maximum skin depth based on the thickness range of the thermally conductive copper layer 41.

[0092] S204. A DBC thermal resistance model is established based on the maximum thermal resistance, coefficient of thermal expansion, and maximum current carrying capacity. The overall thermal resistance of the DBC thermal resistance model is calculated using the thickness ratio combination that meets the maximum skin depth as variables. The thickness ratio combination with the minimum overall thermal resistance is the optimal thickness ratio combination.

[0093] In this embodiment, the DBC thermal resistance model incorporates CTE mismatch stress and maximum carrying current constraints, which can effectively ensure that the optimal combination has no risk of interlayer peeling or overheating during long-term use. Furthermore, the optimized thickness ratio can be directly input into electroplating, sputtering and other process equipment, thereby reducing manual adjustment errors.

[0094] This invention provides a method for presetting the thickness ratio of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 based on the WLCSP chip type. By identifying the WLCSP chip type and determining its junction temperature requirements, power consumption, and maximum ambient temperature, the maximum thermal resistance requirement of the chip can be accurately calculated. This ensures that the thickness ratio design meets the heat dissipation requirements of a specific chip, avoiding performance degradation or damage due to insufficient heat dissipation. Furthermore, by establishing a DBC thermal resistance model and using the thickness ratio combination that conforms to the maximum skin depth as variables, the overall thermal resistance can be accurately calculated. This helps to find the optimal thickness ratio combination. By optimizing the thickness ratio, the heat dissipation performance of the package can be improved, thereby improving the chip's reliability and performance, and extending its lifespan.

[0095] This invention provides a method for fabricating a DBC package architecture with a low thermal resistance path. The method specifically includes:

[0096] S301, obtain the thickness ratio of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41, cut the packaging substrate 2 to the target size, and polish the surface of the packaging substrate 2. In this embodiment of the invention, the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 can be 1-1.4:0.4-1.2, and the number of thermally conductive ceramic layer 42 and thermally conductive copper layer 41 can be 2-4 layers.

[0097] S302 uses magnetron sputtering to deposit a thermally conductive copper layer 41 and a thermally conductive ceramic layer 42 on a substrate, and then uses high temperature and high pressure to alternately bond the thermally conductive copper layer 41 and the thermally conductive ceramic layer 42 to create a target circuit pattern on the thermally conductive copper layer 41.

[0098] S303 uses laser drilling technology to create a vertical via 43 in the DBC package architecture 4, and embeds a temperature sensor in the vertical via 43 to obtain a low thermal resistance path DBC package architecture 4. The DBC package architecture 4 integrates more functions in a limited space and improves the package density through laser drilling technology and the design of vertical via 43.

[0099] In this embodiment of the invention, a method for fabricating a low thermal resistance path DBC packaging architecture 4 is provided. The DBC packaging architecture 4 adopts a low thermal resistance design, and through the alternating stacked structure of copper and ceramic layers and the optimization of the thickness ratio, it effectively solves the problems of interface peeling and solder joint fatigue caused by CTE mismatch in traditional packaging. Moreover, the DBC packaging architecture 4 can flexibly adapt to different types of WLCSP chips.

[0100] This invention provides a method for flip-chip interconnection of a WLCSP chip and a DBC package architecture 4 using DBC flip-chip technology. The method specifically includes:

[0101] S401 uses a robotic arm to grip the DBC package holder, inverts the WLCSP chip, and uses a CCD camera to align the WLCSP chip and the DBC package architecture.

[0102] In step S402, the thermally conductive copper layer 41 on top of the DBC package holder is micro-etched. Micro-etching increases the surface roughness of the DBC copper layer, thereby improving the mechanical bonding ability of the nano-silver paste. Simultaneously, it removes the surface oxide layer, ensuring the quality of the chemical bonding between the silver paste and the copper layer. Nano-silver paste is then printed onto the micro-etched thermally conductive copper layer 41 on top of the DBC package holder. In semiconductor packaging (WLCSP, BGA, Flip Chip), nano-silver paste printing can be used for interconnection between the chip and the substrate / PCB (printed circuit board), replacing traditional solder or conductive adhesive. The thermal conductivity of nano-silver paste is much higher than that of organic conductive adhesives, and it has better thermal compatibility with ceramic and metal substrates. In chip packaging, the interconnect layer printed with nano-silver paste can reduce thermal resistance and chip junction temperature, thereby extending chip lifespan.

[0103] S403, the aligned WLCSP chip and DBC package architecture 4 are aligned and flip-chip bonded, and thermo-bonded at 280-340℃ and 3.5MPa pressure. The thermo-bonded WLCSP chip and DBC package architecture 4 are then reflow soldered to complete the flip-chip interconnection of the WLCSP chip and DBC package architecture 4.

[0104] In this embodiment, when printing nano-silver paste on the thermally conductive copper layer 41 on the top of the micro-etched DBC package frame, the copper layer interconnection point corresponding to the failure bump in the thermally conductive copper layer 41 on the top of the DBC package frame is identified, the marked failure bump and the thickness of the nano-silver paste on the metal bump are obtained, and the thickness of the nano-silver paste on the metal bump of the copper layer interconnection point is adjusted based on the marked failure bump.

[0105] On the other hand, embodiments of the present invention also provide a multi-DBC packaging structure for WLCSP chips, such as... Figures 3-4 As shown, the multi-DBC packaging structure of the WLCSP chip specifically includes:

[0106] The package substrate 2, the DBC package architecture 4, and the heat dissipation frame 3 are provided. The package substrate 2 and the heat dissipation frame 3 are soldered together with large pads. The DBC package architecture 4 is bonded on the package substrate 2. The WLCSP chip and the DBC package architecture 4 are encapsulated by a plastic shell 1. The WLCSP chip is bonded to the top of the DBC package architecture 4, and the chip electrodes are electrically connected to the bottom layer of the DBC package architecture 4 through conductive vias. The DBC package architecture 4 and the WLCSP chip are also described.

[0107] In this embodiment, Figure 6The diagram shows the arrangement of the thermally conductive copper layer 41 and the thermally conductive ceramic layer 42 in the DBC packaging architecture 4. The DBC packaging architecture 4 includes a thermally conductive copper layer 41 and a thermally conductive ceramic layer 42. At least one layer of each thermally conductive copper layer 41 and thermally conductive ceramic layer 42 is provided, and the thermally conductive copper layer 41 and thermally conductive ceramic layer 42 are alternately arranged. The DBC packaging architecture 4 also includes at least one set of vertical through holes 43 penetrating the thermally conductive copper layer 41 and thermally conductive ceramic layer 42. Bonding wires are provided in the vertical through holes 43.

[0108] It should be noted that the DBC encapsulation architecture 4 also integrates module circuits. Figure 5 The diagram shows a schematic of the module circuit of the DBC package architecture 4. The module circuit includes a first thermistor (NTC1) and a second thermistor (NTC2), which act as temperature sensors. They achieve accurate temperature measurement through the characteristic that the resistance changes with temperature, supporting a wide temperature range of -40℃ to 150℃. The resistance of both the first and second thermistors in the module circuit is R = 10KΩ (25℃), and the B value is 3435. The module circuit also includes a first diode (D1) and a second diode (D2). The first anode (D1+) is connected to the common node of the module circuit, and the second cathode (D2-) is also connected to the common node. The module circuit also includes a first gate (G1) and a second gate (G2). A switch (S) is provided between the first gate (G1) and the second gate (G2), and a set of field-effect transistors (MOSFETs) are respectively provided between the first gate (G1) and the switch (S) and between the second gate (G2) and the switch (S). The field-effect transistor (MOSFET) includes a drain, a gate, and a source. The field-effect transistor (MOSFET) is connected to the switch through the source, electrically connected to the first gate (G1) or the second gate (G2) through the gate, and electrically connected to the first diode (D1) or the second diode (D2) through the drain. In this embodiment of the invention, the DBC packaging architecture 4 integrates an NTC sensor and a signal processing chip through a DBC substrate, taking into account temperature measurement accuracy, heat dissipation performance and reliability. It provides a standardized temperature monitoring module for high temperature and high reliability scenarios, simplifies the design of peripheral circuits and improves system stability. In addition, the WLCSP chip provides three power levels of 6kW, 9kW and 12kW, covering small and medium power to medium and high power requirements and adapting to different system scales.

[0109] In summary, this invention provides a multi-DBC packaging structure and packaging method for WLCSP chips. In the embodiments of this invention, by fabricating a low thermal resistance path DBC packaging architecture 4 and performing flip-chip interconnection between the WLCSP chip and the DBC packaging architecture 4 based on the DBC flip-chip process, the heat generated by the chip is more effectively conducted to the outside. By utilizing the high thermal conductivity and high insulation characteristics of the DBC packaging frame, high-reliability chip packaging is achieved, reducing the chip's operating temperature and thus improving the chip's stability and reliability.

[0110] It should be noted that, for the sake of simplicity, the foregoing embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to the present invention. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0111] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art can still combine, add, delete, or otherwise adjust the features of the various embodiments of the present invention according to the circumstances without conflict or creative effort, thereby obtaining different technical solutions that do not fundamentally depart from the concept of the present invention. These technical solutions also fall within the scope of protection of the present invention.

Claims

1. A multi-DBC packaging method for WLCSP chips, characterized in that, The encapsulation method includes: The wafer disk is treated with deionized water and ultrasonic cleaning to remove particulate contaminants from the surface of the wafer disk. Dielectric layer deposition is performed on the wafers in the wafer disk, followed by UBM layer deposition. Metal bumps are installed on the wafer surface in an array of pads to obtain the pre-treated WLCSP chip. Based on the WLCSP chip type, the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer is preset. The thermally conductive ceramic layer and the thermally conductive copper layer are alternately deposited on the packaging substrate. Vertical through holes are made in the DBC packaging architecture by laser drilling technology to create a DBC packaging architecture with a low thermal resistance path. The pre-processed WLCSP chip is inverted, and the WLCSP chip and DBC packaging architecture are flip-chip interconnected using the DBC flip-chip process. Solder paste is printed on the surface of the packaging substrate, and the heat dissipation frame is fastened to the outside of the packaging substrate. The WLCSP chip is completed by welding in a vacuum eutectic furnace. The wafer-level WLCSP chip is cut into individual WLCSP chips using laser cutting. The packaged single WLCSP chip is placed in the mold of the molding machine, and high-temperature resistant thermally conductive material is injected into the mold. After the mold is opened and cooled, the excess structural copper is removed by the trimming machine to form the finished WLCSP chip. The finished WLCSP chip is subjected to electrical testing, and qualified finished WLCSP chips are screened. The reliability of metal bump interconnects is evaluated based on the modal synthesis method, and the thickness of the metal bump nano-silver paste is adjusted based on the reliability evaluation results. The method for reliability assessment of metal bump interconnects based on modal synthesis includes: Obtain the wafer surface pad size parameters and bump distribution coordinate parameters. The 3D visualization tool constructs a 3D model of the bumps based on the wafer surface pad size parameters and bump distribution coordinate parameters. The 3D model of the bumps includes the wafer, pads and metal bumps. Accelerated thermal cycling tests were conducted on simulated wafers to accelerate the fatigue failure of metal bumps. The fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness of the metal bumps were statistically analyzed. Based on the fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness of the bumps, index failure curves were obtained. The indexes were normalized to obtain normalized failure curves. Modal analysis is performed on the normalized failure curve based on the modal synthesis method. Modal analysis is performed on the substructure associated with the metal bump to obtain the substructure modal failure probability. The substructure modal failure probabilities are linearly weighted and combined to obtain the comprehensive failure probability of the metal bump. Determine whether the overall failure probability of the metal bump exceeds a preset probability threshold. If the overall failure probability of the metal bump exceeds the preset probability threshold, locate the metal bump as a failed bump. The failure bumps in the 3D model of the bumps are obtained and marked. The thickness of the metal bump nano-silver paste is adjusted based on the comprehensive failure probability corresponding to the failure bumps, and the marked failure bumps and the thickness of the metal bump nano-silver paste are fed back. The method for presetting the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer based on the WLCSP chip type includes: Identify the WLCSP chip type, determine the chip junction temperature requirement, chip power consumption, and maximum ambient temperature based on the WLCSP chip type, and calculate the chip's maximum thermal resistance using the chip junction temperature requirement, chip power consumption, and maximum ambient temperature. Using the chip's maximum thermal resistance as a constraint, at least one combination of thickness ratios for thermally conductive ceramic and thermally conductive copper layers is simulated based on ANSYS Icepak. Load at least one set of thickness ratio combinations, preset the maximum skin depth, determine the thickness range of the thermally conductive copper layer based on the maximum skin depth, and filter the thickness ratio combinations that meet the maximum skin depth based on the thickness range of the thermally conductive copper layer. A DBC thermal resistance model is established based on the maximum thermal resistance, coefficient of thermal expansion, and maximum current carrying capacity. The overall thermal resistance of the DBC thermal resistance model is calculated using the thickness ratio combination that meets the maximum skin depth as variables. The thickness ratio combination with the minimum overall thermal resistance is taken as the optimal thickness ratio combination.

2. The multi-DBC packaging method for WLCSP chips as described in claim 1, characterized in that: The method for mounting metal bumps in an array of pads on the wafer surface includes: The type of metal bump is determined based on the wafer type. The metal bumps include tin-lead bumps, lead-free bumps, and copper pillar bumps. The dimensional deviation of the metal bumps is detected by a laser thickness gauge, and the surface defect rate of the metal bumps is analyzed by scanning electron microscopy. Oxygen plasma is used to clean the pads on the wafer surface. A robotic arm picks up metal bumps from the bump conveyor belt and a CCD camera aligns the metal bumps with the pads. The laser bonding machine bonds metal bumps to pads according to the material type of the metal bumps, evaluates the reliability of the metal bump interconnect based on the modal synthesis method, and adjusts the thickness of the nano silver paste of the metal bumps based on the reliability evaluation results.

3. The multi-DBC packaging method for WLCSP chips as described in claim 2, characterized in that: The method for creating a low thermal resistance path DBC packaging architecture includes: Obtain the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer, cut the packaging substrate to the target size, and polish the surface of the packaging substrate. A thermally conductive copper layer and a thermally conductive ceramic layer are deposited on a substrate using magnetron sputtering. The thermally conductive copper layer and the thermally conductive ceramic layer are then bonded alternately under high temperature and high pressure to fabricate the target circuit pattern on the thermally conductive copper layer. Vertical vias are fabricated within the DBC packaging architecture using laser drilling technology, and temperature sensors are embedded within these vias to create a DBC packaging architecture with a low thermal resistance path.

4. The multi-DBC packaging method for WLCSP chips as described in claim 1, characterized in that: The method for flip-chip interconnection of WLCSP chips and DBC packaging architecture using DBC flip-chip technology includes: A robotic arm is used to grip the DBC package holder, the WLCSP chip is inverted, and a CCD camera is used to align the WLCSP chip and the DBC package architecture. The thermally conductive copper layer on the top of the DBC package holder was micro-etched, and nano silver paste was printed on the micro-etched thermally conductive copper layer on the top of the DBC package holder. The aligned WLCSP chip and DBC package architecture are flip-chip aligned and thermo-bonded at 280-340℃ and 3.5MPa pressure. The thermo-bonded WLCSP chip and DBC package architecture are then reflow soldered to complete the flip-chip interconnect of the WLCSP chip and DBC package architecture.

5. The multi-DBC packaging method for WLCSP chips as described in claim 4, characterized in that: When printing nano-silver paste on the thermally conductive copper layer on the top of the micro-etched DBC package frame, the copper layer interconnection point corresponding to the failure bump in the thermally conductive copper layer on the top of the DBC package frame is identified, the marked failure bump and the thickness of the nano-silver paste on the metal bump are obtained, and the thickness of the nano-silver paste on the metal bump of the copper layer interconnection point is adjusted based on the marked failure bump.

6. The multi-DBC packaging method for WLCSP chips as described in claim 1, characterized in that: When performing electrical tests on finished WLCSP chips, the test items include insulation test, electrostatic discharge test, leakage current test under drain-source voltage, switching test, reverse recovery time test, resistance over-limit test, and DC parameter test.

7. A multi-DBC packaging structure for a WLCSP chip, used to implement the multi-DBC packaging method for a WLCSP chip as described in any one of claims 1-6, characterized in that: The multi-DBC packaging structure of the WLCSP chip includes: The package includes a substrate, a DBC packaging architecture, and a heat dissipation frame. The substrate and the heat dissipation frame are soldered together using large pads. The DBC packaging architecture is bonded to the substrate. The WLCSP chip is bonded to the top of the DBC packaging architecture, and the chip electrodes are electrically connected to the bottom layer of the DBC packaging architecture through conductive vias.

8. The multi-DBC packaging structure of the WLCSP chip as described in claim 7, characterized in that: The DBC packaging architecture includes a thermally conductive copper layer and a thermally conductive ceramic layer, with at least one thermally conductive copper layer and a thermally conductive ceramic layer respectively, and the thermally conductive copper layer and the thermally conductive ceramic layer are alternately arranged. The DBC packaging architecture also includes at least one set of vertical through holes penetrating the thermally conductive copper layer and the thermally conductive ceramic layer, and bonding wires are arranged in the vertical through holes.

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