Semiconductor cascade device and packaging method thereof

Abstract

The invention relates to a semiconductor cascade device and a packaging method thereof, and belongs to the technical field of semiconductor packaging. The packaging method of the semiconductor cascade device comprises the steps that fan-out packaging of electrodes is carried out on a first semiconductor chip to obtain a third semiconductor chip, a first rewiring layer is formed on the surface of the front face of the third semiconductor chip, the third semiconductor chip comprises a first area and a second area which are transversely arranged, and the first rewiring layer is arranged between the first area and the second area; the first semiconductor chip is packaged in the first region, and the second region comprises a heat dissipation path; the first rewiring layer comprises a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer which at least covers part of the surface of the front surface of the second region; mounting a second semiconductor chip on the cascade metal layer; and performing metal interconnection and plastic packaging to obtain the semiconductor cascade device. According to the invention, the area of the semiconductor chip is reduced, parasitic parameters are reduced, and the overall heat dissipation effect of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a semiconductor cascade device and a packaging method thereof. Background Art

[0002] A GaN HEMT (Gallium Nitride High Electron Mobility Transistor) is a semiconductor chip based on gallium nitride (GaN). Its high-frequency, high-power, and high-efficiency characteristics have made it a key player in modern electronics. In practical applications, depletion-mode GaN HEMTs are often combined with MOSFETs to form a cascode device, a cascode-type device that achieves normally-off operation. To improve device performance, such as leakage balance, switching speed, and overshoot voltage spikes, resistors, capacitors, or diodes are added to the cascode. GaN HEMTs can also function as functional-level components in circuits, integrating with control semiconductor chips to form IC control and discrete power stage circuits, meeting the high-frequency, high-efficiency, and high-reliability requirements of various application scenarios. These various semiconductor chips incorporating GaN HEMTs are collectively referred to as GaN cascode devices.

[0003] There are two main types of packaging for GaN cascode devices: a horizontal package structure and a stacked package structure. Taking cascodes as an example, in existing horizontal package structures, MOSFETs and GaN HEMTs are arranged horizontally, and a DPC (direct copper plating) substrate, silicon substrate, or ceramic substrate is required as the lateral arrangement medium for the MOSFETs (such as the solution in the patent application with publication number CN113782511A). Although this method is mature in technology, the horizontal layout requires a larger substrate area, resulting in a large semiconductor chip size, which is difficult to meet the needs of semiconductor chip miniaturization. The electrode spacing in the horizontal package structure is long, and long-distance wiring will introduce parasitic inductance and capacitance, affecting high-frequency performance. In existing stacked packaging structures, MOSFETs are typically stacked above the active area of ​​a GaN HEMT (as in the proposal in patent application CN113826206A). This reduces the size of the semiconductor chip and addresses the large size issue of the horizontally stacked packaging structure. However, the stacked packaging structure presents a conflict between thermal management and area optimization. Specifically, the heat generated by the MOSFET must pass through the GaN active area to be transferred to the heat sink, resulting in a long heat dissipation path and high thermal resistance. The high local power density of the MOSFET can easily lead to thermal stress concentration in the device, resulting in reduced device reliability. Furthermore, the stacked structure squeezes the active area, limiting the layout of passive components such as resistors and capacitors, making passive device integration difficult. Summary of the Invention

[0004] In response to the technical problems existing in the prior art, the present invention proposes a semiconductor cascade device and its packaging method and packaging structure, which can optimize the thermal management path and reduce parasitic parameters while reducing the area of ​​the semiconductor chip.

[0005] To solve the above technical problems, according to one aspect of the present invention, a method for packaging a semiconductor cascade device is provided. The semiconductor cascade device includes a first semiconductor chip and a second semiconductor chip that are electrically connected. The first semiconductor chip includes a plurality of first electrodes, and the second semiconductor chip includes a plurality of second electrodes. The method for packaging the semiconductor cascade device includes: Performing electrode fan-out packaging on the first semiconductor chip to obtain a third semiconductor chip, and forming a first redistribution layer on the front surface of the third semiconductor chip, wherein the third semiconductor chip includes a first region and a second region arranged laterally, the first region encapsulating the first semiconductor chip, and the second region including a heat dissipation path; the first redistribution layer includes a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a portion of the front surface of the second region; the cascade metal layer is connected to the heat dissipation path in the second region; mounting a second semiconductor chip on the cascade metal layer; Performing metal interconnection between the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve electrical connection between the first semiconductor chip and the second semiconductor chip and obtain a structure including a plurality of device electrodes of the semiconductor cascade device; and The structure with metal interconnection is plastic-sealed to obtain the semiconductor cascade device.

[0006] Optionally, the step of performing fan-out packaging of electrodes on the first semiconductor chip to obtain a third semiconductor chip includes: Performing a first fan-out package of electrodes on the first semiconductor chip to form a second redistribution layer, wherein the second redistribution layer includes a first electrode fan-out metal layer extending toward the front surface and a first electrode fan-out metal layer extending beyond the first semiconductor chip body toward the back surface; The first electrode fan-out metal layer led out to the front is packaged on the front side, and the first electrode fan-out metal layer led out to the back side is packaged on the back side. A first redistribution layer is formed on the front side of the third semiconductor chip obtained after the packaging, and a third redistribution layer is formed on the back side of the third semiconductor chip. The first redistribution layer includes the first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a partial surface of the front side of the second area. The third redistribution layer includes at least the first electrode fan-out metal layer.

[0007] Optionally, the step of performing fan-out packaging of electrodes on the first semiconductor chip includes: Arranging a first semiconductor chip and a third structure in parallel, wherein the front side and the back side of the third structure respectively include a metal layer; and Performing fan-out packaging of electrodes on the first semiconductor chip and the third structure arranged in parallel to obtain a third semiconductor chip, and forming a first redistribution layer on the front surface of the third semiconductor chip; The first semiconductor chip is encapsulated in the first area of ​​the third semiconductor chip, and the third structure is encapsulated in the second area to form the heat dissipation path; the first redistribution layer includes a cascade metal layer obtained by fanning out the front metal layer of the third structure and covering at least part of the front surface of the second area.

[0008] Optionally, when fanning out the electrodes of the first semiconductor chip, a second region beyond the first semiconductor chip body is obtained, and a metal column penetrating the second region is formed inside the second region, the metal column forming the heat dissipation path.

[0009] Optionally, when a first redistribution layer is formed on the front surface of the third semiconductor chip, the first electrode fan-out metal layer of the first semiconductor chip and the cascade metal layer covering at least a partial front surface of the second area are insulated and separated from each other; or, a first electrode fan-out metal layer of the first semiconductor chip and the cascade metal layer are formed integrally; or, the cascade metal layer extends from a partial front surface of the second area to a partial front surface of the first area.

[0010] Optionally, the step of metal interconnecting the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve an electrical connection between the first semiconductor chip and the second semiconductor chip includes: mounting the third semiconductor chip on a lead frame, wherein the lead frame includes device pins serving as device electrodes; and The metal interconnections are made by wire bonding, or by strip bonding, or by metal strips, or by pressure welding, or by metal sheets.

[0011] Optionally, the step of metal interconnecting the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve an electrical connection between the first semiconductor chip and the second semiconductor chip includes: The first electrode fan-out metal layer and the second electrode of the second semiconductor chip are fan-out packaged once or multiple times. During each fan-out package, the electrical connection between the first semiconductor chip and the second semiconductor chip is achieved through the redistribution layer.

[0012] According to another aspect of the present invention, the present invention further provides a semiconductor cascade device, comprising: A third semiconductor chip includes a first region and a second region arranged laterally, wherein the first region encapsulates a first semiconductor chip, and the second region includes a heat dissipation path; a first redistribution layer is formed on a front surface of the third semiconductor chip, the first redistribution layer including a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a portion of the front surface of the second region; the cascade metal layer is connected to the heat dissipation path in the second region; a second semiconductor chip mounted on the cascade metal layer; A metal interconnect structure is connected to the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve an electrical connection between the first semiconductor chip and the second semiconductor chip and obtain a plurality of device electrodes including the semiconductor cascade device.

[0013] Optionally, the interior of the third semiconductor chip also includes a second redistribution layer, the second redistribution layer includes a first electrode fan-out metal layer extending toward the front side and a first electrode fan-out metal layer extending toward the back side beyond the first semiconductor chip body; correspondingly, the back surface of the third semiconductor chip includes a third redistribution layer, and the third redistribution layer includes at least the first electrode fan-out metal layer.

[0014] Optionally, the second region of the third semiconductor chip includes a metal column penetrating the second region for forming a heat dissipation path, and a top of the metal column is connected to the cascade metal layer.

[0015] Optionally, a third structure is encapsulated inside the second area of ​​the third semiconductor chip, and the front and back sides of the third structure respectively include metal layers; correspondingly, part or all of the cascade metal layer in the first redistribution layer is a fan-out metal layer of the front metal layer of the third structure, and the third structure and its fan-out metal structure form the heat dissipation path.

[0016] Optionally, the front metal layer and / or back metal layer of the third structure is one or two or more layers insulated from each other.

[0017] Optionally, the third structure is a substrate, a substrate integrated with an embedded circuit, or a fourth semiconductor chip; When the third structure is a substrate integrated with an embedded circuit, the front metal layer and / or the back metal layer are electrical connection points of the embedded circuit; When the third structure is a fourth semiconductor chip, the front metal layer and / or the back metal layer are electrodes of the fourth semiconductor chip.

[0018] Optionally, the embedded circuit includes any combination of one or more of a resistor, a capacitor and a diode.

[0019] Optionally, the back side of the second semiconductor chip includes a second electrode, a first electrode fan-out metal layer of the first semiconductor chip is electrically connected to the second electrode on the back side of the second semiconductor chip and is insulated and separated from the cascade metal layer, and the second electrode of the second semiconductor chip is simultaneously mounted on the first electrode fan-out metal layer and the cascade metal layer that are electrically connected to it.

[0020] Optionally, the back side of the second semiconductor chip includes a second electrode, a first electrode fan-out metal layer of the first semiconductor chip is electrically connected to the second electrode on the back side of the second semiconductor chip, and the first electrode fan-out metal layer that is electrically connected to the second electrode on the back side of the second semiconductor chip is integrally connected to the cascade metal layer.

[0021] Optionally, the first semiconductor chip is a depletion-mode semiconductor chip, and the second semiconductor chip is an enhancement-mode semiconductor chip; or, the first semiconductor chip is an enhancement-mode semiconductor chip, and the second semiconductor chip is a depletion-mode semiconductor chip; or, the second semiconductor chip is a driver IC chip of the first semiconductor chip, or the first semiconductor chip is a driver IC chip of the second semiconductor chip.

[0022] Optionally, the second semiconductor chip body partially overlaps with the first semiconductor chip body in a longitudinal direction.

[0023] Compared with the existing horizontal packaging structure, the present invention reduces the area of ​​the semiconductor chip and the electrode spacing, thereby reducing parasitic parameters; compared with the existing stacked packaging structure, the present invention optimizes the thermal management path, avoids heat concentration, improves the overall heat dissipation effect of the semiconductor cascade device, and enhances the integration flexibility of the embedded device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Below, the preferred embodiments of the present invention will be further described in detail with reference to the accompanying drawings, in which: Figure 1 is a brief flow chart of a method for packaging a semiconductor cascade device according to an embodiment of the present invention; Figure 2 is an electrical schematic diagram of a semiconductor cascade device according to a first embodiment of the present invention; Figure 3 is a flow chart of a method for packaging a semiconductor cascade device according to a first embodiment of the present invention; Figure 4 corresponds to Figure 3 Schematic diagram of device packaging structure of some steps in the packaging method shown; Figure 5 is based on Figure 3 A schematic diagram of the front packaging structure of a semiconductor cascade device obtained by the packaging method shown; Figure 6 is a flow chart of another method for fan-out packaging of the HEMT 11 and the substrate 13 according to the second embodiment of the present invention; Figure 7 1 is a flow chart of a method for fanning out packaging of the HEMT 11 and substrate 13 arranged in parallel to obtain a third semiconductor chip 14 according to a third embodiment of the present invention; Figure 8 corresponds to Figure 7 Schematic diagram of the packaging structure of some steps in the fan-out packaging method shown; Figure 9 is a schematic diagram of the top surface of the structure corresponding to step S204 in implementation three of the present invention; Figure 10 1 is a schematic diagram of the front packaging structure of a semiconductor cascade device obtained according to the packaging method of Example 3; Figure 11 is a flow chart of a packaging method for a semiconductor cascade device according to a fourth embodiment of the present invention; Figure 12 corresponds to Figure 11 Schematic diagram of device packaging structure of some steps in the packaging method shown; Figure 13 Schematic diagram of the top structure of a lead frame according to a fourth embodiment of the present invention; Figure 14 1 is a schematic diagram of the front packaging structure of a semiconductor cascade device according to a fourth embodiment of the present invention; Figure 15 1 is a schematic diagram of a device packaging structure of a semiconductor cascade device according to a fifth embodiment of the present invention; Figure 16 is an electrical schematic diagram of a first semiconductor cascade device according to a sixth embodiment of the present invention; Figure 17 corresponds to Figure 16 Schematic diagram of the packaging structure of the semiconductor cascade device according to the electrical principle shown; Figure 18 is an electrical schematic diagram of a second semiconductor cascade device according to a sixth embodiment of the present invention; Figure 19 is an electrical schematic diagram of a third semiconductor cascade device according to a sixth embodiment of the present invention; Figure 20 is a schematic diagram of the front structure of the substrate 13 according to the sixth embodiment of the present invention; Figure 21 is a schematic diagram of the back structure of the substrate 13 according to the sixth embodiment of the present invention; Figure 22 corresponds to Figure 19 Schematic diagram of the packaging structure of the semiconductor cascade device according to the electrical principle shown; Figure 23 corresponds to Figure 19 A front view schematic diagram of the package structure of a semiconductor cascade device showing the electrical principle; Figure 24 is an electrical schematic diagram of a fourth semiconductor cascade device according to a sixth embodiment of the present invention; Figure 25 corresponds to Figure 24 Schematic diagram of the packaging structure of the semiconductor cascade device according to the electrical principle shown; Figure 26 is an electrical schematic diagram of a fifth semiconductor cascade device according to a sixth embodiment of the present invention; Figure 27 corresponds to Figure 26 Schematic diagram of the packaging structure of the semiconductor cascade device according to the electrical principle shown; Figure 28 is an electrical schematic diagram of a sixth semiconductor cascade device according to a sixth embodiment of the present invention; Figure 29 corresponds to Figure 28 Schematic diagram of the packaging structure of the semiconductor cascade device according to the electrical principle shown; Figure 30 is an electrical schematic diagram of a seventh semiconductor cascade device according to a sixth embodiment of the present invention; Figure 31 corresponds to Figure 30 Schematic diagram of the packaging structure of the semiconductor cascade device according to the electrical principle shown; Figure 32 1 is a schematic diagram of a packaging structure in some steps of a semiconductor cascade device packaging method according to a seventh embodiment of the present invention; Figure 33 is a schematic diagram of the packaging structure of a semiconductor cascade device according to an eighth embodiment of the present invention; and Figure 34 Schematic diagram of the packaging structure of a semiconductor cascade device according to a ninth embodiment of the present invention. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0026] In the detailed description that follows, reference may be made to the various drawings that are part of this application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar figure numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized or structural, logical or electrical changes may be made to the embodiments of the present application. In addition, the "first", "second", etc. before the names of the technical features of the present invention are only used to distinguish different technical features with the same name, and do not represent serial numbers.

[0027] See also Figure 1 , Figure 1 1 is a simplified flow chart of a method for packaging a semiconductor cascade device according to an embodiment of the present invention. The semiconductor cascade device in the present invention includes a first semiconductor chip and a second semiconductor chip that are electrically connected. The method for packaging the semiconductor cascade device includes: Step S11: Fan-out packaging of the electrodes of the first semiconductor chip is performed to obtain a third semiconductor chip. The third semiconductor chip includes a first region and a second region arranged laterally, the first region encapsulating the first semiconductor chip, and the second region including a heat dissipation path. During the fan-out packaging process, a first redistribution layer is formed on the front surface of the third semiconductor chip. The first redistribution layer includes one or more first electrode fan-out metal layers of the first semiconductor chip and a cascade metal layer covering at least a portion of the front surface of the second region. The cascade metal layer is connected to the heat dissipation path in the second region.

[0028] Step S12: mounting a second semiconductor chip at least on the cascade metal layer, wherein the second semiconductor chip includes a plurality of second electrodes.

[0029] In step S13, metal interconnection is performed on the fan-out metal layer of the first electrode and the second electrode of the second semiconductor chip to realize electrical connection between the first semiconductor chip and the second semiconductor chip, thereby obtaining a structure including multiple device electrodes (or external terminals) of the semiconductor cascade device.

[0030] Step S14: plastic-encapsulating the structure with metal interconnection to obtain the semiconductor cascade device.

[0031] In the present invention, when the first semiconductor chip is a depletion-mode semiconductor chip, the second semiconductor chip is an enhancement-mode semiconductor chip. When the first semiconductor chip is an enhancement-mode semiconductor chip and the second semiconductor chip is a depletion-mode semiconductor chip, the first and second semiconductor chips can form a cascade device.

[0032] When packaging the aforementioned semiconductor cascade device, the present invention performs wafer-level fan-out packaging on a first semiconductor chip (die) to obtain a base semiconductor device. The base semiconductor device is the third semiconductor chip in step S11. A second semiconductor chip is mounted on a metal layer (i.e., the aforementioned cascade metal layer) on the surface of the base semiconductor device, which is connected to the heat dissipation path within the second region. Compared to conventional horizontal packaging solutions, this reduces the lateral package size and the distance between electrical connection points, thereby reducing parasitic parameters such as parasitic resistance, parasitic inductance, and / or parasitic capacitance caused by metal interconnection through wire bonding. Compared to existing vertical stacking solutions, the heat dissipation path of the second semiconductor chip is separated from the heat dissipation path of the first semiconductor chip, thereby improving the device's heat dissipation. Because fan-out packaging can replace some or all wire bonding, it can further reduce parasitic parameters. Furthermore, the second semiconductor chip can be an enhanced chip or a control IC chip, depending on the product design requirements. The present invention can also introduce active components (such as diodes, enhanced chips) or passive components (such as resistors, capacitors, etc.) into the second region or the first semiconductor chip according to the design requirements of the product. It can be seen that the packaging structure of the semiconductor cascade device provided by the present invention has high integration and good heat dissipation effect, and can realize the packaging of semiconductor cascade devices with various electrical structures.

[0033] The following describes in detail the semiconductor cascade device and its packaging method of the present invention through the specific circuit structure and chip structure. It should be noted that the packaging structure diagrams of the semiconductor cascade device in the following embodiments of the present invention are schematic diagrams. The positions, shapes, and sizes of the various structures drawn in the diagrams are for the purpose of illustrating the packaging method and principles, and are not for production. In order to clearly show the various necessary structures in the device in the structure diagrams, some structures are enlarged or simplified when drawing.

[0034] Example 1 Figure 2: This is an electrical schematic diagram of a semiconductor cascade device according to Embodiment 1 of the present invention. The semiconductor cascade device in this embodiment is generally referred to as a cascode device or a common-source common-gate cascade device, and includes a depletion-mode high electron mobility transistor (HEMT) 11 and an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) 12. The drain D of the MOSFET 12 is electrically connected to the source S of the HEMT 11, the gate G of the MOSFET 12 serves as the device gate 101 of the cascode device, and the source S of the MOSFET 12 is connected to the gate G of the HEMT 11 and serves as the device source 103 of the cascode device. The drain D of the HEMT 11 serves as the device drain 102 of the cascode device.

[0035] Figure 3 4 is a flow chart of a packaging method for a semiconductor cascade device according to the first embodiment of the present invention. Figure 4 corresponds to Figure 3 Schematic diagram of the device packaging structure of some steps in the packaging method shown. Figure 5 is based on Figure 3 A schematic diagram of the front packaging structure of a semiconductor cascade device obtained by the packaging method shown, Figure 5 The dotted lines in the figure represent the internal structure of the device. In order to clearly show the lead-out of the chip electrodes during the packaging process, the embodiment Figure 4 The three electrodes of the HEMT 11 are shown in parallel in the xz plane (in actual electrode layout, due to the positional relationship of the electrodes in the y direction, the positions of the three electrodes cannot be shown in the xz plane. In order to express the fan-out of each electrode, the three electrodes are drawn in parallel in this embodiment). Figure 5 The middle figure shows the conventional chip electrode positions. In this embodiment, the three electrodes of HEMT11 are all located on the front of the chip, including two gate electrode surfaces (or PADs). The drain D of MOSFET12 is located on the back of the chip, and the source S and gate G are located on the front of the chip. Figure 4 Taking the coordinate axes in FIG as an example, the front side in the present invention refers to the side with the z-axis pointing upward, and the back side refers to the side with the z-axis pointing downward. Taking the HEMT 11 in this embodiment as an example, the side with three electrodes is the front side of the chip, and the opposite side is the back side of the chip.

[0036] See also Figure 3 The packaging method of the semiconductor cascade device according to the first embodiment of the present invention comprises the following steps: In step S101, a HEMT 11 and a substrate 13 are provided, and conductive adhesive is applied to the backside. Substrate 13 can be a direct-plated copper (DPC) ceramic substrate, a ceramic substrate with a metal layer formed on its surface, a laminated resin board, a sapphire substrate, or a substrate made of other insulating materials, or a silicon substrate with a metal layer formed on the surface of a dielectric layer. The upper and lower surfaces of substrate 13 are electrically insulated. Alternatively, a metal layer can be deposited on the backsides of HEMT 11 and substrate 13.

[0037] Step S102: Using a die bonding process, the HEMT 11 and the substrate 13 are mounted on a temporary carrier 200. In this embodiment, the drain D, source S, and gate G of the HEMT 11 are all located on the front side of the chip.

[0038] Step S103: forming metal posts on the electrode surface of the HEMT 11 and the metal layer surface of the substrate 13. Figure 4 As shown, drain metal pillars 311, gate metal pillars 312, and source metal pillars 313 are formed on the surfaces of the drain D, gate G, and source S of the HEMT 11, and substrate metal pillars 314 are formed on the surface of the metal layer of the substrate 13. The metal pillars formed on the chip electrode surfaces described in the present invention are one specific embodiment of the conductive structure. In addition to metal pillars, other conductive structures may also be used, such as metal balls obtained by ball implantation or conductive structures obtained by other packaging processes.

[0039] Regarding steps S102 and S103, when a HEMT wafer is provided, since the HEMT has not yet been cleaved, metal pillars can be grown on the wafer first, and then bonded to the temporary carrier 200. Since the HEMT 11 provided in this embodiment is a single, already cleaved die, the HEMT 11 is first bonded to the temporary carrier 200 using a die bonding process before metal pillars are grown. The growth of metal pillars on the substrate 13 proceeds similarly.

[0040] Step S104 , plastic-encapsulating the current structure to obtain a first plastic-encapsulated body 300 .

[0041] Step S105: grinding the surface of the first plastic package 300 to expose the surface of the metal column. Figure 4 shown.

[0042] In step S106, a first redistribution layer 320 is formed on the front surface of the first plastic package 300 where the metal pillar surfaces are exposed. The first redistribution layer 320 includes a first drain metal layer 321 electrically connected to the drain D of the HEMT 11, a first gate metal layer 322 electrically connected to the gate G of the HEMT 11, and a cascade metal layer 323 electrically connected to the source S of the HEMT 11 and the front metal layer of the substrate 13. The first drain metal layer 321 and the first gate metal layer 322 can be collectively referred to as the first electrode fan-out metal layer of the HEMT 11.

[0043] From step S103 to step S106 , the fan-out packaging of the HEMT 11 and the substrate 13 is completed.

[0044] In step S107 , the temporary carrier 200 is removed to obtain a complete third semiconductor chip 14 . The third semiconductor chip 14 includes two regions: a left region is a first region 303 where the HEMT 11 is encapsulated, and a right region is a second region 304 where the substrate 13 is encapsulated.

[0045] Step S108: Mount the third semiconductor chip 14 on the lead frame 400. Figure 5 As shown, the lead frame 400 includes a chip pad 401 and pins, such as a device drain pin 402, a device source pin 403, and a KS pin 404. The third semiconductor chip 14 is mounted on the chip pad 401. The lead frame 400 in this embodiment includes four pins, but may also include three pins or a lead frame with other structures.

[0046] Step S109 : mounting the MOSFET 12 on the cascade metal layer 323 on the surface of the third semiconductor chip 14 by a die bonding process.

[0047] Step S110, metal interconnection is performed. When metal interconnection is performed, wire bonding can be used for wire interconnection, or strip bonding can be used for metal strip interconnection, or metal sheet interconnection can be used for pressure welding bridge process. For the sake of simplicity, Figure 4 In the embodiment, bonding wire 410 is used to represent the interconnection. Figure 5 The metal strip 411 interconnection method is adopted. Figure 4 and Figure 5The first drain metal layer 321 on the surface of the third semiconductor chip 14 is connected to the device drain pin 402 of the lead frame 400 via a bonding wire 410 or a metal ribbon 411 (e.g., an aluminum ribbon or a copper ribbon). The first gate metal layer 322 on the surface of the third semiconductor chip 14 is electrically connected to the source electrode S of the MOSFET 12. The source electrode S of the MOSFET 12 is electrically connected to the die pad 401 of the lead frame 400. The die pad 401 of the lead frame 400 is at the same potential as the device source pin 403 and the KS pin 404. The gate G of the MOSFET 12 is electrically connected to the device gate pin 405.

[0048] Step S111: Plastic encapsulates the metal interconnect structure. For example, a molding process is used to encapsulate a plastic encapsulation compound such as epoxy resin around the chip, bonding wires, etc. to provide protection. Depending on the actual production equipment and production line, transfer molding, compression molding, and other processes may be used. This step may also include polishing the surface of the plastic encapsulation compound to expose a flat electrode surface.

[0049] Step S112, electroplating, laser marking, cutting and forming, and deburring. After this step, a single semiconductor cascade device is obtained. Specifically, the electrode surface of the device is chemically plated or electroplated with Ag, Au or sputtered with aluminum or other metals that can be welded to facilitate electrical connection with other devices when used. Mark the surface of the plastic package of the device, for example, use laser or ink to print chip information on the chip surface, such as brand, model, batch, production cycle, version, place of origin, etc. The entire plastic package is cut to remove connecting ribs, flash, etc. After the above processing, a single semiconductor cascade device is obtained.

[0050] pass Figure 4 and Figure 5 As can be seen, the MOSFET 12 in this embodiment is mounted on the cascade metal layer 323 on the surface of the third semiconductor chip 14. The cascade metal layer 323 is integrally connected to the fan-out metal layer of the source S of the HEMT 11. This allows the MOSFET 12 to vertically span above the HEMT 11 body and the substrate 13 body. This not only establishes an electrical connection between the backside drain D of the MOSFET 12 and the source S of the HEMT 11, but also provides a heat dissipation path for the MOSFET 12 that is independent of the HEMT 11. Compared to the prior art solution where a MOSFET is stacked on a HEMT and results in heat accumulation, the overall heat dissipation of the device in this embodiment is improved.

[0051] In step S103, metal posts (posts) are formed on the electrode surface of HEMT 11 and the metal layer surface of substrate 13. Taking the formation of metal posts on the electrode surface of HEMT 11 as an example, a seed layer, such as a copper layer, is first formed on the upper surface of HEMT 11. This seed layer covers the electrode surface of HEMT 11. A dry film is then applied to the surface of the seed layer. Dry film is a photosensitive material typically consisting of a photosensitive layer, a protective layer, and a base layer, with the photosensitive layer sandwiched between the protective layer and the base layer. The photosensitive layer is sensitive to light and undergoes a chemical reaction (dissolving or solidifying) upon exposure to ultraviolet light. Therefore, a specific pattern can be formed by exposing and developing the dry film. A programmed exposure machine is then used to expose designated locations on the dry film. In this embodiment, the dry film is exposed on the electrode surface. A developer (typically a dilute alkaline solution, such as Na2CO3) is then used to remove the exposed dry film, exposing the electrode surface where the copper posts are to be grown. Then, copper, nickel, gold or other metals are electroplated on the exposed areas. When the metal pillars reach the required height, the electroplating is stopped. A special stripping solution (usually an alkaline solution) is used to remove the dry film remaining in other locations, and a flash etching process is used to remove the seed layer in other non-essential locations.

[0052] In addition, the first redistribution layer 320 is formed on the front surface of the first plastic package 300 where the metal pillar surface is exposed in step S106, and the methods of growing metal pillars and forming redistribution layers in the following embodiments are similar to this and will not be repeated here.

[0053] Example 2 Figure 6 FIG2 is a flow chart of another method for fan-out packaging of HEMT 11 and substrate 13 according to a second embodiment of the present invention. In this embodiment, after HEMT 11 and substrate 13 are mounted on temporary carrier 200 using a die bonding process, the following steps are included: Step S1031: Chemically plate or electroplate metal on the electrode surface of the HEMT 11 and the metal layer on the front surface of the substrate 13. The metal may be copper, silver, or gold with a thickness of 3-10 μm.

[0054] Step S1032 : Plastic-encapsulating the HEMT 11 and the substrate 13 arranged in parallel to obtain a plastic-encapsulated body.

[0055] Step S1033: Drill holes on the front surface of the plastic package. Specifically, drill holes downward at positions corresponding to the HEMT 11 electrodes and the front metal layer of the substrate 13 until the holes reach the HEMT 11 electrode surface and the front metal layer of the substrate 13.

[0056] In step S1034 , metal pillars are formed in the holes and a first redistribution layer 320 is formed on the surface by electroplating metal.

[0057] This embodiment implements fan-out packaging in another way.

[0058] Example 3 Figure 7 1 is a flow chart of a method for fanning out the HEMT 11 and substrate 13 arranged in parallel to obtain a third semiconductor chip 14 according to the third embodiment of the present invention. Figure 8 corresponds to Figure 7 A schematic diagram of the packaging structure illustrating some steps in the fan-out packaging method is shown. In this embodiment, the gate G of the HEMT 11 is fanned out to the back of the device and electrically connected to the lead frame 400. This reduces the number of wire bonds between the gate G of the HEMT 11 and the source S of the front side of the MOSFET 12, thereby reducing parasitic parameters caused by the wire bonds.

[0059] Figure 7 Omitted with Figure 3 The same steps, follow Figure 3 In step S102 , after mounting the HEMT 11 and the substrate 13 on the temporary carrier 200 , the method of fanning out the HEMT 11 and the substrate 13 arranged in parallel to obtain the third semiconductor chip 14 specifically includes the following steps: Step S201: forming metal posts on the electrode surface of the HEMT 11 and the front metal layer surface of the substrate 13. Figure 8 As shown, drain metal pillars 311 , gate metal pillars 312 , and source metal pillars 313 are formed on the surfaces of the drain D, source S, and gate G of the HEMT 11 , and substrate metal pillars 314 are formed on the surface of the metal layer of the substrate 13 .

[0060] Step S202 : Plastic-encapsulating the current structure to obtain a first plastic-encapsulated body 300 .

[0061] Step S203: Grind the surface of the first plastic package 300 to expose the surface of the metal column. Figure 8 shown.

[0062] Step S204: Form a second redistribution layer 330 on the front surface of the first plastic package 300 where the metal pillar surfaces are exposed. The second redistribution layer 330 includes a second drain metal layer 331 electrically connected to the drain D of the HEMT 11, a second gate metal layer 332 electrically connected to the gate G of the HEMT 11, a second source metal layer 333 electrically connected to the source S of the HEMT 11, and a substrate metal layer 334 electrically connected to the front metal layer of the substrate 13. Figure 9 , Figure 9This is a schematic top view of the structure corresponding to step S204 in Embodiment 3 of the present invention. The dashed lines in the figure represent metal pillars located beneath the redistribution layer. In this embodiment, the gate G of the HEMT 11 is a fanned-out electrode. The area of ​​the second gate metal layer 332 in the second redistribution layer 330 extends beyond the position of the gate G of the HEMT 11 on the main body.

[0063] Step S205, a second layer of metal pillars is grown on each metal layer that needs to fan out to the front in the second redistribution layer 330, such as Figure 8 As shown in .

[0064] Step S206 , plastic-encapsulating the current structure to obtain a second plastic-encapsulated body 301 .

[0065] Step S207 , grinding the front surface of the second plastic package body 301 to expose the surface of the second layer of metal pillars.

[0066] In step S208, a first redistribution layer 320 is formed on the front surface of the second plastic package 301 where the surface of the second metal pillar is exposed. The first redistribution layer includes a first drain metal layer 321 electrically connected to the drain D of the HEMT 11 and a cascade metal layer 323. The cascade metal layer 323 is a fan-out metal layer that is integrally and electrically connected to the fan-out metal layer of the source S of the HEMT 11 and the front metal layer of the substrate 13.

[0067] Step S209: Remove the current temporary carrier 200 and place the current structure on the temporary carrier 200 with the first redistribution layer 320 facing downwards. At this time, the back of the first plastic package 300 faces upwards. Figure 8 In step S209 , two gates G of the HEMT 11 and their corresponding second gate metal layers 332 are shown.

[0068] In step S210 , a first hole 302 is drilled on the back of the first plastic package 300 . Specifically, a hole is drilled at a location where the gate G of the HEMT 11 needs to be led out until it reaches the second gate metal layer 332 in the second redistribution layer 330 .

[0069] In step S211 , metal pillars are formed in the holes and a third redistribution layer 340 is formed on the surface by electroplating, and the temporary carrier 200 is removed, thereby obtaining the third semiconductor chip 14 .

[0070] The subsequent process and Figure 3 The process shown is the same, that is, the third semiconductor chip 14 is mounted on the lead frame 400, and metal interconnection, plastic packaging, cutting, etc. are performed to finally obtain a single semiconductor cascade device, which will not be repeated here.

[0071] Figure 10This is a schematic diagram of the front-side packaging structure of a semiconductor cascade device obtained using the packaging method of Example 3. In this embodiment, when certain electrodes of the HEMT 11, such as the gate G of the HEMT 11 in this embodiment, need to be routed to the back side, a redistribution layer can be added to the plastic package to transfer the electrodes to the back side. The redistribution layer is then constructed on the back side through drilling, metal plating, or other methods. The back side of the third semiconductor chip 14 thus becomes the gate G of the HEMT 11. When the third semiconductor chip 14 is mounted on the lead frame 400, it is electrically connected to the chip pad of the lead frame 400 through contact. Subsequent metal interconnection allows the chip pad of the lead frame 400 to be electrically connected to the source S of the MOSFET 12, thereby achieving an electrical connection between the gate G of the HEMT 11 and the source S of the MOSFET 12. This eliminates the need for wire bonding, thereby reducing parasitic parameters introduced by methods such as wire bonding.

[0072] Example 4 Figure 11 is a flow chart of a packaging method for a semiconductor cascade device according to a fourth embodiment of the present invention, Figure 12 corresponds to Figure 11 The semiconductor cascade device in this embodiment is still a cascode device, and its electrical schematic diagram is as follows: Figure 2 As shown, the electrode layout of HEMT 11 and MOSFET 12 is the same as that of embodiment 1. In this embodiment, the packaging method of the cascode device in this embodiment includes the following steps: In step S401, a HEMT 11 is provided and a conductive adhesive is applied to the back surface thereof. Alternatively, a metal layer may be deposited on the back surface of the HEMT 11 and the substrate 13.

[0073] Step S402: Mount the HEMT 11 on a temporary carrier 200 using a die bonding process. In this embodiment, the drain D, source S, and gate G of the HEMT 11 are all located on the front side of the chip.

[0074] Step S403: forming a metal column on the electrode surface of the HEMT 11. Figure 12 As shown, a drain metal pillar 311 , a gate metal pillar 312 and a source metal pillar 313 are formed on the surfaces of the drain D, the source S and the gate G of the HEMT 11 .

[0075] In step S404, the current structure is encapsulated to obtain a first encapsulation body 300. The first encapsulation body 300 extends beyond the HEMT 11 in the x-direction by a preset distance. This preset distance is consistent with the mounting width of the MOSFET 12, for example, approximately equal to or less than the chip width of the MOSFET 12. Specifically, the first encapsulation body 300 includes two regions: a left region 303 for encapsulating the HEMT 11, and a right region 304 for filling with the encapsulation compound.

[0076] Step S405: Grind the surface of the first plastic package 300 to expose the surface of the metal column. Figure 12 shown.

[0077] In step S406, a first redistribution layer 320 is formed on the front surface of the first plastic package 300 where the metal pillar surfaces are exposed. The first redistribution layer 320 includes a first drain metal layer 321 electrically connected to the drain D of the HEMT 11, a first gate metal layer 322 electrically connected to the gate G of the HEMT 11, and a first source metal layer electrically connected to the source S of the HEMT 11. The source metal layer extends from the first region 303 to the second region 304 of the first plastic package 300 to form a cascade metal layer 323.

[0078] Step S407 , removing the temporary carrier 200 , and mounting the third semiconductor chip 14 upside down on the temporary carrier 200 .

[0079] Step S408 : drilling a second hole 305 in the second region 304 of the first plastic package body 300 to directly reach the cascade metal layer 323 .

[0080] In step S409 , metal is electroplated in the second hole 305 to form a metal pillar 315 connected to the cascade metal layer 323 inside the first plastic package 300 .

[0081] In step S410 , the temporary carrier 200 is removed, and a complete third semiconductor chip 14 is obtained.

[0082] From step S403 to step S410 , the fan-out packaging of the HEMT 11 is completed.

[0083] Step S411: Provide a lead frame 400 and mount the third semiconductor chip 14 on the lead frame 400. The structure of the lead frame 400 is adapted to the third semiconductor chip 14. In this embodiment, the chip pads in the first area 303 and the second area 304 of the lead frame 400 for mounting the first plastic package 300 are separated. Figure 13 , Figure 13FIG4 is a schematic diagram of the top structure of a lead frame according to a fourth embodiment of the present invention. The lead frame 400 includes a chip pad 401 and pins. The chip pad 401 includes an insulated and separated first pad area 4011 and a second pad area 4012. When the third semiconductor chip 14 is mounted on the chip pad 401, the first area 303 of the third semiconductor chip 14 is soldered to the first pad area 4011 of the chip pad 401, and the second area 304 of the third semiconductor chip 14 is soldered to the second pad area 4012. In this embodiment, four pins are included, but other lead frame configurations may also be used.

[0084] Step S412 : Mounting the MOSFET 12 on the cascade metal layer 323 on the surface of the third semiconductor chip 14 by a die bonding process.

[0085] Step S413, metal interconnection is performed. The first drain metal layer 321 on the surface of the third semiconductor chip 14 is connected to the device drain pin 402 of the lead frame 400 through a bonding wire or a metal strip (such as an aluminum strip or a copper strip), the first gate metal layer 322 on the surface of the third semiconductor chip 14 is electrically connected to the source S of the MOSFET 12, and the source S of the MOSFET 12 is electrically connected to the device source pin 403, the first pad area 4011 and the first gate metal layer 322 of the lead frame 400 respectively. The first pad area 4011 of the lead frame 400 has the same potential as the device source pin 403 and the KS pin 404. The gate G of the MOSFET 12 is electrically connected to the device gate pin 405. The drain D of the MOSFET 12 is electrically connected to the cascade metal layer 323, and then electrically connected to the source S of the HEMT 11. The schematic diagram of the front packaging structure is shown as follows. Figure 14 shown.

[0086] In step S414, the structure with metal interconnection is plastic-sealed, electroplated, laser-marked, cut and formed, and flash removed to obtain a single semiconductor cascade device.

[0087] In this embodiment, a substrate is not used, but a heat dissipation path independent of the HEMT 11 can still be provided for the MOSFET 12 , thereby achieving a better overall heat dissipation effect for the semiconductor cascade device.

[0088] Example 5 Figure 15 1 is a schematic diagram of the device packaging structure of the packaging step of the semiconductor cascade device according to the fifth embodiment of the present invention. The semiconductor cascade device in this embodiment is still a cascode device, and its electrical schematic diagram is as follows Figure 2 As shown, the electrode layout of the HEMT 11 and the MOSFET 12 is the same as that of the fourth embodiment. In this embodiment, the packaging method of the cascode device in this embodiment includes the following steps: In step S501, a HEMT 11 is provided and a conductive adhesive is applied on the back surface thereof. Alternatively, a metal layer may be deposited on the back surface of the HEMT 11 and the substrate 13.

[0089] Step S502: Mount the HEMT 11 on a temporary carrier 200 using a die bonding process. In this embodiment, the drain D, source S, and gate G of the HEMT 11 are all located on the front side of the chip.

[0090] In step S503, a first plastic encapsulation body 300 is formed for the HEMT 11. The first plastic encapsulation body 300 extends beyond the HEMT 11 in the x-direction by a preset distance. This preset distance corresponds to the mounting width of the MOSFET 12, for example, approximately equal to or less than the chip width of the MOSFET 12. Specifically, the first plastic encapsulation body 300 includes two regions: a left region 303 for encapsulating the HEMT 11, and a right region 304 for filling with molding compound. The first plastic encapsulation body 300 extends beyond the HEMT 11 in the z-direction by a preset distance.

[0091] Step S504 : drilling holes in the first area 303 and the second area 304 on the first plastic package body 300 to obtain first holes 302 .

[0092] In step S505, metal is grown in the hole to form a first redistribution layer 320 on the front surface of the first plastic package 300. The first redistribution layer 320 includes a first drain metal layer 321 electrically connected to the drain D of the HEMT 11, a first gate metal layer 322 electrically connected to the gate G of the HEMT 11, and a cascade metal layer 323 electrically connected to the source S of the HEMT 11 and the metal pillars within the second region 304.

[0093] Step S506 , removing the temporary carrier 200 , and obtaining a complete third semiconductor chip 14 .

[0094] From step S503 to step S506 , the fan-out packaging of the HEMT 11 is completed.

[0095] Step S507: Provide a lead frame 400 and mount the third semiconductor chip 14 on the lead frame 400. The structure of the lead frame 400 is adapted to the third semiconductor chip 14. In this embodiment, the chip pads in the first area 303 and the second area 304 of the lead frame 400 for mounting the first plastic package 300 are separated. Figure 13 , Figure 13This is a schematic diagram of the top structure of a lead frame according to a fourth embodiment of the present invention. Lead frame 400 includes a chip pad 401 and pins 402. Chip pad 401 includes a first pad area 4011 and a second pad area 4012, which are separated and insulated from each other. When the third semiconductor chip 14 is mounted on chip pad 401, the first area 303 of the third semiconductor chip 14 is soldered to the first pad area 4011 of chip pad 401, and the second area 304 of the third semiconductor chip 14 is soldered to the second pad area 4012. In this embodiment, four pins are included, but other lead frame configurations may also be used.

[0096] Step S508 : Mounting the MOSFET 12 on the cascade metal layer 323 on the surface of the third semiconductor chip 14 by a die bonding process.

[0097] Step S509: Metal interconnection. The first drain metal layer 321 on the surface of the third semiconductor chip 14 is connected to the device drain pin 402 of the lead frame 400 via bonding wires or metal ribbons (e.g., aluminum or copper ribbons). The first gate metal layer 322 on the surface of the third semiconductor chip 14 is electrically connected to the source electrode S of the MOSFET 12. The source electrode S of the MOSFET 12 is electrically connected to the device source pin 403 of the lead frame. The first pad area 4011 of the lead frame 400 is at the same potential as the device source pin 403 and the KS pin 404. The gate G of the MOSFET 12 is electrically connected to the device gate pin 405. The drain electrode D of the MOSFET 12 is electrically connected to the cascade metal layer 323, thereby achieving electrical connection with the source electrode S of the HEMT 11.

[0098] In step S510 , the structure with metal interconnection is subjected to plastic encapsulation, electroplating, laser marking, rib cutting and forming, and burr removal, thereby obtaining a single semiconductor cascade device.

[0099] Example 6 When the semiconductor cascade device is a cascode device, a circuit such as a capacitor, a resistor, a diode or a circuit composed of a combination of these can also be embedded in the device. Figure 16 As shown, Figure 16This is an electrical schematic diagram of the first semiconductor cascade device in the sixth embodiment of the present invention. A capacitor Cx is connected between the drain D and source S of the MOSFET 12. By adding the capacitor Cx between the MOSFET 12 and the HEMT 11, charge balance can be achieved, which can ensure that the voltage between the drain and source of the MOSFET 12 and between the gate and source of the HEMT 11 under dynamic switching behavior will not produce a large overshoot spike, thereby avoiding the frequent avalanche breakdown of the MOSFET 12 during the switching process, which may cause the cascade device to fail. With respect to this circuit structure, the packaging structure of this embodiment includes a substrate 13, and the metal layer on the front surface and the back metal layer of the substrate 13 constitute the capacitor Cx. The thickness of the substrate 13 and the type of dielectric are determined according to the parameter requirements. Its packaging structure can adopt any one of the packaging structures in the aforementioned embodiments one to three. For example, Figure 17 corresponds to Figure 16 The schematic diagram of the package structure of the semiconductor cascade device with the electrical principle shown is shown in FIG. The substrate 13 is equivalent to the capacitor Cx.

[0100] For example, see Figure 18 , Figure 18 This is an electrical schematic diagram of the second semiconductor cascade device according to the sixth embodiment of the present invention, in which a resistor R is connected between the drain D and source S of the MOSFET 12. By adding the resistor R between the MOSFET 12 and the HEMT 11, leakage balance can be achieved, ensuring that in static shutdown, the voltage between the drain and source of the MOSFET 12 and between the gate and source of the HEMT 11 will not produce a large overshoot spike, thereby avoiding the failure of the cascade device due to frequent avalanche breakdown of the MOSFET 12 during the switching process. Figure 18 The packaging structure of the semiconductor cascade device with the electrical principle shown is also as shown in Figure 17 The substrate 13 corresponds to the resistor R.

[0101] In addition, in the Cascode device, a parallel circuit of a diode and a resistor, and a parallel circuit of a capacitor and a resistor may be included between the drain and source of the MOSFET 12, and the corresponding packaging structure of the Cascode device may also be as follows: Figure 17 As shown, no further details are given here.

[0102] In addition, there are other ways to connect resistors, capacitors, and diodes to Cascode devices. Figure 19 , Figure 19This is an electrical schematic diagram of the third semiconductor cascade device in Example 6 of the present invention. In this embodiment, two reverse-parallel diodes are included between the gate G and source S of MOSFET12. By adding two reverse-parallel diodes at both ends of the gate and source of MOSFET12, the voltage at both ends of the gate and source of MOSFET12 is stabilized, protecting the gate and source of the device from ESD damage, thereby improving the ESD protection capability. When the diode circuit is integrated into the substrate 13, according to the circuit connection relationship and the function of the heat dissipation path of the substrate 13, see Figure 20 , Figure 20 1 is a schematic diagram of the front structure of the substrate 13 according to the sixth embodiment of the present invention. Figure 21 1 is a schematic diagram of the back structure of the substrate 13 according to the sixth embodiment of the present invention. The front side of the substrate 13 includes two mutually isolated first front metal layers 131 and second front metal layers 132, and the back side includes a back metal layer 133. Figure 19 The two electrical connection points of the diode circuit are the second front metal layer 132 and the back metal layer 133 of the substrate 13. When the cascode device of this embodiment is packaged, the first front metal layer 131 and the second front metal layer 132 are simultaneously fanned out to the surface of the plastic package. The first front metal layer 131 of the substrate 13 and the fan-out metal layer of the source S of the HEMT 11 are integrated to form a cascade metal layer 323. The second front metal layer 132 of the substrate 13 is fanned out to the surface of the plastic package to form a metal layer 324. Figure 22 and Figure 23 , Figure 22 corresponds to Figure 19 Schematic diagram of the packaging structure of a semiconductor cascade device showing the electrical principle. Figure 23 corresponds to Figure 19 Schematic diagram of the front side of the packaging structure of the semiconductor cascade device with the electrical principle shown. In this embodiment, the fan-out packaging method for the HEMT 11 electrode is the same as that in the third embodiment, that is, a redistribution layer is formed inside the plastic package to fan out the gate G of the HEMT 11 to the back side. In this embodiment, the diode circuit is integrated into the substrate 13, and one of its electrical connection points is located on the back side of the substrate 13 and is electrically connected to the gate G of the HEMT 11 through the third redistribution layer 340. The second electrical connection point of the diode circuit is the second front metal layer 132 of the substrate 13, which is fanned out to the front side of the plastic package, that is, Figure 23 When mounting the MOSFET 12, the MOSFET 12 is mounted on the cascade metal layer 323 using a die bonding process. During metal interconnection, the source S of the MOSFET 12 is electrically connected to the die pad 401 of the lead frame 400, and the gate G of the MOSFET 12 is electrically connected to the metal layer 324 and the device gate pin 405 of the lead frame 400.

[0103] As can be seen from Example 6, when passive or active components are integrated via the substrate 13, corresponding connection points are formed on the substrate 13 according to the connection relationship with the HEMT 11 and the MOSFET 12. These connection points are then led out to the front or back side of the third semiconductor chip 14 via a fan-out package, thereby achieving electrical connection with the HEMT 11 and the MOSFET 12 during metal interconnection.

[0104] The passive components and active components and their combination constitute a circuit in this embodiment, which is integrated in the substrate 13. However, they can also be integrated in the HEMT 11. When integrated in the HEMT 11, corresponding connection electrodes are formed on the chip surface when necessary according to the electrical connection relationship. For example, for Figure 16 In the circuit shown in FIG. 1 , when a capacitor Cx is formed between the source S and the gate G of the HEMT 11, no external connection electrode needs to be reserved. A similar structure can also be Figure 18 The circuit shown. Figure 19 In the circuit shown, an electrical connection electrode for the diode circuit is reserved on the front surface of the HEMT 11 chip for electrical connection to the gate G of the MOSFET 12. Therefore, when the electrodes of the HEMT 11 are fanned out and packaged, the connection electrode and drain D of the diode circuit on the front surface are simultaneously fanned out and packaged onto the front surface of the third semiconductor chip 14. During metal interconnection, conventional interconnection methods are used to electrically connect to the gate G of the MOSFET 12.

[0105] In addition, the substrate 13 and the components integrated thereon can also be replaced with other chips according to the needs of the cascade device, such as Figure 24 As shown, Figure 24 FIG1 is an electrical schematic diagram of a fourth semiconductor cascade device according to a sixth embodiment of the present invention. In this embodiment, another enhancement mode device is connected in parallel to the drain and source of the MOSFET 12, such as the second MOSFET 15 in the figure. According to the position of the MOSFET chip electrodes, when the third semiconductor chip 14 is formed in the fan-out package, various packaging structures can be formed, such as Figure 25 As shown, Figure 25 corresponds to Figure 24 The schematic diagram of the packaging structure of the semiconductor cascade device with the electrical principle shown in FIG. The drain D and gate G of the second MOSFET 15 are distributed on the front of the chip, and the source S is distributed on the back of the chip. Figure 25In the illustrated package structure, the fan-out packaging method for the HEMT 11 electrodes is the same as in Example 3. Since the gate G of the second MOSFET 15 is not connected to the other two chips, it does not need to be extended outside the third semiconductor chip 14. Instead, the drain D of the second MOSFET 15 is extended upward, forming a cascade metal layer 323 on the front surface of the third semiconductor chip 14. When the MOSFET 12 is mounted on the cascade metal layer 323, it is electrically connected to the drain D on the back surface of the MOSFET 12. The gate G of the HEMT 11 is fanned out to the back surface of the third semiconductor chip 14 through an internal redistribution layer and electrically connected to the third redistribution layer 340. The source S of the second MOSFET 15 is electrically connected to the third redistribution layer 340 on the back surface of the third semiconductor chip 14, thereby establishing an electrical connection between the source S of the second MOSFET 15 and the gate G of the HEMT 11. In this embodiment, the second MOSFET 15 not only realizes the electrical connection relationship with the other two chips, but also provides a heat dissipation path for the MOSFET 12. Moreover, since it is packaged internally, the distance from the HEMT 11 can be minimized, thereby reducing the overall volume of the semiconductor cascade device.

[0106] Figure 26 is an electrical schematic diagram of a fifth semiconductor cascade device according to a sixth embodiment of the present invention, Figure 27 corresponds to Figure 26 Schematic diagram of the package structure of a semiconductor cascade device according to the electrical principle shown. In this embodiment, the drain D of the second MOSFET 15 is electrically connected to the drain D of the MOSFET 12 and the source S of the HEMT 11; the gate G of the second MOSFET 15 is electrically connected to the source S of the MOSFET 12 and the gate G of the HEMT 11; the source S of the second MOSFET 15 has no electrical connection. Correspondingly, see Figure 27 The drain D and source S of the second MOSFET 15 are located on the front side of the chip, and the gate G is located on the back side. The drain D of the second MOSFET 15 is extended upward to form a cascade metal layer 323 on the front side of the third semiconductor chip 14. When the MOSFET 12 is mounted on the cascade metal layer 323, it is electrically connected to the drain D on the back side of the MOSFET 12. The gate G of the HEMT 11 is fanned out to the back side of the third semiconductor chip 14 through an internal redistribution layer and is electrically connected to the third redistribution layer 340. The gate G of the second MOSFET 15 is electrically connected to the third redistribution layer 340 on the back side of the third semiconductor chip 14, thereby achieving an electrical connection between the gate G of the second MOSFET 15 and the gate G of the HEMT 11.

[0107] Figure 28 is an electrical schematic diagram of a sixth semiconductor cascade device according to a sixth embodiment of the present invention, Figure 29 corresponds to Figure 28 Schematic diagram of the packaging structure of a semiconductor cascade device according to the electrical principle shown. In this embodiment, the drain D of the second MOSFET 15 is electrically connected to the drain D of the MOSFET 12 and the source S of the HEMT 11; the gate G and source S of the second MOSFET 15 are also electrically connected to the source S of the MOSFET 12 and the gate G of the HEMT 11. Correspondingly, see Figure 29 The drain D of the second MOSFET 15 is located on the front side of the chip, while the gate G and source S are located on the back side. This embodiment utilizes the same fan-out packaging as the third embodiment, fanning out the drain D of the second MOSFET 15 to the front side of the third semiconductor chip 14 and forming a cascade metal layer 323. When the MOSFET 12 is mounted on the cascade metal layer 323, the drain D of the second MOSFET 15 is electrically connected to the drain D on the back side of the MOSFET 12. The gate G and source S of the second MOSFET 15 are electrically connected to the third redistribution layer 340 on the back side of the third semiconductor chip 14, thereby electrically connecting the gate G and source S of the second MOSFET 15 to the gate G of the HEMT 11.

[0108] Figure 30 is an electrical schematic diagram of the seventh semiconductor cascade device according to the sixth embodiment of the present invention, Figure 31 corresponds to Figure 30 Schematic diagram of the packaging structure of a semiconductor cascade device with the electrical principle shown. In this embodiment, the drain D of the second MOSFET 15 is not electrically connected to other chips, and the gate G and source S of the second MOSFET 15 are electrically connected to the source S of the MOSFET 12 and the gate G of the HEMT 11. Correspondingly, see Figure 31 The drain D of the second MOSFET 15 is located on the front side of the chip, while the gate G and source S are located on the back side. In this embodiment, a metal layer insulated from the drain D is grown on the front side of the second MOSFET 15, fanning out to the front surface of the third semiconductor chip 14 to form a cascade metal layer 323. The gate G and source S of the second MOSFET 15 are electrically connected to the third redistribution layer 340 on the back side of the third semiconductor chip 14, thereby electrically connecting the gate G and source S of the second MOSFET 15 to the gate G of the HEMT 11. Although the drain D of the second MOSFET 15 in this embodiment is not electrically connected, it can still be connected to the MOSFET 12 through the metal layer on its surface, providing a heat dissipation path for the MOSFET 12.

[0109] As can be seen from the aforementioned embodiment, based on the electrode distribution of the second MOSFET 15 and its electrical connection with the HEMT 11 and MOSFET 12, fan-out packaging not only achieves the corresponding electrical connection but also provides a heat dissipation path for the MOSFET 12 in the cascade device. The other electrical connections between the second MOSFET 15 and the HEMT 11 and MOSFET 12, as well as the corresponding packaging structure, are not further described.

[0110] Example 7 Figure 32 1 is a schematic diagram of the packaging structure in some steps of the semiconductor cascade device packaging method according to the seventh embodiment of the present invention. In this embodiment, the cascode device is still taken as an example. The packaging structure of the cascode device in this embodiment includes a depletion-mode HEMT 11, an enhancement-mode MOSFET 12, and a substrate 13. The three electrodes of the HEMT 11 are located on the front side of the chip, the drain D of the MOSFET 12 is located on the back side of the chip, and the gate G and source S of the MOSFET 12 are located on the front side of the chip. The substrate 13 in this embodiment can be the substrate 13 of the aforementioned embodiments 1 to 3, or it can be a substrate with integrated components or circuits as in the sixth embodiment, or it can be replaced by other chips. Some steps in the semiconductor cascade device packaging method of this embodiment are the same as those in the third embodiment, that is, the third semiconductor chip 14 is obtained according to steps S201 to S211 in the third embodiment, and then the following steps are continued: Step S711 : Mounting the MOSFET 12 on the cascade metal layer 323 on the surface of the third semiconductor chip 14 by a die bonding process.

[0111] In step S712 , a third layer of metal pillars is formed on the first drain metal layer 321 and the electrode surfaces of the source S and the gate G of the MOSFET 12 .

[0112] Step S713 , plastic-encapsulating the current structure to obtain a third plastic-encapsulated body 306 .

[0113] Step S714 , grinding the front surface of the third plastic package body 306 to expose the surface of the third layer of metal pillars.

[0114] In step S715, a fourth redistribution layer 350 is formed on the front surface of the third plastic package 306 where the surface of the third metal pillar is exposed. The fourth redistribution layer 350 includes a fourth drain metal layer 351 electrically connected to the drain D of the HEMT 11, a fourth source metal layer 352 electrically connected to the source S of the MOSFET 12, and a fourth gate metal layer 353 electrically connected to the gate G of the MOSFET 12. Each metal layer extends to a position a suitable distance outside the package boundary of the third semiconductor chip 14.

[0115] Step S716 , removing the current temporary carrier 200 , and mounting the current structure on the temporary carrier 200 with the fourth redistribution layer 350 facing downward.

[0116] In step S717, a hole is drilled on the back side of the third plastic package 306 to form the first hole 302. Specifically, a hole is drilled at the location where the gate G of the HEMT 11 needs to be led out until it reaches the second gate metal layer 332 in the second redistribution layer 330. Holes are then drilled at locations corresponding to the fourth drain metal layer 351 electrically connected to the drain D of the HEMT 11, the fourth source metal layer 352 electrically connected to the source S of the MOSFET 12, and the fourth gate metal layer 353 electrically connected to the gate G of the MOSFET 12, until each metal layer is connected.

[0117] In step S718, a metal column is formed in the hole and a third redistribution layer 340 is formed on the surface by electroplating, wherein the third redistribution layer 340 includes three metal layers separated from each other, including a third drain metal layer 3041 serving as the drain D of the cascade device, a third source metal layer 3042 serving as the source S of the cascade device, and a third gate metal layer 3043 serving as the gate G of the cascade device.

[0118] In step S719 , the temporary carrier 200 is removed, and subsequent processing such as plastic encapsulation and electroless metal plating on the electrode surface is performed to obtain a single semiconductor cascade device.

[0119] In this embodiment, metal interconnection is achieved through the metal structure of the fan-out package, such as the redistribution layer and the metal pillars, thereby omitting the lead frame.

[0120] Example 8 Figure 33: This is a schematic diagram of the packaging structure of a semiconductor cascode device according to an eighth embodiment of the present invention. In this embodiment, the cascode device is still used as an example. The packaging structure of the cascode device in this embodiment includes a depletion-mode HEMT 11, an enhancement-mode MOSFET 12, and a substrate 13. The three electrodes of the HEMT 11 are located on the front side of the chip, the drain of the MOSFET 12 is located on the back side of the chip, and the gate and source of the MOSFET 12 are located on the front side of the chip. The packaging method of this eighth embodiment differs from the packaging method of the third embodiment in step S208. The other steps are the same and will not be repeated here. In step S208 of this eighth embodiment, when a first redistribution layer 320 is formed on the front surface of the second plastic package 301, where the surface of the second layer of metal pillars is exposed, the first redistribution layer 320 includes a first drain metal layer 321 electrically connected to the drain D of the HEMT 11, a source metal layer 325 electrically connected to the source S of the HEMT 11, and a cascade metal layer 323 electrically connected to the front metal layer of the substrate 13. When mounting the MOSFET 12, the drain D on the back side of the MOSFET 12 is partially mounted on the source metal layer 325 electrically connected to the source S of the HEMT 11, and partially mounted on the cascade metal layer 323. In a preferred embodiment, the area of ​​the source metal layer 325 is smaller than that of the cascade metal layer 323. For example, the area of ​​the cascade metal layer 323 can be at least three times the area of ​​the source metal layer 325.

[0121] The wiring structure in this embodiment, in which the source metal layer 325 is separated from the cascade metal layer 323, facilitates testing. Specifically, after the HEMT 11 and substrate 13 are packaged to obtain the third semiconductor chip 14, the HEMT 11 and substrate 13 can be independently tested to determine whether their respective functions are functioning properly. This is particularly advantageous when the substrate 13 integrates components or is itself a chip.

[0122] Secondly, interference between different circuits is prevented. Because the main power circuit is between HEMT 11 and MOSFET 12, the operating current of the Cascade device primarily flows through this main power circuit. The current flowing between substrate 13 and MOSFET 12 is much smaller than the current in the main power circuit. When the source metal layer 325 is separated from the cascade metal layer 323, the two circuits can be separated, effectively preventing interference between the circuits.

[0123] In addition, heat dissipation is improved. The heat dissipation path of the MOSFET 12 in this embodiment is shown by the arrows in the figure. When the cascade metal layer 323 is separated from the source metal layer 325 and the area of ​​the cascade metal layer 323 is larger than that of the source metal layer 325, most of the heat from the MOSFET 12 is conducted through the cascade metal layer 323 and the substrate 13. This prevents some heat from being conducted back to the HEMT 11 through the source metal layer 325 when the cascade metal layer 323 and the source metal layer 325 are integrated.

[0124] The first redistribution layer structure of this embodiment is also applicable to other embodiments and will not be described in detail here.

[0125] Embodiment 9 Figure 34 FIG2 is a schematic diagram of the packaging structure of a semiconductor cascade device according to a ninth embodiment of the present invention. In this embodiment, the three electrodes of MOSFET 12 are located on the front side of the chip. Therefore, in the packaging structure of this semiconductor cascade device, during metal interconnection, the drain D on the front side of the MOSFET 12 chip is connected to the cascade metal layer 323 via wire bonding. Because the cascade metal layer 323 is integrally connected to the fan-out metal layer of the source S of the HEMT 11, electrical connection is achieved between the drain D of the MOSFET 12 and the source S of the HEMT 11. The remaining structure is the same as that of the previous embodiment and will not be further described here.

[0126] In addition, since the electrode distribution of the first semiconductor chip in the semiconductor cascade device may vary, it can be determined whether the electrode lead-out needs to be transferred through a redistribution layer within the package based on the electrode distribution. For example, when the gate of the HEMT 11 is located on the back side of the chip, the intermediate second redistribution layer 330 is not required.

[0127] In the aforementioned embodiments using cascodes as an example, a depletion-mode (D-mode) HEMT is used as the first semiconductor chip, and an enhancement-mode (E-mode) MOSFET is used as the second semiconductor chip. The HEMT is fanned out first. However, it is understood that the first semiconductor chip can also be a D-mode MOSFET, a D-mode J FET, or other D-mode device; and the second semiconductor chip can also be an E-mode HEMT or other E-mode device. Furthermore, the positions of the two types of chips can be swapped during packaging, with the E-mode device serving as the first semiconductor chip and the D-mode device serving as the second semiconductor chip, with the E-mode device fanned out first. The packaging method remains the same and is not further described here.

[0128] In the electrical structures of other semiconductor cascade devices, the semiconductor cascade devices may be composed of semiconductor chips and integrated chips, such as HEMT and its driver IC chip. Semiconductor devices with such electrical structures may still be packaged using the packaging method provided by the present invention.

[0129] The semiconductor cascade device provided by the present invention has high integration and good heat dissipation effect. It can flexibly match passive devices such as capacitors and resistors or active devices such as diodes in the semiconductor device as needed, thereby improving the performance of the device. In addition, discrete chips or integrated chips can be selected based on product needs, which makes product design more flexible.

[0130] The above embodiments are only used to illustrate the present invention, and are not intended to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A method for packaging a semiconductor cascade device, wherein the semiconductor cascade device comprises a first semiconductor chip and a second semiconductor chip in an electrically connected relationship, wherein the first semiconductor chip comprises a plurality of first electrodes, and the second semiconductor chip comprises a plurality of second electrodes, wherein: The packaging method of the semiconductor cascade device includes: Performing electrode fan-out packaging on the first semiconductor chip to obtain a third semiconductor chip, and forming a first redistribution layer on the front surface of the third semiconductor chip, wherein the third semiconductor chip includes a first region and a second region arranged laterally, the first region encapsulating the first semiconductor chip, and the second region including a heat dissipation path; the first redistribution layer includes a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a portion of the front surface of the second region, the cascade metal layer being connected to the heat dissipation path in the second region; mounting a second semiconductor chip on the cascade metal layer; Performing metal interconnection between the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve electrical connection between the first semiconductor chip and the second semiconductor chip and obtain a structure including a plurality of device electrodes of the semiconductor cascade device; and The structure with metal interconnection is plastic-sealed to obtain the semiconductor cascade device.

2. The method for packaging a semiconductor cascade device according to claim 1, wherein: The step of performing fan-out packaging of electrodes on the first semiconductor chip to obtain a third semiconductor chip includes: Performing a first fan-out package of electrodes on the first semiconductor chip to form a second redistribution layer, wherein the second redistribution layer includes a first electrode fan-out metal layer extending toward the front surface and a first electrode fan-out metal layer extending beyond the first semiconductor chip body toward the back surface; The first electrode fan-out metal layer led out to the front is packaged on the front side, and the first electrode fan-out metal layer led out to the back side is packaged on the back side. A first redistribution layer is formed on the front side of the third semiconductor chip obtained after the packaging, and a third redistribution layer is formed on the back side of the third semiconductor chip. The first redistribution layer includes the first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a partial surface of the front side of the second area. The third redistribution layer includes at least the first electrode fan-out metal layer.

3. The method for packaging a semiconductor cascade device according to claim 1 or 2, wherein: The step of performing fan-out packaging of electrodes on the first semiconductor chip includes: Arranging a first semiconductor chip and a third structure in parallel, wherein the front side and the back side of the third structure respectively include a metal layer; and Performing fan-out packaging of electrodes on the first semiconductor chip and the third structure arranged in parallel to obtain a third semiconductor chip, and forming a first redistribution layer on the front surface of the third semiconductor chip; The first semiconductor chip is encapsulated in the first area of ​​the third semiconductor chip, and the third structure is encapsulated in the second area to form the heat dissipation path; the first redistribution layer includes a cascade metal layer obtained by fanning out the front metal layer of the third structure and covering at least part of the front surface of the second area.

4. The method for packaging a semiconductor cascade device according to claim 1 or 2, wherein: When the first semiconductor chip is fanned out to encapsulate the electrodes, a second region extending beyond the first semiconductor chip body is obtained. A metal column penetrating the second region is formed inside the second region, and the metal column forms the heat dissipation path.

5. The method for packaging a semiconductor cascade device according to claim 1, wherein: When the first redistribution layer is formed on the front surface of the third semiconductor chip, the first electrode fan-out metal layer of the first semiconductor chip and the cascade metal layer covering at least the partial front surface of the second area are insulated and separated from each other; or, a first electrode fan-out metal layer of the first semiconductor chip and the cascade metal layer are formed integrally; or, the cascade metal layer extends from the partial front surface of the second area to the partial front surface of the first area.

6. The method for packaging a semiconductor cascade device according to claim 1, wherein: The step of metal interconnecting the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve an electrical connection between the first semiconductor chip and the second semiconductor chip includes: mounting the third semiconductor chip on a lead frame, wherein the lead frame includes device pins serving as device electrodes; and The metal interconnections are performed by bonding wires using a wire bonding process, or by metal strips using a strip bonding process, or by metal sheets using a pressure welding bridge process.

7. The method for packaging a semiconductor cascade device according to claim 1, wherein: The step of metal interconnecting the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve an electrical connection between the first semiconductor chip and the second semiconductor chip includes: The first electrode fan-out metal layer and the second electrode of the second semiconductor chip are fan-out packaged once or multiple times. During each fan-out package, the electrical connection between the first semiconductor chip and the second semiconductor chip is achieved through the redistribution layer.

8. A semiconductor cascade device, characterized in that: include: a third semiconductor chip comprising a first region and a second region arranged laterally, wherein the first region encapsulates a first semiconductor chip, and the second region comprises a heat dissipation path; a first redistribution layer is formed on a front surface of the third semiconductor chip, the first redistribution layer comprising a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a portion of the front surface of the second region, the cascade metal layer being connected to the heat dissipation path in the second region; a second semiconductor chip mounted on the cascade metal layer; A metal interconnect structure is connected to the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve an electrical connection between the first semiconductor chip and the second semiconductor chip and obtain a plurality of device electrodes of the semiconductor cascade device.

9. The semiconductor cascade device according to claim 8, characterized in that The interior of the third semiconductor chip also includes a second redistribution layer, which includes a first electrode fan-out metal layer extending to the front and a first electrode fan-out metal layer extending to the back side beyond the first semiconductor chip body; correspondingly, the back surface of the third semiconductor chip includes a third redistribution layer, which includes at least the first electrode fan-out metal layer.

10. The semiconductor cascade device according to claim 8 or 9, characterized in that: The second region of the third semiconductor chip includes a metal column penetrating the second region for forming a heat dissipation path, and the top of the metal column is connected to the cascade metal layer.

11. The semiconductor cascade device according to claim 8 or 9, characterized in that: A third structure is encapsulated inside the second area of ​​the third semiconductor chip, and the front and back sides of the third structure respectively include metal layers; correspondingly, part or all of the cascade metal layer in the first redistribution layer is a fan-out metal layer of the front metal layer of the third structure, and the third structure and its fan-out metal structure form the heat dissipation path.

12. The semiconductor cascade device according to claim 11, wherein: The front metal layer and / or back metal layer of the third structure are one or two or more layers insulated from each other.

13. The semiconductor cascade device according to claim 12, wherein: The third structure is a substrate, a substrate integrated with an embedded circuit, or a fourth semiconductor chip; When the third structure is a substrate integrated with an embedded circuit, the front metal layer and / or the back metal layer are electrical connection points of the embedded circuit; When the third structure is a fourth semiconductor chip, the front metal layer and / or the back metal layer are electrodes of the fourth semiconductor chip.

14. The semiconductor cascade device according to claim 13, wherein: The embedded circuit includes any combination of one or more of a resistor, a capacitor, and a diode.

15. The semiconductor cascade device according to claim 8, wherein: The back side of the second semiconductor chip includes a second electrode, a first electrode fan-out metal layer of the first semiconductor chip is electrically connected to the second electrode on the back side of the second semiconductor chip and is insulated and separated from the cascade metal layer, and the second electrode of the second semiconductor chip is simultaneously mounted on the first electrode fan-out metal layer and the cascade metal layer that are electrically connected to it.

16. The semiconductor cascade device according to claim 8, wherein: The back side of the second semiconductor chip includes a second electrode, a first electrode fan-out metal layer of the first semiconductor chip is electrically connected to the second electrode on the back side of the second semiconductor chip, and the first electrode fan-out metal layer electrically connected to the second electrode on the back side of the second semiconductor chip is integrally connected to the cascade metal layer.

17. The semiconductor cascade device according to claim 8, wherein: The first semiconductor chip is a depletion-mode semiconductor chip, and the second semiconductor chip is an enhancement-mode semiconductor chip; or the first semiconductor chip is an enhancement-mode semiconductor chip, and the second semiconductor chip is a depletion-mode semiconductor chip; Alternatively, the second semiconductor chip is a driver IC chip of the first semiconductor chip; Alternatively, the first semiconductor chip is a driver IC chip of the second semiconductor chip.

18. The semiconductor cascade device according to claim 8, wherein: The second semiconductor chip body partially overlaps with the first semiconductor chip body in a longitudinal direction.

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