Packaging structure and electronic equipment
By setting through-hole vias on the interposer to achieve vertical interconnection between HBM and Logic IC/SOC, the problems of multiple wiring layers occupied and long wiring length are solved, and the signal quality and transmission efficiency are improved.
Patent Information
- Application Number
- CN202510706460.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2025-09-26
AI Technical Summary
The connection method between HBM and Logic IC/SOC requires more routing layers and longer wiring length, which affects signal integrity.
An interposer is used to arrange the first chip and the second chip on opposite surfaces in the thickness direction thereof, and vertical interconnection is achieved through through-holes, thereby reducing the need for horizontal wiring and shortening the signal transmission path.
Optimize wiring layers, reduce trace length, improve signal quality, simplify wiring requirements, reduce system design complexity, and improve signal transmission efficiency.
Smart Images
Figure CN120709243A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the field of semiconductor technology, and particularly relates to a packaging structure and an electronic device. Background Art
[0002] HBM (High Bandwich Memory) is connected to the Logic IC (Logic Chip) / SOC (System on Chip) through an interposer using an SBS (side by side) approach. This approach requires more routing layers and wiring layers, and the routing length is longer, affecting the chip signal integrity. Summary of the Invention
[0003] The present disclosure aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the embodiments of the present disclosure provide a packaging structure that is conducive to optimizing wiring layers, reducing wiring lengths, and improving signal quality.
[0004] The present disclosure also provides an electronic device.
[0005] The packaging structure of the embodiment of the present disclosure includes an interposer, a first chip, and a second chip. The interposer has a first surface and a second surface opposite to each other in the thickness direction of the interposer, and the interposer has a through hole passing through the thickness direction of the interposer; the first chip is arranged on the first surface of the interposer; the second chip is arranged on the second surface of the interposer, and the second chip and the first chip are interconnected through the through hole.
[0006] Optionally, there are multiple first chips, at least one first chip among the multiple first chips is interconnected with the second chip through the through-hole, and the remaining first chips among the multiple first chips are interconnected with the at least one first chip, so as to be interconnected with the second chip through the at least one first chip.
[0007] Optionally, there is one second chip, one first chip among multiple first chips is interconnected with the second chip through the through-hole, and the remaining first chips among the multiple first chips are interconnected with the one first chip through the routing in the interposer, so as to be interconnected with the second chip through the one first chip.
[0008] Optionally, there are multiple first chips and multiple second chips, at least one first chip among the multiple first chips is interconnected with the multiple second chips through the through-holes, and the remaining first chips among the multiple first chips are interconnected with the at least one first chip, so as to be interconnected with the second chip through the at least one first chip.
[0009] Optionally, one first chip among the multiple first chips is interconnected with the multiple second chips through the through-holes, and the remaining first chips among the multiple first chips are respectively interconnected with the one first chip through the routing in the interposer, so as to be interconnected with the second chip through the one first chip.
[0010] Optionally, the intermediate layer has a thickness of 20 μm to 60 μm.
[0011] Optionally, the packaging structure further includes a plastic package, and the plastic package is provided on the first surface of the interposer to wrap the first chip.
[0012] Optionally, the first chip includes a logic chip, and the second chip includes a memory chip.
[0013] Optionally, the packaging structure further includes a substrate, which is disposed on a side of the first chip facing the interposer, and the interposer and the second chip are both disposed on the substrate.
[0014] Optionally, the interposer and the second chip are both embedded in the substrate.
[0015] Optionally, the interposer is located between the first chip and the substrate, and the second chip is embedded in the substrate.
[0016] Optionally, there are multiple first chips, and at least one first chip is electrically connected to the substrate.
[0017] Optionally, the at least one first chip is electrically connected to the substrate through the through-hole in the interposer.
[0018] The electronic device in the embodiment of the present disclosure includes a printed circuit board and a packaging structure, the packaging structure is the above-mentioned packaging structure, and the printed circuit board is connected to the packaging structure.
[0019] The packaging structure of the embodiment of the present disclosure achieves vertical interconnection between the second chip and the first chip by respectively placing the first chip and the second chip on the first surface and the second surface opposite to each other in the thickness direction of the interposer, and providing a through-hole in the thickness direction of the interposer. The second chip and the first chip are vertically interconnected through the through-hole, so that the signal can be directly transmitted vertically, thereby reducing the need for horizontal wiring, thereby reducing the occupation of routing layer and wiring layer resources, and also reducing the routing length between the second chip and the first chip, shortening the signal transmission path, which is conducive to improving signal quality. In addition, the second chip and the first chip are vertically interconnected through the through-hole, and the pin layout of the first chip can be optimized by adjusting the interconnection position between the first chip and the second chip, thereby avoiding the design limitation of the first chip caused by the PHY interconnected with the second chip being located on the side close to the second chip when the first chip and the second chip are arranged side by side. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a structural diagram of the packaging structure of the first embodiment of the present disclosure.
[0021] Figure 2 It is a structural diagram of the packaging structure of the second embodiment of the present disclosure.
[0022] Reference numerals:
[0023] 1. Intermediary layer; 11. First surface; 12. Second surface; 13. Through hole;
[0024] 2. First chip;
[0025] 3. Second chip;
[0026] 4. Base plate; 41. First accommodating cavity; 42. Second accommodating cavity;
[0027] 5. Pins. DETAILED DESCRIPTION
[0028] The embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to be used to explain the present disclosure, but should not be understood as limiting the present disclosure.
[0029] Example 1
[0030] like Figure 1 As shown, the package structure of the embodiment of the present disclosure includes an interposer 1, a first chip 2, and a second chip 3. The interposer 1 has a first surface 11 and a second surface 12 that are opposite to each other in the thickness direction of the interposer 1. The interposer 1 has a through-hole 13 that runs through the thickness direction of the interposer 1. The first chip 2 is disposed on the first surface 11 of the interposer 1; the second chip 3 is disposed on the second surface 12 of the interposer 1, and the second chip 3 and the first chip 2 are interconnected through the through-hole 13.
[0031] The interposer 1 may be a silicon interposer or a glass substrate interposer.
[0032] In detail, the through-hole 13 may be a through-silicon via 13 , which is formed by drilling a hole in the interposer 1 and filling the hole with a conductive material such as metal to realize vertical interconnection between the first chip 2 and the second chip 3 .
[0033] The packaging structure of the embodiment of the present disclosure is achieved by arranging the first chip 2 and the second chip 3 on the first surface 11 and the second surface 12 opposite to each other in the thickness direction of the interposer 1, respectively, and providing a through hole 13 in the thickness direction of the interposer 1. The second chip 3 and the first chip 2 are vertically interconnected through the through hole 13, so that the signal can be directly transmitted vertically, reducing the need for horizontal wiring, thereby reducing the occupation of the routing layer and wiring layer resources of the interposer 1, and also reducing the routing length between the second chip 3 and the first chip 2, shortening the signal transmission path, which is conducive to improving signal quality. In addition, the second chip 3 and the first chip 2 are vertically interconnected through the through hole 13. By adjusting the position of the interconnection between the first chip 2 and the second chip 3, the pin 5 layout of the first chip 2 is optimized, avoiding the design limitation of the first chip 2 caused by the PHY (Port Physical Layer) interconnected with the second chip 3 must be located on the side close to the second chip 3 when the first chip 2 and the second chip 3 are arranged side by side.
[0034] In some embodiments, the first chip 2 includes a logic chip, and the second chip 3 includes a memory chip.
[0035] The logic chip may be a CPU chip, a GPU chip, or an XPU chip. The memory chip may be an HBM (High Bandwich Memory) chip or a memory chip. The logic chip can achieve higher memory bandwidth and faster memory access speeds through HBM technology, enabling faster data transmission and improved computing efficiency. The specific types of the first chip 2 and the second chip 3 can be set according to actual needs and are not limited here.
[0036] It can be understood that the first chip 2 includes a logic chip and the second chip 3 includes a memory chip. By integrating chips with different functions in the same package, the data transmission path can be significantly shortened, which is conducive to improving the data transmission rate, reducing the energy required for signal transmission, and saving space.
[0037] In some embodiments, there are multiple first chips 2, at least one first chip 2 among the multiple first chips 2 is interconnected with the second chip 3 through a through-hole 13, and the remaining first chips 2 among the multiple first chips 2 are interconnected with at least one first chip 2, so as to be interconnected with the second chip 3 through at least one first chip 2.
[0038] Specifically, when multiple first chips 2 are provided, the first chips 2 may be two, three, or four, etc. The number of first chips 2 may be set according to actual needs to improve the performance after packaging. One or more of the multiple first chips 2 may be interconnected with the second chip 3 via the through-holes 13, and the remaining first chips 2 are respectively connected to the first chips 2 interconnected with the second chip 3, thereby enabling the second chip 3 to be interconnected via the first chip 2 interconnected with the second chip 3.
[0039] It is understood that by providing multiple first chips 2, if the multiple first chips 2 are of the same type, integrating the multiple first chips 2 of the same type can improve the performance of the package structure; if the multiple first chips 2 are of different types, the package structure can support multiple functions. Integrating multiple first chips 2 in a single package can save space and reduce signal transmission distance.
[0040] In some embodiments, as Figure 1 As shown, there is one second chip 3, one first chip 2 among the multiple first chips 2 is interconnected with the second chip 3 through a through-hole 13, and the remaining first chips 2 among the multiple first chips 2 are interconnected with one first chip 2 through the wiring inside the interposer 1, so as to be interconnected with the second chip 3 through one first chip 2.
[0041] Among them, the remaining first chips 2 among the multiple first chips 2 are interconnected with one first chip 2 through routing inside the intermediate layer 1. In specific settings, the remaining first chips 2 can be arranged on the circumferential side of the first chip 2 interconnected with the second chip 3 to shorten the routing distance between the first chips 2.
[0042] It can be understood that by interconnecting one of the multiple first chips 2 with the second chip 3 through the through-hole 13 of the interposer 1, it is helpful to simplify wiring requirements, reduce signal interference, and reduce the complexity of system design. Having one first chip 2 responsible for communicating with the second chip 3 can achieve centralized data management, improve overall efficiency, and reduce energy consumption.
[0043] In some embodiments, there are multiple first chips 2 and multiple second chips 3, at least one first chip 2 among the multiple first chips 2 is interconnected with the multiple second chips 3 through through-holes 13, and the remaining first chips 2 among the multiple first chips 2 are interconnected with at least one first chip 2, so as to be interconnected with the second chip 3 through at least one first chip 2.
[0044] The first chip 2 and the second chip 3 can each be provided in multiple numbers. For example, if two, three, or four first chips 2 are provided, two or three second chips 3 can also be provided. Of course, due to space limitations and to ensure signal transmission quality, the number of second chips 3 should not be too large. The specific number of first chips 2 and second chips 3 can be adjusted according to actual needs.
[0045] Specifically, when multiple first chips 2 are interconnected with multiple second chips 3, the multiple first chips 2 and the multiple second chips 3 connected to the multiple second chips 3 can be connected in a one-to-one correspondence, or one first chip 2 can be connected to two or more second chips 3. The specific connection method of the multiple first chips 2 and the multiple second chips 3 can be set according to actual needs and is not limited here.
[0046] In some embodiments, one first chip 2 among multiple first chips 2 is interconnected with multiple second chips 3 through a through-hole 13, and the remaining first chips 2 among the multiple first chips 2 are respectively interconnected with a first chip 2 through the wiring in the interposer 1, so as to be interconnected with the second chip 3 through a first chip 2.
[0047] For example, when the first chip 2 is a logic chip and the second chip 3 is a memory chip, one of the multiple logic chips is interconnected with multiple memory chips via vias 13. A single first chip 2 acts as a "master" to manage multiple second chips 3, enabling centralized management. The first chip 2 can simultaneously read or write data from different second chips 3, improving processing power. If a second chip 3 fails, the other second chips 3 can be switched to another, enhancing reliability. As can be seen from the above, the overall performance of the package structure can be improved by interconnecting one of the multiple first chips 2 with multiple second chips 3.
[0048] In this embodiment, the thickness of the interposer 1 is 20 μm to 60 μm.
[0049] For example, the thickness of the interposer 1 can be 20 μm, 30 μm, 40 μm, 50 μm, or 60 μm. If the interposer 1 is too thick, it will be difficult to process the through holes 13. The spacing between the through holes 13 will be too large, which will reduce the density of the through holes 13 on the interposer 1 and will not be conducive to improving the reliability of the sealing structure. If the interposer 1 is too thin, it will affect the processing of the interposer 1.
[0050] By setting the thickness of the interposer 1 to 20 μm to 60 μm, the processing of the interposer 1 and the through holes 13 in the interposer 1 is facilitated, the strength of the interposer 1 is ensured, and the density of the through holes 13 in the interposer 1 is increased, thereby improving the reliability of the sealing structure.
[0051] In this embodiment, the packaging structure further includes a plastic package (not shown in the figure). The plastic package is provided on the first surface 11 of the interposer 1 to wrap the first chip 2 .
[0052] It is understandable that by providing a plastic package to wrap the first chip 2, the plastic package can protect the first chip 2. Of course, whether to provide a plastic package does not affect the function of the packaging structure and can be selected according to actual needs.
[0053] In this embodiment, Figure 1 As shown, the package structure further includes a substrate 4 , which is disposed on a side of the first chip 2 facing the interposer 1 , and both the interposer 1 and the second chip 3 are disposed on the substrate 4 .
[0054] By providing the substrate 4 , the packaging structure can be supported by the substrate 4 , which is beneficial to improving the overall strength, and signal transmission can be performed by providing the substrate 4 .
[0055] In some embodiments, as Figure 1 As shown, the interposer 1 and the second chip 3 are both embedded in the substrate 4 .
[0056] In detail, a first accommodating cavity 41 and a second accommodating cavity 42 that are interconnected are provided in sequence along the thickness direction of the substrate 4. The first accommodating cavity 41 and the second accommodating cavity 42 are interconnected, the interposer 1 is embedded in the second accommodating cavity 42, and the second chip 3 is embedded in the first accommodating cavity 41.
[0057] It can be understood that by embedding both the interposer 1 and the second chip 3 in the substrate 4 , the substrate 4 can provide stable support for the second chip 3 and the interposer 1 , and space can be saved.
[0058] like Figure 1 As shown, the package structure further includes pins 5, which are arranged on a side of the substrate 4 away from the first chip 2. The package structure is connected to an external device through the pins 5. For example, the pins 5 are solder balls.
[0059] In this embodiment, there are multiple first chips 2 , and at least one first chip 2 is electrically connected to the substrate 4 .
[0060] It should be noted that when there are multiple first chips 2, due to space limitations, there are a large number of output ports of the first chip 2 that are not directly interconnected with the second chip 3. When it is impossible to directly output through the first chip 2 directly interconnected with the second chip 3, the first chip 2 is electrically connected to the substrate 4 to lead out the output of the first chip 2 through the substrate 4.
[0061] In this embodiment, at least one first chip 2 is electrically connected to the substrate 4 through a through-hole 13 in the interposer 1 .
[0062] It should be noted that the first chip 2 is electrically connected to the substrate 4 via the through-holes 13 in the interposer 1, which can shorten the routing distance of the output ports of the first chip 2 when outputting through the substrate 4, thereby saving wiring layer resources of the substrate 4. In addition, as needed, some of the output ports of the first chip 2 can be output through the second chip 3, while others can be output after passing through the interposer 1 and the substrate 4; alternatively, some of the output ports of the first chip 2 can be output through the second chip 3, some can be output through the interposer 1 and the substrate 4, and some can be output directly through the substrate 4.
[0063] The electronic device of the embodiment of the present disclosure includes a printed circuit board and a packaging structure. The packaging structure is the above-mentioned packaging structure, and the printed circuit board is connected to the packaging structure.
[0064] Example 2
[0065] The working principle of the second embodiment of the present disclosure is the same as that of the first embodiment, except that: Figure 2 As shown, the interposer 1 is located between the first chip 2 and the substrate 4 , and the second chip 3 is embedded in the substrate 4 .
[0066] In detail, a first accommodating cavity 41 is provided on the substrate 4 and passes through the substrate 4 in a thickness direction, and the second chip 3 is provided in the second accommodating cavity 42 .
[0067] It is understandable that the interposer 1 is disposed between the first chip 2 and the substrate 4 , and the second chip 3 is embedded in the substrate 4 , which can provide stable support for the second chip 3 and the interposer 1 through the substrate 4 while saving space.
[0068] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present disclosure.
[0069] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.
[0070] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication between them; direct connections or indirect connections through an intermediate medium; and internal communication between two elements or interaction between two elements, unless otherwise expressly limited. Those skilled in the art will understand the specific meanings of the above terms in this disclosure based on specific circumstances.
[0071] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.
[0072] In the present disclosure, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.
[0073] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and are not to be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.
Claims
1. A packaging structure, characterized in that: include: an interposer having a first surface and a second surface opposite to each other in a thickness direction of the interposer, and the interposer having a through hole penetrating along the thickness direction of the interposer; a first chip, the first chip being disposed on a first surface of the interposer; The second chip is disposed on the second surface of the interposer, and the second chip is interconnected with the first chip through the through hole.
2. The packaging structure according to claim 1, wherein: There are multiple first chips, at least one first chip among the multiple first chips is interconnected with the second chip through the through-hole, and the remaining first chips among the multiple first chips are interconnected with the at least one first chip, so as to be interconnected with the second chip through the at least one first chip.
3. The packaging structure according to claim 2, wherein: There is one second chip, one first chip among the multiple first chips is interconnected with the second chip through the through-hole, and the remaining first chips among the multiple first chips are interconnected with the one first chip through the wiring in the interposer, so as to be interconnected with the second chip through the one first chip.
4. The packaging structure according to claim 1, wherein: There are multiple first chips and multiple second chips, at least one first chip among the multiple first chips is interconnected with the multiple second chips through the through holes, and the remaining first chips among the multiple first chips are interconnected with the at least one first chip, so as to be interconnected with the second chip through the at least one first chip.
5. The packaging structure according to claim 4, wherein: One first chip among the plurality of first chips is interconnected with the plurality of second chips through the through-holes, and the remaining first chips among the plurality of first chips are respectively interconnected with the one first chip through the routing in the interposer, so as to be interconnected with the second chip through the one first chip.
6. The packaging structure according to claim 1, wherein: The thickness of the intermediate layer is 20 μm to 60 μm.
7. The packaging structure according to claim 1, wherein: The packaging structure further includes a plastic package body, which is disposed on the first surface of the interposer to wrap the first chip.
8. The packaging structure according to claim 1, wherein: The first chip includes a logic chip, and the second chip includes a memory chip.
9. The packaging structure according to any one of claims 1 to 8, characterized in that: The packaging structure further includes a substrate, which is disposed on a side of the first chip facing the intermediary layer, and the intermediary layer and the second chip are both disposed on the substrate.
10. The packaging structure according to claim 9, wherein: The interposer and the second chip are both embedded in the substrate.
11. The packaging structure according to claim 9, wherein: The interposer is located between the first chip and the substrate, and the second chip is embedded in the substrate.
12. The packaging structure according to claim 9, wherein: There are multiple first chips, and at least one first chip is electrically connected to the substrate.
13. The packaging structure according to claim 12, wherein: The at least one first chip is electrically connected to the substrate through the through-hole in the interposer.
14. An electronic device, characterized in that: include: printed circuit boards; A packaging structure, wherein the packaging structure is the packaging structure according to any one of claims 1 to 13, and the printed circuit board is connected to the packaging structure.