Packaging structure and packaging method of power semiconductor

Abstract

The invention provides a packaging structure and a packaging method of a power semiconductor. The packaging structure of the power semiconductor comprises a lead frame base island, a chip arranged on the lead frame base island, D-pole pins which are integrally formed with the lead frame base island and are respectively arranged at two sides of the lead frame base island, and an S-pole copper sheet arranged at the top of the chip, the lead frame G-pole pin is arranged on one side of the lead frame base island; the plastic package body wraps the chip, the lead frame base island, the S-pole copper sheet and the lead frame G-pole pin; the S-pole copper sheet comprises an inverted trapezoidal groove and two S-pole pins, the two S-pole pins respectively extend from two edges of the inverted trapezoidal groove and are parallel to the bottom surface of the inverted trapezoidal groove, the bottom of the inverted trapezoidal groove is connected with the top of the chip, and at least one surface of each S-pole pin is exposed out of the plastic package body. And the back surface of the lead frame base island is exposed out of the plastic package body. The packaging structure of the power semiconductor has the advantage of high heat dissipation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit packaging, and in particular to a packaging structure and a packaging method for a power semiconductor. Background Art

[0002] As the power density required in application fields continues to increase, power semiconductors, as important components in systems such as power supply control, need to further reduce size and power loss to meet the demand.

[0003] Reducing power loss in power semiconductors primarily involves two approaches: improving the heat dissipation performance of the package and reducing the device's on-resistance and parasitic capacitance. Power semiconductor packages primarily dissipate heat through contact with the external environment, but existing heat dissipation structures have limited contact area, resulting in limited heat dissipation performance and room for improvement.

[0004] like Figure 1-Figure 3 As shown, in the packaging structure of power semiconductors in the prior art, heat is usually dissipated through the externally exposed drain (D pole), resulting in low heat dissipation efficiency and being unsuitable for products with high heat dissipation requirements. Summary of the Invention

[0005] The object of the present invention is to provide a packaging structure and a packaging method for a power semiconductor with high heat dissipation efficiency.

[0006] In an embodiment of the present invention, a packaging structure for a power semiconductor is provided, which includes a lead frame base island, a chip arranged on the lead frame base island, D-pole pins integrally formed with the lead frame base island and respectively arranged on both sides of the lead frame base island, an S-pole copper sheet arranged on the top of the chip, a lead frame G-pole pin arranged on one side of the lead frame base island, and a plastic package that wraps the chip, the lead frame base island, the S-pole copper sheet and the lead frame G-pole pin, wherein the S-class copper sheet includes an inverted trapezoidal groove and two S-pole pins extending from two edges of the inverted trapezoidal groove and parallel to the bottom surface of the inverted trapezoidal groove, the bottom of the inverted trapezoidal groove is connected to the top of the chip, at least one surface of the S-pole pin is exposed outside the plastic package, the back surface of the lead frame base island is exposed outside the plastic package, the G-pole pin and the D-pole pin are bent and each has a bottom parallel to the lead frame base island, and the plane where the bottom is located is in the same plane as the S-pole pin.

[0007] In an embodiment of the present invention, the lead frame structure further includes a suspended functional pin, and the functional pin and the G-pole pin are symmetrically arranged on both sides of the lead frame base island.

[0008] In the embodiment of the present invention, both sides of the inverted trapezoidal groove extend out of the plastic package body, so that both surfaces of the S-pole pin are exposed outside the plastic package body.

[0009] In an embodiment of the present invention, the two D-pole pins are respectively arranged on both sides of the lead frame base island, one of the D-pole pins is adjacent to the lead frame G-pole pin, and its width is the same as the width of the lead frame G-pole pin, and the width of the other D-pole pin is equivalent to the width of the lead frame base island 20.

[0010] In an embodiment of the present invention, the S pole and G pole of the chip are arranged on the top surface of the chip, the D pole of the chip is arranged on the bottom surface of the chip, the G pole of the chip is electrically connected to the G pole pin of the lead frame through a welding wire, the S pole of the chip is electrically connected to the S pole copper sheet of the lead frame through the mounting glue, and the D pole of the chip is electrically connected to the lead frame base island through the mounting glue.

[0011] In an embodiment of the present invention, a packaging method of the lead frame structure is further provided, which includes: Mounting the chip on the lead frame base island; Bonding the G-pole of the chip to the G-pole pin of the lead frame by means of a bonding wire; Mounting the S-grade copper sheet on the top surface of the chip; Injection molding is performed on the chip, the lead frame base island, the lead frame G-pole pin and the S-pole copper sheet; The exposed pins after injection molding are bent and molded.

[0012] Compared with the prior art, the packaging structure of the power semiconductor of the present invention adopts the S-level copper sheet including an inverted trapezoidal groove and two S-pole pins extending from the two edges of the inverted trapezoidal groove and parallel to the bottom surface of the inverted trapezoidal groove, the bottom of the inverted trapezoidal groove is connected to the top of the chip, at least one surface of the S-pole pin is exposed outside the plastic package, and the back side of the lead frame base island is exposed outside the plastic package, thereby achieving double-sided heat dissipation of the chip after packaging, with high heat dissipation efficiency; the G-pole pin and the D-pole pin are bent and formed so that they have a bottom parallel to the lead frame base island, and the plane where the bottom is located is on the same plane as the S-pole pin, thereby facilitating mounting on a circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention is a schematic structural diagram of a power semiconductor packaging structure using existing technology.

[0014] Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA.

[0015] Figure 3 yes Figure 1 Schematic cross-section along line BB.

[0016] Figure 4 It is a structural diagram of a power semiconductor packaging structure according to an embodiment of the present invention.

[0017] Figure 5 yes Figure 4 Schematic diagram of the cross section along line AA.

[0018] Figure 6 yes Figure 4 Schematic cross-section along line BB.

[0019] Figure 7 It is a schematic diagram of the three-dimensional structure of a packaged chip in one direction according to an embodiment of the present invention.

[0020] Figure 8 It is a schematic diagram of the three-dimensional structure of the packaged chip in another direction according to an embodiment of the present invention.

[0021] Figure 9 Schematic diagram of the packaging process of a power semiconductor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] The implementation of the present invention is described in detail below with reference to specific embodiments.

[0024] like Figure 4-Figure 6 As shown, in an embodiment of the present invention, a packaging structure of a power semiconductor is provided, which includes a lead frame base island 20, a chip 21 arranged on the lead frame base island, D-pole pins 22 integrally formed with the lead frame base island 20 and respectively arranged on both sides of the lead frame base island 20, an S-pole copper sheet 23 arranged on the top of the chip 21, a lead frame G-pole pin 24 arranged on one side of the lead frame base island 20, and a plastic package 25 that wraps the chip 21, the lead frame base island 29, the S-pole copper sheet 23 and the lead frame G-pole pin 24.

[0025] like Figure 5As shown, the S-grade copper sheet 23 includes an inverted trapezoidal groove 231 and two S-pole pins 232 extending from two edges of the inverted trapezoidal groove and parallel to the bottom surface of the inverted trapezoidal groove 231. The bottom of the inverted trapezoidal groove 231 is connected to the top of the chip 21. Figure 7 As shown, at least one surface of the S-pole pin 232 is exposed outside the plastic package 25, so that the heat emitted by the chip 21 can be dissipated through the S-pole pin 232. Figure 8 As shown, the back side of the lead frame island 20 is exposed to the plastic package, also acting as a heat sink, achieving double-sided heat dissipation for the chip 21 and improving heat dissipation efficiency. The two D-pole pins 22 are respectively arranged on both sides of the lead frame island 20. One of the D-pole pins 22 is adjacent to the lead frame G-pole pin 24 and has the same width as the lead frame G-pole pin 24. The width of the other D-pole pin 22 is comparable to the width of the lead frame island 20. While providing heat dissipation, it also serves to maintain pin balance on both sides after packaging.

[0026] like Figure 6 As shown, the G-pole pin 24 and the D-pole pin 22 are bent and formed so that they have a bottom portion parallel to the lead frame base island 20, and the plane where the bottom portion lies is coplanar with the S-pole pin 232. When mounting the packaged chip, since they are coplanar, the G-pole pin 24, the D-pole pin 22, and the S-pole pin 232 can be conveniently mounted on a circuit board, thereby facilitating the installation of the packaged chip.

[0027] It should be noted that in the embodiment of the present invention, the S and G poles of the chip 21 are arranged on the top surface of the chip, and the D pole of the chip is arranged on the bottom surface of the chip. The G pole of the chip is electrically connected to the G pole pin 24 of the lead frame via a bonding wire 27, the S pole of the chip is electrically connected to the S pole copper sheet 23 of the lead frame via a die bonding adhesive, and the D pole of the chip is electrically connected to the lead frame base island 20 via a die bonding adhesive.

[0028] Furthermore, in an embodiment of the present invention, the leadframe structure further includes a suspended functional pin 26. The functional pin 26 is symmetrically arranged on either side of the leadframe base island with the G-pole pin 24. It is not electrically connected to the chip 21 and serves to maintain pin balance, thereby ensuring a more stable mounting of the packaged chip on the circuit board. It should be noted that in other embodiments of the present invention, the functional pin 26 is not necessary; the arrangement of the D-pole pin 22 and the G-pole pin 24 can be adjusted to achieve pin balance.

[0029] Furthermore, in another embodiment of the present invention, both sides of the inverted trapezoidal groove 231 extend out of the plastic package 25, so that both surfaces of the S-pole pin 232 are exposed outside the plastic package 25, thereby making the S-pole pin 232 completely exposed outside the plastic package 25, and also realizing double-sided heat dissipation.

[0030] like Figure 9 As shown, in an embodiment of the present invention, a packaging method for the lead frame structure is further provided, and the process includes steps S1 to S5, which are described below respectively.

[0031] Step S1: mounting the chip 21 on the lead frame island 20 .

[0032] In this step, the chip 21 can be mounted on the lead frame island 20 by die bonding adhesive, and the D pole of the chip can be electrically connected to the lead frame 20.

[0033] Step S2: bonding the G-pole of the chip 21 to the G-pole 24 pin of the lead frame via a bonding wire 27 .

[0034] Step S3: attaching the S-grade copper sheet 23 to the top surface of the chip 21 .

[0035] In this step, the S pole of the chip 21 is electrically connected to the bottom of the trapezoidal groove of the S-level copper sheet 23 by mounting.

[0036] In this step, you can first use a solder paste brushing device to brush a layer of solder on the chip surface, and then use the mounting or SMT equipment to move the preformed S-grade copper sheet to the fixed position on the chip surface where the solder has been brushed through the nozzle, and then pass it through the reflow oven for curing.

[0037] Step S4: performing injection molding on the chip 21, the lead frame base island 29, the lead frame G-pole pin 24 and the S-pole copper sheet 23.

[0038] Step S5: performing a bending molding process on the exposed pins after the injection molding.

[0039] In this step, the exposed pins are formed by reverse molding so that they all have a bottom that is parallel to the lead frame base island and has the same height to facilitate mounting.

[0040] In summary, the packaging structure of the power semiconductor of the present invention is adopted, and the S-level copper sheet includes an inverted trapezoidal groove and two S-pole pins extending from the two edges of the inverted trapezoidal groove and parallel to the bottom surface of the inverted trapezoidal groove, respectively. The bottom of the inverted trapezoidal groove is connected to the top of the chip, at least one surface of the S-pole pin is exposed outside the plastic package, and the back side of the lead frame base island is exposed outside the plastic package, thereby achieving double-sided heat dissipation of the chip after packaging, and high heat dissipation efficiency; the G-pole pin and the D-pole pin are bent and formed so that they have a bottom parallel to the lead frame base island, and the plane where the bottom is located is on the same plane as the S-pole pin, thereby facilitating mounting on a circuit board.

[0041] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A power semiconductor packaging structure, characterized in that: It includes a lead frame base island, a chip arranged on the lead frame base island, D-pole pins integrally formed with the lead frame base island and respectively arranged on both sides of the lead frame base island, an S-pole copper sheet arranged on the top of the chip, a lead frame G-pole pin arranged on one side of the lead frame base island, and a plastic package that wraps the chip, the lead frame base island, the S-pole copper sheet and the lead frame G-pole pin, the S-level copper sheet includes an inverted trapezoidal groove and two S-pole pins extending from two edges of the inverted trapezoidal groove and parallel to the bottom surface of the inverted trapezoidal groove, the bottom of the inverted trapezoidal groove is connected to the top of the chip, at least one surface of the S-pole pin is exposed outside the plastic package, the back side of the lead frame base island is exposed outside the plastic package, the G-pole pin and the D-pole pin are formed by bending, and both have a bottom parallel to the lead frame base island, and the plane where the bottom is located is in the same plane as the S-pole pin.

2. The lead frame structure according to claim 1, wherein: It also includes a suspended functional pin, which is symmetrically arranged on both sides of the lead frame base island with the G-pole pin.

3. The lead frame structure according to claim 1, wherein: Both sides of the inverted trapezoidal groove extend out of the plastic package body, so that both surfaces of the S-pole pin are exposed outside the plastic package body.

4. The lead frame structure according to claim 1, wherein: The two D-pole pins are respectively arranged on both sides of the lead frame base island, one of the D-pole pins is adjacent to the lead frame G-pole pin, and its width is the same as the width of the lead frame G-pole pin, and the width of the other D-pole pin is equivalent to the width of the lead frame base island 20.

5. The lead frame structure according to claim 1, wherein: The S pole and G pole of the chip are arranged on the top surface of the chip, the D pole of the chip is arranged on the bottom surface of the chip, the G pole of the chip is electrically connected to the G pole pin of the lead frame through a welding wire, the S pole of the chip is electrically connected to the S pole copper sheet of the lead frame through the mounting glue, and the D pole of the chip is electrically connected to the lead frame base island through the mounting glue.

6. A packaging method using the lead frame structure according to any one of claims 1 to 5, characterized in that: include: Mounting the chip on the lead frame base island; Bonding the G-pole of the chip to the G-pole pin of the lead frame by means of a bonding wire; Mounting the S-grade copper sheet on the top surface of the chip; Injection molding is performed on the chip, the lead frame base island, the lead frame G-pole pin and the S-pole copper sheet; The exposed pins after injection molding are bent and molded.

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