Substrate, substrate layering failure test method and device, test equipment and storage medium

Abstract

The invention relates to a substrate, a substrate layering failure test method and device, test equipment and a storage medium. The substrate comprises at least two layers and a core plate, the layers are sequentially arranged on the core plate, each layer further comprises a test circuit, the test circuit of each layer comprises a first port, a second port, a characteristic load and an interconnection line, and the first port, the second port and the characteristic load are connected through the interconnection lines to form the test circuit; wherein the layered test circuit is used for testing whether the layering has a failure phenomenon or not. The testing circuits are prepared in the substrate, each layer of the substrate corresponds to one testing circuit, external testing equipment can be directly connected with the testing circuits through the testing circuits, failure detection of the corresponding layers is achieved, and therefore layering failure detection is conducted on the substrate under the condition that the substrate is not damaged, and the testing efficiency is improved. The convenience of substrate layering failure detection can be improved, and the efficiency of substrate layering failure detection can also be improved.

Description

Technical Field

[0001] The present application relates to the field of hardware testing technology, and in particular to a substrate, a substrate delamination failure testing method, an apparatus, a testing device, and a storage medium. Background Art

[0002] In electronic products, organic substrates are the core carriers of electronic devices, providing electrical connections, mechanical support, and heat dissipation. As the number of transistors in integrated circuits increases, the number of stacked layers of organic substrates that electrically interconnect the integrated circuits increases to achieve high-density packaging. These organic substrates are also prone to delamination failure.

[0003] Traditionally, before an organic substrate leaves a factory, it is necessary to perform a delamination failure test on the organic substrate. Usually, ultrasonic scanning can be used to perform the delamination failure test on the organic substrate.

[0004] However, since ultrasonic scanning requires the organic substrate to be immersed in a medium such as water, the organic substrate needs to be dried and cleaned before it can be used after the test is completed, resulting in poor convenience in delamination failure detection. Summary of the Invention

[0005] Based on this, it is necessary to provide a substrate, substrate delamination failure test method, device, test equipment, computer-readable storage medium and computer program product that can improve the convenience of organic substrate delamination failure detection and improve the efficiency of delamination failure detection in response to the above technical problems.

[0006] In a first aspect, the present application provides a substrate comprising at least two layers and a core board, wherein the layers are sequentially arranged on the core board, and each layer further comprises a test circuit, wherein the layered test circuit comprises a first port, a second port, a characteristic load, and an interconnection line, wherein the first port, the second port, and the characteristic load are connected by the interconnection line to form a test circuit;

[0007] Among them, the layered test circuit is used to test whether the layer fails.

[0008] In one embodiment, for each layer, the first port and the second port are arranged on the top layer of the substrate and away from the core board; the top layer is the layer farthest from the core board among the at least two layers.

[0009] In one embodiment, for each layer, the interconnection line connects the first port, the second port, and the characteristic load through a via.

[0010] In one embodiment, for each layer, the characteristic load is set on a side of the layer close to the core panel, or on a side of the layer far from the core panel.

[0011] In a second aspect, the present application provides a substrate delamination failure test method, which is applied to a test device, the test device being used to perform a delamination failure test on the substrate in the first aspect, the method comprising:

[0012] For each layer of the substrate, connect the test equipment to the test circuit of the layer to form a test loop;

[0013] Input a test signal into the test loop through the test equipment and collect the reflected signal of the test loop;

[0014] The reflected signal is compared and analyzed with the reference signal corresponding to the delamination in the preset good product waveform library to determine whether delamination failure occurs.

[0015] In one embodiment, comparing and analyzing the reflected signal with a reference signal corresponding to the delamination in a preset waveform library to determine whether delamination failure occurs includes:

[0016] Determine a first impedance corresponding to a peak of the reflected signal, and determine a second impedance corresponding to a peak of the reference signal;

[0017] determining a differential impedance between the first impedance and the second impedance;

[0018] If the difference impedance is greater than or equal to the preset difference threshold, it is determined that delamination failure has occurred.

[0019] In one embodiment, the method further comprises:

[0020] When it is determined that delamination failure occurs, the acquisition time of the reflection signal corresponding to the delamination is obtained;

[0021] Determine the failure location of the layer based on the acquisition time and the preset transmission speed.

[0022] In one embodiment, the method further comprises:

[0023] Determining a qualified substrate from a plurality of sample substrates; wherein a test circuit of each layer of the qualified substrate meets a preset test condition;

[0024] Collect the reflection signal of the test circuit of each layer of the good substrate;

[0025] Based on the reflection signal of the test circuit of each layer of the good substrate, a preset good waveform library is constructed.

[0026] In a third aspect, the present application further provides a substrate delamination failure test device, which is applied to a test device for performing a delamination failure test on the substrate in the first aspect. The device comprises:

[0027] A connection module, used for connecting the test equipment and the test circuit of each layer of the substrate to form a test loop;

[0028] An acquisition module, configured to input a test signal into the test loop through a test device and acquire a reflected signal from the test loop;

[0029] The test module is used to compare and analyze the reflected signal with the reference signal corresponding to the delamination in the preset good product waveform library to determine whether delamination failure occurs.

[0030] In a fourth aspect, the present application further provides a testing device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the substrate delamination failure testing method in the second aspect are implemented.

[0031] In a fifth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the substrate delamination failure test method in the second aspect.

[0032] In a sixth aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the substrate delamination failure test method in the second aspect.

[0033] The above-mentioned substrate, substrate delamination failure test method, device, test equipment, storage medium and computer program product, wherein the substrate includes at least two layers and a core board, each layer is sequentially arranged on the core board, each layer also includes a test circuit, the layered test circuit includes a first port, a second port, a characteristic load and an interconnection line, the first port, the second port and the characteristic load are connected by the interconnection line to form a test circuit; wherein the layered test circuit is used to test whether a failure phenomenon occurs in the layer. That is, by preparing a test circuit inside the substrate, and each layer of the substrate corresponds to a test circuit, an external test device can be directly connected to the test circuit through the test circuit to realize failure detection of the corresponding layer, thereby realizing delamination failure detection of the substrate without damaging the substrate, which not only improves the convenience of substrate delamination failure detection, but also improves the efficiency of substrate delamination failure detection; in addition, after the detection is completed, no damage will be caused to the substrate, which can ensure the integrity and reliability of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 is a schematic structural diagram of a substrate in one embodiment;

[0036] FIG2( a ) is a side view of each layer of test circuits in a substrate test structure according to one embodiment;

[0037] FIG2( b ) is a top view of each layer of test circuits in a substrate test structure according to an embodiment;

[0038] Figure 3 A diagram illustrating an application environment of a substrate delamination failure testing method according to an embodiment;

[0039] Figure 4 1 is a schematic flow chart of a substrate delamination failure testing method according to an embodiment;

[0040] Figure 5 1 is a flow chart of a substrate delamination failure testing method according to another embodiment;

[0041] Figure 6 1 is a flow chart of a substrate delamination failure testing method according to another embodiment;

[0042] Figure 7 A schematic diagram of a complete process of substrate delamination failure testing in one embodiment;

[0043] Figure 8 Schematic diagram of TDR waveform when the third and fourth layers are cracked in one embodiment;

[0044] Figure 9 is a structural block diagram of a substrate delamination failure testing device according to one embodiment;

[0045] Figure 10 FIG. 4 is a diagram showing the internal structure of a test device in one embodiment.

[0046] Description of reference numerals:

[0047] 10: substrate; 20: layer; 30: core board; 21: test circuit; 211: first port;

[0048] 212: second port; 213: characteristic load; 214: interconnection line. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0050] In electronic products, organic substrates are the core carriers of electronic devices, assuming functions such as electrical connection, mechanical support, and heat dissipation. Common types include carrier-like boards, printed circuit boards (PCBs), and packaging substrates. The choice of materials directly affects device performance. The main materials include thermosetting resins (BT resins), epoxy resins (FR4), polyimides, etc. They are low-cost and flexible, and are widely used in consumer electronics and flexible fields.

[0051] According to Moore's Law, the number of transistors on an integrated circuit doubles every 18 months, and packaging density increases accordingly. To achieve high-density packaging for integrated circuits, organic substrates, which provide electrical interconnects for the integrated circuits, are stacking more and more layers, increasing wiring density and narrowing line widths and line spacing.

[0052] Due to the significant difference in thermal expansion coefficients between the resin matrix and the copper foil in organic substrates, delamination failure is a common occurrence during actual service, impacting the proper functioning of the entire electronic device and even causing device burnout. Furthermore, moisture from the environment can enter the substrate, exacerbating delamination and cracking under thermal conditions. To ensure the quality and reliability of organic substrates, environmental stress loading and delamination defect detection are required before shipment.

[0053] There are two main existing methods for delamination detection: ultrasonic scanning and metallographic sample preparation and section analysis. Ultrasonic scanning requires immersing the organic substrate in a medium such as water. After the test, the organic substrate needs to be dried and cleaned before use, making delamination failure detection less convenient. Ultrasonic scanning also has a low test resolution, making it difficult to identify the specific location of the failure. Metallographic sample preparation and section analysis requires destructive testing such as cutting and grinding on the organic substrate. After the analysis, the organic substrate cannot be reused, which does not meet production needs.

[0054] Based on this, the embodiment of the present application addresses the problem of rapid screening of delamination failure of organic substrates and proposes a test structure and non-destructive testing method based on time domain reflectometry (TDR). The test structure is integrated inside the organic substrate and can efficiently test the organic substrate without damaging the organic substrate. It is convenient and fast, and can effectively and accurately locate the delamination failure position of the organic substrate, reducing screening time and improving product quality and reliability.

[0055] In one embodiment, Figure 1 As shown, the present application provides a substrate 10, which includes at least two layers 20 and a core board 30, and each layer 20 is arranged in sequence on the core board 30, wherein each layer 20 also includes a test circuit 21, and the test circuit 21 of the layer 20 includes a first port 211, a second port 212, a characteristic load 213 and an interconnection line 214, and the first port 211, the second port 212 and the characteristic load 213 are connected by the interconnection line 214 to form the test circuit 21; the test circuit 21 of each layer 20 is used to test whether each layer 20 has a failure phenomenon.

[0056] For example, the substrate 10 may be an organic substrate, an inorganic substrate, a ceramic substrate, etc., wherein the organic substrate may include but is not limited to a carrier-like substrate, a packaging substrate, a PCB board, etc. Figure 1 As shown, for the substrate 10, a test structure can be set up for performing failure tests on each layer of the substrate 10 respectively. The test structure can be composed of multiple test circuits parallel to each other, wherein the number of test circuits is consistent with the number of layers of the substrate, that is, for each layer 20 of the substrate 10, a corresponding test circuit 21 is set up respectively.

[0057] Among them, the test line 21 corresponding to each layer 20 is composed of two test ports, namely the first port 211 and the second port 212, a characteristic load 213 and an interconnection line 214. Here, the test ports of the test line 21 of each layer 20 are independent, that is, through the two test ports of the test line 21, failure detection can be performed in a targeted manner on the layer 20 where the test line 21 is located.

[0058] For example, for each layer 20 of the substrate 10, the first port 211 and the second port 212 can be set on the top layer of the substrate 10 and away from the side of the core board 30; wherein the top layer is the layer farthest from the core board 30 among the at least two layers. Figure 1 As shown, the top layer can be the topmost layer of the core board 30, for example, from top to bottom, it can be the first layer, the second layer, the third layer, etc., and the top layer can be the first layer. In this example, the first port 211 and the second port 212 in the test circuit 21 of each layer 20 can be set on the first layer of the substrate 10, and located on the side of the first layer away from the core board 30, that is, the first port 211 and the second port 212 of the test circuit 21 of each layer 20 are exposed to the outside of the substrate 10, which is conducive to connection with the test equipment, thereby forming a test loop. For example, the two port probes of the test equipment can be connected to the first port 211 and the second port 212 of the test circuit 21 respectively to form a test loop.

[0059] In this case, since the first port 211 and the second port 212 of the test circuit 21 of each layer 20 are both arranged on the side of the top layer away from the core board 30, the interconnection line 214 of the test circuit 21 of each layer 20 can be connected to the first port 211, the second port 212, and the characteristic load 213 through a via. A via, also known as a metalized hole, is a common hole drilled at the intersection of the printed conductors that need to be connected on each layer in a double-sided or multi-layer board to connect the printed conductors between the layers.

[0060] For example, for each layer 20, the characteristic load 213 of the test circuit 21 of the layer 20 can be set on the side of the layer 20 close to the core board 30, or it can also be set on the side of the layer 20 away from the core board 30. That is to say, for the second layer, its characteristic load can be set on the side close to the first layer, or it can also be set on the side close to the third layer. For the first layer, its characteristic load can be set on the side close to the second layer, or it can be directly exposed at the top, that is, the side away from the second layer. It should be noted that when the characteristic load is exposed, it is easily affected by external forces, water vapor, etc. Therefore, in order to prevent the wires from being exposed and avoid interference from external factors, the wires can be set inside the substrate.

[0061] Refer to Figure 2, which shows a schematic diagram of a substrate test structure. Taking a four-layer structure as an example, a cross-sectional view of the test circuits on each layer is shown in Figure 2(a), and a top view of the test circuits on each layer is shown in Figure 2(b). Each layer's test circuits are equipped with two independent test ports, facilitating failure detection for each layer separately.

[0062] Among them, the test port and characteristic load of the test circuit 1 of the first layer are arranged on the first layer of the substrate, and the interconnection line is connected to the test port and characteristic load on the first layer; the test port of the test circuit 2 of the second layer is arranged on the first layer of the substrate, and the characteristic load is arranged on the second layer, and the interconnection line enters the second layer through the hole from the first port of the first layer and is connected to the characteristic load, and then returns to the first layer through the hole and is connected to the second port; the test port of the test circuit 3 of the third layer is arranged on the first layer of the substrate, and the characteristic load is arranged on the third layer, and the interconnection line enters the third layer through the hole from the first port of the first layer and is connected to the characteristic load, and then returns to the first layer through the hole and is connected to the second port; and so on for the Nth test circuit.

[0063] For example, for each layer 20, the first port 211 and the second port 212 may also be located on the side of the layer 20, that is, on the side of the substrate 10. In other words, the test circuit 21 of the layer 20 may be located entirely on the layer 20, that is, the test circuit 21, including the two test ports, are located in the plane of the layer 20. If the layer 20 includes multiple sides, the first port 211 and the second port 212 may be located on the same side or on different sides. For example, the first port 211 and the second port 212 may be located on the left and right sides of the plane of the layer 20 (when placed horizontally). In this case, the characteristic load 213 may be located on the upper and lower sides of the layer 20, or embedded within the layer 20. The interconnect line 214 may be located in the plane of the layer 20 to sequentially connect the first port 211, the characteristic load 213, and the second port 212.

[0064] Illustratively, the test port, characteristic load (such as characteristic impedance), and interconnection line in the above-mentioned test circuit 21 can be made of metal materials such as Cu, Au, Ag, and Ni. The test circuit 21 can be integrated on each layer 20 of the substrate 10 by semi-additive deposition, electroplating, physical vapor deposition, chemical vapor deposition, magnetic pump sputtering, etc., that is, the test structure is prepared during the processing of the substrate 10 to form a test circuit 21 on each layer 20.

[0065] For example, for test circuit 21, its test ports include first port 211 and second port 212, which can be circular, with a diameter between 200 µm and 500 µm and a center distance between 1 mm and 5 mm. Characteristic load 213 can be rectangular, with a length between 0.2 mm and 0.8 mm, a width between 10 µm and 100 µm, and an impedance between 2 and 8 times the impedance of interconnect 214. The width of interconnect 214 can be between 5 µm and 30 µm, and the impedance can be between 25Ω and 100Ω. It should be noted that the parameter data of the test circuit provided in this example is only provided as an example and is not intended to limit specific values.

[0066] The substrate in the above embodiment includes at least two layers and a core board, each layer is sequentially arranged on the core board, and each layer further includes a test circuit. The layered test circuit includes a first port, a second port, a characteristic load, and an interconnection line. The first port, the second port, and the characteristic load are connected by the interconnection line to form a test circuit; wherein the layered test circuit is used to test whether a layer failure occurs. In other words, by preparing a test circuit inside the substrate, and each layer of the substrate corresponds to a test circuit, an external test device can be directly connected to the test circuit through the test circuit to realize failure detection of the corresponding layer, thereby realizing delamination failure detection of the substrate without damaging the substrate, which not only improves the convenience of substrate delamination failure detection, but also improves the efficiency of substrate delamination failure detection; in addition, after the detection is completed, no damage will be caused to the substrate, which can ensure the integrity and reliability of the substrate.

[0067] In one embodiment, a substrate delamination failure test method for performing delamination failure test on the substrate in each of the above embodiments is also provided, which can be applied to Figure 3 In the application environment shown, the test device 301 can be electrically connected to each test circuit of the substrate, thereby performing failure testing on the layer corresponding to each test circuit. For example, the test device 301 can be a test device based on TDR technology, capable of sending a test signal to the test circuit and receiving a reflected signal reflected from the test circuit. The test signal can be any type of pulse signal. Based on the reflected signal, the test device 301 can determine whether the layer corresponding to the test circuit has failed.

[0068] In an exemplary embodiment, Figure 4 As shown, a substrate delamination failure test method is provided, which is applied to Figure 3 The test equipment in the example is used to illustrate the method, which includes the following steps 401 to 403. Among them:

[0069] Step 401 : For each layer of the substrate, connect the test equipment to the test circuit of the layer to form a test loop.

[0070] For example, the test device may include two connection ports, such as an input port and an output port. When performing layer testing on a substrate, the two connection ports of the test device may be connected to the first and second ports of a test circuit corresponding to the layer to be tested on the substrate to form a test loop corresponding to the layer to be tested. As an optional implementation, the two connection ports of the test device may be in the form of probes. In this way, the user simply connects the two port probes to the first and second ports of the test circuit corresponding to the layer to be tested to form a test loop.

[0071] For example, for the first port and the second port of the test line, it is not necessary to distinguish which port is the input port and which port is the output port, that is, the user can arbitrarily contact the two port probes of the test device with the first port and the second port; of course, in some scenarios, the first port and the second port of the test line can also be distinguished, for example: the first port is the input port and the second port is the output port, then the user can contact the input port probe of the test device with the first port of the test line, and contact the output port probe of the test device with the second port of the test line, thereby forming a test loop.

[0072] It should be noted that the above-mentioned probe can be a contact probe, or it can be an insertion probe, such as inserting the probe into the first port and the second port of the test circuit to form a test loop; optionally, the two wiring ports of the test device can also be other forms besides probes, such as clip form or hook form, etc. The embodiment of the present application does not specifically limit the electrical connection method between the test device and the test circuit.

[0073] Step 402: Input a test signal into the test loop through the test equipment, and collect the reflection signal of the test loop.

[0074] For example, when the test device is connected to a test circuit of a certain layer of the substrate, the test device can be started and controlled to input a test signal into the test circuit. The test signal can be any type of pulse signal, and the test device can receive a reflected signal reflected back from the test circuit, such as a reflected pulse signal.

[0075] It should be noted that, when the test equipment includes multiple test channels, ie, multiple pairs of connection ports, it can also simultaneously connect test circuits of multiple layers of the substrate, so as to simultaneously perform failure detection on multiple layers of the substrate.

[0076] Step 403 : Compare and analyze the reflected signal with a reference signal corresponding to delamination in a preset good product waveform library to determine whether delamination failure occurs.

[0077] The preset good waveform library may include reference signals corresponding to each layer of the substrate, i.e., reference reflection signals. Of course, the preset good waveform library also includes reference signals corresponding to each layer of other substrates. It should be noted that for substrates of the same model and batch, a good waveform library corresponding to these substrates can be constructed based on the good substrates among these substrates. Using this good waveform library, delamination failure detection can be performed on these substrates of the same model and batch.

[0078] For example, taking a certain model and a certain batch of substrates as an example, after collecting the reflection signal of each layer of the substrate, the reference waveform corresponding to each layer can be determined from the preset good waveform library for each layer of the substrate. Then, the collected reflection waveform of each layer is compared with the reference waveform of the corresponding layer. If the waveform characteristics of the reflection waveform and the corresponding reference waveform are similar (such as the similarity is greater than or equal to the preset similarity threshold), it can be considered that there is no failure phenomenon in the layer; on the contrary, if the waveform characteristics of the reflection waveform and the corresponding reference waveform are greatly different (such as the similarity is less than the preset similarity threshold), it can be considered that there is a failure phenomenon in the layer.

[0079] The waveform characteristics may include but are not limited to at least one of a time characteristic corresponding to a peak and an impedance characteristic corresponding to a peak.

[0080] In the above-mentioned substrate delamination failure test method, for each layer of the substrate, the test device is first connected to the test circuit of the layer to form a test loop. Then, the test signal is input into the test loop through the test device, and the reflection signal of the test loop is collected. The reflection signal is compared and analyzed with the reference signal corresponding to the layer in the preset good product waveform library to determine whether the delamination failure occurs. In other words, since the substrate of the present application has integrated a test circuit for each layer during the preparation process, when performing delamination failure detection on the substrate, the test circuit of each layer can be directly connected through the test device, and the reflection signal of each layer can be collected based on the time domain reflection technology. The difference between the waveforms is used to determine whether delamination failure occurs; using this method, the substrate can be tested for delamination failure without damaging the substrate, which not only improves the convenience of substrate delamination failure detection, but also improves the efficiency of substrate delamination failure detection; in addition, after the detection is completed, no damage will be caused to the substrate, which can ensure the integrity and reliability of the substrate.

[0081] In an exemplary embodiment, Figure 5 As shown, the above step 403 may include steps 501 to 503. Among them:

[0082] Step 501 : determining a first impedance corresponding to a peak of a reflected signal, and determining a second impedance corresponding to a peak of a reference signal.

[0083] Exemplarily, the horizontal axis of the reflected signal is the time parameter, and the vertical axis is the impedance parameter. When the reflected signal is obtained, the first impedance corresponding to the peak of the reflected signal can be further determined, and the second impedance corresponding to the peak of the corresponding reference signal can be determined.

[0084] Step 502: Determine the difference impedance between the first impedance and the second impedance.

[0085] Exemplarily, the first impedance and the second impedance may be subtracted to obtain a differential impedance.

[0086] Step 503: If the difference impedance is greater than or equal to the preset difference threshold, it is determined that a delamination failure phenomenon occurs.

[0087] If the difference impedance is greater than or equal to the preset difference threshold, it means that the impedance characteristic of the reflected signal is significantly different from the impedance characteristic of the reference signal. In this case, it can be determined that the layer has failed.

[0088] It should be noted that for different layers of the substrate, the corresponding preset difference thresholds may be the same or different; the preset difference threshold may be determined based on the peak impedance of the reference signal of the layer, for example: a preset multiple of the peak impedance, wherein the preset multiple may be any value greater than 1.

[0089] In this embodiment, whether delamination failure occurs is determined by using the peak impedance of the signal, and the failure phenomenon can be quantitatively analyzed and processed, thereby improving the detection accuracy of delamination failure.

[0090] In an exemplary embodiment, when it is determined that a delamination failure phenomenon occurs, the specific location of the delamination failure can be further determined, that is, the delamination failure can be located; based on the above embodiment, if Figure 6 As shown, the above method may further include steps 601 to 602. In which:

[0091] Step 601: When it is determined that a delamination failure occurs, the acquisition time of the reflection signal corresponding to the delamination is obtained.

[0092] For example, for each layer of the substrate, if failure is determined to have occurred, the failure can be further located, that is, the specific location of the failure can be determined. Based on the principle of time-domain reflectometry, the transmission speed of the pulse waveform in the substrate remains constant, and the failure location can be determined based on the transmission time and transmission speed of the reflected signal. When the reflection signal corresponding to the layer is collected, the acquisition time of the reflection signal can be recorded. Combined with the transmission time of the test signal, the corresponding acquisition duration of the reflection signal can be determined, that is, the signal transmission time from the transmission time to the acquisition time.

[0093] Step 602: Determine the failure position of the layer according to the acquisition time and the preset transmission speed.

[0094] The preset transmission speed can be determined based on the acquisition time of the reference signal corresponding to the layer and the test distance of the test circuit corresponding to the layer. The test distance of the test circuit can be obtained when preparing the test circuit, or determined based on the layout of the substrate. For example, the preset transmission speed can also be determined based on the acquisition time of the reference signal corresponding to other layers in the substrate and the test distance of the test circuit. For the same substrate, the signal transmission speed in each layer should be the same. Therefore, the preset transmission speed can be determined for any layer in the substrate.

[0095] The preset transmission speed is calculated using the following formula (1):

[0096] (1)

[0097] Where v is the preset transmission speed, S is the test distance of the test line, and t is the acquisition time of the reference signal.

[0098] On this basis, when locating layer failures, the layer failure position can be determined based on the acquisition time of the reflection signal and the preset transmission speed, as shown in the following formula (2):

[0099] (2)

[0100] Where t' is the acquisition time of the reflection signal, and S' is the failure distance.

[0101] When the failure distance is determined, the position at the failure distance from the input port of the test signal can be determined, which is the failure position of the layer.

[0102] In this embodiment, the time domain reflection principle is adopted. When it is determined that the delamination failure phenomenon occurs, the failure location of the delamination can be further determined so that the delamination failure location can be improved subsequently, thereby eliminating the failure phenomenon, ensuring that the substrate can be used normally, and improving the reliability of the substrate.

[0103] In an exemplary embodiment, Figure 7 As shown in FIG, a complete process for lossless failure detection and location is provided, including the following steps:

[0104] Step S1 : preparing a test structure during processing of a substrate.

[0105] The test structure includes a test circuit corresponding to each layer of the substrate.

[0106] Step S2: Electrically test the good substrate and use time domain reflectometry to establish a good reflection waveform library, i.e., a preset good waveform library. This includes the following steps:

[0107] Step a: determining a qualified substrate from a plurality of sample substrates; and each layered test circuit of the qualified substrate meets a preset test condition.

[0108] Step b: collecting the reflection signal of the test circuit of each layer of the good substrate.

[0109] Step c: constructing a preset good product waveform library based on the reflection signal of the test circuit of each layer of the good product substrate.

[0110] First, an electrical testing device, such as a semiconductor parameter tester, can be used to test each test circuit on the sample substrate. The resistance value can be used to confirm whether the sample substrate is good, thereby identifying good substrates from the sample substrates. If the resistance value of each test circuit on the sample substrate is within a preset range of resistance values, such as approximately 50 ohms, the sample substrate can be considered a good substrate. If a layer cracks and fails, the resistance value at the crack location will be infinite.

[0111] For example, for multiple substrates of the same model and the same batch, the number of good substrates can be one or more; when multiple good substrates are involved, when subsequently constructing a preset good waveform library, for each layer, the average signal of the reflection signals of multiple good substrates can be used as the reference signal corresponding to the layer.

[0112] The reference signal of each layer of the good substrate is stored to obtain a good waveform library corresponding to the good substrate. Of course, the good waveform library can include reference signals of each layer corresponding to good substrates of different models and batches.

[0113] Step S3: placing the substrate to be tested in an environmental test chamber and performing an environmental test according to test conditions.

[0114] Among them, environmental tests include but are not limited to hot and humid test, hot and humid bias test, temperature cycle test, high temperature storage test, high temperature cooking test, hot oil test, etc.

[0115] Step S4: performing a time domain reflectometry test on the substrate after the environmental test and analyzing its failure condition.

[0116] After environmental testing, the reflected signals of each layer of the substrate are collected. Failure analysis is performed on each layer based on the corresponding reference signals from the good product waveform library. If all waveforms of the substrate layers show no significant differences, the substrate passes the test. If the reflected waveform of the Nth (N = 1, 2, 3, ...) test line shows a significant anomaly, it indicates that delamination has occurred between layers N-1 and N.

[0117] Next, based on the principles of time-domain reflectometry, the failure location of the delamination can be further determined, achieving failure localization. Once the delamination failure location is identified, the microscopic morphology of the failure site can be observed using instruments such as optical microscopes, electron microscopes, and energy spectrum analyzers to confirm the failure mechanism and, as a result, improve the substrate.

[0118] Step S5, environmental testing is performed again on the improved substrate. If failure still occurs, improvement is continued; if failure no longer occurs, the test is completed.

[0119] This embodiment provides a substrate test structure and delamination failure detection and location method based on TDR technology. This method addresses delamination failures that may occur during substrate service by creating test circuits on different substrate layers. These circuits are then tested using a time-domain reflectometry device to obtain a library of test waveforms for qualified substrates. By comparing the test waveforms of the substrate under test with the library of test waveforms for qualified substrates, the specific location of delamination in the substrate under test can be determined. This method significantly reduces failure analysis time and detection complexity, improves the resolution of failure location, and ultimately enhances substrate quality and reliability.

[0120] This method can efficiently and quickly identify delamination caused by stress damage during the service life of substrates. Compared to conventional substrate failure analysis methods, this method improves detection efficiency and failure location accuracy, reduces testing costs, and supports process improvements. Furthermore, this method is in demand by product developers, third-party evaluation agencies, and product users, generating significant economic value.

[0121] The feasibility of this method is experimentally verified using the substrate structure shown in Figure 2. The test structure consists of four parallel test lines, each of which consists of two test ports, a characteristic load, and interconnects, all made of copper. The test ports have a diameter of 400µm and a center-to-center spacing of 2mm; the interconnects have an impedance of 40Ω and a line width of 30µm; and the characteristic load has an impedance of 100Ω, a length of 0.5mm, and a line width of 20µm.

[0122] When processing the substrate, the semi-additive method is used to process the test structure inside the organic substrate; then the substrate is tested with a semiconductor tester to confirm that it is a good product. Subsequently, the four test lines of the substrate are tested one by one using a time domain reflection technology tester to obtain a reflection waveform library of good substrates. The tested substrate is placed in an environmental test chamber at 85°C and 85% RH humidity for 30 days. After the test is completed, another test is carried out. The test results show that the peak value in the reflection waveform of the fourth test line is shifted forward compared to the peak value in the good waveform library, and its peak impedance increases from 55Ω to 88Ω. Figure 8As shown in the figure, it is shown that the third and fourth layers of the substrate have delaminated after the environmental test. Since the test distance of the first test line of the good product is 4mm, the signal delay time read from the reference waveform of the first test line of the good product waveform library is 2.0×10 -10 s, from which we can calculate that the test speed of the signal in the substrate is 4×10 7 m / s. At the same time, the time of failure waveform can be measured to be 3.6×10 -10 s, the failure distance can be calculated according to the formula to be 7.31 mm. Subsequent microscopic observation of the failure location revealed that the failure was primarily due to sulfur contamination at the interface during the electroplating process, which reduced the interfacial bonding strength. Subsequent adjustments to the plating solution and retesting of the substrate after environmental testing revealed no significant abnormalities, thus improving the quality and reliability of the substrate.

[0123] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0124] Based on the same inventive concept, embodiments of the present application also provide a substrate delamination failure testing device for implementing the aforementioned substrate delamination failure testing method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more embodiments of the substrate delamination failure testing device provided below can be found in the aforementioned limitations of the substrate delamination failure testing method and will not be further elaborated here.

[0125] In an exemplary embodiment, Figure 9 As shown, a substrate delamination failure test device is provided, which is applied to a test device. The test device is used to perform a delamination failure test on the substrate in any of the above embodiments, including: a connection module 901, a collection module 902 and a test module 903, wherein:

[0126] The connection module 901 is used to connect the test equipment and the test circuit of each layer of the substrate to form a test loop.

[0127] The acquisition module 902 is configured to input a test signal into the test loop through a test device and acquire a reflected signal of the test loop.

[0128] The testing module 903 is used to compare and analyze the reflected signal with the reference signal corresponding to the delamination in the preset good product waveform library to determine whether the delamination failure occurs.

[0129] In one embodiment, the testing module 903 includes:

[0130] a first determining unit, configured to determine a first impedance corresponding to a peak of the reflected signal, and to determine a second impedance corresponding to a peak of the reference signal;

[0131] a second determining unit, configured to determine a differential impedance between the first impedance and the second impedance;

[0132] The third determining unit is configured to determine that a delamination failure phenomenon occurs when the difference impedance is greater than or equal to a preset difference threshold.

[0133] In one embodiment, the apparatus further comprises:

[0134] An acquisition module, configured to acquire the acquisition time of the reflection signal corresponding to the delamination when it is determined that the delamination has failed;

[0135] The first determining module is used to determine the failure position of the layer according to the acquisition time and the preset transmission speed.

[0136] In one embodiment, the apparatus further comprises:

[0137] A second determination module is configured to determine a good substrate from a plurality of sample substrates; the test circuit of each layer of the good substrate meets a preset test condition;

[0138] The acquisition module 902 is further used to acquire the reflection signal of the test circuit of each layer of the good substrate;

[0139] The building module is used to build a preset good product waveform library based on the reflection signal of the test circuit of each layer of the good product substrate.

[0140] Each module in the aforementioned substrate delamination failure test apparatus can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor within the test equipment in hardware form, or stored in memory within the test equipment in software form, allowing the processor to call and execute the corresponding operations of each module.

[0141] In an exemplary embodiment, a test device is provided. The test device may be a test device based on TDR technology, and its internal structure diagram may be as shown in FIG. Figure 10As shown. The test equipment includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the test equipment is used to provide computing and control capabilities. The memory of the test equipment includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the test equipment is used to exchange information between the processor and external devices. The communication interface of the test equipment is used to communicate with external terminals via wired or wireless means, and the wireless means can be implemented via Wi-Fi, a mobile cellular network, near field communication (NFC), or other technologies. When the computer program is executed by the processor, a substrate delamination failure test method is implemented. The display unit of the test equipment is used to form a visually visible image, and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the test equipment can be a touch layer covering the display screen, or a button, trackball or touchpad set on the test equipment shell, or an external keyboard, touchpad or mouse, etc.

[0142] Those skilled in the art will understand that Figure 10 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present application, and does not constitute a limitation on the test equipment to which the scheme of the present application is applied. The specific test equipment may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0143] In an exemplary embodiment, a testing device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps of the substrate delamination failure testing method in any of the above embodiments when executing the computer program.

[0144] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the substrate delamination failure test method in any of the above embodiments are implemented.

[0145] In one embodiment, a computer program product is provided, comprising a computer program. When the computer program is executed by a processor, the steps of the substrate delamination failure test method in any of the above embodiments are implemented.

[0146] It should be noted that the data involved in this application (including but not limited to data used for analysis, storage, display, etc.) are all information and data fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0147] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0148] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0149] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A substrate comprising at least two layers and a core, wherein the layers are sequentially arranged on the core, characterized in that: Each of the layers further includes a test circuit, each of the layered test circuits includes a first port, a second port, a characteristic load, and an interconnection line, wherein the first port, the second port, and the characteristic load are connected through the interconnection line to form the test circuit; The layered test circuit is used to test whether the layer fails.

2. The substrate according to claim 1, wherein For each of the layers, the first port and the second port are arranged on the top layer of the substrate and away from one side of the core board; the top layer is the layer farthest from the core board among the at least two layers.

3. The substrate according to claim 2, wherein For each layer, the interconnection line connects the first port, the second port, and the characteristic load through a via.

4. The substrate according to any one of claims 1 to 3, characterized in that For each layer, the characteristic load is set on a side of the layer close to the core plate, or on a side of the layer far from the core plate.

5. A substrate delamination failure testing method, characterized in that: Applied to a testing device for performing a delamination failure test on a substrate according to any one of claims 1 to 4, the method comprising: For each layer of the substrate, connecting the test device with a test circuit of the layer to form a test loop; Inputting a test signal into the test loop through the test device and collecting a reflected signal of the test loop; The reflected signal is compared and analyzed with a reference signal corresponding to the delamination in a preset good product waveform library to determine whether the delamination has failed.

6. The method according to claim 5, characterized in that The comparing and analyzing the reflected signal with a reference signal corresponding to the layer in a preset waveform library to determine whether the layer fails includes: Determining a first impedance corresponding to a peak of the reflected signal, and determining a second impedance corresponding to a peak of the reference signal; determining a differential impedance between the first impedance and the second impedance; If the difference impedance is greater than or equal to a preset difference threshold, it is determined that the delamination failure occurs.

7. The method according to claim 5, characterized in that The method further comprises: When it is determined that the layer fails, obtaining a collection time of a reflection signal corresponding to the layer; The failure position of the layer is determined according to the acquisition time and the preset transmission speed.

8. A substrate delamination failure testing device, characterized in that: Applicable to a testing device for performing a delamination failure test on a substrate according to any one of claims 1 to 4, the device comprising: A connection module, configured to connect the test device to a test circuit of each layer of the substrate to form a test loop; an acquisition module, configured to input a test signal into the test loop through the test device and acquire a reflected signal of the test loop; The testing module is used to compare and analyze the reflected signal with a reference signal corresponding to the delamination in a preset good product waveform library to determine whether the delamination has failed.

9. A test device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 5 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 5 to 7 are implemented.

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