Capacitor formed in interconnect layer

Abstract

The invention relates to a capacitor formed in an interconnect layer. A process for manufacturing a capacitor in an interconnect layer of a semiconductor die. The process includes forming an interconnect structure including a portion in a metal layer of the interconnect layer. The interconnect structures are laterally separated by a dielectric material in the metal layer. The dielectric material of the metal layer is selectively removed to form an opening, wherein a capacitor dielectric layer and then a conductive material are formed in the opening. The wafer is planarized to form a remaining structure in the metal layer. One electrode of the capacitor includes the remaining structure, and a second electrode of the capacitor includes the interconnect structure. A portion of the capacitor dielectric layer acts as a capacitor dielectric of the capacitor.

Description

Technical Field

[0001] The present invention generally relates to capacitors formed in an interconnect layer of a semiconductor die. Background Art

[0002] Capacitors are used in the circuitry of electronic systems. For example, they can be used as decoupling capacitors. Summary of the Invention

[0003] In some embodiments, a method includes forming a first interconnect structure, the first interconnect structure comprising a first portion located in a first metal layer of an interconnect layer of a wafer, the first portion being directly laterally separated from other interconnect structures in the first metal layer by dielectric material of the first metal layer; after forming the first interconnect structure, selectively removing a portion of the dielectric material directly laterally adjacent to the first portion to form an opening; forming a dielectric layer on the wafer, including on sidewalls of the opening directly laterally adjacent to the first portion; forming a conductive material on the wafer, the conductive material filling the opening; and planarizing the wafer, wherein the planarizing removes the conductive material above the opening to form a remaining portion of the conductive material in the opening, at least a portion of the remaining portion being located in the first metal layer. A first electrode of a capacitor comprises the first portion, and a second electrode of the capacitor comprises the remaining portion, and a capacitor dielectric of the capacitor comprises a portion of the dielectric layer directly laterally between the first portion and the remaining portion.

[0004] Illustratively, the selectively removing a portion of the dielectric material exposes a conductive sidewall of the first portion.

[0005] For example,

[0006] The forming of a first interconnect structure including a first portion in a first metal layer includes forming a second interconnect structure including a first portion in the first metal layer, the first portion of the first interconnect structure and the first portion of the second interconnect structure being directly laterally separated by the dielectric material;

[0007] the opening being directly laterally adjacent the first portion of the second interconnect structure;

[0008] The first electrode includes the first portion of the second interconnect structure.

[0009] Illustratively, the method further comprises:

[0010] After the forming of the interconnect structure and before the selectively removing, a capping layer is selectively formed on the first interconnect structure.

[0011] Illustratively, the cover layer is formed by an electroless plating process.

[0012] Illustratively, the selectively removing includes removing the dielectric material using an etching chemistry, wherein the etching chemistry is selective to the material of the capping layer.

[0013] Illustratively, the capacitor is characterized as a decoupling capacitor.

[0014] Illustratively, the method further comprises:

[0015] singulating the wafer into a plurality of semiconductor dies;

[0016] Wherein the first portion of the first interconnect structure is connected to a first voltage supply rail, and the remaining portion is connected to a second voltage supply rail.

[0017] Illustratively, the method further includes singulating the wafer into a plurality of semiconductor dies.

[0018] For example,

[0019] a first semiconductor die comprising said capacitor;

[0020] each of the other semiconductor dies of the plurality of semiconductor dies includes a capacitor having a first electrode, the first electrode including a portion that is located in the first metal layer and is part of an interconnect structure formed simultaneously with the first interconnect structure,

[0021] the capacitor of each of the other semiconductor dies of the plurality of semiconductor dies comprising a second electrode including a portion located in the first metal layer and formed concurrently with the remaining portion;

[0022] The capacitor of each of the other semiconductor dies in the plurality of semiconductor dies includes a capacitor dielectric, the capacitor dielectric including a portion of the dielectric layer, the portion of the dielectric layer being directly laterally located between the portion that is located in the first metal layer and is part of an interconnect structure formed simultaneously with the first interconnect structure, and the portion that is located in the first metal layer and is formed simultaneously with the remaining portion.

[0023] Illustratively, forming a conductive material on the wafer includes forming a conductive barrier layer on the dielectric layer, and then forming a second type of conductive material on the wafer.

[0024] Illustratively, the forming the second type of conductive material includes forming a seed layer of the second type of conductive material on the wafer, and then performing an electroplating process to form an additional amount of the second type of conductive material.

[0025] Illustratively, the method further comprises:

[0026] After planarizing the wafer, a second interconnect structure and a third interconnect structure are formed, the second interconnect structure including a first portion in a metal layer higher than the first metal layer, the second interconnect structure being electrically connected to the first interconnect structure, and the third interconnect structure including a first portion in the higher metal layer, the third interconnect structure being electrically connected to the remaining portion.

[0027] Illustratively, the forming the first interconnect structure includes planarizing the wafer to define a top surface of the first interconnect structure and a top surface of the portion of the dielectric material directly and laterally adjacent to the first portion of the first interconnect structure.

[0028] Illustratively, the forming of a first interconnect structure including a first portion located in a first metal layer includes simultaneously forming a plurality of interconnect structures including portions in the first metal layer, wherein a minimum direct lateral spacing between any two of the plurality of interconnect structures is a first width, and wherein a closest direct lateral distance between the first portion and the remaining portion is less than the first width.

[0029] Illustratively, the first interconnect structure includes a through-hole structure located directly below the first portion.

[0030] In other embodiments, a method includes forming a first interconnect structure comprising a first portion in a first metal layer of an interconnect layer of a wafer, the first portion being directly laterally separated from other interconnect structures in the first metal layer by dielectric material of the first metal layer; after forming the first interconnect structure, selectively removing a portion of the dielectric material directly laterally adjacent to the first portion to form an opening; forming a dielectric layer on the wafer, including on sidewalls of the opening directly laterally adjacent to the first portion; forming a conductive material on the wafer, the conductive material filling the opening; planarizing the wafer, wherein the planarizing removes the conductive material above the opening to form a remaining portion of the conductive material in the opening, at least a portion of the remaining portion being located in the first metal layer; and singulating the wafer into a plurality of semiconductor die, wherein a first semiconductor die of the plurality of semiconductor die comprises a decoupling capacitor, the decoupling capacitor comprising a first electrode and a second electrode, the first electrode comprising the first portion, the second electrode comprising the remaining portion, and a capacitor dielectric of the decoupling capacitor comprising a portion of the dielectric layer directly laterally between the first portion and the remaining portion.

[0031] Illustratively, the selectively removing a portion of the dielectric material exposes a conductive sidewall of the first portion.

[0032] Illustratively, the first electrode is configured to be biased by a first voltage supply rail, and the second electrode is configured to be biased by a second voltage supply rail.

[0033] Illustratively, the method further comprises:

[0034] After the forming of the first interconnect structure and before the selectively removing, a capping layer is selectively formed on the first interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0036] Figure 1 is a partial cross-sectional side view of a wafer during one stage of fabrication of a semiconductor die in accordance with one embodiment of the present invention.

[0037] Figure 2-10 is a partial cross-sectional side view of a wafer during various stages of fabrication of a semiconductor die in accordance with one embodiment of the present invention.

[0038] Figure 11 is a circuit diagram of a decoupling capacitor according to one embodiment of the present invention.

[0039] Unless otherwise indicated, the use of the same reference numerals in different drawings indicates the same items.The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0040] The following describes a detailed description of at least one mode for carrying out the invention. This description is intended to be illustrative of the invention and should not be considered limiting.

[0041] This article describes a process for fabricating a capacitor in an interconnect layer of a semiconductor die. The process includes forming an interconnect structure, the interconnect structure including a portion located in a metal layer of the interconnect layer. The interconnect structure is laterally separated in the metal layer by dielectric material. Dielectric material of the metal layer is selectively removed to form an opening, wherein a capacitor dielectric layer and then a conductive material are formed in the opening. The wafer is planarized to form a remaining structure in the metal layer. One electrode of the capacitor includes the remaining structure, and a second electrode of the capacitor includes the interconnect structure. A portion of the capacitor dielectric layer serves as the capacitor dielectric of the capacitor.

[0042] One advantage of this process that may occur in some embodiments is that the residual structure capacitor electrodes can be formed in the "unused space" of the metal layer of the interconnect layer with minimal changes to the processing of the wafer. For example, because the interconnect structure of the metal layer is formed first, the residual structure can be formed in the space not occupied by the interconnects of the metal layer. Moreover, in some embodiments, the residual structure can be formed with only one additional mask. In addition, in some embodiments where the process manufacturing rules govern the minimum lateral distance between two simultaneously formed interconnects in the metal layer, the residual structure electrode can be formed closer to the opposing interconnect electrode than if both interconnect electrodes were formed simultaneously in the metal layer.

[0043] In some embodiments, this process can be beneficial for forming decoupling capacitors. In some embodiments, the interconnect structure can be coupled to one power supply rail, and the remaining structure can be coupled to another power supply rail, providing a decoupling capacitor between the two rails. Accordingly, in some embodiments, the decoupling capacitor can be implemented in "unused" space in the interconnect layer, rather than in a specifically designated area on the die or off-die. This capacitor can be more easily added to different semiconductor circuit designs and saves die space.

[0044] Figure 1 is a cross-sectional side view of a wafer according to one embodiment of the present invention. Wafer 101 includes a substrate 103, which in one embodiment is made of single crystal silicon, but in other embodiments can be made of other types of semiconductor materials (e.g., silicon germanium, silicon carbon, gallium nitride, or other III-V semiconductor materials). In the embodiment shown, substrate 103 has a bulk semiconductor configuration. In other embodiments, substrate 103 can have other configurations, such as an SOI (semiconductor on insulator) configuration. Substrate 103 can be formed from a slice of a semiconductor ingot. In some embodiments, substrate 103 can include epitaxial layers grown on the ingot slice. Figure 1 Dielectric materials in the substrate 103 (such as, for example, isolation structures and buried oxide layers) are not shown.

[0045] During wafer processing, semiconductor devices (such as transistors, resistors, and diodes) may be formed in substrate 103 by selectively doping regions of substrate 103 with conductive dopants, such as N-type dopants (arsenic and phosphorus) and P-type dopants (boron). Figure 1In the example shown, a plurality of transistors 107 are formed in substrate 103. In the embodiment shown, the transistors are field effect transistors in which source and drain regions (e.g., region 127) are located in substrate 103 and a gate (e.g., gate 129) is located on a gate dielectric above substrate 103. However, in other embodiments, the wafer may include other types of semiconductor devices including other types of transistors.

[0046] Wafer 101 includes an interconnect layer 104 located above substrate 103. Interconnect layer 104 includes one or more metal layers, wherein layers M1-M5 are located on the substrate. Figure 1 As used herein, a "metal layer" of an interconnect layer is a layer that includes interconnects laterally separated by dielectric material, wherein at least some of the interconnects of the metal layer are between semiconductor device terminals of a semiconductor die and / or between at least one semiconductor device terminal of the die and at least one external terminal (e.g., bonding pads, bonding studs- Figure 1 The conductive signal paths or bias paths between the interconnects (not shown) provide both horizontal and vertical components. The interconnects are made of one type of conductive material (e.g., copper, gold, aluminum) and may include a conductive barrier material (e.g., tantalum, titanium, tantalum nitride, titanium nitride).

[0047] The interconnect layer 104 includes a via layer (110) located between the metal layers. The via layer includes conductive vias (e.g., 113) for providing a vertical conductive path between an interconnect (e.g., 111) of one metal layer (e.g., M3) and an interconnect (e.g., 115) of another metal layer (e.g., M4). In one embodiment, the conductive vias are made of the same type of material as the interconnects. However, in other embodiments, the conductive vias can be made of different types of conductive materials. The via layer also includes a dielectric material (e.g., oxide) that laterally separates the vias of each via layer.

[0048] exist Figure 1 , dielectric material 121 of the via and metal layers is shown as a continuous material throughout the interconnect layer 104. However, dielectric material 121 is formed in layers as part of forming the metal and intermediate via layers. Interconnect layer 104 also includes contacts (e.g., contacts 123) for providing a conductive path from an end of the semiconductor device (e.g., region 127) to the interconnect of metal layer M1.

[0049] In one embodiment, the metal layers M2-M5 and the intermediate via layer are formed by a dual damascene process, wherein the interconnects of the metal layers and the conductive vias of the underlying via layer are adjacent and formed using the same process steps. In some examples of processes for forming the metal layers, a layer of dielectric material (e.g., an oxide formed by a tetraethyl orthosilicate (TEOS) process) is formed on the wafer 101. The layer is double patterned to form openings for the conductive vias and openings for the interconnects. A barrier layer material (e.g., titanium, tantalum, titanium nitride, tantalum nitride) is formed above the wafer 101, followed by a second type of conductive material (e.g., copper or gold). The wafer 101 is then planarized to form adjacent interconnect / via structures. Figure 1 The fabrication stage is shown after metal layer M5 and underlying via layer 110 have been formed.

[0050] In other embodiments, the metal layer and the via layer can be formed using other processes. For example, the via layer and the metal layer can be formed separately. In one such example, a dielectric layer for the via layer is formed above the wafer. A photolithographically defined opening is formed in the dielectric layer. Then, a barrier layer and a second conductive layer are sequentially formed on the wafer, followed by planarization. The metal layer is then formed using the same process. However, in other embodiments, other processes may be used.

[0051] Figure 2 is Figure 1 FIG. 1 is a partial cross-sectional side view of the interconnect layer 104 after the stage of FIG. Figure 2 , a view of metal layer M4, metal layer M5, and intermediate via layer 110 is shown. Metal layer M4 includes interconnect structures 209 and 211 separated by dielectric 203. Figure 2 In the embodiment of the present invention, interconnect structures 209 and 211 include underlying interconnects ( Figure 2 2 and 3. The underlying through-hole portion (not shown for structure 211) is also shown.

[0052] Interconnect structures 206, 207, and 208 each include interconnects 213, 217, and 221, respectively, located in metal layer M5, and vias 215, 219, and 223, respectively, located in via layer 110. The interconnects and vias also include external barrier layer surfaces. For example, a portion of interconnect structure 206 includes a portion of barrier layer 237, a portion of interconnect structure 207 includes a portion of barrier layer 239, and a portion of interconnect structure 208 includes a portion of barrier layer 241. Interconnect structures 206-208 are laterally separated from each other by dielectric material 205 of metal layer M5 and via layer 110.

[0053] The dielectric material of interconnect layer 104 includes a dielectric copper diffusion layer 242 located above metal layer M4. In one embodiment, layer 242 is made of silicon nitride or silicon carbon nitride, but can be made of other types of dielectric materials in other embodiments. Openings are formed in layer 242 so that the barrier layer surfaces of vias 215, 219, and 223 of via layer 110 can contact the interconnects of metal layer M4.

[0054] like Figure 2 As shown, capping layers 231, 233, and 235 are selectively grown on interconnects 213, 217, and 221, respectively, by a self-aligned electroless plating process. In one embodiment, layers 231, 233, and 235 are made of a cobalt-based material. However, layers 231, 233, and 235 may be made of other types of materials that can be selectively grown and selectively etched relative to dielectric material 205. Capping layers 231, 233, and 235 act as etching masks in subsequent processes and also act as copper diffusion barriers.

[0055] Figure 3 is a partial cross-sectional side view of interconnect layer 104 after forming a patterned mask 301 on wafer 101, wherein patterned mask 301 has photolithographically defined openings 303 to expose the top surfaces of layers 231, 233, and 235 and portions of dielectric material 205. In one embodiment, mask 301 is made of photoresist, however other types of mask materials may be used in other embodiments.

[0056] Figure 4 is a partial cross-sectional side view of interconnect layer 104 after openings are formed in dielectric material 205. Openings 401 and 403 are formed by a timed anisotropic etch in which the etch chemistry is selective to the materials of mask 301, layers 231, 233, and 235, and barrier layers 237, 239, and 241, and is selective relative to dielectric material 205. In the embodiment shown, the timed etch removes dielectric material 205 to a level below the bottoms of interconnects 213, 217, and 221. However, in other embodiments, openings 401 and 403 may be etched to different levels, including to the top surface of layer 242 or to the top surface of interconnect structure 209.

[0057] Figure 5 FIG. 1 is a partial cross-sectional side view of interconnect layer 104 after mask 301 is removed and a capacitor dielectric material layer 501 is deposited over wafer 101, including in openings 401 and 403. In one embodiment, layer 501 is made of silicon oxide and has a thickness of 5-30 nm, but in other embodiments may have other thicknesses and be made of other types of dielectric materials, including high-K dielectric materials such as Al2O3, HfO2, BaSm2Ti4O, and others. 12, Sm2TiO7. In the embodiment shown below, the thickness of the dielectric layer 501 defines the distance between the electrodes of the capacitor formed subsequently.

[0058] Figure 6 4 is a partial cross-sectional side view of interconnect layer 104 after forming a conductive barrier layer 601 and a seed layer 603 over wafer 101, including in openings 401 and 403. In one embodiment, barrier layer 601 is made of tantalum, titanium, tantalum nitride, or titanium nitride, but may be made of other types of barrier materials in other embodiments.

[0059] The seed layer 603 is formed on the layer 601 from metal (eg, copper, gold) by sputtering, atomic layer deposition, seedless plating, or other methods.

[0060] Figure 7 1 is a partial cross-sectional side view of interconnect layer 104 after metal layer 701 has been formed on wafer 101 to fill the remaining portions of openings 401 and 403. In one embodiment, layer 701 is made of copper and is formed by a plating process using seed layer 603 as a cathode plating layer. However, in other embodiments, layer 701 can be made by other processes and / or made of other types of materials.

[0061] Figure 8 1 is a partial cross-sectional side view of interconnect layer 104 after wafer 101 has been planarized (e.g., using chemical mechanical polishing (CMP)) to remove the conductive material of layers 601, 603, and 701 outside of openings 401 and 403 to form remaining structures 800 and 802. Figure 8 As shown, remaining structure 800 includes portion 801 of layer 701, a portion of seed layer 603, and a portion of barrier layer 601. Remaining structure 802 includes portion 803 of layer 701, a portion of seed layer 603, and a portion of barrier layer 601. Planarization also removes portions of capacitive dielectric layer 501 outside of openings 401 and 403, and removes capping layers 231, 233, and 235.

[0062] like Figure 8 As shown, interconnects 213, 217, and 221 are separated from remaining structures 800 and 802 by the remaining portion of dielectric layer 501. In subsequent processing, remaining structures 800 and 802 will be electrically connected together to form one electrode of the capacitor, and interconnects 213, 217, and 221 are or will be electrically connected together to form the other electrode of the capacitor. In the embodiment shown, the capacitance of the capacitor depends on the amount of surface area of ​​the two electrodes in contact with the remaining capacitive dielectric material layer 501, the thickness of dielectric material layer 501, and the dielectric constant of the dielectric material type of dielectric layer 501.

[0063] Figure 9 is a partial cross-sectional side view of interconnect layer 104 after forming a diffusion barrier layer 901 on the planarized surface of wafer 101. In one embodiment, layer 901 is made of a type of dielectric material, such as silicon nitride or silicon carbon nitride, to prevent copper from diffusing in interconnect layer 104. However, other types of dielectric materials may be used in other embodiments.

[0064] Figure 10 FIG1 is a partial cross-sectional side view of interconnect layer 104 after forming another metal layer M6 and via layer 1002 on wafer 101. Metal layer M6 and via layer 1002 each include portions of interconnect structures 1003, 1005, and 1007, as well as portions of dielectric material 1001. Dielectric diffusion layer 1009 is formed on metal layer M6.

[0065] In the embodiment shown, interconnect structure 1003 is in electrical contact with interconnect structure 206. Interconnect structure 1005 is in electrical contact with remaining structure 802, and interconnect structure 1007 is in electrical contact with interconnect structure 208.

[0066] In one embodiment, interconnects 213, 217, and 221 may be a voltage supply rail (e.g., Figure 11 The VDD voltage supply rail 1105 in FIG. 8 is a portion of the VDD voltage supply rail 1105 in FIG. 8 , and the remaining structures 800 and 802 can be connected to another voltage supply rail ( Figure 11 VSS voltage supply rail 1107 in the circuit) to provide decoupling capacitors between the two voltage supply rails. Figure 11 , which shows a decoupling capacitor 1103, one electrode of which is connected to the VDD voltage supply rail 1105 and the other electrode of which is connected to the VSS voltage supply rail 1107. A decoupling capacitor is a capacitor connected between two nodes to decouple AC current from DC current, wherein the decoupling capacitor allows AC current on one node (e.g., the VDD voltage supply rail 1105) to pass to the other node (e.g., the VSS voltage supply rail 1107). In some cases, a decoupling capacitor may be referred to as a bypass capacitor. Decoupling capacitors can be used to reduce noise on the voltage supply rail to keep the supply voltage within tolerance even when the current draw changes rapidly. A decoupling capacitor placed between the VDD rail and the VSS rail can be used to provide a local energy source to minimize the VDD rail voltage drop during circuit operation.

[0067] One advantage of using the above process to manufacture decoupling capacitors is that the decoupling capacitors do not necessarily require precise capacitance values ​​for the circuit to operate effectively. Accordingly, depending on the design, the decoupling capacitors can be located anywhere in the interconnect layer where there is space. Because the capacitance of the decoupling capacitors does not have to be precise, the lateral area of ​​the remaining electrodes (e.g., 802) does not have to be clearly defined, thereby simplifying the mask definition. In addition, the decoupling capacitors connected between the voltage supply rails can be distributed at various locations of the supply rails. Accordingly, decoupling capacitors can be manufactured at multiple locations in the interconnect layer where space is available.

[0068] In other embodiments, the processes described herein can be used to form other types of capacitors, including, for example, smoothing capacitors for voltage regulators, sampling capacitors for sample-and-hold circuits, and capacitors for matching networks. In some embodiments of RF circuit applications, adding capacitance as described herein can improve the quality factor (i.e., keep energy dissipation low and energy storage high), provide superior cutoff frequency, and provide better matching due to lateral coupling.

[0069] One advantage of the process described herein for fabricating a capacitor is that the lateral distance between two capacitor electrode structures in an interconnect layer can be brought closer together than if both electrode structures were formed simultaneously in the same metal layer. Figure 10 The lateral distance 1024 between the electrode residual structure 800 and the electrode interconnect structure 207 in the metal layer M5 is the thickness of the capacitor dielectric layer 501. In one embodiment, this thickness is in the range of 5 to 30 nm.

[0070] If both electrodes include interconnects formed simultaneously with other interconnects of the metal layer, the lateral spacing between the two interconnects will be limited by the process spacing rules used to form the laterally adjacent interconnects. For example, the process spacing rules may limit the lateral spacing to no closer than a certain width (e.g., 15 nm in some advanced technologies, but in other technologies, including less advanced technologies, the minimum lateral spacing may be wider). Figure 10 In the embodiment of FIG, the width 1026 between structures 1005 and 1007 is the minimum lateral spacing between any two interconnects in the metal layers on wafer 101. Using the processes described herein, it is possible to reduce the lateral spacing between capacitive electrodes by using thinner capacitor dielectric layers (e.g., layer 501). In some embodiments, the ability to more closely space capacitor electrodes not only allows for increased capacitance, but also allows the capacitive electrodes to be more compact. For example, in Figure 10 In FIG. 8 , electrode structure 800 is laterally adjacent to both structures 206 and 207 , wherein the total lateral spacing between the three structures is less than if the three structures were formed simultaneously.

[0071] Another advantage of the processes of at least some embodiments described herein is that the capacitive dielectric layer (e.g., 501) can be a different type of dielectric material than the other types of dielectric materials of the interconnect layers (e.g., 205). For example, the capacitive dielectric layer can have a higher (or lower) dielectric constant than material 205.

[0072] exist Figure 10 After the manufacturing stages shown, subsequent processes can be performed on wafer 101. For example, additional metal layers and via layers can be formed above metal layer M6. After forming the final metal layer (M6 or higher) of interconnect layer 104, die terminals (e.g., bumps, pads, pillars - not shown) will be formed above the final metal layer, wherein each die terminal is electrically connected to the interconnect on the final metal layer. Thereafter, wafer 101 is singulated into a plurality of semiconductor dies, wherein each die includes at least one capacitor including an electrode structure similar to structures 206, 207, 208, 800, and 802. The dies are then protected in a semiconductor package, which can be implemented in electronic systems, such as RF communication systems, motor controllers, automotive electronic systems, computers, industrial equipment, appliances, and cellular phones.

[0073] In some embodiments, remaining capacitive electrode structures (similar to structures 800 and 802 ) may be located in other portions of metal layer M5 or in other metal layers of wafer 101 .

[0074] Furthermore, the process described herein can be used to manufacture multi-metal layer capacitors. Figure 8 , the interconnect structure (e.g., 209) in metal layer M4 can extend across the entire capacitor structure. In this embodiment, the opening in dielectric material 205 will extend to the top surface of this interconnect structure of metal layer M4, wherein the capacitor dielectric will be formed on the top surface of the interconnect structure, and wherein the interconnect structure will be part of the capacitor electrode. In some embodiments, the interconnect structure / via structure (e.g., 206) in the via layer (110) and metal layer (M5) immediately above will completely surround the perimeter of the top surface of the interconnect structure of the lower metal layer (M4). In embodiments where etching comprises isotropic etching, all dielectric material within the surrounding interconnect structure / via structure will be removed, wherein the entire surrounding structure and the interconnect structure of the lower metal layer (M4) will be part of the capacitive electrode.

[0075] As disclosed herein, a first structure is "directly above" a second structure if the first structure is positioned above the second structure on a line oriented perpendicular to the generally planar major side of a wafer or substrate. Figure 10, structure 1007 is directly above structure 211. Structure 1007 is not directly above structure 209. As disclosed herein, a first structure is "directly below" or "directly beneath" a second structure if the first structure is positioned below the second structure on a line oriented perpendicular to the generally planar major side of the wafer or substrate. For example, in Figure 10 In , structure 209 is directly below structure 1003. Structure 209 is not directly below structure 1007. A structure is "directly between" two other structures on a line if the other two structures are on opposite sides of the line. For example, in Figure 10 The remaining structure 800 is Figure 10 213 and interconnect 217 on a line in the cross-sectional side view of FIG. Structure 209 is not located directly between structures 1003 and 1005. A first structure is “directly transverse” to a second structure if the first structure and the second structure are located on a line parallel to the major side of the generally planar surface of the wafer or substrate. For example, structure 1003 and structure 1005 are directly transverse to each other. A structure is “directly transversely located” to two structures if the two other structures are located on opposite sides of the structure on a line parallel to the major side of the generally planar surface of the wafer or substrate. For example, Figure 10 , structure 802 is laterally located centered between structure 206 and structure 208. A surface is at a "higher elevation" than another surface if it is positioned closer to the top of the active side of the wafer or die on a line perpendicular to the generally planar major side of the wafer or die. Figure 1-10 In the view of FIG, the active side of the wafer is the top side of the figure. For example, structure 1003 is at a higher elevation than structure 211.

[0076] Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

[0077] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and therefore, the appended claims are intended to cover within their scope all such changes and modifications as fall within the true spirit and scope of this invention.

Claims

1. A method, characterized in that include: forming a first interconnect structure, the first interconnect structure comprising a first portion in a first metal layer of an interconnect layer of a wafer, the first portion being directly laterally separated from other interconnect structures in the first metal layer by a dielectric material of the first metal layer; After said forming said first interconnect structure, selectively removing a portion of said dielectric material directly and laterally adjacent to said first portion to form an opening; forming a dielectric layer on the wafer, including on sidewalls of the opening directly laterally adjacent to the first portion; forming a conductive material on the wafer, wherein the conductive material fills the opening; planarizing the wafer, wherein the planarizing removes the conductive material above the opening to form a remaining portion of the conductive material in the opening, at least a portion of the remaining portion being located in the first metal layer; Wherein a first electrode of a capacitor comprises the first portion and a second electrode of the capacitor comprises the remaining portion, a capacitor dielectric of the capacitor comprises a portion of the dielectric layer directly laterally located between the first portion and the remaining portion.

2. The method according to claim 1, wherein: The forming of a first interconnect structure including a first portion in a first metal layer includes forming a second interconnect structure including a first portion in the first metal layer, the first portion of the first interconnect structure and the first portion of the second interconnect structure being directly laterally separated by the dielectric material; the opening being directly laterally adjacent the first portion of the second interconnect structure; The first electrode includes the first portion of the second interconnect structure.

3. The method according to claim 1, characterized in that Also includes: After the forming of the interconnect structure and before the selectively removing, a capping layer is selectively formed on the first interconnect structure.

4. The method according to claim 1, wherein Also included is singulating the wafer into a plurality of semiconductor dies.

5. The method according to claim 4, characterized in that: a first semiconductor die comprising said capacitor; each of the other semiconductor dies of the plurality of semiconductor dies includes a capacitor having a first electrode, the first electrode including a portion that is located in the first metal layer and is part of an interconnect structure formed simultaneously with the first interconnect structure, the capacitor of each of the other semiconductor dies of the plurality of semiconductor dies comprising a second electrode including a portion located in the first metal layer and formed concurrently with the remaining portion; the capacitor of each of the other semiconductor dies of the plurality of semiconductor dies comprises a capacitor dielectric, the capacitor dielectric comprising a portion of the dielectric layer, the portion of the dielectric layer being directly laterally located between; The portion that is in the first metal layer and is part of an interconnect structure formed simultaneously with the first interconnect structure, and the portion that is in the first metal layer and is formed simultaneously with the remaining portion.

6. The method according to claim 1, characterized in that Also includes: After planarizing the wafer, a second interconnect structure and a third interconnect structure are formed, the second interconnect structure including a first portion in a metal layer higher than the first metal layer, the second interconnect structure being electrically connected to the first interconnect structure, and the third interconnect structure including a first portion in the higher metal layer, the third interconnect structure being electrically connected to the remaining portion.

7. The method according to claim 1, characterized in that The forming of a first interconnect structure including a first portion located in a first metal layer includes simultaneously forming a plurality of interconnect structures including portions in the first metal layer, wherein a minimum direct lateral spacing between any two of the plurality of interconnect structures is a first width, and wherein a closest direct lateral distance between the first portion and the remaining portions is less than the first width.

8. A method, characterized in that include: forming a first interconnect structure, the first interconnect structure comprising a first portion in a first metal layer of an interconnect layer of a wafer, the first portion being directly laterally separated from other interconnect structures in the first metal layer by a dielectric material of the first metal layer; After said forming said first interconnect structure, selectively removing a portion of said dielectric material directly and laterally adjacent to said first portion to form an opening; forming a dielectric layer on the wafer, including on sidewalls of the opening directly laterally adjacent to the first portion; forming a conductive material on the wafer, wherein the conductive material fills the opening; planarizing the wafer, wherein the planarizing removes the conductive material above the opening to form a remaining portion of the conductive material in the opening, at least a portion of the remaining portion being located in the first metal layer; The wafer is singulated into a plurality of semiconductor die, wherein a first semiconductor die of the plurality of semiconductor dies comprises a decoupling capacitor, the decoupling capacitor comprising a first electrode and a second electrode, the first electrode comprising the first portion, the second electrode comprising the remaining portion, a capacitor dielectric of the decoupling capacitor comprising a portion of the dielectric layer directly laterally located between the first portion and the remaining portion.

9. The method according to claim 8, characterized in that The selectively removing a portion of the dielectric material exposes a conductive sidewall of the first portion.

10. The method according to claim 8, characterized in that Also includes: After the forming of the first interconnect structure and before the selectively removing, a capping layer is selectively formed on the first interconnect structure.

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