Method, device and equipment for regulating and controlling output electric power of inverter and storage medium

Abstract

The invention provides an inverter output electric power regulation and control method, device and equipment and a storage medium, and particularly relates to the technical field of inverter output electric power regulation and control. The method comprises the following steps: a processor obtains a direct current bus voltage of an nth switching mode of the inverter, a floating ground capacitor voltage of the nth switching mode at a (k + 1) th moment and an inverter neutral point voltage of the nth switching mode at the (k + 1) th moment; calculating to obtain a cost value of the nth switching mode; comparing the cost values of every two switching modes in the cost values of the first n switching modes to obtain a minimum cost value; and regulating and controlling the output electric power of the inverter according to the floating ground capacitor voltage corresponding to the minimum cost value and the neutral point voltage of the inverter. According to the method, the harmonic content of the output voltage of the inverter is reduced, the fluctuation of the output voltage of the inverter is reduced, the stability of the output voltage of the inverter is improved, and the accuracy and stability of the output electric power of the inverter are further improved.

Description

Technical Field

[0001] The present application relates to the technical field of output power control of an inverter, and in particular to a method, device, equipment and storage medium for controlling the output power of an inverter. Background Art

[0002] With the rapid development of power electronics technology, the use of renewable energy is becoming increasingly widespread, and a large amount of clean energy is continuously flowing into the power grid. Inverters, as key devices connecting renewable energy to the power grid, are showing a rapid growth in both types and quantity.

[0003] In the field of photovoltaic power supply applications, transformerless inverters (five-level active neutral-point clamped inverters) are gradually becoming a popular inverter. This inverter not only effectively reduces system cost and weight, but also improves energy conversion efficiency, bringing many advantages to the promotion and application of photovoltaic systems.

[0004] However, the voltages of the DC link capacitor and floating capacitor in the inverter often differ significantly from the set reference values, which in turn causes the output power of the inverter to be unstable, thereby affecting the power generation efficiency and reliability of the entire photovoltaic system. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide an inverter output power control method, device, equipment and storage medium to solve the above problems, improve the stability of the inverter output power, and thus improve the power generation efficiency and reliability of the entire photovoltaic system.

[0006] In a first aspect, an embodiment of the present application provides a method for controlling output power of an inverter, the method comprising: The processor obtains a DC bus voltage of the inverter in an nth switching mode, a floating capacitor voltage at a k+1th moment in the nth switching mode, and a neutral point voltage of the inverter at a k+1th moment in the nth switching mode; The processor calculates a cost value of the nth switching mode according to the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment of the nth switching mode, and the neutral point voltage of the inverter at the k+1th moment of the nth switching mode; wherein the cost value is used to represent the difference between the floating capacitor voltage at the k+1th moment and the floating capacitor voltage at the kth moment, and the difference between the neutral point voltage of the inverter at the k+1th moment and the neutral point voltage of the inverter at the kth moment; The processor compares the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain a minimum cost value; The processor regulates the output power of the inverter according to the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value.

[0007] Preferably, the processor calculates the cost value of the nth switching mode according to the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment of the nth switching mode, and the inverter neutral point voltage at the k+1th moment of the nth switching mode, including: The cost value of the nth switching mode is calculated according to the following formula:

[0008] in, is the cost value of the nth switching mode, is the weight coefficient, Used to indicate the inverter neutral point voltage at the k+1th moment of the nth switching mode, is the DC bus voltage of the inverter in the nth switching mode, is the floating capacitor voltage of one of phases a, b, and c at the k+1th moment in the nth switching mode.

[0009] Preferably, the calculation formula for the neutral point voltage of the inverter at the k+1th moment in the nth switching mode is as follows:

[0010] in, Used to indicate the inverter neutral point voltage at the k+1th moment of the nth switching mode, Used to indicate the inverter neutral point voltage at the kth moment of the nth switching mode, is the output time of the inverter output w-th voltage vector, is the capacitance of the DC link capacitor, is the inverter's a-phase output current, is the inverter’s b-phase output current, is the inverter’s c-phase output current, is the neutral point current coefficient of phase a when the inverter outputs the wth voltage vector, is the neutral point current coefficient of phase b when the inverter outputs the wth voltage vector, is the neutral point current coefficient of phase a when the inverter outputs the wth voltage vector.

[0011] Preferably, the calculation formula of the floating capacitor voltage at the k+1th moment in the nth switching mode is as follows:

[0012] in, is the floating capacitor voltage at the k+1th moment of the nth switching mode, is the floating capacitor voltage at the kth moment of the nth switching mode, is the output current of the inverter at the kth moment of the nth switching mode, is the output time of the inverter output w-th voltage vector, is the capacitance of the floating capacitor, is the floating capacitance current coefficient of phase x when the inverter outputs the wth voltage vector.

[0013] Preferably, the method further comprises: The processor obtains an output state parameter of an inverter phase a bridge arm, an output state parameter of an inverter phase b bridge arm, and an output state parameter of an inverter phase c bridge arm; The processor calculates the common mode voltage of the wth voltage vector output by the inverter based on the output state parameter of the inverter phase a bridge arm, the output state parameter of the inverter phase b bridge arm, the output state parameter of the inverter phase c bridge arm, and the DC bus voltage of the inverter in the nth switching mode; The processor compares the common mode voltages of every two voltage vectors among the common mode voltages of the first w voltage vectors output by the inverter to obtain a minimum common mode voltage of the inverter; The processor generates an output pulse of the inverter according to a voltage vector sequence corresponding to a minimum common-mode voltage of the inverter.

[0014] Preferably, the processor calculates the common-mode voltage of the wth voltage vector output by the inverter based on the output state parameter of the inverter's phase a bridge arm, the output state parameter of the inverter's phase b bridge arm, the output state parameter of the inverter's phase c bridge arm, and the DC bus voltage of the inverter in the nth switching mode, including:

[0015] in, is the common mode voltage of the inverter output w-th voltage vector, is the DC bus voltage of the inverter in the nth switching mode, is the output state parameter of the inverter's phase a bridge arm, is the output state parameter of the inverter's b-phase bridge arm, is the output state parameter of the C-phase bridge arm of the inverter.

[0016] The output power control method of the inverter provided in this application brings the following beneficial effects: The present application provides a method for controlling the output power of an inverter, in which a processor compares the cost values ​​of each of the first n switching modes to obtain a minimum cost value, and controls the output power of the inverter based on the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value. This method can determine the floating capacitor voltage and the inverter neutral point voltage based on the minimum cost value, and then determine the output power of the inverter, thereby maintaining the stability of the inverter's output power. This method reduces the harmonic content of the inverter's output voltage, reduces the fluctuation of the inverter's output voltage, improves the stability of the inverter's output voltage, and thereby improves the accuracy and stability of the inverter's output power.

[0017] In a second aspect, the present application further provides an output power control device for an inverter, the device comprising: An acquisition module is used to acquire the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment in the nth switching mode, and the inverter neutral point voltage at the k+1th moment in the nth switching mode; a calculation module, configured to calculate a cost value of the nth switching mode of the inverter based on a DC bus voltage of the nth switching mode, a floating capacitor voltage at the k+1th moment of the nth switching mode, and a neutral point voltage of the inverter at the k+1th moment of the nth switching mode; wherein the cost value is used to represent a difference between the floating capacitor voltage at the k+1th moment and the floating capacitor voltage at the kth moment, and a difference between the neutral point voltage of the inverter at the k+1th moment and the neutral point voltage of the inverter at the kth moment; a comparison module, configured to compare the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain a minimum cost value; The control module is used to regulate the output electric power of the inverter according to the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value.

[0018] The output electric power control device of the inverter provided in the embodiment of the present application has the same technical features as the output electric power control method of the inverter provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0019] In a third aspect, the present application provides a computing device, including a memory and a processor; One or more computer programs are stored in the memory, and the one or more computer programs include instructions; when the instructions are executed by the processor, the computing device executes the method as described in any one of the first aspects.

[0020] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program for executing the method as described in any one of the first aspects.

[0021] In a fifth aspect, the present application provides a computer program product, which includes one or more computer instructions. When the computer instructions are executed by a computer, the computer executes the method as described in any one of the first aspects.

[0022] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures particularly pointed out in the description and drawings.

[0023] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 A schematic flow chart of a method for controlling output power of an inverter provided in an embodiment of the present application; Figure 2 A schematic diagram of the inverter structure provided in an embodiment of the present application; Figure 3 A schematic diagram of voltage vectors provided in an embodiment of the present application; Figure 4 A schematic diagram of some voltage vectors provided in an embodiment of the present application; Figure 5 A waveform diagram of the inverter output voltage vector provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of an output power control device of an inverter provided in an embodiment of the present application; Figure 7 A schematic diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] To facilitate understanding of this embodiment, the embodiments of this application are described in detail below.

[0028] The embodiment of the present application provides a method for controlling the output power of an inverter, such as Figure 1 As shown, Figure 1 A flow chart of a method for controlling the output power of an inverter provided in an embodiment of the present application. The method includes the following steps: S101: The processor obtains the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment in the nth switching mode, and the inverter neutral point voltage at the k+1th moment in the nth switching mode.

[0029] Specifically, if Figure 2 As shown, Figure 2 Schematic diagram of the inverter structure provided in an embodiment of the present application. The inverter includes: a floating capacitor Cf, a DC link capacitor, a first switching element S1, a second switching element S2, a third switching element S3, a fourth switching element S4, a fifth switching element S5, a sixth switching element S6, a seventh switching element S7, an eighth switching element S8, a ninth switching element S9, a tenth switching element S10, an eleventh switching element S11, and a twelfth switching element S12; wherein the DC link capacitor includes: a first DC link capacitor C1 and a second DC link capacitor C2.

[0030] The source of the first switching element S1 is respectively connected to the positive electrode of the DC bus voltage Udc and the first end of the first DC link capacitor C1, the drain of the first switching element S1 is connected to the source of the second switching element S2, and the drain of the second switching element S2 is respectively connected to the source of the fifth switching element S5 and the source of the tenth switching element S10.

[0031] The drain of the seventh switching element S7 is respectively connected to the negative electrode of the DC bus voltage Udc and the first end of the second DC link capacitor C2, the source of the seventh switching element S7 is connected to the drain of the eighth switching element S8, and the drain of the eighth switching element S8 is respectively connected to the drain of the fourth switching element S4 and the drain of the eleventh switching element S11.

[0032] The drain of the ninth switching element S9 is respectively connected to the second end of the first DC link capacitor C1, the second end of the second DC link capacitor C2 and the source of the third switching element S3, the source of the ninth switching element S9 is connected to the drain of the tenth switching element S10, and the drain of the third switching element S3 is connected to the source of the fourth switching element S4.

[0033] The drain of the fifth switching element S5 is respectively connected to the first end of the floating capacitor Cf and the source of the sixth switching element S6, the drain of the sixth switching element S6 is respectively connected to the output voltage U0 of the inverter and the source of the twelfth switching element S12, and the drain of the twelfth switching element S12 is respectively connected to the second end of the floating capacitor Cf and the source of the eleventh switching element S11.

[0034] The output voltage of the inverter corresponding to each of the above switching modes has a mapping relationship, as shown in Table 1, which is a switching mode table provided in an embodiment of the present application.

[0035] Table 1:

[0036] In Table 1, 1 indicates that the IGBT is in the on state, 0 indicates that the IGBT is in the off state, and Mode represents each switching mode. Each bridge arm of the inverter has eight switching modes, but the output voltage of the inverter has five parameters: -2E, -E, 0, E, and 2E. Therefore, the output voltage of the inverter needs to be converted by switching between different switching modes to avoid the occurrence of undesirable output voltages. The switching modes corresponding to the same inverter output voltage are called redundant modes. As can be seen from Table 1, when the inverter output voltage is E or -E, there are two redundant modes. However, the redundant modes have opposite effects on the floating capacitor voltage. Therefore, by selecting different redundant modes, the floating capacitor voltage can be balanced to keep the floating capacitor voltage stable.

[0037] The DC bus voltage is obtained by connecting a voltmeter in parallel to the positive pole of the DC bus voltage and the negative pole of the DC bus voltage.

[0038] The calculation formula for the inverter neutral point voltage at the k+1th moment in the above-mentioned nth switching mode is as follows:

[0039] in, Used to indicate the inverter neutral point voltage at the k+1th moment of the nth switching mode, Used to indicate the inverter neutral point voltage at the kth moment of the nth switching mode, is the output time of the inverter output w-th voltage vector, is the capacitance of the DC link capacitor, is the inverter's a-phase output current, is the inverter’s b-phase output current, is the inverter’s c-phase output current, is the neutral point current coefficient of phase a when the inverter outputs the wth voltage vector, is the neutral point current coefficient of phase b when the inverter outputs the wth voltage vector, is the neutral point current coefficient of phase a when the inverter outputs the wth voltage vector.

[0040] The DC bus voltage and DC link current of the inverter in the nth switching mode are constant. The inverter neutral point voltage at the kth moment in the nth switching mode is equal to twice the current flowing through the first DC link capacitor at the kth moment in the nth switching mode, and is also equal to twice the current flowing through the second DC link capacitor at the kth moment in the nth switching mode. Therefore, the relationship function between the DC link current and the current flowing through the first DC link capacitor at the kth moment in the nth switching mode and the current flowing through the second DC link capacitor at the kth moment in the nth switching mode is:

[0041] in, is the DC link current, is the current flowing through the first DC link capacitor at the kth moment of the nth switching mode, is the current flowing through the second DC link capacitor at the kth moment of the nth switching mode, is the capacitance of the first DC link capacitor, is the capacitance of the second DC link capacitor.

[0042] More specifically, the DC link current is calculated according to the following formula:

[0043] in, is the DC link current, is the inverter's a-phase output current, is the inverter’s b-phase output current, is the C-phase output current of the inverter.

[0044] Referring to Table 1, the mapping relationship between the neutral point current coefficient of phase a when the inverter outputs the wth voltage vector, the neutral point current coefficient of phase b when the inverter outputs the wth voltage vector, and the neutral point current coefficient of phase c when the inverter outputs the wth voltage vector and the switching mode is the same Right now

[0045] ; in, For switch mode.

[0046] The calculation formula for the floating capacitor voltage at the k+1th moment in the above-mentioned nth switching mode is as follows:

[0047] in, is the floating capacitor voltage at the k+1th moment of the nth switching mode, is the floating capacitor voltage at the kth moment of the nth switching mode, is the output current of the inverter at the kth moment of the nth switching mode, is the output time of the inverter output w-th voltage vector, is the capacitance of the floating capacitor, is the floating capacitance current coefficient of phase x when the inverter outputs the wth voltage vector.

[0048] The current coefficient flowing through the floating capacitor when the above-mentioned inverter outputs the wth voltage vector can represent a function of the relationship between the output current of the inverter at the kth moment of the nth switching mode and the current flowing through the floating capacitor at the kth moment of the nth switching mode, that is, ; in, is the current flowing through the floating capacitor at the kth moment of the nth switching mode, is the output current of the inverter at the kth moment of the nth switching mode.

[0049] Referring to Table 1, the floating capacitance current coefficient of the x-phase when the inverter outputs the w-th voltage vector is calculated according to the following formula:

[0050] in, For switch mode.

[0051] S102, the processor calculates the cost value of the nth switching mode based on the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment of the nth switching mode, and the inverter neutral point voltage at the k+1th moment of the nth switching mode.

[0052] The cost value is used to represent the difference between the floating capacitor voltage at the k+1th moment and the floating capacitor voltage at the kth moment, and the difference between the inverter neutral point voltage at the k+1th moment and the inverter neutral point voltage at the kth moment.

[0053] Specifically, the cost value of the nth switching mode is calculated according to the following formula:

[0054] in, is the cost value of the nth switching mode, is the weight coefficient, Used to indicate the inverter neutral point voltage at the k+1th moment of the nth switching mode, is the DC bus voltage of the inverter in the nth switching mode, is the floating capacitor voltage of one of phases a, b, and c at the k+1th moment in the nth switching mode.

[0055] S103 : The processor compares the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain a minimum cost value.

[0056] Specifically, the cost value is a quantitative indicator that comprehensively considers multiple factors affecting the output voltage of the inverter, namely, the difference between the floating capacitor voltage at the k+1th moment and the floating capacitor voltage at the kth moment, and the difference between the inverter neutral point voltage at the k+1th moment and the inverter neutral point voltage at the kth moment.

[0057] Variations in floating capacitor voltage and inverter neutral point voltage at different times directly affect the inverter's output voltage, and thus the harmonic content of the inverter's output voltage. Harmonics in the inverter's output voltage can adversely affect load devices, such as causing overheating and reducing their lifespan. The floating capacitor voltage and inverter neutral point voltage corresponding to the minimum cost switching mode minimize the harmonic content of the inverter's output voltage, thereby improving output voltage quality.

[0058] S104: The processor regulates the output power of the inverter according to the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value.

[0059] Specifically, the floating capacitor voltage and inverter neutral point voltage corresponding to the switching mode with the minimum cost value obtained above minimize the harmonic content of the inverter's output voltage, thereby minimizing the inverter's output power loss. During inverter operation, different switching modes produce different power losses, such as switching loss and conduction loss. The minimum cost value means that the total system loss is likely to be the lowest under this switching mode.

[0060] In this way, when the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value are used to control the inverter output voltage, the harmonic content of the inverter output voltage is reduced, and the stability of the inverter output voltage is improved, thereby effectively reducing the output power loss of the inverter and improving the efficiency of the inverter's output power.

[0061] An embodiment of the present application provides a method for controlling the output power of an inverter, in which a processor compares the cost values ​​of each of the first n switching modes to obtain a minimum cost value, and controls the output power of the inverter based on the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value. This method can determine the floating capacitor voltage and the inverter neutral point voltage based on the minimum cost value, and thus determine the output power of the inverter, thereby maintaining the stability of the inverter's output power. Compared with the prior art, which determines the vector of the inverter's output voltage by performing complex calculations on the time of the inverter's output voltage, this method has a simple calculation process. By comparing the minimum cost value obtained, the floating capacitor voltage and the inverter neutral point voltage used to control the inverter's output power can be determined. This method reduces the harmonic content of the inverter's output voltage, reduces the fluctuation of the inverter's output voltage, improves the stability of the inverter's output voltage, and thereby improves the accuracy and stability of the inverter's output power.

[0062] In one embodiment, the processor obtains the output state parameters of the inverter's phase a bridge arm, the output state parameters of the inverter's phase b bridge arm, and the output state parameters of the inverter's phase c bridge arm, and calculates the common-mode voltage of the inverter output w-th voltage vector based on the inverter's phase a bridge arm output state parameters, the inverter's phase b bridge arm output state parameters, the inverter's phase c bridge arm output state parameters, and the DC bus voltage of the inverter's n-th switching mode.

[0063] Specifically, the calculation formula for the common-mode voltage of the w-th voltage vector output by the inverter is as follows:

[0064] in, is the common mode voltage of the inverter output w-th voltage vector, is the DC bus voltage of the inverter in the nth switching mode, is the output state parameter of the inverter's phase a bridge arm, is the output state parameter of the inverter's b-phase bridge arm, is the output state parameter of the C-phase bridge arm of the inverter.

[0065] The processor compares the common-mode voltages of every two voltage vectors output by the inverter among the common-mode voltages of the first w voltage vectors output by the inverter to obtain the minimum common-mode voltage of the inverter, and generates an output pulse of the inverter according to a voltage vector sequence corresponding to the minimum common-mode voltage of the inverter.

[0066] More specifically, the value ranges of the output state parameters of the inverter's phase a bridge arm, the inverter's phase b bridge arm, and the inverter's phase c bridge arm are {0, 1, 2, 3, 4}, and the inverter's output voltage, i.e., the redundant vector voltage, includes: the output voltage of the phase a, the output voltage of the phase b, and the output voltage of the phase c. Figure 3 As shown, Figure 3 The voltage vector diagram provided in the embodiment of the present application. The calculation formulas for the above-mentioned a-phase output voltage, b-phase output voltage and c-phase output voltage are as follows:

[0067] in, is the output voltage of phase a, is the b-phase output voltage, is the c-phase output voltage, is the output state parameter of the inverter's phase a bridge arm, is the output state parameter of the inverter's b-phase bridge arm, is the output state parameter of the C-phase bridge arm of the inverter, and E is the input voltage of the inverter.

[0068] From the above, we can know that the calculation formula of the inverter output voltage is as follows:

[0069] in, is the output voltage of the inverter, E is the input voltage of the inverter, is the output state parameter of the inverter's phase a bridge arm, is the output state parameter of the inverter's b-phase bridge arm, is the output state parameter of the inverter's phase C bridge arm, is the imaginary unit, is a natural constant.

[0070] like Figure 4 As shown, Figure 4 Schematic diagram of some voltage vectors provided in the embodiments of this application. Triangle A represents the vector in the line voltage coordinate system, and triangle B represents the redundant vector in the traditional coordinate system after the transition. The reference vector voltage is calculated according to the following formula:

[0071] in, is the reference vector voltage, is the vector voltage of the first point of the vector in the line voltage coordinate system, is the output time of the first vector voltage of the vector in the line voltage coordinate system, is the vector voltage of the second point of the vector in the line voltage coordinate system, is the output time of the vector voltage of the second point of the vector in the line voltage coordinate system, is the vector voltage of the third point of the vector in the line voltage coordinate system, It is the output time of the vector voltage of the third point of the vector in the line voltage coordinate system.

[0072] The output time of the vector voltage at the first point of the vector in the line voltage coordinate system, the output time of the vector voltage at the second point of the vector in the line voltage coordinate system, and the output time of the vector voltage at the third point of the vector in the line voltage coordinate system are calculated according to the following formula:

[0073] in, is the output time of the vector voltage of the first point of the vector in the line voltage coordinate system, is the output time of the vector voltage of the second point of the vector in the line voltage coordinate system, is the output time of the vector voltage of the third point of the vector in the line voltage coordinate system, is the distance between the second point of the vector from the reference vector voltage to the line voltage coordinate system and the third point of the vector from the reference vector voltage to the line voltage coordinate system, is the distance between the first point of the vector from the reference vector voltage to the line voltage coordinate system and the third point of the vector from the reference vector voltage to the line voltage coordinate system, It is the distance between the first point of the vector from the reference vector voltage to the line voltage coordinate system and the third point of the vector from the reference vector voltage to the line voltage coordinate system.

[0074] In the above triangle A, the calculation formulas for the first point of the vector in the line voltage coordinate system, the second point of the vector in the line voltage coordinate system, and the third point of the vector in the line voltage coordinate system are as follows:

[0075] in, is the first point of the vector in the line voltage coordinate system, is the second point of the vector in the line voltage coordinate system, is the third point of the vector in the line voltage coordinate system, is the rounded-down value of the vector voltage of the first point of the vector in the line voltage coordinate system, is the rounded-down value of the vector voltage at the second point of the vector in the line voltage coordinate system, The rounded-down value of the vector voltage at the third point of the vector in the line voltage coordinate system.

[0076] The calculation formulas for the distance between the second point of the reference vector voltage to the line voltage coordinate system and the third point of the reference vector voltage to the line voltage coordinate system, the distance between the first point of the reference vector voltage to the line voltage coordinate system and the third point of the reference vector voltage to the line voltage coordinate system, and the distance between the first point of the reference vector voltage to the line voltage coordinate system and the third point of the reference vector voltage to the line voltage coordinate system are as follows:

[0077] in, is the distance between the second point of the vector from the reference vector voltage to the line voltage coordinate system and the third point of the vector from the reference vector voltage to the line voltage coordinate system, is the distance between the first point of the vector from the reference vector voltage to the line voltage coordinate system and the third point of the vector from the reference vector voltage to the line voltage coordinate system, is the distance between the first point of the vector from the reference vector voltage to the line voltage coordinate system and the third point of the vector from the reference vector voltage to the line voltage coordinate system, is the vector voltage of the first point of the vector in the line voltage coordinate system, is the vector voltage of the second point of the vector in the line voltage coordinate system, is the vector voltage of the third point of the vector in the line voltage coordinate system, is the rounded-down value of the vector voltage of the first point of the vector in the line voltage coordinate system, is the rounded-down value of the vector voltage at the second point of the vector in the line voltage coordinate system, The rounded-down value of the vector voltage at the third point of the vector in the line voltage coordinate system.

[0078] In the above triangle B, the calculation formulas for the first point of the redundant vector in the traditional coordinate system after transition, the second point of the redundant vector in the traditional coordinate system after transition, and the third point of the redundant vector in the traditional coordinate system after transition are as follows:

[0079] in, is the first point of the redundant vector in the traditional coordinate system after transition, is the second point of the redundant vector in the traditional coordinate system after transition, is the third point of the redundant vector in the traditional coordinate system after transition, is the rounded-down value of the redundant vector voltage of the first point of the redundant vector in the traditional coordinate system after the transition, is the rounded-down value of the redundant vector voltage of the second point of the redundant vector in the traditional coordinate system after the transition, It is the rounded-down value of the redundant vector voltage at the third point of the redundant vector in the traditional coordinate system after the transition.

[0080] The calculation formulas for the distance between the reference redundant vector voltage and the second point of the redundant vector in the traditional coordinate system after the transition and the third point of the redundant vector in the traditional coordinate system after the transition, the distance between the reference redundant vector voltage and the first point of the redundant vector in the traditional coordinate system after the transition and the third point of the redundant vector in the traditional coordinate system after the transition, and the distance between the reference redundant vector voltage and the first point of the redundant vector in the traditional coordinate system after the transition and the third point of the redundant vector in the traditional coordinate system after the transition are as follows:

[0081] in, is the distance between the reference redundant vector voltage and the second point of the redundant vector in the traditional coordinate system after the transition and the reference redundant vector voltage and the third point of the redundant vector in the traditional coordinate system after the transition, is the distance between the reference redundant vector voltage and the first point of the redundant vector in the traditional coordinate system after the transition and the reference redundant vector voltage and the third point of the redundant vector in the traditional coordinate system after the transition, is the distance between the reference redundant vector voltage and the first point of the redundant vector in the traditional coordinate system after the transition and the reference redundant vector voltage and the third point of the redundant vector in the traditional coordinate system after the transition, is the redundant vector voltage of the first point of the redundant vector in the traditional coordinate system after the transition, is the redundant vector voltage of the second point of the redundant vector in the traditional coordinate system after transition, is the redundant vector voltage of the third point of the redundant vector in the traditional coordinate system after transition, is the rounded-down value of the redundant vector voltage of the first point of the redundant vector in the traditional coordinate system after the transition, is the rounded-down value of the redundant vector voltage of the second point of the redundant vector in the traditional coordinate system after the transition, It is the rounded-down value of the redundant vector voltage at the third point of the redundant vector in the traditional coordinate system after the transition.

[0082] As shown in Table 2, Table 2 is a comparison table of inverter common-mode voltage and voltage vector sequence provided in an embodiment of the present application.

[0083] Table 2:

[0084] like Figure 5 As shown in Table 2, Figure 5This is a waveform diagram of the inverter output voltage vector provided by an embodiment of the present application. In triangle A, four voltage vector sequences can be obtained. To suppress the inverter common-mode voltage within the expected range, the common-mode voltages of every two voltage vectors output by the inverters are compared among the common-mode voltages of the first w voltage vectors output by the first w inverters to obtain the minimum inverter common-mode voltage. For example, when the sequence number is 3 or 4, the inverter common-mode voltage is Udc / 6, which is the minimum inverter common-mode voltage. Therefore, the voltage vector sequence corresponding to the inverter common-mode voltage when the sequence number is 3 or 4 is selected as the qualified sequence, and the inverter output pulse is generated based on the qualified sequence.

[0085] In this approach, the voltage vector sequence corresponding to the minimum common-mode voltage significantly reduces high-frequency common-mode current components, lowering system radiated and conducted interference. By comparing the common-mode voltages of every two inverter output voltage vectors within the common-mode voltages of the first w voltage vectors output by the inverter, this approach accurately locates the inverter switching mode combination that produces the minimum common-mode voltage. This directly reduces the inverter's ground leakage current and shaft current, extending the inverter's service life and improving the stability of the inverter's output pulses, providing stable and reliable power supply to downstream loads.

[0086] On the basis of the above method embodiment, the embodiment of the present application further provides an output power control device of an inverter, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of an inverter output power control device provided in an embodiment of the present application. The device includes: an acquisition module 61, a calculation module 62, a comparison module 63 and a control module 64. The functions of each module are as follows: An acquisition module 61 is configured to acquire the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment in the nth switching mode, and the inverter neutral point voltage at the k+1th moment in the nth switching mode; a calculation module 62 configured to calculate a cost value for the nth switching mode of the inverter based on the DC bus voltage of the nth switching mode, the floating capacitor voltage at the k+1th moment of the nth switching mode, and the inverter neutral point voltage at the k+1th moment of the nth switching mode; wherein the cost value is used to represent the difference between the floating capacitor voltage at the k+1th moment and the floating capacitor voltage at the kth moment, and the difference between the inverter neutral point voltage at the k+1th moment and the inverter neutral point voltage at the kth moment; a comparison module 63 for comparing the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain a minimum cost value; The control module 64 is configured to regulate the output power of the inverter according to the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value.

[0087] Preferably, the calculation module 62 is specifically configured to calculate the cost value of the nth switching mode according to the following formula:

[0088] in, is the cost value of the nth switching mode, is the weight coefficient, Used to indicate the inverter neutral point voltage at the k+1th moment of the nth switching mode, is the DC bus voltage of the inverter in the nth switching mode, is the floating capacitor voltage of one of phases a, b, and c at the k+1th moment in the nth switching mode.

[0089] Preferably, the calculation formula for the neutral point voltage of the inverter at the k+1th moment in the nth switching mode is as follows:

[0090] in, Used to indicate the inverter neutral point voltage at the k+1th moment of the nth switching mode, Used to indicate the inverter neutral point voltage at the kth moment of the nth switching mode, is the output time of the inverter output w-th voltage vector, is the capacitance of the DC link capacitor, is the inverter's a-phase output current, is the inverter’s b-phase output current, is the inverter’s c-phase output current, is the neutral point current coefficient of phase a when the inverter outputs the wth voltage vector, is the neutral point current coefficient of phase b when the inverter outputs the wth voltage vector, is the neutral point current coefficient of phase a when the inverter outputs the wth voltage vector.

[0091] Preferably, the calculation formula of the floating capacitor voltage at the k+1th moment in the nth switching mode is as follows:

[0092] in, is the floating capacitor voltage at the k+1th moment of the nth switching mode, is the floating capacitor voltage at the kth moment of the nth switching mode, is the output current of the inverter at the kth moment of the nth switching mode, is the output time of the inverter output w-th voltage vector, is the capacitance of the floating capacitor, is the floating capacitance current coefficient of phase x when the inverter outputs the wth voltage vector.

[0093] Preferably, the acquisition module 61 is further configured to acquire an output state parameter of the inverter's a-phase bridge arm, an output state parameter of the inverter's b-phase bridge arm, and an output state parameter of the inverter's c-phase bridge arm; The calculation module 62 is further configured to calculate the common-mode voltage of the inverter output voltage vector w according to the output state parameters of the inverter phase a bridge arm, the output state parameters of the inverter phase b bridge arm, the output state parameters of the inverter phase c bridge arm, and the DC bus voltage of the inverter in the nth switching mode; The comparison module 63 is further configured to compare the common-mode voltages of every two voltage vectors output by the inverter among the common-mode voltages of the first w voltage vectors output by the inverter to obtain a minimum common-mode voltage of the inverter; The control module 64 is further configured to generate an output pulse of the inverter according to a voltage vector sequence corresponding to the minimum common mode voltage of the inverter.

[0094] Preferably, the calculation module 62 is specifically configured to calculate the common-mode voltage of the w-th voltage vector output by the inverter according to the following formula:

[0095] in, is the common mode voltage of the inverter output w-th voltage vector, is the DC bus voltage of the inverter in the nth switching mode, is the output state parameter of the inverter's phase a bridge arm, is the output state parameter of the inverter's b-phase bridge arm, is the output state parameter of the C-phase bridge arm of the inverter.

[0096] The output electric power control device of the inverter provided in the embodiment of the present application has the same technical features as the output electric power control method of the inverter provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0097] The present application also provides a computing device. Figure 7 As shown, this figure is a schematic diagram of a computing device provided by an embodiment of the present application, wherein the computing device 400 includes a bus 401, a processor 402, a communication interface 403, and a memory 404. The processor 402, the memory 404, and the communication interface 403 communicate with each other via the bus 401.

[0098] The bus 401 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0099] The processor 402 may be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0100] Communication interface 403 is used for external communication. Memory 404 may include volatile memory, such as random access memory (RAM). Memory 404 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0101] The memory 404 stores executable codes, and the processor 402 executes the executable codes to perform the aforementioned method for controlling the output power of the inverter.

[0102] Embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium can be any available medium capable of storing data on a computing device, or a data storage device such as a data center that contains one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, hard disk, or magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to execute the above method.

[0103] The present application also provides a computer program product comprising one or more computer instructions that, when loaded and executed on a computing device, fully or partially generate the process or function described in the present application.

[0104] The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer or data center to another website, computer or data center via wired (e.g., coaxial cable, optical fiber) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0105] When the computer program product is executed by a computer, the computer performs any of the aforementioned methods for controlling the output power of an inverter. The computer program product may be a software installation package. When any of the aforementioned methods for controlling the output power of an inverter is required, the computer program product may be downloaded and executed on the computer.

[0106] The descriptions of the processes or structures corresponding to the above figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0107] The above description is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A method for controlling the output power of an inverter, characterized in that: The method comprises: The processor obtains a DC bus voltage of the inverter in an nth switching mode, a floating capacitor voltage at a k+1th moment in the nth switching mode, and a neutral point voltage of the inverter at a k+1th moment in the nth switching mode; The processor calculates a cost value of the nth switching mode according to the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment of the nth switching mode, and the neutral point voltage of the inverter at the k+1th moment of the nth switching mode; wherein the cost value is used to represent the difference between the floating capacitor voltage at the k+1th moment and the floating capacitor voltage at the kth moment, and the difference between the neutral point voltage of the inverter at the k+1th moment and the neutral point voltage of the inverter at the kth moment; The processor compares the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain a minimum cost value; The processor regulates the output power of the inverter according to the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value.

2. The method for controlling the output power of an inverter according to claim 1, wherein: The processor calculates the cost value of the nth switching mode according to the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment of the nth switching mode, and the neutral point voltage of the inverter at the k+1th moment of the nth switching mode, including: The cost value of the nth switching mode is calculated according to the following formula: in, is the cost value of the nth switching mode, is the weight coefficient, Used to indicate the inverter neutral point voltage at the k+1th moment of the nth switching mode, is the DC bus voltage of the inverter in the nth switching mode, is the floating capacitor voltage of one of phases a, b, and c at the k+1th moment in the nth switching mode.

3. The method for controlling the output power of an inverter according to claim 1, wherein: The calculation formula of the inverter neutral point voltage at the k+1th moment of the nth switching mode is as follows: in, Used to indicate the inverter neutral point voltage at the k+1th moment of the nth switching mode, Used to indicate the inverter neutral point voltage at the kth moment of the nth switching mode, is the output time of the common mode voltage of the inverter output w voltage vector, is the capacitance of the DC link capacitor, is the inverter's a-phase output current, is the inverter's b-phase output current, is the inverter’s c-phase output current, is the neutral point current coefficient of phase a when the inverter outputs the wth voltage vector, is the neutral point current coefficient of phase b when the inverter outputs the wth voltage vector, is the neutral point current coefficient of phase c when the inverter outputs the wth voltage vector.

4. The method for controlling the output power of an inverter according to claim 1, wherein: The calculation formula for the floating capacitor voltage at the k+1th moment in the nth switching mode is as follows: in, is the floating capacitor voltage at the k+1th moment of the nth switching mode, is the floating capacitor voltage at the kth moment of the nth switching mode, is the output current of the inverter at the kth moment of the nth switching mode, is the output time of the common mode voltage of the inverter output w voltage vector, is the capacitance of the floating capacitor, is the floating capacitance current coefficient of phase x when the inverter outputs the wth voltage vector.

5. The method for controlling the output power of an inverter according to claim 1, wherein: The method further comprises: The processor obtains an output state parameter of an inverter phase a bridge arm, an output state parameter of an inverter phase b bridge arm, and an output state parameter of an inverter phase c bridge arm; The processor calculates the common mode voltage of the wth voltage vector output by the inverter based on the output state parameter of the inverter phase a bridge arm, the output state parameter of the inverter phase b bridge arm, the output state parameter of the inverter phase c bridge arm, and the DC bus voltage of the inverter in the nth switching mode; The processor compares the common mode voltages of every two voltage vectors output by the inverter among the common mode voltages of the first w voltage vectors output by the inverter to obtain a minimum common mode voltage of the inverter; The processor generates an output pulse of the inverter according to a voltage vector sequence corresponding to a minimum common-mode voltage of the inverter.

6. The method for controlling the output power of an inverter according to claim 5, wherein: The processor calculates the common mode voltage of the wth voltage vector output by the inverter based on the output state parameter of the inverter's phase a bridge arm, the output state parameter of the inverter's phase b bridge arm, the output state parameter of the inverter's phase c bridge arm, and the DC bus voltage of the inverter's nth switching mode, including: in, is the common mode voltage of the inverter output w-th voltage vector, is the DC bus voltage of the inverter in the nth switching mode, is the output state parameter of the inverter's phase a bridge arm, is the output state parameter of the inverter's b-phase bridge arm, is the output state parameter of the C-phase bridge arm of the inverter.

7. An output power control device for an inverter, characterized in that: The device comprises: An acquisition module is used to acquire the DC bus voltage of the inverter in the nth switching mode, the floating capacitor voltage at the k+1th moment in the nth switching mode, and the inverter neutral point voltage at the k+1th moment in the nth switching mode; a calculation module, configured to calculate a cost value of the nth switching mode of the inverter based on a DC bus voltage of the nth switching mode, a floating capacitor voltage at the k+1th moment of the nth switching mode, and a neutral point voltage of the inverter at the k+1th moment of the nth switching mode; wherein the cost value is used to represent a difference between the floating capacitor voltage at the k+1th moment and the floating capacitor voltage at the kth moment, and a difference between the neutral point voltage of the inverter at the k+1th moment and the neutral point voltage of the inverter at the kth moment; a comparison module, configured to compare the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain a minimum cost value; The control module is used to regulate the output electric power of the inverter according to the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value.

8. A computing device, characterized in that including memory and processor; One or more computer programs are stored in the memory, and the one or more computer programs include instructions; when the instructions are executed by the processor, the computing device executes the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium is used to store a computer program, and the computer program is used to execute the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The computer program product comprises one or more computer instructions. When the computer instructions are executed by a computer, the computer performs the method according to any one of claims 1 to 6.

Images