Phase-locked loop circuit

Abstract

A phase-locked loop (PLL) circuit is provided for generating an output signal having an output frequency. The PLL circuit includes a voltage-to-current conversion circuit, a frequency compensation circuit, and a current controlled oscillator (ICO). The voltage-to-current conversion circuit is configured to generate a first control current according to a control voltage, where the control voltage is generated according to a reference signal and a feedback signal obtained from an output signal. The frequency compensation circuit is configured to generate a second control current according to the control voltage. A current controlled oscillator (ICO) generates an output signal according to an oscillating current, where the oscillating current is a sum of the first control current and the second control current. In response to the frequency compensation circuit detecting that the control voltage exceeds the predetermined range, the second control current is controlled to be negatively correlated with the output frequency.

Description

Technical field

[0001] The present invention relates to a phase-locked loop (PLL) circuit, and more particularly to a phase-locked loop (PLL) circuit with frequency compensation. [Background Technology]

[0002] A phase-locked loop (PLL) is a frequency and phase control system that operates based on feedback control principles, synchronizing the PLL's output signal with an external reference input. When a frequency or phase difference exists between the output signal and the external reference signal, the PLL adjusts the output signal's frequency until the output signal resynchronizes with the external reference signal. After the PLL is locked, variations in process, voltage, and temperature (PVT) can cause the PLL to become unlocked. Therefore, protecting the PLL from the effects of PVT variations is a critical issue. [Summary of the invention]

[0003] An embodiment of the present invention provides a phase-locked loop (PLL) circuit. The PLL circuit generates an output signal having an output frequency, and the PLL circuit includes a voltage-to-current conversion circuit, a frequency compensation circuit, and a current-controlled oscillator (ICO). The voltage-to-current conversion circuit is configured to generate a first control current according to a control voltage, wherein the control voltage is generated according to a reference signal and a feedback signal obtained from the output signal. The frequency compensation circuit is configured to generate a second control current according to the control voltage. The ICO is configured to generate the output signal according to an oscillating current, wherein the oscillating current is the sum of the first control current and the second control current. In response to the frequency compensation circuit detecting that the control voltage exceeds a predetermined range, the second control current is controlled to be negatively correlated with the output frequency.

[0004] In some embodiments, in response to the frequency compensation circuit detecting that the control voltage is higher than the predetermined range, the frequency compensation circuit reduces the second control current; and in response to the frequency compensation circuit detecting that the control voltage is lower than the predetermined range, the frequency compensation circuit increases the second control current.

[0005] In some embodiments, the frequency compensation circuit includes: a voltage monitor configured to generate a selection signal to indicate whether the control voltage exceeds the predetermined range; a frequency selector configured to select one of the reference signal and the feedback signal as the control signal according to the selection signal; a phase generation circuit configured to generate a first switching signal and a second switching signal according to the control signal, wherein the first switching signal and the second switching signal have the same switching frequency; a frequency-to-current conversion circuit configured to receive the first switching signal and the second switching signal and generate a first bias current according to the switching frequency, wherein the first bias current is positively correlated with the switching frequency; and a current bias circuit coupled to the frequency-to-current conversion circuit and configured to generate the second control current according to the first bias current, wherein the second control current is negatively correlated with the first bias current.

[0006] In some embodiments, in response to the voltage monitor detecting that the control voltage is higher than the predetermined range, the frequency selector selects the feedback signal as the control signal according to the selection signal, the frequency-to-current conversion circuit increases the first bias current according to the switching frequency corresponding to the feedback signal, and the current bias circuit reduces the second control current; and, in response to the voltage monitor detecting that the control voltage is lower than the predetermined range, the frequency selector selects the feedback signal as the control signal according to the selection signal, the frequency-to-current conversion circuit reduces the first bias current according to the switching frequency corresponding to the feedback signal, and the current bias circuit increases the second control current.

[0007] In some embodiments, the voltage monitor includes: a first comparator, whose positive input terminal is used to receive the control voltage, and whose negative input terminal is used to receive a first voltage threshold, and the first comparator is configured to generate a first comparison signal; a second comparator, whose positive input terminal is used to receive a second voltage threshold, and whose negative input terminal is used to receive the control voltage, and the second comparator is configured to generate a second comparison signal, wherein the second voltage threshold is greater than the first voltage threshold, and the predetermined range is defined by the first voltage threshold and the second voltage threshold; and a NAND gate configured to generate the selection signal according to the first comparison signal and the second comparison signal.

[0008] In some embodiments, the first comparator and the second comparator are hysteresis comparators.

[0009] In some embodiments, the frequency selector includes: a multiplexer, whose first input terminal is used to receive the reference signal, the second input terminal is used to receive the feedback signal, and the output terminal is used to output the control signal, wherein, in response to the selection signal being asserted, the multiplexer transmits the feedback signal to the output terminal of the multiplexer as the control signal; and, in response to the selection signal being de-asserted, the multiplexer transmits the reference signal to the output terminal of the multiplexer as the control signal.

[0010] In some embodiments, the switching frequencies of the first switching signal and the second switching signal are equal to the frequency of the control signal, and the first switching signal and the second switching signal have opposite phases.

[0011] In some embodiments, the frequency-to-current conversion circuit includes: a first switch coupled between a second node and a ground terminal and controlled by the second switching signal; a first capacitor coupled between the second node and the ground terminal; a second switch coupled between a third node and the second node and controlled by the first switching signal; a P-type transistor, a source coupled to a fourth node and a drain coupled to the third node; and an operational amplifier, a positive input coupled to the third node, a negative input for receiving a reference voltage, and an output of the operational amplifier coupled to the gate of the P-type transistor, wherein the first bias current flows through the first P-type transistor.

[0012] In some embodiments, the frequency-to-current conversion circuit further includes: a second capacitor coupled between the third node and the ground terminal, wherein a capacitance value of the second capacitor is greater than a capacitance value of the first capacitor.

[0013] In some embodiments, the current bias circuit includes: a second P-type transistor, whose gate is coupled to the output terminal of the operational amplifier, whose source is coupled to the fourth node, and whose drain is coupled to the fifth node; a current source, which is coupled between the fifth node and the ground terminal and is configured to provide a predetermined current; a third P-type transistor, whose gate is coupled to the sixth node, whose source is coupled to the fourth node, and whose drain is coupled to the fifth node; and a current generating circuit, which is coupled to the fourth node and the ICO; wherein the second bias current flows through the third P-type transistor, and the current generating circuit is configured to generate the second control current according to the second bias current.

[0014] In some embodiments, the second control current is a multiple of the second bias current.

[0015] In some embodiments, the current generating circuit includes: a fourth P-type transistor, a gate coupled to the sixth node, a source coupled to the fourth node, and a drain coupled to the ICO, wherein the second control current flows through the fourth P-type transistor.

[0016] In some embodiments, the current generating circuit includes: a fourth P-type transistor, whose gate is coupled to the sixth node and whose source is coupled to the fourth node; a fifth P-type transistor, whose gate is used to receive a first bit signal, whose source is coupled to the drain of the fourth P-type transistor, and the drain of the fifth P-type transistor is coupled to the seventh node; a sixth P-type transistor, whose gate is coupled to the sixth node and whose source is coupled to the fourth node; and a seventh P-type transistor, whose gate is used to receive a second bit signal, whose source is coupled to the drain of the sixth P-type transistor, and the drain of the seventh P-type transistor is coupled to the seventh node, wherein at least one of the fifth P-type transistor and the seventh P-type transistor is turned on, and the second control current flows from the seventh node to the ICO.

[0017] In some embodiments, the current bias circuit further includes: a resistor coupled between the sixth node and the current generating circuit; and a third capacitor coupled between the fourth node and the current generating circuit.

[0018] In some embodiments, the frequency-to-current conversion circuit includes: a first switch coupled between the second node and the ground terminal and controlled by the second switch signal; a first capacitor coupled between the second node and the ground terminal; a second switch coupled between the third node and the second node and controlled by the first switch signal; a first P-type transistor, whose gate is coupled to the fifth node and whose source is coupled to the fourth node; a first N-type transistor, whose gate and drain are both coupled to the drain of the first P-type transistor at the sixth node, and the source of the first N-type transistor is coupled to the ground terminal; a second P-type transistor, whose gate is coupled to the fifth node, whose source is coupled to the fourth node, and whose drain is coupled to the fifth node; and a second N-type transistor, whose gate is coupled to the sixth node, whose drain is coupled to the fifth node, and whose source is coupled to the third node, wherein the first bias current flows through the second P-type transistor and the second N-type transistor.

[0019] In some embodiments, the frequency-to-current conversion circuit further includes: a second capacitor coupled between the third node and the ground; wherein the capacitance of the second capacitor is greater than the capacitance of the first capacitor.

[0020] In some embodiments, the current bias circuit includes: a third P-type transistor, whose gate is coupled to the fifth node, the source is coupled to the fourth node, and the drain is coupled to the seventh node; a current source, which is coupled between the seventh node and the ground terminal and is configured to provide a predetermined current; a fourth P-type transistor, whose gate is coupled to the eighth node, the source is coupled to the fourth node, and the drain is coupled to the seventh node; and a current generating circuit, which is coupled to the fourth node and the ICO, wherein the second bias current flows through the fourth P-type transistor, and the current generating circuit is configured to generate the second control current according to the second bias current.

[0021] In some embodiments, the bias circuit further includes: a resistor coupled between the eighth node and the current generating circuit; and a third capacitor coupled between the fourth node and the current generating circuit.

[0022] In some embodiments, the current generating circuit includes: a fifth P-type transistor, whose gate is coupled to the eighth node and whose source is coupled to the fourth node; a sixth P-type transistor, whose gate is used to receive a first bit signal, whose source is coupled to the drain of the fifth P-type transistor, and whose drain is coupled to the ninth node; a seventh P-type transistor, whose gate is coupled to the eighth node and whose source is coupled to the fourth node; and an eighth P-type transistor, whose gate is used to receive a second bit signal, whose source is coupled to the drain of the seventh P-type transistor, and whose drain is coupled to the ninth node; wherein the sixth P-type transistor and the eighth P-type transistor are turned on, and the second control current flows from the ninth node to the ICO.

[0023] According to the above embodiment, when the control voltage exceeds a predetermined range (for example, due to a frequency shift of the output signal caused by PVT variation), the frequency compensation circuit adjusts the control current I BAND , thereby compensating for the frequency offset to stabilize the output signal at the desired target frequency.

[0024] Those skilled in the art will readily appreciate these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. Detailed description will be given in the following embodiments with reference to the accompanying drawings.

Brief Description of the Drawings

[0025] A more complete understanding of the present invention may be obtained by reading the following detailed description and by referring to the examples in the accompanying drawings.

[0026] Figure 1 An exemplary embodiment of a phase-locked loop (PLL) circuit is shown.

[0027] Figure 2 Shown Figure 1 An exemplary embodiment of a voltage monitor and frequency selector in a PLL circuit is shown.

[0028] Figure 3 Shown Figure 1 An exemplary embodiment of a frequency-to-current conversion circuit and a current bias circuit in a PLL circuit is shown.

[0029] Figure 4 Shown Figure 1 Another exemplary embodiment of a frequency-to-current conversion circuit and a current bias circuit in a PLL circuit is shown.

[0030] Figure 5 Shown Figure 1 Another exemplary embodiment of a frequency-to-current conversion circuit and a current bias circuit in a PLL circuit is shown.

[0031] Figure 6 Shown Figure 1 Another exemplary embodiment of a frequency-to-current conversion circuit and a current bias circuit in a PLL circuit is shown.

[0032] Figure 7 An exemplary embodiment of a phase generation circuit is shown.

[0033] In the following detailed description, for illustrative purposes, numerous specific details are set forth to enable those skilled in the art to more thoroughly understand the embodiments of the present invention. However, it is apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and the present invention should not be limited to the embodiments illustrated in the accompanying drawings. [Specific implementation method]

[0034] The following description is of preferred embodiments of the present invention and is intended only to illustrate the technical features of the present invention and is not intended to limit the scope of the invention. Certain terms are used throughout the specification and claims to refer to specific components. Those skilled in the art will appreciate that manufacturers may use different names for the same components. Therefore, this specification and claims do not distinguish components by name, but rather by functional differences. The terms "component," "system," and "device" used in this invention may refer to entities related to a computer, which may be hardware, software, or a combination of hardware and software. The terms "including" and "comprising" used in the following description and claims are open-ended and should be interpreted as meaning "including, but not limited to..." Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, when a device is described as being coupled to another device, this means that the device may be directly electrically connected to the other device or indirectly electrically connected to the other device through other devices or connections.

[0035] Corresponding numerals and symbols in the various figures of the drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0036] As used herein, the terms "substantially" or "approximately" mean that a person skilled in the art is able to solve the desired technical problem and substantially achieve the desired technical effect within an acceptable range. For example, "approximately equal to" means that a certain deviation from "exactly equal to" is acceptable to a person skilled in the art without affecting the accuracy of the result.

[0037] The present invention provides a phase-locked loop (PLL), including a frequency compensation circuit (frequency compensation circuit) and a current-controlled oscillator (ICO). This configuration enhances the stability of the PLL output signal and can synchronize the PLL output signal with a reference signal, thereby ensuring that the output signal is maintained at a desired target frequency that matches the reference signal. It should be noted that the focus of the present invention is on the frequency compensation circuit, the purpose of which is to stabilize the frequency of the output signal at the desired target frequency, and other structures in the PLL should not be limited to the specific example embodiments shown in the accompanying drawings. In an embodiment, the voltage-to-current (V-to-I) conversion circuit is configured to generate a first control current (I LPF ), wherein the control voltage is generated according to the output signal and the reference signal, for example, the control voltage is generated according to the reference signal and the output signal (including its derivative signal, such as Figure 1 The feedback signal S shown DIV ) is related to the frequency and phase difference between the two. It is worth noting that the generation of the control voltage is well known to those skilled in the art, and therefore, the present invention does not limit the specific generation of the control voltage. Generally, ICO is also often referred to as voltage-controlled oscillator (VCO). The frequency compensation circuit is configured to generate a second control current (I BAND ), and the ICO is configured to generate an output signal based on an oscillating current that is the sum of a first control current and a second control current. In an embodiment, in response to the frequency compensation circuit detecting that the control voltage is outside a predetermined range (VL-VH), the frequency compensation circuit adjusts the second control current such that the second control current is negatively correlated with the output frequency of the output signal. However, if the frequency compensation circuit detects that the control voltage is within the predetermined range (VL-VH), the second control current is related to the frequency of the reference signal.

[0038] Figure 1 An example embodiment of a phase-locked loop (PLL) circuit is shown. Figure 1As shown, the PLL circuit 1 includes a phase frequency detector (PFD) 10, a charge pump circuit 11, a low pass filter (LPF, also often called a loop filter in PLL) 12, a voltage-to-current (V-to-I) conversion circuit 13, a current controlled oscillator (ICO) 14, a frequency divider (DIV) 15, and a frequency compensation circuit 16. The PLL circuit 1 receives a reference frequency F REF The reference signal S REF , and generates an output signal S ICO The PLL circuit 1 also generates a signal based on the reference signal S REF and feedback signal S DIV Lock output signal S ICO The output frequency F ICO , where the feedback signal S DIV The output signal S ICO Obtained by performing frequency division operation.

[0039] The frequency divider (DIV) 15 receives the output signal S ICO And the output signal S ICO Specifically, the frequency divider 15 outputs the signal S ICO Divide by X to generate the feedback signal S DIV , for example, X≥1. Therefore, the feedback signal S DIV Frequency F DIV Equal to the output signal S ICO The output frequency F ICO 1 / X of the phase frequency detector (PFD) 10 receives the reference signal S REF and feedback signal S DIV , the PFD 10 is configured to detect the reference signal S REF and feedback signal S DIV The frequency and phase differences between the two signals are used to generate detection signals UP and DN, wherein the detection signals UP and DN are used to indicate the reference signal S REF and feedback signal S DIV For example, the detection signals UP and DN are digital signals.

[0040] exist Figure 1In the embodiment, LPF 12 is implemented as a dual-path LPF. Therefore, charge pump circuit 11 includes two charge pumps (CHPs) 110 and 111, but the present invention is not limited to this example. Each charge pump 110 and 111 receives detection signals UP and DN. Each charge pump 110 and 111 charges or discharges LPF 12 based on the detection signals UP and DN. According to the embodiment, LPF 12 includes a resistor 120, capacitors 121 and 122, and an operational amplifier 123. Operational amplifier 123 has a positive input terminal (+), a negative input terminal (-), and an output terminal coupled to node N10. Each of resistor 120 and capacitor 121 is coupled between the positive input terminal of operational amplifier 123 and ground terminal GND. Capacitor 122 is coupled between the negative input terminal and the output terminal of operational amplifier 123. Control voltage V10 is generated at node N10 (the output terminal of LPF 12). During normal operation when the PLL circuit 1 is in a locked state, the control voltage V10 will vary within a predetermined range.

[0041] exist Figure 1 In the example shown, the V-to-I conversion circuit 13 includes a resistor 130 and generates a control current I LPF , where the control current I LPF It is related to the control voltage V10 and the resistance value R130 of the resistor 130. In particular, the control current I LPF The frequency compensation circuit 16 is coupled to the node N10 to receive the control voltage V10 and is configured to generate a control current I according to the control voltage V10. BAND In response to the control voltage V10 exceeding or deviating from the predetermined range, the control current I BAND is regulated / controlled to exhibit an output signal S ICO The output frequency F ICO Negative correlation. For example, for negative correlation, the output signal S ICO The output frequency F ICO The increase in the control current I BAND The output signal S ICO The output frequency F ICO The reduction of the control current I BAND However, when the control voltage V10 is within the predetermined range, the control current I BAND Maintained at a predetermined value or updated value corresponding to the desired target frequency. ICO 14 receives the oscillating current I ICO, for example, the oscillating current I ICO is the control current I LPF and I BAND The sum (I ICO =I LPF +I BAND ), ICO 14 is configured to be based on the oscillating current I ICO Generate output signal S ICO It can be understood that the oscillating current I ICO Related to the control voltage V10.

[0042] After the phase-locked loop PLL circuit 1 is locked, the control current I LPF By the oscillating current I ICO With the control current I BAND The difference between the two is determined, that is, I LPF =I ICO -I BAND Due to changes in the environment or operating parameters of the PLL circuit 1 (for example, PVT changes), the control current I BAND Or oscillating current I ICO may change, causing the control current I LPF When the control current I LPF When the change of V10 is large, the control voltage V10 may exceed the predetermined range, causing the LPF 12 to fail to operate normally. Therefore, the PLL circuit 1 switches to an unlocked state or no longer remains in a locked state, and the output signal S ICO The output frequency F ICO According to this embodiment, the frequency compensation circuit 16 operates based on the control voltage V10 to adjust the control current I BAND , thereby compensating for the frequency offset.

[0043] The frequency compensation circuit 16 includes a voltage monitor 160, a frequency selector 161, a phase generation circuit 162, a frequency-to-current (F-to-I) conversion circuit 163, and a current bias circuit 164. The voltage monitor 160 is coupled to the node N10 to receive the control voltage V10. The voltage monitor 160 defines a predetermined range for the control voltage V10 and is configured to generate a selection signal S160 to indicate whether the control voltage V10 exceeds the predetermined range. The frequency selector 161 receives a reference signal S REF and feedback signal S DIV, and is configured to select the reference signal S according to the selection signal 160 REF and feedback signal S DIV As the control signal S161. The phase generating circuit 162 receives the control signal S161 and is configured to generate switching signals S162A and S162B according to the control signal S161. In this embodiment, the switching signals S162A and S162B are signals with equal frequencies and opposite phases. That is, the switching signals S162A and S162B are in opposite phases to each other. The switching frequency F of the switching signals S162A and S162B is 162 is equal to the frequency of the control signal S161, that is, the switching frequency of the switching signals S162A and S162B is equal to the reference signal S REF Reference frequency F REF Or feedback signal S DIV Frequency F DIV , which depends on the value of the selection signal 160. The frequency to current conversion circuit 163 receives the switching signals S162A and S162B and is configured to convert the switching frequency F of the switching signals S162A and S162B into a value corresponding to the switching frequency F of the switching signals S162A and S162B. 162 Generates bias current I A The current bias circuit 164 is coupled to the frequency-to-current conversion circuit 163 and is configured to operate through negative feedback based on the bias current I A Generate control current I BAND When the control voltage V10 exceeds the predetermined range, the frequency compensation circuit 16 is based on the feedback signal S DIV Operation to adjust the control current I BAND Based on the control current I BAND Adjustment of the oscillating current I ICO changes, and thus, the output frequency F ICO The above operation is repeated until the control voltage V10 returns to within the predetermined range through the operation of the PLL circuit 1.

[0044] Figure 2 An exemplary embodiment of a voltage monitor 160 and a frequency selector 161 is shown. Figure 2As shown, voltage monitor 160 includes comparators 160A and 160B and a NAND gate 160C. In a preferred embodiment, comparators 160A and 160B are hysteresis comparators. Comparator 160A receives a control voltage V10 at its positive input (+), a lower voltage threshold VL at its negative input (-), and generates a comparison signal S160A at its output. Comparator 160B receives a higher voltage threshold VH at its positive input (+), a control voltage V10 at its negative input (-), and generates a comparison signal S160B at its output. NAND gate 160C receives comparison signals S160A and S160B and generates a select signal S160. The higher voltage threshold VH is greater than the lower voltage threshold VL, and the predetermined range is bounded or defined by the higher voltage threshold VH and the lower voltage threshold VL.

[0045] The frequency selector 161 includes a multiplexer (MUX) 161A. The first input terminal (0) of the multiplexer 161A is used to receive the reference signal S REF The second input terminal (1) is used to receive the feedback signal S DIV , and its output terminal is used to output the control signal S161. The multiplexer 161A is used to receive the selection signal S160 and is configured to select the reference signal S according to the selection signal S160. REF Or feedback signal S DIV When the selection signal S160 is asserted (also described as “valid”, for example, a high voltage level), the multiplexer 161A selects the feedback signal S DIV And the feedback signal S DIV The output terminal of the multiplexer 161A is transmitted to serve as the control signal S161, so that the frequency of the control signal S161 is equal to the feedback signal S DIV Frequency F DIV When the selection signal S160 is de-asserted (also described as “invalid”), the multiplexer 161A selects the reference signal S REF And the reference signal S REF The signal S161 is transmitted to the output terminal of the multiplexer 161A as the control signal S161, so that the frequency of the control signal S161 is equal to the reference signal S REF Reference frequency F REF .

[0046] Figure 3 An exemplary embodiment of a frequency to current conversion circuit 163 and a current bias circuit 164 is shown. Figure 3The frequency-to-current conversion circuit 163 includes switches 163A and 163B, capacitors 163C and 163D, an operational amplifier 163E, and a P-type transistor 163F. It should be noted that the capacitor 163D is optional, and the purpose of including the capacitor 163D is to reduce the current I A The ripple on the A stability. In this embodiment, the P-type transistor 163F is implemented by a P-type metal-oxide-semiconductor (PMOS) transistor. The switch 163A is coupled between the node N30 and the ground terminal GND and is controlled by the switching signal S162B. The capacitor 163C is coupled between the node N30 and the ground terminal GND. The switch 163B is coupled between the node N31 and the node N30 and is controlled by the switching signal S162. The capacitor 163D is coupled between the node N31 and the ground terminal GND. The source of the PMOS transistor 163F is coupled to the node N35, and the drain is coupled to the node N31. The positive input terminal (+) of the operational amplifier 163E is coupled to the node N31, and the negative input terminal (-) is used to receive the reference voltage V REF , and its output terminal is coupled to the gate of the PMOS transistor 163F. In this embodiment, the capacitance value of the capacitor 163D is greater than the capacitance value C of the capacitor 163C. 163C .

[0047] like Figure 3 As shown, the bias current I A Flows through the P-type transistor 163F. Bias current I A By the reference voltage V REF , the frequency F of the switching signals S162A and S162B (or the control signal S161) 162 and the capacitance value of capacitor 163C (C 163C ) determines, that is, the bias current I A With reference voltage V REF , the frequency F of the switching signals S162A, S162B (or the control signal S161) 162 and the capacitance value of capacitor 163C (C 163C ) is related. In this embodiment, the bias current I A With frequency F 162 For example, in one example implementation, the bias current I A Equal to the reference voltage V REF , frequency F 162 and capacitance C 163C The product of (I A =V REF*F 162 *C 163C ).

[0048] refer to Figure 3 The current bias circuit 164 includes P-type transistors 164A and 164B, a current source 164C, a resistor 164D, a capacitor 164E, and a current generation circuit 30. In this embodiment, the P-type transistors 164A and 164B are implemented by PMOS transistors. The gate of the P-type transistor 164A is coupled to the output terminal of the operational amplifier 163E (also coupled to the gate of the P-type transistor 163F), its source is coupled to the node N35, and its drain is coupled to the node N32. The current source 164C is coupled between the node N32 and the ground terminal GND and provides a predetermined current I C The gate of the PMOS transistor 164B is coupled to the node N33, the source thereof is coupled to the node N35 (e.g., the node N35 is coupled to the power supply voltage), and the drain thereof is coupled to the node N32. A first end of the resistor 164D is coupled to the node N33, and a second end thereof is coupled to the node N34. A first end of the capacitor 164E is coupled to the node N35, and a second end thereof is coupled to the node N34.

[0049] exist Figure 3 In the embodiment of FIG. 1 , the current generating circuit 30 is coupled to the node N35 and the ICO 14. The current generating circuit 30 generates a single-band current. Figure 3 The current generating circuit 30 includes a P-type transistor 164G. In this embodiment, the P-type transistor 164G is implemented by a PMOS transistor. The gate of the transistor 164G is coupled to the node N34, the source is coupled to the node N35, and the drain is coupled to the ICO 14.

[0050] refer to Figure 3 , the P-type transistors 164A and 164B and the current source 164C perform a negative feedback operation. Based on the negative feedback operation, according to the bias current I A and the predetermined current I C Generates bias current I B , where the bias current I B With the bias current I A Negative correlation. For example, in one example implementation, I B =I C -I A . Bias current I B Flows through PMOS transistor 164B. Resistor 164D and capacitor 164E form a low-pass filter to filter out the bias current I BIt should be noted that the resistor 164D and the capacitor 164E are optional. The current generating circuit 30 generates the current according to the bias current I B Generate control current I BAND . Control current I BAND Flows through PMOS transistor 164G. Figure 3 In the embodiment, the control current I BAND With the bias current I B For example, by changing the channel size ratio of the P-type transistors 164G and 164B, the control current I BAND With the bias current I B The ratio between them, for example, the control current I BAND Can be equal to the bias current I B .

[0051] refer to Figures 1 to 3 When the PLL circuit 1 is locked, the output signal S ICO The output frequency F ICO When the control voltage V10 is higher than the upper voltage threshold VH, the voltage monitor 160 generates a high-level selection signal S160, and the multiplexer 161A of the frequency selector 161 selects the feedback signal S DIV As the control signal S161, the phase generating circuit 162 generates a phase signal having the same frequency as the output frequency F according to the control signal S161. ICO Related frequency F DIV The switching signals S162A and S162B. DIV From the output signal S ICO , therefore, the frequency F of the switching signals S162A and S162B 162 As the frequency of the feedback signal S DIV Since the bias current I A With frequency F 162 Positive correlation (e.g., I A =V REF *F 162 *C 163C ), therefore, the bias current I A As the frequency F of the switching signals S162A and S162B increases 162 Based on the negative feedback operation performed by the PMOS transistors 164A and 164B and the current source 164C, the bias current I B With the bias current I A The control current I BAND With the bias current IB Due to the decrease of the control current I BAND The reduction of oscillating current I ICO Decrease, thus outputting the signal S ICO The output frequency F ICO In response to the output frequency F ICO As the control voltage V10 decreases, the control voltage V10 will decrease. The above operation will be repeated until the control voltage V10 returns to the predetermined range. Therefore, the LPF 12 can work normally, and the PLL circuit 1 enters the locked state again, and the output signal is maintained at the desired target frequency.

[0052] After the phase-locked loop PLL circuit 1 is locked, when the output signal S ICO The output frequency F ICO When the control voltage V10 decreases (for example, due to a decrease in PVT variation), the control voltage V10 decreases. When the control voltage V10 is lower than the lower voltage threshold VH, the voltage monitor 160 generates a selection signal S160 having a high voltage level, and the multiplexer 161A of the frequency selector 161 selects the feedback signal S DIV As the control signal S161, the phase generating circuit 162 generates a phase with a frequency F according to the control signal S161. DIV The switching signals S162A and S162B. DIV The output signal S ICO The frequency F of the switching signals S162A and S162B is obtained. 162 With the feedback signal S DIV Or output frequency F ICO Similarly, due to the decrease of bias current I A With frequency F 162 Positive correlation (e.g., I A =V REF *F 162 *C 163C ), therefore, the bias current I A In response to the frequency F of the switching signals S162A and S162B 162 Based on the negative feedback operation performed by the PMOS transistors 164A and 164B and the current source 164C, the bias current I B In response to the bias current I A The control current I BAND With the bias current I B Since the control current I BAND As the oscillating current I ICO Increase, and the output signal S ICO The output frequency F ICO Increase. In response to the output frequency FICO As the control voltage V10 increases, the control voltage V10 increases. The above operation is repeated until the control voltage V10 returns to the predetermined range. Therefore, the LPF 12 can operate normally, and the PLL circuit 1 enters the locked state again, and the output signal is maintained at the desired target frequency.

[0053] exist Figure 3 In the embodiment, the current generating circuit 30 generates a single-band current. In other embodiments, the current generating circuit 30 can generate multi-band currents. For example, Figure 4 As shown, the current generating circuit 30 includes P-type transistors 164G1-164G N and 164H1-164H N To generate multiple gear currents. In this embodiment, the P-type transistors in the current generating circuit 30 are implemented by PMOS transistors. PMOS transistors 164G1 and 164H1 can generate a first gear current. The gate of transistor 164G1 is coupled to node N34, and its source is coupled to node N35. The gate of transistor 164H1 is used to receive a bit signal S1, its source is coupled to the drain of PMOS transistor 164G1, and its drain is coupled to node N36. PMOS transistors 164G2 and 164H2 can generate a second gear current. The gate of transistor 164G2 is coupled to node N34, and its source is coupled to node N35. The gate of transistor 164H2 receives a bit signal S2, its source is coupled to the drain of PMOS transistor 164G2, and its drain is coupled to node N36. PMOS transistor 164G N and 164H N Can generate Nth gear current. Transistor 164G N The gate of transistor 164H is coupled to node N34, and the source thereof is coupled to node N35. N The gate receives the bit signal S N , whose source is coupled to the PMOS transistor 164G N The drain of the Nth gear current is coupled to the node N36. In an exemplary embodiment, the ratio of the Nth gear current to the Lth gear current is 2 (N-1) :2 (L-1) , where 1≦M <N。

[0054] exist Figure 4 In the embodiment of the present invention, the frequency compensation circuit 16 further includes a calibrator 165, which receives a reference signal S REF The PLL circuit 1 is used to lock the output signal S ICO During the initial operation of the frequency, the frequency compensation circuit 16 is based on the reference signal S REFGenerate bit signal S1-S N , and PMOS transistors 164H1-164H N At least one of the bit signals S1-S N After the initial operation, the control current I BAND It is generated by the current of the selected gear. Figure 4 In the embodiment, based on the selected gear current, the control current I BAND Can be bias current I B In particular, the control current I BAND Can be bias current I B M times, for example, 1≦M≦2 N -1.

[0055] In other embodiments, the frequency-to-current conversion circuit 163 may include a self-bias circuit. Figures 5 and 6 As shown, the frequency to current conversion circuit 163 includes P-type transistors 50 and 51 and N-type transistors 52 and 53, which are used to replace Figures 3 and 4 , wherein the operational amplifier 163E and the PMOS transistor 163F are shown in FIG. , wherein the P-type transistors 50 and 51 and the N-type transistors 52 and 53 form a self-bias circuit. In this embodiment, the P-type transistors 50 and 51 are implemented by PMOS transistors, and the N-type transistors 52 and 53 are implemented by N-type metal-oxide-semiconductor (NMOS) transistors. The gate of the PMOS transistor 50 is coupled to the node N50, its source is coupled to the node N35, and its drain is coupled to the node N51. The gate and drain of the NMOS transistor 52 are both coupled to the node N51, and its source is coupled to the ground terminal GND. The gate and drain of the PMOS transistor 51 are both coupled to the node N50, and its source is coupled to the node N35. The gate of the NMOS transistor 53 is coupled to the node N51, its drain is coupled to the node N50, and its source is coupled to the node N31. The bias current I A Flows through the PMOS transistor 51 and the NMOS transistor 53. Figure 5 In the embodiment, the gate of the PMOS transistor 164A is coupled to the node N50 (ie, the gates of the PMOS transistors 50 and 51 ).

[0056] Figure 7 An exemplary embodiment of the phase generation circuit 162 is shown. Figure 7Phase generation circuit 162 includes NOR gates 163A and 163B and inverters 163C and 163F. One input of NOR gate 163A is coupled to node N70 to receive control signal S161, and the other input of NOR gate 163A is coupled to node N72. An input of inverter 163C is coupled to the output of NOR gate 163A. An input of inverter 163D is coupled to the output of inverter 163C, and the output of inverter 163D is coupled to node N71. One input of NOR gate 163B is coupled to node N70 to receive control signal S161, and the other input of NOR gate 163B is coupled to node N71. An input of inverter 163E is coupled to the output of NOR gate 163B. The input of inverter 163F is coupled to the output of inverter 163E, and the output of inverter 163F is coupled to node N72. Switching signal S162 is generated at node N71 (the output of inverter 163D), and switching signal S162B is generated at node N72 (the output of inverter 163F).

[0057] Although the present invention has been described by way of example and in terms of preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar configurations (as will be apparent to those skilled in the art), for example, combinations or substitutions of different features from different embodiments. Accordingly, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar configurations.

Claims

1. A phase-locked loop (PLL) circuit for generating an output signal having an output frequency, wherein: The PLL circuit includes: a voltage-to-current conversion circuit configured to generate a first control current according to a control voltage, wherein the control voltage is generated according to a reference signal and a feedback signal obtained from the output signal; a frequency compensation circuit configured to generate a second control current according to the control voltage; and a current controlled oscillator ICO configured to generate the output signal according to an oscillating current, wherein the oscillating current is the sum of the first control current and the second control current, In response to the frequency compensation circuit detecting that the control voltage exceeds a predetermined range, the second control current is controlled to be negatively correlated with the output frequency.

2. The PLL circuit according to claim 1, wherein In response to the frequency compensation circuit detecting that the control voltage is higher than the predetermined range, the frequency compensation circuit reduces the second control current; as well as In response to the frequency compensation circuit detecting that the control voltage is lower than the predetermined range, the frequency compensation circuit increases the second control current.

3. The PLL circuit according to claim 1, wherein The frequency compensation circuit includes: a voltage monitor configured to generate a selection signal to indicate whether the control voltage exceeds the predetermined range; a frequency selector configured to select one of the reference signal and the feedback signal as a control signal according to the selection signal; a phase generating circuit configured to generate a first switching signal and a second switching signal according to the control signal, wherein the first switching signal and the second switching signal have the same switching frequency; a frequency-to-current conversion circuit configured to receive the first switching signal and the second switching signal and generate a first bias current according to the switching frequency, wherein the first bias current is positively correlated with the switching frequency; and The current bias circuit is coupled to the frequency-to-current conversion circuit and is configured to generate the second control current according to the first bias current, wherein the second control current is negatively correlated with the first bias current.

4. The PLL circuit according to claim 3, wherein: In response to the voltage monitor detecting that the control voltage is higher than the predetermined range, the frequency selector selects the feedback signal as the control signal according to the selection signal, the frequency-to-current conversion circuit increases the first bias current according to the switching frequency corresponding to the feedback signal, and the current bias circuit reduces the second control current; and In response to the voltage monitor detecting that the control voltage is lower than the predetermined range, the frequency selector selects the feedback signal as the control signal according to the selection signal, the frequency-to-current conversion circuit reduces the first bias current according to the switching frequency corresponding to the feedback signal, and the current bias circuit increases the second control current.

5. The PLL circuit according to claim 3, wherein: The voltage monitor includes: a first comparator, wherein a positive input terminal thereof is used to receive the control voltage, a negative input terminal thereof is used to receive a first voltage threshold, and the first comparator is configured to generate a first comparison signal; a second comparator, whose positive input terminal is used to receive a second voltage threshold and whose negative input terminal is used to receive the control voltage, and the second comparator is configured to generate a second comparison signal, wherein the second voltage threshold is greater than the first voltage threshold, and the predetermined range is defined by the first voltage threshold and the second voltage threshold; and The NAND gate is configured to generate the selection signal according to the first comparison signal and the second comparison signal.

6. The PLL circuit according to claim 5, wherein: The first comparator and the second comparator are hysteresis comparators.

7. The PLL circuit according to claim 3, wherein: The frequency selector includes: a multiplexer having a first input terminal for receiving the reference signal, a second input terminal for receiving the feedback signal, and an output terminal for outputting the control signal, In response to the selection signal being asserted, the multiplexer transmits the feedback signal to the output end of the multiplexer as the control signal; and in response to the selection signal being de-asserted, the multiplexer transmits the reference signal to the output end of the multiplexer as the control signal.

8. The PLL circuit according to claim 3, wherein: The switching frequencies of the first switching signal and the second switching signal are equal to the frequency of the control signal, and the phases of the first switching signal and the second switching signal are opposite.

9. The PLL circuit according to claim 3, wherein: The frequency-to-current conversion circuit includes: a first switch coupled between the second node and the ground and controlled by the second switching signal; a first capacitor coupled between the second node and the ground; a second switch coupled between the third node and the second node and controlled by the first switching signal; A P-type transistor, a source of which is coupled to the fourth node, and a drain of which is coupled to the third node; and an operational amplifier, wherein a positive input terminal of the operational amplifier is coupled to the third node, a negative input terminal of the operational amplifier is used to receive a reference voltage, and an output terminal of the operational amplifier is coupled to the gate of the P-type transistor. The first bias current flows through the first P-type transistor.

10. The PLL circuit according to claim 9, wherein The frequency-to-current conversion circuit further includes: a second capacitor coupled between the third node and the ground terminal, The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

11. The PLL circuit according to claim 9, wherein The current bias circuit includes: a second P-type transistor, having a gate coupled to the output terminal of the operational amplifier, a source coupled to the fourth node, and a drain coupled to the fifth node; a current source coupled between the fifth node and the ground terminal and configured to provide a predetermined current; a third P-type transistor, having a gate coupled to the sixth node, a source coupled to the fourth node, and a drain coupled to the fifth node; and a current generating circuit coupled to the fourth node and the ICO; The second bias current flows through the third P-type transistor, and the current generating circuit is configured to generate the second control current according to the second bias current.

12. The PLL circuit according to claim 11, wherein The second control current is a multiple of the second bias current.

13. The PLL circuit according to claim 11, wherein The current generating circuit comprises: a fourth P-type transistor, having a gate coupled to the sixth node, a source coupled to the fourth node, and a drain coupled to the ICO; The second control current flows through the fourth P-type transistor.

14. The PLL circuit according to claim 11, wherein The current generating circuit comprises: a fourth P-type transistor, having a gate coupled to the sixth node and a source coupled to the fourth node; a fifth P-type transistor, having a gate for receiving the first bit signal, a source coupled to the drain of the fourth P-type transistor, and a drain coupled to the seventh node; a sixth P-type transistor, having a gate coupled to the sixth node and a source coupled to the fourth node; and a seventh P-type transistor, whose gate is used to receive the second bit signal, whose source is coupled to the drain of the sixth P-type transistor, and whose drain is coupled to the seventh node; At least one of the fifth P-type transistor and the seventh P-type transistor is turned on, and the second control current flows from the seventh node to the ICO.

15. The PLL circuit according to claim 11, wherein The current bias circuit further includes: a resistor coupled between the sixth node and the current generating circuit; and The third capacitor is coupled between the fourth node and the current generating circuit.

16. The PLL circuit according to claim 3, wherein: The frequency-to-current conversion circuit includes: a first switch coupled between the second node and the ground and controlled by the second switching signal; a first capacitor coupled between the second node and the ground; a second switch coupled between the third node and the second node and controlled by the first switch signal; a first P-type transistor, having a gate coupled to the fifth node and a source coupled to the fourth node; a first N-type transistor, a gate and a drain of which are coupled to the drain of the first P-type transistor at the sixth node, and a source of the first N-type transistor coupled to the ground terminal; a second P-type transistor, having a gate coupled to the fifth node, a source coupled to the fourth node, and a drain coupled to the fifth node; and a second N-type transistor, a gate coupled to the sixth node, a drain coupled to the fifth node, and a source coupled to the third node; The first bias current flows through the second P-type transistor and the second N-type transistor.

17. The PLL circuit according to claim 16, wherein: The frequency-to-current conversion circuit further includes: a second capacitor coupled between the third node and a ground terminal; The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

18. The PLL circuit according to claim 16, wherein: The current bias circuit includes: a third P-type transistor, having a gate coupled to the fifth node, a source coupled to the fourth node, and a drain coupled to the seventh node; a current source coupled between the seventh node and the ground terminal and configured to provide a predetermined current; a fourth P-type transistor, having a gate coupled to the eighth node, a source coupled to the fourth node, and a drain coupled to the seventh node; and a current generating circuit coupled to the fourth node and the ICO, The second bias current flows through the fourth P-type transistor, and the current generating circuit is configured to generate the second control current according to the second bias current.

19. The PLL circuit according to claim 18, wherein The bias circuit also includes: a resistor coupled between the eighth node and the current generating circuit; and The third capacitor is coupled between the fourth node and the current generating circuit.

20. The PLL circuit according to claim 18, wherein The current generating circuit comprises: a fifth P-type transistor, having a gate coupled to the eighth node and a source coupled to the fourth node; a sixth P-type transistor, having a gate for receiving the first bit signal, a source coupled to the drain of the fifth P-type transistor, and a drain coupled to the ninth node; a seventh P-type transistor, having a gate coupled to the eighth node and a source coupled to the fourth node; and an eighth P-type transistor, having a gate for receiving the second bit signal, a source coupled to the drain of the seventh P-type transistor, and a drain coupled to the ninth node; The sixth P-type transistor and the eighth P-type transistor are turned on, and the second control current flows from the ninth node to the ICO.

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