Head unit and liquid ejecting apparatus

Abstract

The invention relates to a head unit and a liquid ejecting apparatus, and provides a head unit capable of reducing the possibility of distortion in a signal waveform of a drive signal. In a head unit, a wiring substrate includes a first side and a second side located at a position opposite the first side, and a first supply point to which a first driving signal is supplied, a first electrode is supplied with a first reference voltage signal when viewed along a second axis orthogonal to a first axis connecting the first side and the second side, and a second electrode is supplied with a second reference voltage signal when viewed along a second axis orthogonal to the first axis connecting the first side and the second side. A first capacitor to which a ground signal is supplied to a second electrode is located between an output connector electrically connected to the first print head and the first supply point, and the shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode. The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

Description

Technical Field

[0001] The present invention relates to a head unit and a liquid ejecting device. Background Art

[0002] A device known for using a piezoelectric element in a liquid ejection device that ejects liquid to form text or images on a medium is known. A piezoelectric element is provided in a printhead corresponding to each of a plurality of ejection units. The piezoelectric element is driven by a drive signal, and an amount of liquid corresponding to the drive of the piezoelectric element is ejected from the corresponding ejection unit, forming a dot on the medium.

[0003] For example, Patent Document 1 discloses that the possibility of distortion in the signal waveform of a driving signal that drives a piezoelectric element being reduced by optimizing the propagation path of the driving signal.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2023-063709

[0005] However, from the perspective of reducing the possibility of distortion occurring in the signal waveform of the drive signal, the technology described in Patent Document 1 alone is not sufficient and there is room for further improvement. Summary of the Invention

[0006] One aspect of the head unit according to the present invention includes:

[0007] The first print head includes a first drive element having one end supplied with a first drive signal and the other end supplied with a first reference voltage signal having a constant voltage value, and ejects liquid in response to the driving of the first drive element; and

[0008] a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head;

[0009] The driving unit comprises:

[0010] a first driving circuit, outputting the first driving signal;

[0011] A first reference voltage signal output circuit, outputting the first reference voltage signal;

[0012] an output connector electrically connected to the first print head;

[0013] a first capacitor, a first electrode of the first capacitor being supplied with the first reference voltage signal, and a second electrode of the first capacitor being supplied with a ground signal; and

[0014] A wiring substrate is provided with the output connector and is used for transmitting the first drive signal and the first reference voltage signal.

[0015] The wiring substrate includes a first side, a second side located opposite to the first side, and a first supply point to which the first drive signal is supplied.

[0016] The first capacitor is located between the output connector and the first supply point when viewed along a second axis orthogonal to a first axis connecting the first side and the second side,

[0017] The shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode.

[0018] The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

[0019] One embodiment of the liquid ejection device according to the present invention comprises:

[0020] Conveying unit, conveying medium;

[0021] The first print head includes a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, and ejects liquid onto the medium in response to the driving of the first driving element; and

[0022] a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head;

[0023] The driving unit comprises:

[0024] a first driving circuit, outputting the first driving signal;

[0025] A first reference voltage signal output circuit, outputting the first reference voltage signal;

[0026] an output connector electrically connected to the first print head;

[0027] a first capacitor, a first electrode of the first capacitor being supplied with the first reference voltage signal, and a second electrode of the first capacitor being supplied with a ground signal; and

[0028] A wiring substrate is provided with the output connector and is used for transmitting the first drive signal and the first reference voltage signal.

[0029] The wiring substrate includes a first side, a second side located opposite to the first side, and a first supply point to which the first drive signal is supplied.

[0030] The first capacitor is located between the output connector and the first supply point when viewed along a second axis orthogonal to a first axis connecting the first side and the second side,

[0031] The shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode.

[0032] The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a diagram showing a schematic configuration of a liquid ejecting device.

[0034] Figure 2 It is a diagram showing a schematic configuration of a head unit.

[0035] Figure 3 1 is a diagram showing an example of the signal waveforms of the drive signals COMA, COMB, and COMC.

[0036] Figure 4 1 is a diagram showing the functional configuration of a drive signal selection circuit.

[0037] Figure 5 This is a diagram showing an example of the decoded content in the decoder.

[0038] Figure 6 This is a diagram showing an example of the configuration of a selection circuit corresponding to one ejection unit.

[0039] Figure 7 This is a diagram for explaining the operation of the drive signal selection circuit.

[0040] Figure 8 This is a diagram showing an example of the configuration of a drive circuit.

[0041] Figure 9 This is a diagram showing an example of the configuration of a drive signal discharge circuit.

[0042] Figure 10 : is a diagram showing an example of the configuration of a reference voltage signal output circuit.

[0043] Figure 11 This is a diagram showing an example of the configuration of a VHV control signal output circuit.

[0044] Figure 12 This is a diagram showing the configuration of a status signal input / output circuit.

[0045] Figure 13 This is a diagram showing the configuration of an abnormal signal input and output circuit.

[0046] Figure 14 This is a diagram showing an example of the configuration of a step-down circuit.

[0047] Figure 15 This is a diagram showing an example of the configuration of a first step-down circuit.

[0048] Figure 16 It is a diagram showing the structure of the discharge unit.

[0049] Figure 17 This is a diagram showing an example of the structure of a print head.

[0050] Figure 18 This is a diagram showing an example of a cross section of a print head.

[0051] Figure 19 It is a diagram showing the structure of a drive unit.

[0052] Figure 20 FIG. 1 is a diagram showing an example of the configuration of a drive circuit module.

[0053] Figure 21 This is a diagram showing an example of a cross-sectional structure of a head substrate.

[0054] Figure 22 This is a diagram showing an example of the arrangement of a plurality of electronic components mounted on a head substrate.

[0055] Figure 23 This is a diagram showing an example of a wiring pattern formed on the head substrate for transmitting drive signals COMA1 to COMA6 .

[0056] Figure 24 This is a diagram showing an example of a wiring pattern formed on the head substrate for transmitting the drive signals COMB1 to COMB6 .

[0057] Figure 25 This is a diagram showing an example of a wiring pattern formed on the head substrate for transmitting the drive signals COMC1 to COMC6 and the reference voltage signals VBS1 to VBS3 .

[0058] Figure 26 1 is a diagram showing an example of a wiring pattern formed on a head substrate for transmitting reference voltage signals VBS4 to VBS6 .

[0059] Description of Reference Numerals

[0060] 1: Liquid ejection device; 2: Control unit; 3: Liquid container; 4: Transport unit; 5: Head unit; 10: Drive unit; 20: Ejection unit; 23: Print head; 30: Connecting component; 31: Frame; 33: Assembly substrate; 34: Flow path structure; 35: Head substrate; 37: Distribution flow path; 39: Fixing plate; 41: Transport motor; 42: Transport roller; 50: Drive signal output circuit; 52: Drive circuit; 60: Piezoelectric element; 100: Control circuit; 110-1 to 110-6: Capacitors; 120: Conversion circuit; 130: Buck circuit; 140: VHV supply switching circuit; 150a: First buck circuit; 150b: Second buck circuit; 152a, 152b: Coils 153a, 153b: capacitors; 154a, 155a: resistors; 156a: capacitors; 160a, 160b: integrated circuits; 161: drive circuit; 162: drive control circuit; 163: level shift circuit; 164: switch circuit; 165-167: transistors; 190-1-190-6: capacitors; 200: drive signal selection circuit; 201: integrated circuit; 210: selection control circuit; 212: shift register; 214: latch circuit; 216: decoder; 220: recovery circuit; 230: selection circuit; 232a, 232b, 232c: inverters; 234a, 234b, 234c: transmission gates; 311: opening; 313: collector Substrate insertion portion; 315: Holding component; 330: Connecting portion; 341: Introduction portion; 343: Through hole; 351: Opening portion; 352, 353, 355: Notch portions; 371: Opening portion; 373: Introduction portion; 388: Wiring component; 391: Opening portion; 400: Internal voltage generation circuit; 410: Oscillation circuit; 411: Clock selection circuit; 430: Abnormality detection circuit; 431: Oscillation abnormality detection portion; 432: Operation abnormality detection portion; 433: Power supply voltage abnormality detection portion; 440: Register control circuit; 441: Sequence register; 442: Status register; 443: Register control portion; 450: Drive signal discharge circuit; 451: Resistor; 452: Crystal Tube; 453: Inverter; 460: Reference voltage signal output circuit; 461: Comparator; 462, 462: Transistors; 464, 465, 466: Resistors; 467: Inverter; 470: VHV control signal output circuit; 471: Transistor; 472: Resistor; 480: Status signal input / output circuit; 481: Transistor; 482: Inverter; 483: Resistor; 490: Abnormal signal input / output circuit; 491: Transistor; 492: Inverter; 493: Resistor; 500: Integrated circuit; 501: Drive signal generation circuit; 502: Amplification control signal generation circuit; 510: DAC interface; 520: DAC unit; 530: Modulation unit; 540: Gate drive unit;542: transistor; 550: amplifier circuit; 551, 552: transistors; 560: demodulation circuit; 561: coil; 562: capacitor; 570: feedback circuit; 571, 572, 576: resistor; 600: ejection portion; 601: piezoelectric element; 602, 603: electrodes; 610: vibration plate; 611: lead electrode; 620: flexible substrate; 621: sealing film; 622: fixed substrate; 623: nozzle plate; 623a: liquid ejection surface; 630: connecting plate; 641: protective substrate; 642: flow path forming substrate; 643: through hole; 644: protective space; 660: housing; 661: inlet path; 662: connection port; 665: recess; 801, 802: surface; 810: Insulation layer; 811: Surface wiring layer; 812: Surface wiring layer; 820: Internal wiring layer; 821-824: Edge; B1: Base substrate; B2: Converter circuit substrate; CB: Pressure chamber; CN1, CN2, CN3a, CN3b, CN4b: Connectors; DRV: Drive circuit module; FC: Wiring component; IC1: Integrated circuit; Ln1, Ln2: Nozzle array; MN: Manifold; N: Nozzle; P: Medium; RA, RB: Supply channels; RK1, RK2: Pressure chamber channels; RR: Nozzle channels; RX: Connector channels; Su1, Su2: Flow path plates; Wca1-Wca6, Wcb1-Wcb6, Wcc1-Wcc6, Wvb1-Wvb6, Wvhv: Wiring. DETAILED DESCRIPTION

[0061] The following drawings illustrate preferred embodiments of the present invention. The drawings are provided for ease of description. It should be noted that the embodiments described below are not intended to unduly limit the scope of the present invention as set forth in the claims. Furthermore, not all of the components described below are essential components of the present invention.

[0062] 1. Structure of liquid ejection device

[0063] Figure 1 1 is a diagram showing a schematic structure of the liquid ejecting device 1. Figure 1 As shown, the liquid ejection device 1 is a so-called line inkjet printer that forms a desired image on the medium P by ejecting ink at a desired timing onto the medium P transported by the transport unit 4. In the following description, the direction in which the medium P is transported is sometimes referred to as the transport direction, and the width direction of the transported medium P is sometimes referred to as the main scanning direction.

[0064] like Figure 1 As shown, the liquid ejecting device 1 includes a control unit 2 , a liquid container 3 , a transport unit 4 , and a plurality of head units 5 .

[0065] The control unit 2 includes an AC / DC converter and inputs a commercial AC voltage signal from outside the liquid ejection device 1. The AC / DC converter included in the control unit 2 generates a voltage signal VDC having a predetermined voltage value, for example, a DC voltage signal having a voltage value of 48V, and supplies the generated voltage signal VDC to each element included in the liquid ejection device 1. Furthermore, the control unit 2 includes processing circuits such as a CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array), and storage circuits such as semiconductor memories. Furthermore, the processing circuit included in the control unit 2 outputs control signals for controlling each element of the liquid ejection device 1 based on image data input from an external device such as a host computer (not shown) located outside the liquid ejection device 1.

[0066] The liquid container 3 stores ink as an example of liquid supplied to the head unit 5. Specifically, the liquid container 3 stores inks of various colors such as black, cyan, magenta, yellow, red, and gray to be ejected onto the medium P.

[0067] The conveying unit 4 includes a conveying motor 41 and conveying rollers 42. The conveying unit 4 receives a conveying control signal Ctrl-T from the control unit 2. The conveying motor 41 is driven based on the input conveying control signal Ctrl-T, and the conveying rollers 42 rotate in response to the drive of the conveying motor 41. The rotation of the conveying rollers 42 conveys the medium P in the conveying direction.

[0068] The plurality of head units 5 are electrically connected to the control unit 2 via a flexible cable such as a flexible flat cable (FFC). The length of the flexible cable such as the FFC electrically connecting the control unit 2 and the head unit 5 can be more than 2 m. In addition, the plurality of head units 5 each have a drive unit 10 and a discharge unit 20. The voltage signal VDC and the image information signal IP output by the control unit 2 are input to the head unit 5 via the above-mentioned FFC, and the ink stored in the liquid container 3 is supplied to the head unit 5 via an ink tube not shown. The head unit 5 operates using the voltage signal VDC as driving power. In addition, the drive unit 10 controls the operation of the discharge unit 20 based on the image information signal IP, and the discharge unit 20 discharges the ink supplied from the liquid container 3 onto the medium P in accordance with the control of the drive unit 10.

[0069] In the liquid ejection device 1 of this embodiment, the ejection units 20 included in each of the multiple head units 5 are arranged side by side in the main scanning direction with a width greater than the width of the medium P. This allows the ejection units 20 to eject ink across the entire width of the transported medium P. Specifically, the liquid ejection device 1 of this embodiment constitutes a so-called line inkjet printer, in which the multiple ejection units 20 arranged side by side with a width greater than the width of the medium P each eject ink as the medium P is transported, thereby forming a desired image on the medium P. It should be noted that the liquid ejection device 1 is not limited to a line inkjet printer and may also be a so-called serial inkjet printer, in which the ejection units 20 eject ink onto the medium P being transported synchronously with this reciprocating movement while moving back and forth in the main scanning direction, i.e., the width of the medium P, thereby forming a desired image on the medium P.

[0070] 2. Functional composition of the head unit

[0071] 2.1 Functional composition of the head unit

[0072] Next, a general structure of the head unit 5 will be described. Here, the plurality of head units 5 included in the liquid ejection device 1 all have the same structure. Therefore, in the following description, only the structure of one head unit 5 will be described. Figure 2 : is a diagram showing a schematic structure of the head unit 5. Figure 2 As shown, the head unit 5 includes a driving unit 10 and a discharge unit 20. In the head unit 5, the driving unit 10 and the discharge unit 20 are electrically connected via a connection member 30.

[0073] The connecting component 30 electrically connects the drive unit 10 and the ejection unit 20. Flexible printed circuits (FPCs) or flexible printed circuits (FFCs) can be used. Note that a board-to-board (BtoB) connector can be used instead of an FPC or FFC as the connecting component 30, or a combination of a BtoB connector and an FPC or FFC can be used.

[0074] The driving unit 10 includes a control circuit 100 , driving signal output circuits 50 - 1 to 50 - 6 , a conversion circuit 120 , a step-down circuit 130 , and capacitors 110 - 1 to 110 - 6 and 190 - 1 to 190 - 6 .

[0075] The step-down control signals VHVc1 to VHVc6 and the voltage signal VDC are input to the step-down circuit 130. That is, the voltage signal VDC is supplied to the drive unit 10 through a cable electrically connected to the control unit 2. The step-down circuit 130 steps down the input DC voltage of 48V, that is, the voltage signal VDC, and generates a plurality of DC voltage signals including a voltage signal VHV with a constant voltage value of 42V and a voltage signal VDD with a constant voltage value of 5V, and outputs the generated plurality of DC voltage signals to each component of the head unit 5. At this time, the step-down circuit 130 switches whether to output the voltage signal VHV obtained by stepping down the input voltage signal VDC by operating based on the logic level of the step-down control signals VHVc1 to VHVc6. It should be noted that a specific example of the structure and operation of the step-down circuit 130 will be described later.

[0076] The control circuit 100 includes a processing circuit such as a CPU and FPGA, and a storage circuit such as a semiconductor memory. The control circuit 100 receives an image information signal IP output by the control unit 2. Based on the input image information signal IP, the control circuit 100 outputs signals for controlling various components of the head unit 5.

[0077] The control circuit 100 generates a basic data signal dDATA for controlling the operation of the ejection unit 20 based on the image information signal IP, and outputs the generated basic data signal dDATA to the conversion circuit 120. The conversion circuit 120 converts the basic data signal dDATA into a differential signal such as LVDS (Low Voltage Differential Signaling) and outputs the differential signal as the data signal DATA to the ejection unit 20. It should be noted that the conversion circuit 120 may also convert the basic data signal dDATA into a differential signal using a high-speed transmission method other than LVDS, such as LVPECL (Low Voltage Positive Emitter Coupled Logic) or CML (Current Mode Logic), and output the differential signal as the data signal DATA to the ejection unit 20. Furthermore, the conversion circuit 120 may also convert part or all of the input basic data signal dDATA into a predetermined single-ended signal and output the predetermined single-ended signal as the data signal DATA to the ejection unit 20.

[0078] In addition, the control circuit 100 outputs basic drive data signals dA1, dB1, and dC1 to the drive signal output circuit 50-1. Voltage signals VHV and VDD are also input to the drive signal output circuit 50-1. The drive signal output circuit 50-1 includes drive circuits 52a, 52b, and 52c. The basic drive data signal dA1 is input to the drive circuit 52a included in the drive signal output circuit 50-1. The drive circuit 52a included in the drive signal output circuit 50-1 operates based on the voltage signal VDD and, after performing digital / analog conversion on the input basic drive data signal dA1, performs D-class amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMA1. The generated drive signal COMA1 is then output to the ejection unit 20. The basic drive data signal dB1 is input to the drive circuit 52b included in the drive signal output circuit 50-1. The drive circuit 52b included in the drive signal output circuit 50-1 operates based on the voltage signal VDD, performs digital-to-analog conversion on the input basic drive data signal dB1, and then performs D-class amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMB1. The generated drive signal COMB1 is output to the ejection unit 20. The basic drive data signal dC1 is input to the drive circuit 52c included in the drive signal output circuit 50-1. The drive circuit 52c included in the drive signal output circuit 50-1 operates based on the voltage signal VDD, performs digital-to-analog conversion on the input basic drive data signal dC1, and then performs D-class amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMC1. The generated drive signal COMC1 is output to the ejection unit 20. That is, the driving signal output circuit 50 - 1 generates driving signals COMA1 , COMB1 , COMC1 having signal waveforms corresponding to the input basic driving data signals dA1 , dB1 , dC1 , and outputs the generated driving signals COMA1 , COMB1 , COMC1 to the discharge unit 20 .

[0079] Furthermore, the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1 each generate a constant reference voltage signal VBS1 having a voltage value of 5.5V, 6V, or the like. The reference voltage signals VBS1 generated by the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1 are propagated through a common wiring and are output from the drive signal output circuit 50-1 to the ejection unit 20. It should be noted that the drive signal output circuit 50-1 may also output the reference voltage signal VBS1 output by any one of the drive circuits 52a, 52b, and 52c to the ejection unit 20. Alternatively, the reference voltage signal VBS1 may be generated by a power supply circuit (not shown) that is configured separately from the drive circuits 52a, 52b, and 52c.

[0080] The control circuit 100 also outputs basic drive data signals dAi, dBi, and dCi to the drive signal output circuit 50-i (i is any of 2 to 6). Voltage signals VHV and VDD are also input to the drive signal output circuit 50-i. The drive signal output circuit 50-i includes drive circuits 52a, 52b, and 52c. The basic drive data signal dAi is input to the drive circuit 52a of the drive signal output circuit 50-i. The drive circuit 52a of the drive signal output circuit 50-i operates based on the voltage signal VDD. After performing digital-to-analog conversion on the input basic drive data signal dAi, the converted signal is subjected to D-class amplification based on the voltage signal VHV to generate the drive signal COMAi. The generated drive signal COMAi is then output to the ejection unit 20. The basic drive data signal dBi is input to the drive circuit 52b of the drive signal output circuit 50-i. The drive circuit 52b included in the drive signal output circuit 50-i operates based on the voltage signal VDD, performs digital-to-analog conversion on the input basic drive data signal dBi, and then performs D-class amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMBi. The generated drive signal COMBi is output to the ejection unit 20. The basic drive data signal dCi is input to the drive circuit 52c included in the drive signal output circuit 50-i. The drive circuit 52c included in the drive signal output circuit 50-i operates based on the voltage signal VDD, performs digital-to-analog conversion on the input basic drive data signal dCi, and then performs D-class amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMCi. The generated drive signal COMCi is output to the ejection unit 20. That is, the drive signal output circuit 50 - i generates drive signals COMAi, COMBi, COMCi having signal waveforms corresponding to the input basic drive data signals dAi, dBi, dCi, and outputs the generated drive signals COMAi, COMBi, COMCi to the ejection unit 20 .

[0081] Furthermore, the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i each generate a constant reference voltage signal VBSi having a voltage value of 5.5V, 6V, or the like. The reference voltage signals VBSi generated by the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i are propagated through a common wiring and are output from the drive signal output circuit 50-i to the ejection unit 20. It should be noted that the drive signal output circuit 50-i may output the reference voltage signal VBSi outputted by any one of the drive circuits 52a, 52b, and 52c to the ejection unit 20. Furthermore, the reference voltage signal VBSi may be generated by a power supply circuit (not shown) that is configured separately from the drive circuits 52a, 52b, and 52c.

[0082] The drive signal output circuit 50-1 also generates a step-down control signal VHVc1 and outputs the generated step-down control signal VHVc1 to the step-down circuit 130. The step-down control signal VHVc1 is generated by the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1. The drive signal output circuit 50-1 then transmits the step-down control signal VHVc1 generated by the drive circuits 52a, 52b, and 52c using a common wiring and supplies the step-down control signal VHVc1 to the step-down circuit 130. It should be noted that the drive signal output circuit 50-1 may also output the step-down control signal VHVc1 generated by any one of the drive circuits 52a, 52b, and 52c and supply the step-down control signal VHVc1 to the step-down circuit 130. Similarly, the drive signal output circuit 50-i generates a step-down control signal VHVci and outputs the generated step-down control signal VHVci to the step-down circuit 130. The step-down control signal VHVci is generated by the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i. The drive signal output circuit 50-i then transmits the step-down control signal VHVci generated by the drive circuits 52a, 52b, and 52c using common wiring and supplies the step-down control signal VHVci to the step-down circuit 130. It should be noted that the drive signal output circuit 50-i may also output the step-down control signal VHVci generated by any one of the drive circuits 52a, 52b, and 52c from the drive signal output circuit 50-1 and supply the step-down control signal VHVci to the step-down circuit 130.

[0083] Here, the drive signal output circuit 50-1 and the drive signal output circuits 50-2 to 50-6 have the same configuration and, when there is no need to distinguish them, are sometimes simply referred to as the drive signal output circuit 50. In this case, the drive signal output circuit 50 includes drive circuits 52a, 52b, and 52c, where the drive circuit 52a outputs the drive signal COMA, the drive circuit 52b outputs the drive signal COMB, and the drive circuit 52c outputs the drive signal COMC. Furthermore, the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50 all have the same configuration and, when there is no need to distinguish them, are sometimes simply referred to as the drive circuit 52. In this case, the drive circuit 52 generates the drive signal COM based on the basic drive data signal d0 and outputs the generated drive signal COM to the ejection unit 20.

[0084] On the other hand, when explaining the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1 and the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i separately, the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1 may be referred to as drive circuits 52a1, 52b1, and 52c1, respectively, and the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i may be referred to as drive circuits 52ai, 52bi, and 52ci, respectively. A specific example of the configuration of the drive circuit 52 will be described later.

[0085] One end of capacitor 110-1 is electrically connected to the propagation path of voltage signal VHV supplied to drive signal output circuit 50-1, while the other end is supplied with a ground signal at ground potential. One end of capacitor 110-i is electrically connected to the propagation path of voltage signal VHV supplied to drive signal output circuit 50-i, while the other end is supplied with a ground signal. In other words, capacitors 110-1 to 110-6 function as stabilizing capacitors that stabilize the voltage values ​​of voltage signals VHV supplied to the corresponding drive signal output circuits 50-1 to 50-6. Capacitors 110-1 to 110-6 have relatively large electrostatic capacitance, and electrolytic capacitors, for example, can be used. It should be noted that in the following description, capacitors 110-1 to 110-6 are described as electrolytic capacitors. However, capacitors 110-1 to 110-6 may be ceramic capacitors or film capacitors, as long as they have sufficient capacitance to stabilize the voltage value of voltage signal VHV and supply sufficient current to each of drive signal output circuits 50-1 to 50-6. Furthermore, the electrolytic capacitors used as capacitors 110-1 to 110-6 may be either aluminum or tantalum.

[0086] One end of capacitor 190-1 is electrically connected to the propagation path of reference voltage signal VBS1 output by drive signal output circuit 50-1, while the other end is supplied with a ground signal. One end of capacitor 190-i is electrically connected to the propagation path of reference voltage signal VBSi output by drive signal output circuit 50-i, while the other end is supplied with a ground signal. In other words, capacitors 190-1 through 190-6 function as stabilizing capacitors, stabilizing the voltage values ​​of reference voltage signals VBS1 through VBS6 output by corresponding drive signal output circuits 50-1 through 50-6. Capacitors 190-1 through 190-6 have relatively large capacitance, and electrolytic capacitors, for example, can be used. It should be noted that in the following description, capacitors 190-1 to 190-6 are described as electrolytic capacitors. However, as long as capacitors 190-1 to 190-6 have an electrostatic capacitance sufficient to stabilize the voltage values ​​of reference voltage signals VBS1 to VBS6 and to supply sufficient current to the piezoelectric element 60 (described later) included in the discharge unit 20, they may be ceramic capacitors or film capacitors. Furthermore, the electrolytic capacitors used as capacitors 190-1 to 190-6 may be aluminum or tantalum.

[0087] That is, the drive unit 10 includes: a capacitor 190-1, one end, i.e., the + pole, to which the reference voltage signal VBS1 is supplied, and the other end, i.e., the - pole, to which the ground signal is supplied; a capacitor 190-2, one end, i.e., the + pole, to which the reference voltage signal VBS2 is supplied, and the other end, i.e., the - pole, to which the ground signal is supplied; a capacitor 190-3, one end, i.e., the + pole, to which the reference voltage signal VBS3 is supplied, and the other end, i.e., the - pole, to which the ground signal is supplied; a capacitor 190-4, one end, i.e., the + pole, to which the reference voltage signal VBS1 is supplied, and the other end, i.e., the - pole, to which the ground signal is supplied. The quasi-voltage signal VBS4 is supplied to one end, i.e., the - pole, and the ground signal is supplied to the other end, i.e., the - pole; the capacitor 190-5, one end, i.e., the + pole, is supplied with the reference voltage signal VBS5, and the other end, i.e., the - pole, is supplied with the ground signal; the capacitor 190-6, one end, i.e., the + pole, is supplied with the reference voltage signal VBS6, and the other end, i.e., the - pole, is supplied with the ground signal; and the capacitors 110-1~110-6, one end, i.e., the + pole, is supplied with the voltage signal VHV, and the other end, i.e., the - pole, is supplied with the ground signal.

[0088] The ejection unit 20 includes a reset circuit 220 and print heads 23 - 1 to 23 - 6 .

[0089] The data signal DATA is input to the restoration circuit 220. The restoration circuit 220 restores the input differential signal data signal DATA to a single-ended signal, converts the restored single-ended signal into parallel signals corresponding to the print heads 23-1 to 23-6, and inputs the parallel signals to the corresponding print heads 23-1 to 23-6.

[0090] Specifically, the restoration circuit 220 restores the data signal DATA and converts the restored data signal DATA into parallel signals to generate a clock signal SCK1, a print data signal SI1, and a latch signal LAT1. The restoration circuit 220 then outputs the generated clock signal SCK1, print data signal SI1, and latch signal LAT1 to the print head 23-1. Furthermore, the restoration circuit 220 restores the data signal DATA and converts the restored data signal DATA into parallel signals to generate a clock signal SCKi, a print data signal SIi, and a latch signal LATi. The restoration circuit 220 then outputs the generated clock signal SCKi, print data signal SIi, and latch signal LATi to the print head 23-i. It should be noted that any of the clock signals SCK1-SCK6, print data signals SI1-SI6, and latch signals LAT1-LAT6 corresponding to the print heads 23-1-23-6, respectively, output by the restoration circuit 220, can be commonly input to the print heads 23-1-23-6.

[0091] Here, since the restoration circuit 220 restores the data signal DATA and converts it into parallel signals to generate the clock signals SCK1-SCK6, print data signals SI1-SI6, and latch signals LAT1-LAT6, the data signal DATA output by the conversion circuit 120 is a differential signal that serially includes signals corresponding to the clock signals SCK1-SCK6, print data signals SI1-SI6, and latch signals LAT1-LAT6. Therefore, the basic data signal dDATA output by the control circuit 100 includes single-ended signals corresponding to the clock signals SCK1-SCK6, print data signals SI1-SI6, and latch signals LAT1-LAT6, respectively. In other words, the control circuit 100 outputs the basic data signal dDATA as a signal for controlling the operation of the print heads 23-1-23-6 of the ejection unit 20.

[0092] The print head 23-1 includes a drive signal selection circuit 200 and multiple ejection units 600. Each of the multiple ejection units 600 includes a piezoelectric element 60. That is, the print head 23-1 includes the same number of piezoelectric elements 60 as the ejection units 600. Voltage signals VHV and VDD, drive signals COMA1, COMB1, and COMC1, a reference voltage signal VBS1, a clock signal SCK1, a print data signal SI1, and a latch signal LAT1 are input to the print head 23-1. The voltage signals VHV and VDD, drive signals COMA1, COMB1, and COMC1, the clock signal SCK1, the print data signal SI1, and the latch signal LAT1 are input to the drive signal selection circuit 200 included in the print head 23-1. The drive signal selection circuit 200 generates a drive signal VOUT by selecting or deselecting the drive signals COMA1, COMB1, and COMC1, respectively, based on the input voltage signal VHV, clock signal SCK1, print data signal SI1, and latch signal LAT1, using voltage signal VDD as the drive power. The drive signal selection circuit 200 then supplies the generated drive signal VOUT to one end of the piezoelectric element 60 included in the corresponding ejection unit 600. At this time, a reference voltage signal VBS1 is supplied to the other end of the piezoelectric element 60. The piezoelectric element 60 is driven by the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS1 supplied to the other end. Ink corresponding to the amount of drive applied to the piezoelectric element 60 is ejected from the corresponding ejection unit 600.

[0093] Similarly, the print head 23-i includes a drive signal selection circuit 200 and multiple ejection units 600. Furthermore, each of the multiple ejection units 600 includes a piezoelectric element 60. That is, the print head 23-i includes the same number of piezoelectric elements 60 as the multiple ejection units 600. Voltage signals VHV and VDD, drive signals COMAi, COMBi, and COMCi, reference voltage signal VBSi, clock signal SCKi, print data signal SIi, and latch signal LATi are input to the print head 23-i. The voltage signals VHV and VDD, drive signals COMAi, COMBi, and COMCi, clock signal SCKi, print data signal SIi, and latch signal LATi are input to the drive signal selection circuit 200 included in the print head 23-i. The drive signal selection circuit 200 generates a drive signal VOUT by selecting or deselecting the drive signals COMAi, COMBi, and COMCi based on the input voltage signal VHV, clock signal SCKi, print data signal SIi, and latch signal LATi, using voltage signal VDD as the drive power. The drive signal selection circuit 200 then supplies the generated drive signal VOUT to one end of the piezoelectric element 60 included in the corresponding ejection unit 600. At this time, a reference voltage signal VBSi is supplied to the other end of the piezoelectric element 60. The piezoelectric element 60 is driven by the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBSi supplied to the other end. Ink corresponding to the amount of drive applied to the piezoelectric element 60 is ejected from the corresponding ejection unit 600.

[0094] As described above, the head unit 5 of the liquid ejection device 1 includes a drive unit 10 and an ejection unit 20. The drive unit 10 controls the operation of the ejection unit 20 based on the image information signal IP output by the control unit 2. Following the control of the drive unit 10, the ejection unit 20 ejects ink supplied from the liquid container 3 onto the medium P. Thus, the head unit 5 ejects a predetermined amount of ink toward the medium P at a predetermined timing based on the image information signal IP. As a result, the liquid ejection device 1 forms a desired image on the medium P.

[0095] Specifically, the head unit 5 includes a drive unit 10, which receives an external voltage signal VDC and outputs drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, and reference voltage signals VBS1 to VBS6; and an ejection unit 20, which ejects ink based on the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6. In other words, the drive unit 10 outputs the drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, and reference voltage signals VBS1 to VBS6 to the corresponding print heads 23-1 to 23-6.

[0096] Here, the print heads 23-1 to 23-6 included in the ejection unit 20 have the same configuration, differing only in the signals they receive. Therefore, in the following description, when it is not necessary to distinguish between the print heads 23-1 to 23-6, they may be simply referred to as the print head 23. In this case, the drive signals COMA1 to COMA6 input to the print head 23 may be referred to as drive signals COMA, the drive signals COMB1 to COMB6 may be referred to as drive signals COMB, the drive signals COMC1 to COMC6 may be referred to as drive signals COMC, the clock signals SCK1 to SCK6 may be referred to as clock signals SCK, the print data signals SI1 to SI6 may be referred to as print data signals SI, and the latch signals LAT1 to LAT6 may be referred to as latch signals LAT.

[0097] 2.2 Configuration and Operation of the Drive Signal Selection Circuit

[0098] Next, the configuration and operation of the drive signal selection circuit 200 included in the print head 23 will be described. When describing the configuration and operation of the drive signal selection circuit 200 included in the print head 23, an example of the signal waveforms included in the drive signals COMA, COMB, and COMC input to the drive signal selection circuit 200 will be described.

[0099] Figure 3 : is a diagram showing an example of the signal waveforms of the drive signals COMA, COMB, and COMC. Figure 3 As shown, the driving signal COMA includes a trapezoidal waveform Adp arranged in a period T from the rise of the latch signal LAT to the rise of the next latch signal LAT. The trapezoidal waveform Adp is a signal waveform supplied to one end of the piezoelectric element 60 to drive the piezoelectric element 60 so as to eject a predetermined amount of ink from the corresponding ejection portion 600.

[0100] The driving signal COMB includes a trapezoidal waveform Bdp arranged within a period T. The trapezoidal waveform Bdp is a signal waveform having a smaller voltage amplitude than the trapezoidal waveform Adp. When the trapezoidal waveform Bdp is supplied to one end of the piezoelectric element 60, it causes a smaller amount of ink than a predetermined amount to be ejected from the ejection portion 600 corresponding to the piezoelectric element 60. In other words, the trapezoidal waveform Bdp is a signal waveform supplied to one end of the piezoelectric element 60 to drive the piezoelectric element 60 so that a smaller amount of ink than a predetermined amount is ejected from the corresponding ejection portion 600.

[0101] Here, when the driving signal COMA is supplied to the piezoelectric element 60, the amount of ink ejected from the corresponding ejection portion 600 is greater than the amount of ink ejected from the corresponding ejection portion 600 when the driving signal COMB is supplied to the piezoelectric element 60. Therefore, the driving amount of the piezoelectric element 60 when the driving signal COMA is supplied to the piezoelectric element 60 is greater than the driving amount of the piezoelectric element 60 when the driving signal COMB is supplied to the piezoelectric element 60. In other words, the amount of ink ejected from the ejection portion 600 corresponding to the piezoelectric element 60 when the drive signal COMA is supplied to the piezoelectric element 60 is different from the amount of ink ejected from the ejection portion 600 corresponding to the piezoelectric element 60 when the drive signal COMB is supplied to the piezoelectric element 60. The amount of ink ejected from the ejection portion 600 corresponding to the piezoelectric element 60 when the drive signal COMA is supplied to the piezoelectric element 60 is greater than the amount of ink ejected from the ejection portion 600 corresponding to the piezoelectric element 60 when the drive signal COMB is supplied to the piezoelectric element 60. Therefore, the amount of current generated by the propagation of the drive signal COMA is greater than the amount of current generated by the propagation of the drive signal COMB.

[0102] Furthermore, the drive signal COMC includes a trapezoidal waveform Cdp arranged within a period T. The trapezoidal waveform Cdp is a signal waveform with a smaller voltage amplitude than the trapezoidal waveforms Adp and Bdp. When the trapezoidal waveform Cdp is supplied to one end of the piezoelectric element 60, it causes the ink near the nozzle opening to vibrate to such an extent that ink is not ejected from the ejection portion 600 corresponding to the piezoelectric element 60. In other words, the trapezoidal waveform Cdp is a signal waveform supplied to one end of the piezoelectric element 60 that drives the piezoelectric element 60 to such an extent that ink is not ejected from the corresponding ejection portion 600. This trapezoidal waveform Cdp causes the ink near the nozzle opening of the ejection portion 600 of the piezoelectric element 60 to vibrate. As a result, the likelihood of the ink viscosity increasing near the corresponding nozzle opening is reduced.

[0103] As described above, the drive signals COMA and COMB drive the corresponding piezoelectric element 60 so that ink is ejected from the ejection portion 600, while the drive signal COMC drives the corresponding piezoelectric element 60 so that ink is not ejected from the ejection portion 600. Specifically, the amount of drive of the piezoelectric element 60 when the drive signals COMA and COMB are supplied to the piezoelectric element 60 is greater than the amount of drive of the piezoelectric element 60 when the drive signal COMC is supplied to the piezoelectric element 60. Therefore, the voltage amplitude of the drive signals COMA and COMB is greater than the voltage amplitude of the drive signal COMC, and the amount of current generated by the propagation of the drive signals COMA and COMB is greater than the amount of current generated by the propagation of the drive signal COMC.

[0104] Furthermore, at the start and end timings of the trapezoidal waveforms Adp, Bdp, and Cdp, the voltage values ​​of the trapezoidal waveforms Adp, Bdp, and Cdp are all the same voltage Vc. That is, the trapezoidal waveforms Adp, Bdp, and Cdp are signal waveforms that start and end at voltage Vc, respectively.

[0105] In the following description, the amount of ink ejected from the ejection portion 600 corresponding to the piezoelectric element 60 when the trapezoidal waveform Adp is supplied to one end of the piezoelectric element 60 may be referred to as the "large amount," and the amount of ink ejected from the ejection portion 600 corresponding to the piezoelectric element 60 when the trapezoidal waveform Bdp is supplied to one end of the piezoelectric element 60 may be referred to as the "small amount," which is different from the "large amount." Furthermore, the action of vibrating the ink near the nozzle opening to such an extent that ink is not ejected from the ejection portion 600 corresponding to the piezoelectric element 60 when the trapezoidal waveform Cdp is supplied to one end of the piezoelectric element 60 may be referred to as "microvibration BSD."

[0106] That is, in the liquid ejection device 1 of this embodiment, the driving circuit 52a outputs a driving signal COMA, which drives the piezoelectric element 60 in a manner such that the ejection portion 600 of the print head 23 ejects a predetermined amount, that is, a large amount of ink. The driving circuit 52b outputs a driving signal COMB, which drives the piezoelectric element 60 in a manner such that the ejection portion 600 of the print head 23 ejects an amount less than the predetermined amount, that is, a small amount of ink. The driving circuit 52c outputs a driving signal COMC, which drives the piezoelectric element 60 in a manner such that the ejection portion 600 of the print head 23 does not eject ink.

[0107] It should be noted that the signal waveforms of the driving signals COMA, COMB, and COMC are not limited to Figure 3The illustrated shapes may also use various signal waveform shapes depending on the type of ink ejected from the ejection portion 600, the number of piezoelectric elements 60 driven by the drive signals COMA, COMB, and COMC, the wiring length for propagation of the drive signals COMA, COMB, and COMC, and the like. Therefore, the drive signals COMA1 to COMA6 may each have a signal waveform of a different shape, and the amount of ink ejected from the corresponding ejection portion 600 in response to the drive signal COMA1 may differ from the amount of ink ejected from the corresponding ejection portion 600 in response to the drive signal COMAi. Similarly, the drive signals COMB1 to COMB6 may each have a signal waveform of a different shape, and the amount of ink ejected from the corresponding ejection portion 600 in response to the drive signal COMB1 may differ from the amount of ink ejected from the corresponding ejection portion 600 in response to the drive signal COMBi. Similarly, the drive signals COMC1 to COMC6 may each have a signal waveform of a different shape, and the amount of displacement generated by the piezoelectric element 60 in response to the drive signal COMC1 may differ from the amount of displacement generated by the piezoelectric element 60 in response to the drive signal COMCi.

[0108] Next, the configuration and operation of the drive signal selection circuit 200 that outputs the drive signal VOUT by selecting or not selecting the drive signals COMA, COMB, and COMC will be described. Figure 4 2 is a diagram showing the functional configuration of the drive signal selection circuit 200. Figure 4 As shown, the driving signal selection circuit 200 includes a selection control circuit 210 and a plurality of selection circuits 230 .

[0109] The selection control circuit 210 receives inputs such as the print data signal SI, the latch signal LAT, and the clock signal SCK. Furthermore, the selection control circuit 210 includes n sets of shift registers (S / R) 212, latch circuits 214, and decoders 216, corresponding to the n ejection units 600. Specifically, the drive signal selection circuit 200 includes n shift registers 212, n latch circuits 214, and n decoders 216, the same number as the n ejection units 600.

[0110] The print data signal SI is synchronized with the clock signal SCK and includes two bits of print data [SIH, SIL] for specifying the dot size formed by ink ejected from each of the n ejection units 600, using one of "large dot LD," "small dot SD," "non-ejection ND," and "micro vibration BSD." The print data signal SI is stored in the shift register 212 corresponding to the ejection unit 600 as two bits of print data [SIH, SIL].

[0111] Specifically, n shift registers 212 corresponding to the ejection unit 600 are connected in cascade. The 2-bit print data [SIH, SIL] included in the print data signal SI is sequentially transmitted to the subsequent stage of the cascade-connected shift register 212 according to the clock signal SCK. Then, when the clock signal SCK stops, the 2-bit print data [SIH, SIL] corresponding to the ejection unit 600 corresponding to the shift register 212 is retained in the n shift registers 212. It should be noted that Figure 4 In FIG. 1 , in order to distinguish the n shift registers 212 connected in cascade, the shift registers 212 are shown as 1st stage, 2nd stage, . . . , nth stage from the upstream side to the downstream side to which the print data signal SI is input.

[0112] When the latch signal LAT rises, each of the n latch circuits 214 simultaneously latches the 2-bit print data [SIH, SIL] held in the corresponding shift register 212 .

[0113] The 2-bit print data [SIH, SIL] latched by the latch circuit 214 is input to the corresponding decoder 216. The n decoders 216 each decode the input 2-bit print data [SIH, SIL] and output selection signals S1, S2, and S3 of logic levels corresponding to the decoded data in each cycle T. Figure 5 This is a diagram showing an example of the decoding content in the decoder 216. The decoder 216 generates a 2-bit print data [SIH, SIL] input and Figure 5 The decoder 216 outputs select signals S1, S2, and S3 by level-shifting the generated signals to high-amplitude logic levels according to the voltage value of the voltage signal VHV. For example, if the 2-bit print data [SIH, SIL] input to the decoder 216 is [1, 0], the decoder 216 sets the logic levels of the select signals S1, S2, and S3 to L, H, and L, respectively, within a period T.

[0114] return Figure 4 The selection circuit 230 is provided for each of the n ejection units 600. That is, the drive signal selection circuit 200 includes n selection circuits 230. The selection circuits 230 receive the selection signals S1, S2, and S3 output by the decoder 216 corresponding to the same ejection unit 600, as well as the drive signals COMA, COMB, and COMC. The selection circuits 230 generate the drive signal VOUT by selecting or not selecting the drive signals COMA, COMB, and COMC based on the selection signals S1, S2, and S3, respectively, and output the generated drive signal VOUT to the corresponding ejection unit 600.

[0115] Figure 61 is a diagram showing an example of the configuration of the selection circuit 230 corresponding to one ejection unit 600. Figure 6 As shown, the selection circuit 230 includes inverters 232a, 232b, 232c and transmission gates 234a, 234b, 234c.

[0116] The select signal S1 is input to the positive control terminal (not marked with a circle) of transmission gate 234a. After being logically inverted by inverter 232a, it is also input to the negative control terminal (marked with a circle) of transmission gate 234a. The drive signal COMA is input to the input terminal of transmission gate 234a. When the input select signal S1 is at an H level, transmission gate 234a establishes conduction between the input terminal and the output terminal. When the input select signal S1 is at an L level, transmission gate 234a establishes non-conduction between the input terminal and the output terminal. That is, transmission gate 234a outputs the drive signal COMA to the output terminal when the select signal S1 is at an H level, and does not output the drive signal COMA to the output terminal when the select signal S1 is at an L level.

[0117] The select signal S2 is input to the positive control terminal (not marked with a circle) of transmission gate 234b and, after being logically inverted by inverter 232b, is also input to the negative control terminal (marked with a circle) of transmission gate 234b. The drive signal COMB is input to the input terminal of transmission gate 234b. When the input select signal S2 is at an H level, transmission gate 234b establishes conduction between the input terminal and the output terminal. When the input select signal S2 is at an L level, transmission gate 234b establishes non-conduction between the input terminal and the output terminal. That is, transmission gate 234b outputs the drive signal COMB to the output terminal when the select signal S2 is at an H level, and does not output the drive signal COMB to the output terminal when the select signal S2 is at an L level.

[0118] The select signal S3 is input to the positive control terminal (not marked with a circle) of transmission gate 234c and, after being logically inverted by inverter 232c, is also input to the negative control terminal (marked with a circle) of transmission gate 234c. The drive signal COMC is input to the input terminal of transmission gate 234c. When the input select signal S3 is at an H level, transmission gate 234c establishes conduction between the input terminal and the output terminal. When the input select signal S3 is at an L level, transmission gate 234c establishes non-conduction between the input terminal and the output terminal. That is, transmission gate 234c outputs the drive signal COMC to the output terminal when the select signal S3 is at an H level, and does not output the drive signal COMC to the output terminal when the select signal S3 is at an L level.

[0119] In the selection circuit 230, the output terminals of the transmission gates 234a, 234b, and 234c are commonly connected. Specifically, the drive signals COMA, COMB, and COMC, which are selected or deselected by the selection signals S1, S2, and S3, are output from the commonly connected output terminals of the transmission gates 234a, 234b, and 234c. The drive signal selection circuit 200 then supplies the signals from the output terminals of the transmission gates 234a, 234b, and 234c as the drive signals VOUT to the corresponding piezoelectric elements 60 included in the ejection unit 600.

[0120] The operation of the driving signal selection circuit 200 configured as described above will be described. Figure 7 This diagram illustrates the operation of the drive signal selection circuit 200. The print data signal SI serially includes two bits of print data [SIH, SIL] and is input to the drive signal selection circuit 200 in synchronization with the clock signal SCK. The two bits of print data [SIH, SIL] included in the print data signal SI are then sequentially transmitted to the subsequent shift register 212 in synchronization with the clock signal SCK. Subsequently, by stopping the input of the clock signal SCK, the two bits of print data [SIH, SIL] corresponding to each ejection unit 600 are retained in the shift register 212 corresponding to the same ejection unit 600.

[0121] Then, when the latch signal LAT rises, the latch circuit 214 latches the 2-bit print data [SIH, SIL] held by the shift register 212. Figure 7 , 2-bit print data [SIH, SIL] corresponding to the shift register 212 at the 1st, 2nd, . . . , nth stages latched by the latch circuit 214 are shown as LT1 , LT2 , . . . , LTn.

[0122] The 2-bit print data [SIH, SIL] latched by the latch circuit 214 is input to the decoder 216. The decoder 216 outputs selection signals S1, S2, and S3 of logic levels corresponding to the dot size specified by the input 2-bit print data [SIH, SIL].

[0123] Specifically, when the input 2-bit printing data [SIH, SIL] is [1, 1], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 to H, L, and L levels respectively within the period T and outputs them to the selection circuit 230. As a result, the selection circuit 230 selects the trapezoidal waveform Adp within the period T. As a result, the output from the drive signal selection circuit 200 is the same as the output of the signal S1, S2, and S3. Figure 7 The “large dot LD” shown corresponds to the driving signal VOUT.

[0124] In addition, when the input 2-bit printing data [SIH, SIL] is [1, 0], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 to L, H, and L levels respectively within the period T and outputs them to the selection circuit 230. As a result, the selection circuit 230 selects the trapezoidal waveform Bdp within the period T. As a result, the output from the drive signal selection circuit 200 is the same as the output from the drive signal selection circuit 200. Figure 7 The “small dot SD” shown corresponds to the driving signal VOUT.

[0125] In addition, when the input 2-bit printing data [SIH, SIL] is [0, 1], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 to L, L, and L levels respectively within the period T and outputs them to the selection circuit 230. As a result, the selection circuit 230 does not select any of the trapezoidal waveforms Adp, Bdp, and Cdp within the period T. As a result, the output from the drive signal selection circuit 200 is the same as the output of the drive signal selection circuit 200. Figure 7 The driving signal VOUT corresponding to “non-discharge ND” is shown.

[0126] Here, when the selection circuit 230 does not select any of the trapezoidal waveforms Adp, Bdp, and Cdp, the voltage Vc most recently supplied to the piezoelectric element 60 is held at one end of the corresponding piezoelectric element 60 by the capacitance component of the piezoelectric element 60. That is, the output of the constant drive signal VOUT at the voltage Vc from the drive signal selection circuit 200 includes the case where, when none of the trapezoidal waveforms Adp, Bdp, and Cdp is selected as the drive signal VOUT, the most recently held voltage Vc by the capacitance component of the piezoelectric element 60 is supplied to the piezoelectric element 60 as the drive signal VOUT.

[0127] In addition, when the input 2-bit printing data [SIH, SIL] is [0, 0], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 to L, L, and H levels respectively within the period T and outputs them to the selection circuit 230. As a result, the selection circuit 230 selects the trapezoidal waveform Cdp within the period T. As a result, the output from the drive signal selection circuit 200 is the same as the output of the drive signal selection circuit 200. Figure 7 The “micro-vibration BSD” shown corresponds to the driving signal VOUT.

[0128] As described above, the drive signal selection circuit 200 generates drive signals VOUT corresponding to each of the plurality of ejection units 600 by selecting or not selecting the drive signals COMA, COMB, and COMC based on the voltage signal VHV, the print data signal SI, the latch signal LAT, and the clock signal SCK, and outputs the generated drive signals VOUT to the corresponding ejection units 600. As a result, the amount of ink ejected from each of the plurality of ejection units 600 is individually controlled.

[0129] Furthermore, in the liquid ejection device 1 of this embodiment, when forming a large dot on medium P, the drive signal selection circuit 200 supplies the drive signal COMA output by the drive circuit 52a as the drive signal VOUT to the ejection unit 600. When forming a small dot on medium P, the drive signal selection circuit 200 supplies the drive signal COMB output by the drive circuit 52b as the drive signal VOUT to the ejection unit 600. In other words, the drive signal selection circuit 200 selects either drive signal COMA or COMB based on the dot size to be formed on medium P. Therefore, compared to a configuration in which a single drive signal includes multiple signal waveforms and these waveforms are selected in a time-sharing manner to determine the dot size to be formed on medium P, the waveform periods of the drive signals COMA and COMB can be shortened. Consequently, the liquid ejection device 1 can achieve a higher speed at which it can form a desired image on medium P.

[0130] Furthermore, in addition to the drive signals COMA and COMB, the liquid ejection device 1 of this embodiment includes a drive signal COMC for driving the piezoelectric element 60 so that ink is not ejected onto the medium P. This prevents a decrease in the image forming speed for forming the desired image on the medium P, and reduces the likelihood of ejection abnormalities caused by increased ink viscosity in the ejection unit 600. Specifically, in addition to the drive signals COMA and COMB, the liquid ejection device 1 of this embodiment includes a drive signal COMC, thereby increasing the image forming speed for forming the desired image on the medium P without degrading the quality of the image formed on the medium P and reducing the likelihood of a decrease in ink ejection accuracy.

[0131] Here, the drive signal VOUT supplied to the piezoelectric element 60 is generated by selecting the signal waveforms included in each of the drive signals COMA, COMB, and COMC. Specifically, when the drive signal selection circuit 200 selects the drive signal COMA, the drive signal COMA is supplied to the corresponding piezoelectric element 60 as the drive signal VOUT. When the drive signal selection circuit 200 selects the drive signal COMB, the drive signal COMB is supplied to the corresponding piezoelectric element 60 as the drive signal VOUT. When the drive signal selection circuit 200 selects the drive signal COMC, the drive signal COMC is supplied to the corresponding piezoelectric element 60 as the drive signal VOUT. Specifically, the drive circuit 52a outputs the drive signal COMA supplied to the piezoelectric element 60, the drive circuit 52b outputs the drive signal COMB supplied to the piezoelectric element 60, and the drive circuit 52c outputs the drive signal COMC supplied to the piezoelectric element 60.

[0132] 2.3 Configuration and Operation of the Driving Circuit

[0133] Next, the configuration and operation of the drive circuit 52 that generates and outputs the drive signal COM will be described. Figure 8 1 is a diagram showing an example of the configuration of the driving circuit 52. The driving circuit 52 includes an integrated circuit 500, an amplifier circuit 550, a demodulation circuit 560, and a feedback circuit 570.

[0134] The integrated circuit 500 includes an amplification control signal generating circuit 502, an internal voltage generating circuit 400, an oscillation circuit 410, a clock selection circuit 411, an abnormality detection circuit 430, a register control circuit 440, a drive signal discharge circuit 450, a reference voltage signal output circuit 460, a VHV control signal output circuit 470, a status signal input and output circuit 480, and an abnormality signal input and output circuit 490.

[0135] A voltage signal VDD is supplied to the internal voltage generating circuit 400. The internal voltage generating circuit 400 generates a voltage signal GVDD having a voltage value of, for example, DC 7.5V by boosting or stepping down the input voltage signal VDD. This voltage signal GVDD is input to various components of the integrated circuit 500, including the gate driver 540 (described later). It should be noted that the integrated circuit 500 may use the input voltage signal VDD as is, without boosting or stepping down the voltage.

[0136] The basic drive data signal dO is input to the amplifier control signal generation circuit 502 via the terminal dO_i. Based on the input basic drive data signal dO, the amplifier control signal generation circuit 502 generates the amplifier control signals Hgd and Lgd. The amplifier control signal generation circuit 502 includes a DAC interface (DAC_I / F: Digital to Analog Converter Interface) 510, a DAC unit 520, a modulation unit 530, and a gate driver unit 540.

[0137] The DAC interface 510 receives inputs of a basic drive data signal dO supplied via terminal dO_i and a clock signal MCK supplied via terminal MCK_i. The clock signal MCK may also be generated by an oscillator circuit (not shown) included in the drive unit 10 or the control unit 2. The DAC interface 510 accumulates the basic drive data signal dO based on the clock signal MCK and generates, for example, 10-bit drive waveform data dW that defines the waveform of the drive signal COM. The drive waveform data dW is input to the DAC unit 520. The DAC unit 520 converts the input drive waveform data dW into an analog drive waveform signal aW. This drive waveform signal aW is the target signal before amplification of the drive signal COM. The drive waveform signal aW is input to the modulator 530. The modulator 530 generates and outputs a modulated signal Ms by pulse-width modulating the drive waveform signal aW. In other words, the modulator 530 outputs the modulated signal Ms obtained by modulating the drive waveform signal aW. The gate driver 540 receives inputs of the voltage signals VHV and GVDD, and the modulation signal Ms. The gate driver 540 amplifies the input modulation signal Ms based on the voltage signal GVDD, and generates an amplified control signal Hgd that is level-shifted to high-amplitude logic based on the voltage signal VHV, and an amplified control signal Lgd that is the result of inverting the logic level of the input modulation signal Ms and amplifying it based on the voltage signal GVDD. Specifically, the logic levels of the amplified control signal Hgd and the amplified control signal Lgd are exclusively H levels.

[0138] Here, "the logic level exclusively becomes H level" means that the logic level of the amplification control signal Hgd and the logic level of the amplification control signal Lgd do not become H level at the same time, and excludes the case where the logic level of the amplification control signal Hgd and the logic level of the amplification control signal Lgd simultaneously become L level. Therefore, the gate driver 540 may include a timing control circuit or the like that controls the timing so that the logic level of the amplification control signal Hgd and the logic level of the amplification control signal Lgd do not become H level at the same time.

[0139] Amplification control signal Hgd is output from integrated circuit 500 via terminal Hg_o and input to amplifier circuit 550. Amplification control signal Lgd is output from integrated circuit 500 via terminal Lg_o and input to amplifier circuit 550. Here, amplification control signal Hgd is a signal obtained by level-shifting the logic level of modulation signal Ms, while amplification control signal Lgd is a signal obtained by inverting the logic level of modulation signal Ms. Therefore, amplification control signal Hgd and amplification control signal Lgd can also be broadly considered as modulation signals generated by modulation section 530.

[0140] The amplifier circuit 550 operates based on the amplification control signals Hgd and Lgd to output the amplified modulation signal AMs. In other words, the amplifier circuit 550 amplifies the modulation signal Ms and outputs the amplified modulation signal AMs.

[0141] Specifically, amplifier circuit 550 includes transistors 551 and 552. Transistors 551 and 552 are each, for example, N-channel FETs (Field Effect Transistors). A voltage signal VHV is supplied to the drain terminal of transistor 551. An amplification control signal Hgd is supplied to the gate terminal of transistor 551 via terminal Hg_o. The source terminal of transistor 551 is electrically connected to the drain terminal of transistor 552. In addition, an amplification control signal Lgd is supplied to the gate terminal of transistor 552 via terminal Lg_o. A ground signal is supplied to the source terminal of transistor 552. In amplifier circuit 550 configured as described above, transistor 551 operates in response to amplification control signal Hgd, and transistor 552 operates in response to amplification control signal Lgd. At this time, transistors 551 and 552 are exclusively turned on. Furthermore, transistors 551 and 552 are driven to generate an amplified modulation signal AMs at a connection point connecting the source terminal of transistor 551 and the drain terminal of transistor 552. The modulation signal Ms is amplified based on the voltage signal VHV. The amplifier circuit 550 outputs the amplified modulation signal AMs generated at this connection point.

[0142] The amplified modulation signal AMs output by the amplifier circuit 550 is input to the demodulation circuit 560. The demodulation circuit 560 includes a coil 561 and a capacitor 562. One end of the coil 561 is electrically connected to the source terminal of the transistor 551 and the drain terminal of the transistor 552. The other end of the coil 561 is electrically connected to one end of the capacitor 562. A ground signal is supplied to the other end of the capacitor 562. That is, the coil 561 and the capacitor 562 constitute a low-pass filter. The demodulation circuit 560 generates a drive signal COM by smoothing and demodulating the supplied amplified modulation signal AMs using the low-pass filter. The drive signal COM generated by the demodulation circuit 560 is output from the drive circuit 52 through the terminal COM-Out. That is, the amplifier circuit 550 and the demodulation circuit 560 operate under the control of the integrated circuit 500, thereby outputting a drive signal COM corresponding to the voltage signal VHV.

[0143] In addition, the drive signal COM output by the demodulation circuit 560 is fed back to the modulation unit 530 through the feedback circuit 570. The feedback circuit 570 includes resistors 571 and 572. One end of the resistor 571 is electrically connected to the other end of the coil 561, and the other end of the resistor 571 is electrically connected to one end of the resistor 572. The voltage signal VHV is supplied to the other end of the resistor 572. In addition, the other end of the resistor 571 and one end of the resistor 572 are electrically connected to the modulation unit 530 through the terminal Com-Dis. That is, the signal based on the drive signal COM is fed back to the modulation unit 530. As a result, the waveform accuracy of the signal waveform of the drive signal COM output by the demodulation circuit 560 is improved. It should be noted that in addition to the structure composed of the above-mentioned resistor 571 and resistor 572, the feedback circuit 570 can also have a feedback path that extracts a specific frequency component from the drive signal COM and feeds the extracted signal back to the modulation unit 530.

[0144] As described above, the amplification control signal generating circuit 502, the amplification circuit 550, the demodulation circuit 560, and the feedback circuit 570 generate and output the driving signal COM for driving the piezoelectric element 60 based on the basic driving data signal dO. In the following description, the amplification control signal generating circuit 502, the amplification circuit 550, the demodulation circuit 560, and the feedback circuit 570 that output the driving signal COM for driving the piezoelectric element 60 based on the basic driving data signal dO are sometimes referred to as the driving signal generating circuit 501. In addition, the driving signal COM generated by the driving signal generating circuit 501 is supplied to the piezoelectric element 60 through the terminal COM-Out. The driving signal generating circuit 501 configured as above can output the driving signal COM as shown in FIG. Figure 3 In addition to the driving signal COM having a varying voltage value such as the trapezoidal waveforms Adp, Bdp, and Cdp shown, a signal having a constant voltage value can also be output when a basic driving data signal dO corresponding to a constant voltage value is supplied.

[0145] Specifically, the driver circuit 52 includes an amplifier circuit 550 and a demodulator circuit 560, which are supplied with a voltage signal VHV and output a drive signal COM corresponding to the voltage signal VHV; and an integrated circuit 500, which is supplied with a voltage signal VDD and controls the driving of the amplifier circuit 550 based on the voltage signal VDD. Furthermore, the driver circuit 52 amplifies a drive waveform signal aW corresponding to the drive data signal d0, which serves as a basis for the drive signal COM, based on the voltage signal VHV, and thereby outputs the drive signal COM.

[0146] The oscillation circuit 410 generates and outputs a clock signal LCK that defines the operation timing of the integrated circuit 500. The clock signal LCK is input to the clock selection circuit 411 and the abnormality detection circuit 430.

[0147] Clock signals MCK and LCK, as well as a clock selection signal CSW, are input to the clock selection circuit 411. Based on the logic level of the clock selection signal CSW, the clock selection circuit 411 switches between outputting the clock signal MCK as the clock signal RCK to the register control circuit 440 or outputting the clock signal LCK as the clock signal RCK to the register control circuit 440. For example, when the input clock selection signal CSW is at an H level, the clock selection circuit 411 outputs the clock signal MCK as the clock signal RCK to the register control circuit 440. On the other hand, when the input clock selection signal CSW is at an L level, the clock selection circuit 411 outputs the clock signal LCK as the clock signal RCK to the register control circuit 440.

[0148] The abnormality detection circuit 430 includes an oscillation abnormality detection unit 431 , an operation abnormality detection unit 432 , and a power supply voltage abnormality detection unit 433 .

[0149] The clock signal LCK output by the oscillation circuit 410 is input to the oscillation abnormality detection unit 431. The oscillation abnormality detection unit 431 obtains the frequency, voltage value, and other information of the input clock signal LCK, and detects whether the clock signal LCK is normal based on the obtained information. Then, if the oscillation abnormality detection unit 431 detects that the input clock signal LCK is abnormal, it generates a clock selection signal CSW indicating the abnormality and outputs the generated clock selection signal CSW to the clock selection circuit 411. It also generates an error signal NES indicating the abnormality and outputs the generated error signal NES to the register control circuit 440. If no abnormality is detected in the input clock signal LCK, it generates a clock selection signal CSW indicating that the clock is normal and outputs the generated clock selection signal CSW to the clock selection circuit 411. It also generates an error signal NES indicating that the clock is normal and outputs the generated error signal NES to the register control circuit 440.

[0150] The abnormal operation detection unit 432 receives an operation status signal ASS indicating the operation status of various components included in the drive circuit 52. Based on the input operation status signal ASS, the abnormal operation detection unit 432 detects whether the various components of the drive circuit 52 are operating normally. If the abnormal operation detection unit 432 receives an operation status signal ASS indicating that an abnormality has occurred in any of the various components of the drive circuit 52, it generates an error signal NES indicating the abnormality and outputs the generated error signal NES to the register control circuit 440.

[0151] The voltage signal VHV is input to the power supply voltage abnormality detection unit 433. The power supply voltage abnormality detection unit 433 detects whether the voltage value of the input voltage signal VHV is normal. If the voltage value of the detected voltage signal VHV is abnormal, the power supply voltage abnormality detection unit 433 generates an error signal FES indicating the abnormality and outputs the generated error signal FES to the register control circuit 440.

[0152] Register control circuit 440 includes a sequence register 441, a status register 442, and a register control unit 443. Sequence register 441 and status register 442 store operational information, etc., input as a base drive data signal d0 in synchronization with clock signal MCK. Register control unit 443 generates control signals CNT1 through CNT5 based on the information stored in sequence register 441 and status register 442 in synchronization with clock signal RCK. Register control circuit 440 then outputs control signals CNT1 through CNT5 generated by register control unit 443 to the corresponding components.

[0153] The control signal CNT1 output by the register control circuit 440 is input to the drive signal discharge circuit 450. The drive signal discharge circuit 450 is electrically connected to the terminal COM-Out via the terminal Com-Dis and the feedback circuit 570. The drive signal discharge circuit 450 controls the discharge of residual charge accumulated in the propagation path of the drive signal COM.

[0154] Figure 9 This diagram illustrates an example of the configuration of a drive signal discharge circuit 450. Drive signal discharge circuit 450 includes a resistor 451, a transistor 452, and an inverter 453. It should be noted that transistor 452 is illustrated as an NMOS transistor. One end of resistor 451 is electrically connected to terminal Com-Dis. The other end of resistor 451 is electrically connected to the drain terminal of transistor 452. A ground signal is supplied to the source terminal of transistor 452. A control signal CNT1 is input to the gate terminal of transistor 452 via inverter 453. Drive signal discharge circuit 450 configured as described above, when input with an L-level control signal CNT1, discharges residual charge accumulated in the propagation path of drive signal COM. Specifically, when an L-level control signal CNT1 is input to drive signal discharge circuit 450, transistor 452 is controlled to be on. Consequently, terminal Com-Out is electrically connected to the propagation path for the ground signal via resistor 571, terminal Com-Dis, resistor 451, and transistor 542. As a result, the residual charge accumulated in the propagation path of the drive signal COM including the terminal COM-Out is discharged.

[0155] The control signal CNT2 output by the register control circuit 440 is input to the reference voltage signal output circuit 460. The reference voltage signal output circuit 460 is electrically connected to the piezoelectric element 60 via the terminal VBS_o and the terminal VBS-Out. The reference voltage signal output circuit 460 generates and outputs a reference voltage signal VBS to be supplied to the piezoelectric element 60 based on the control signal CNT2.

[0156] Figure 10 This diagram shows an example of the configuration of a reference voltage signal output circuit 460. Reference voltage signal output circuit 460 includes a comparator 461, transistors 462 and 463, resistors 464, 465, and 466, and an inverter 467. It should be noted that transistor 462 is illustrated as a PMOS transistor, and transistor 463 is illustrated as an NMOS transistor. A reference voltage Vref is supplied to the negative input terminal of comparator 461. For example, the bandgap reference voltage of integrated circuit 500 can be used as reference voltage Vref. The positive input terminal of comparator 461 is electrically connected to one end of resistor 464 and one end of resistor 465. The output terminal of comparator 461 is electrically connected to the gate terminal of transistor 462. A voltage signal GVDD is supplied to the source terminal of transistor 462. The drain terminal of transistor 462 is electrically connected to the other end of resistor 464, one end of resistor 466, and terminal VBS_o for outputting a reference voltage signal VBS. The other end of the resistor 466 is electrically connected to the drain terminal of the transistor 463. The control signal CNT2 is input to the gate terminal of the transistor 463 via the inverter 467. A ground signal is supplied to the source terminal of the transistor 463 and the other end of the resistor 465.

[0157] In the reference voltage signal output circuit 460 configured as described above, when the voltage value supplied to the +-side input terminal of comparator 461 is greater than the voltage value of the reference voltage Vref supplied to the --side input terminal of comparator 461, comparator 461 outputs an H-level signal. Consequently, transistor 462 is controlled to be OFF, and no voltage signal GVDD is supplied to terminal VBS_o. On the other hand, when the voltage value supplied to the +-side input terminal of comparator 461 is less than the voltage value of the reference voltage Vref supplied to the --side input terminal of comparator 461, comparator 461 outputs an L-level signal. Consequently, transistor 462 is controlled to be ON, and the voltage signal GVDD is supplied to terminal VBS_o. That is, in the reference voltage signal output circuit 460, comparator 461 controls the conduction state of transistor 462 so that the voltage value obtained by dividing the voltage value of terminal VBS_o by resistors 464 and 465 is equal to the voltage value of the reference voltage Vref. Thus, the reference voltage signal output circuit 460 generates a signal with a constant voltage value based on the voltage signal GVDD. The constant voltage signal generated by the reference voltage signal output circuit 460 is output as the reference voltage signal VBS. The reference voltage signal VBS output by the reference voltage signal output circuit 460 is then supplied to the piezoelectric element 60 via the terminal VBS_o and the terminal VBS-Out.

[0158] In addition, a control signal CNT2 is input to the reference voltage signal output circuit 460. When the control signal CNT2 at an H level is input to the reference voltage signal output circuit 460, the transistor 463 is controlled to be turned off. As a result, the impedance between the terminal VBS_o and the propagation path for transmitting the ground signal is controlled to be high. Therefore, the reference voltage signal VBS generated by the reference voltage signal output circuit 460 is output through the terminal VBS_o. On the other hand, when the control signal CNT2 at an L level is input to the reference voltage signal output circuit 460, the transistor 463 is controlled to be turned on. As a result, the terminal VBS_o is electrically connected to the propagation path for transmitting the ground signal via the resistor 576 and the transistor 463. Therefore, the reference voltage signal VBS generated by the reference voltage signal output circuit 460 is not output, and the potential of the terminal VBS_o becomes the ground signal. That is, when the L-level control signal CNT2 is input to the reference voltage signal output circuit 460 , the reference voltage signal output circuit 460 stops outputting the reference voltage signal VBS to the piezoelectric element 60 and discharges the charge accumulated in the terminal VBS_o.

[0159] The control signal CNT3 output by the register control circuit 440 is input to the VHV control signal output circuit 470. The VHV control signal output circuit 470 is electrically connected to the step-down circuit 130 via the terminal VHVc_o and the terminal VHVc-Out. The VHV control signal output circuit 470 controls the operation of the step-down circuit 130 by outputting a step-down control signal VHVc to the step-down circuit 130, the logic level of which changes according to the control signal CNT3.

[0160] Figure 11 4 is a diagram showing an example of the structure of the VHV control signal output circuit 470. The VHV control signal output circuit 470 includes a transistor 471 and a resistor 472. It should be noted that the transistor 471 is described as a PMOS transistor. The voltage signal GVDD is supplied to the source terminal of the transistor 471. The drain terminal of the transistor 471 is electrically connected to one end of the resistor 472 and the terminal VHVc_o. The control signal CNT3 is input to the gate terminal of the transistor 471. The ground signal is supplied to the other end of the resistor 472. When the low-level control signal CNT3 is input to the VHV control signal output circuit 470 constructed as described above, the VHV control signal output circuit 470 supplies the voltage signal GVDD to the terminal VHVc_o. In other words, the VHV control signal output circuit 470 outputs a step-down control signal VHVc of the voltage signal GVDD. Furthermore, when the control signal CNT3 at an H level is input to the VHV control signal output circuit 470, the VHV control signal output circuit 470 supplies a ground signal to the terminal VHVc_o. In other words, the VHV control signal output circuit 470 outputs the step-down control signal VHVc, which is a ground signal. Specifically, the VHV control signal output circuit 470 generates the step-down control signal VHVc, whose H level corresponds to the voltage value of the voltage signal GVDD and whose L level corresponds to a ground signal, based on the logic level of the control signal CNT3, and outputs the step-down control signal VHVc to the step-down circuit 130.

[0161] The control signal CNT4 output by the register control circuit 440 is input to the status signal input / output circuit 480. The status signal input / output circuit 480 is electrically connected to other components via the terminal BUSY_io. This status signal input / output circuit 480 outputs a status signal BUSY, whose logic level changes according to the control signal CNT4, to notify other components of the operating status of the drive circuit 52 and to receive the status signal BUSY output by the other components. Here, the other components may be, for example, any of the drive signal output circuits 50-1 to 52-6 included in the liquid ejection device 1, or the control circuit 100.

[0162] Figure 12: is a diagram showing the structure of the status signal input and output circuit 480. The status signal input and output circuit 480 includes a transistor 481, an inverter 482 and a resistor 483. It should be noted that the transistor 481 is described as a PMOS transistor. In addition, the inverter 482 functions as a COMS input terminal of the integrated circuit 500. That is, the status signal input and output circuit 480 generates a status signal BUSY based on the control signal CNT4 output from the register control circuit 440, and outputs the status signal BUSY to other structures through the terminal BUSY_io, and outputs the signal input through the terminal BUSY_io to the register control circuit 440. It should be noted that in Figure 12 In FIG. 4 , the control signal CNT4 output from the register control circuit 440 is shown as a control signal CNT4 -out, and the control signal CNT4 output to the register control circuit 440 is shown as a control signal CNT4 -in.

[0163] The source terminal of transistor 481 is supplied with a voltage signal GVDD. The drain terminal of transistor 481 is electrically connected to the input terminal of inverter 482, one end of resistor 483, and terminal BUSY_io. The gate terminal of transistor 481 receives a control signal CNT4-out output by register control circuit 440. The output terminal of inverter 482 outputs a control signal CNT4-in to register control circuit 440. A ground signal is supplied to the other end of resistor 483. When the state signal I / O circuit 480 configured as described above receives an L-level control signal CNT4, the state signal I / O circuit 480 supplies the voltage signal GVDD to terminal BUSY_io. In other words, the state signal I / O circuit 480 outputs the state signal BUSY, which is a voltage signal GVDD. On the other hand, when the state signal I / O circuit 480 receives an H-level control signal CNT4, the state signal I / O circuit 480 supplies a ground signal to terminal BUSY_io. In other words, the state signal I / O circuit 480 outputs the state signal BUSY, which is a ground signal. That is, the state signal input / output circuit 480 generates the state signal BUSY having an H level equal to the voltage value of the voltage signal GVDD and an L level equal to the ground signal according to the logic level of the control signal CNT4 , and outputs the state signal BUSY to other components.

[0164] Control signal CNT5 output by register control circuit 440 is input to abnormal signal input / output circuit 490. Abnormal signal input / output circuit 490 is electrically connected to other components via terminal ERR-io. Abnormal signal input / output circuit 490 outputs abnormal signal ERR, whose logic level changes according to control signal CNT5, to notify other components of whether an abnormality has occurred in drive circuit 52, and to receive abnormal signal ERR output from other components. Here, other components may be, for example, any of drive signal output circuits 50-1 to 50-6 included in liquid ejection device 1, or control circuit 100.

[0165] Figure 13 4 is a diagram showing the structure of the abnormal signal input and output circuit 490. The abnormal signal input and output circuit 490 includes a transistor 491, an inverter 492 and a resistor 493. It should be noted that in the following description, the transistor 491 is described as a PMOS transistor. In addition, the inverter 492 functions as a COMS input terminal of the integrated circuit 500. That is, the abnormal signal input and output circuit 490 produces an abnormal signal ERR based on the control signal CNT5 output from the register control circuit 440, and outputs the abnormal signal ERR through the terminal ERR-io, and outputs the signal input through the terminal ERR-io to the register control circuit 440. It should be noted that in Figure 13 In FIG. 4 , the control signal CNT5 output from the register control circuit 440 is shown as a control signal CNT5 -out, and the control signal CNT5 output to the register control circuit 440 is shown as a control signal CNT5 -in.

[0166] The source terminal of transistor 491 is supplied with a voltage signal GVDD. The drain terminal of transistor 491 is electrically connected to the input terminal of inverter 492, one end of resistor 493, and terminal ERR-io. The gate terminal of transistor 491 receives a control signal CNT5-out output by register control circuit 440. The output terminal of inverter 492 outputs a control signal CNT5-in to register control circuit 440. A ground signal is supplied to the other end of resistor 493. When an L-level control signal CNT5 is input to abnormal signal input / output circuit 490 configured as described above, abnormal signal input / output circuit 490 supplies voltage signal GVDD to terminal ERR-io. In other words, abnormal signal input / output circuit 490 outputs abnormal signal ERR, which is a voltage signal GVDD. On the other hand, when an H-level control signal CNT5 is input to abnormal signal input / output circuit 490, abnormal signal input / output circuit 490 supplies a ground signal to terminal ERR-io. In other words, abnormal signal input / output circuit 490 outputs abnormal signal ERR, which is a ground signal. That is, the abnormal signal input / output circuit 490 generates the abnormal signal ERR having an H level equal to the voltage value of the voltage signal GVDD and an L level equal to the ground signal according to the logic level of the control signal CNT5 , and outputs the abnormal signal ERR to other components.

[0167] As described above, the driving unit 10 of the present embodiment includes the driving circuit 52 that outputs the driving signal COM and the reference voltage signal output circuit 460 that outputs the reference voltage signal VBS. Specifically, the driving circuit 52 of this embodiment has: a driving signal generating circuit 501, which generates a driving signal COM for driving the piezoelectric element 60 based on the basic driving data signal dO; a driving signal discharging circuit 450, which releases the residual charge remaining in the propagation path of the driving signal COM; a reference voltage signal output circuit 460, which outputs the reference voltage signal VBS and releases the residual charge remaining in the propagation path of the reference voltage signal VBS; a VHV control signal output circuit 470, which controls the operation of the step-down circuit 130; a status signal input and output circuit 480 and an abnormal signal input and output circuit 490, which mutually transmit the status and the presence or absence of abnormalities between the status signal input and output circuit 480 and the abnormal signal input and output circuit 490 and other components; and a register control circuit 440, which controls the operation of the driving signal discharging circuit 450, the reference voltage signal output circuit 460, the VHV control signal output circuit 470, the status signal input and output circuit 480 and the abnormal signal input and output circuit 490 by switching the logic levels of the control signals CN1~CN5.

[0168] Furthermore, in the drive circuit 52 of this embodiment, the register control circuit 440 uses control signals CNT1 to CN3 to control the operation of the drive signal discharge circuit 450, the reference voltage signal output circuit 460, and the VHV control signal output circuit 470, thereby enabling control of the supply of the voltage signal VHV, the drive signal COM, and the reference voltage signal VBS to the print head 23 without passing through the control circuit 100. This reduces the processing burden on the control circuit 100, and since control is not performed through the control circuit 100, the supply of the voltage signal VHV, the drive signal COM, and the reference voltage signal VBS to the print head 23 can be controlled at appropriate timing and in a short time.

[0169] For example, when the liquid ejection device 1 is in a standby mode or sleep mode, in which it stops operating without ejecting ink onto the medium P, the register control circuit 440 controls the logic levels of the control signals CNT1-CNT3 so that: the drive signal discharge circuit 450 discharges residual charge accumulated in the propagation path of the drive signal COM, including the terminal COM-Out; the reference voltage signal output circuit 460 stops outputting the reference voltage signal VBS to the piezoelectric element 60 and discharges the charge accumulated at the terminal VBS_o; and the VHV control signal output circuit 470 stops outputting the voltage signal VHV from the step-down circuit 130. This discharges the charge across the piezoelectric element 60 of the print head 23. Therefore, even if the liquid ejection device 1 remains in a standby mode or sleep mode for an extended period of time, the likelihood of an unintended voltage being applied to the piezoelectric element 60 of the print head 23 or of an unintended displacement being continuously applied to the piezoelectric element 60 of the print head 23 is reduced. As a result, the possibility of changes in the driving characteristics of the piezoelectric element 60 is reduced, the possibility of a decrease in the ejection accuracy of the ink ejected by the drive of the piezoelectric element 60 is reduced, and the possibility of abnormalities occurring in the piezoelectric element 60 due to unexpected displacement applied to the piezoelectric element 60 is also reduced.

[0170] Furthermore, when the operating mode of the liquid ejection device 1 shifts from the aforementioned standby mode or sleep mode to the drive mode for ejecting ink onto the medium P, the register control circuit 440 sequentially switches the logic levels of the control signals CNT1 to CNT3 according to a predetermined operating sequence. This allows for smooth transitions between operating modes of the liquid ejection device 1 and reduces the likelihood of unintended voltage being applied to the piezoelectric element 60 of the print head 23 even during the operating mode transition.

[0171] Furthermore, in the drive circuit 52 of this embodiment, the register control circuit 440 controls the operation of the status signal input / output circuit 480 and the abnormality signal input / output circuit 490 using control signals CNT4 to CN5. This allows the multiple drive circuits 52 included in the liquid ejection device 1 and the head unit 5 to share information about their operating status and the presence or absence of abnormalities. Thus, in the drive circuit 52 of this embodiment, when the liquid ejection device 1 and the head unit 5 include multiple drive circuits 52, if an abnormality occurs in any of the multiple drive circuits 52, information about the abnormality can be obtained without going through the control circuit 100. Consequently, in the drive circuit 52 of this embodiment, it is possible to execute a stop process for the drive circuit 52 at an appropriate timing and in a short period of time.

[0172] 2.4 Composition and Operation of Buck Circuit

[0173] Next, the configuration and operation of the step-down circuit 130 will be described. Figure 14 1 is a diagram showing an example of the configuration of the step-down circuit 130. Figure 14 As shown, the step-down circuit 130 includes a VHV supply switching circuit 140 , a first step-down circuit 150 a , and a second step-down circuit 150 b .

[0174] The VHV supply switching circuit 140 receives inputs from the step-down control signals VHVc1 to VHVc6 output by the drive signal output circuits 50-1 to 50-6, respectively. If the step-down control signals VHVc1 to VHVc6 received from the drive signal output circuits 50-1 to 50-6 each include information requesting output of the voltage signal VHV, the VHV supply switching circuit 140 outputs an enable signal ENvh that activates the output voltage signal VHV. If at least one of the step-down control signals VHVc1 to VHVc6 received from the drive signal output circuits 50-1 to 50-6 does not include information requesting output of the voltage signal VHV, the VHV supply switching circuit 140 outputs an enable signal ENvh that does not activate the output voltage signal VHV. Such a VHV supply switching circuit 140 can be implemented by combining logic circuits such as an AND circuit or an OR circuit.

[0175] The first step-down circuit 150a receives inputs of the voltage signal VDC output by the control unit 2 and the enable signal ENvh output by the VHV supply switching circuit 140. When the enable signal ENvh, which activates the output voltage signal VHV, is input, the first step-down circuit 150a generates the voltage signal VHV by stepping down the voltage value of the voltage signal VDC. However, when the enable signal ENvh, which deactivates the output voltage signal VHV, is input, the first step-down circuit 150a stops generating the voltage signal VHV. Specifically, the integrated circuit 500 included in the driver circuit 52 controls whether the voltage signal VHV is output from the first step-down circuit 150a by outputting the step-down control signal VHVc.

[0176] The second step-down circuit 150b receives inputs of the voltage signal VDC and the enable signal ENvd output by the control unit 2. The enable signal ENvd switches whether the voltage signal VDD output from the second step-down circuit 150b is asserted. For example, the enable signal ENvd is input from the control unit 2. Furthermore, when the enable signal ENvd is input, which asserts the output voltage signal VDD, the second step-down circuit 150b generates the voltage signal VDD by stepping down the voltage value of the voltage signal VDC. When the enable signal ENvd is input, which deasserts the output voltage signal VDD, the second step-down circuit 150b stops generating the voltage signal VDD.

[0177] That is, the step-down circuit 130 included in the driving unit 10 includes a first step-down circuit 150 a that steps down the voltage signal VDC and outputs the voltage signal VHV, and a second step-down circuit 150 b that steps down the voltage signal VDC and outputs the voltage signal VDD.

[0178] As described above, the voltage signal VHV is used as a power supply voltage for amplification when the drive circuit 52 generates the drive signal COM, and is used to level-shift the selection signals S1, S2, and S3 output by the decoder 216 of the drive signal selection circuit 200 to a high-amplitude logic voltage. Specifically, the voltage signal VHV is primarily used when the operation mode of the liquid ejection device 1 is a drive mode for ejecting ink onto the medium P, i.e., when the piezoelectric element 60 is driven. Whether the first step-down circuit 150a outputs this voltage signal VHV is controlled by the enable signal ENvh corresponding to the step-down control signals VHVc1 to VHVc6 output by the drive signal output circuits 50-1 to 50-6, respectively. The first step-down circuit 150a can output the voltage signal VHV only when the voltage signal VHV is in use, for example, when the operation mode of the liquid ejection device 1 is the drive mode. This reduces the power consumed by generating the voltage signal VHV, reduces the likelihood of unintended voltage being applied to the piezoelectric element 60 due to leakage current, etc., which may be generated by the propagation of the voltage signal VHV, and reduces the likelihood of unintended displacement being continuously applied to the piezoelectric element 60 included in the print head 23. As a result, the likelihood of changes in the driving characteristics of the piezoelectric element 60 is reduced, reducing the likelihood of a decrease in the ejection accuracy of ink ejected by driving the piezoelectric element 60. Furthermore, the likelihood of abnormalities occurring in the piezoelectric element 60 due to unintended displacement applied to the piezoelectric element 60 is reduced.

[0179] On the other hand, voltage signal VDD, a DC voltage signal with a lower voltage value than voltage signal VHV, is primarily used as a power supply voltage for the control circuit 100, the integrated circuit 500 included in the driver circuit 52, the drive signal selection circuit 200, and the like. Such control circuit 100, integrated circuit 500, and drive signal selection circuit 200 need to operate independently of the operating mode of the liquid ejection device 1. Therefore, the second step-down circuit 150b outputs voltage signal VDD regardless of the operating mode of the liquid ejection device 1. In the step-down circuit 130 of this embodiment, an enable signal ENvd, independent of the enable signal ENvh, is input to the second step-down circuit 150b. This allows the second step-down circuit 150b to continuously output voltage signal VDD regardless of the operating status of the first step-down circuit 150a. It should be noted that the enable signal ENvd input to the second step-down circuit 150b is not limited to being input from the control unit 2. For example, it may also be a signal fixed to a predetermined logic level in the second step-down circuit 150b that sets the output voltage signal VDD to active.

[0180] Here, an example of the configuration of the first step-down circuit 150a and the second step-down circuit 150b is described. The first step-down circuit 150a and the second step-down circuit 150b have the same configuration, differing only in the voltage values ​​of the output signals. Therefore, in the following description, only the example of the configuration of the first step-down circuit 150a is described, and the description of the example of the configuration of the second step-down circuit 150b is simplified or omitted.

[0181] Figure 15 1 is a diagram showing an example of the configuration of the first step-down circuit 150a. Figure 15 A step-down switching regulator is illustrated as an example of the first step-down circuit 150a. Figure 15 As shown, the first step-down circuit 150a includes an integrated circuit 160a, a coil 152a, capacitors 153a and 156a, and resistors 154a and 155a.

[0182] Integrated circuit 160a has terminals tvdd, tvbt, tvsw, tvfb, tvss, tgnd, and ten that are electrically connected to the various circuits included in the first step-down circuit 150a. Integrated circuit 160a operates using a voltage signal VDC input through terminal tvdd as driving power. Furthermore, an enable signal ENvh is input to integrated circuit 160a through terminal ten, enabling operation of the first step-down circuit 150a. Integrated circuit 160a generates a switching signal VSW and outputs it through terminal tvsw. Integrated circuit 160a also includes a driver circuit 161, a switch circuit 164, and a transistor 167.

[0183] The excitation circuit 161 includes an excitation control circuit 162 and a level shift circuit 163. An enable signal ENvh and a feedback voltage signal VFB are input to the excitation control circuit 162. During the period in which the enable signal ENvh that sets the output voltage signal VHV to be valid is input, the excitation control circuit 162 outputs a basic excitation signal BDS with a logic level inversion according to the voltage value of the input feedback voltage signal VFB. The basic excitation signal BDS output by the excitation control circuit 162 is input to the level shift circuit 163. The startup voltage signal VBT and the switching signal VSW are input to the level shift circuit 163. The level shift circuit 163 shifts the H-level voltage value of the input basic excitation signal BDS to the voltage value of the startup voltage signal VBT, and generates and outputs an excitation signal HDRV obtained by shifting the L-level voltage value of the input basic excitation signal BDS to the voltage value of the switching signal VSW. Furthermore, the driver control circuit 162 outputs the driver signal LDRV whose logic level is inverted according to the voltage value of the input feedback voltage signal VFB during a period in which the enable signal ENvh for activating the output voltage signal VHV is input.

[0184] The excitation signal HDRV and the excitation signal LDRV output by the excitation circuit 161 are input to the switching circuit 164. The switching circuit 164 includes transistors 165 and 166, which are n-channel FETs (Field Effect Transistors). The excitation signal HDRV output by the excitation circuit 161 is supplied to the gate terminal of the transistor 165. The drain terminal of the transistor 165 is electrically connected to the terminal tvdd, and the source terminal thereof is electrically connected to the terminal tvsw. In addition, the excitation signal LDRV output by the excitation circuit 161 is supplied to the gate terminal of the transistor 166. The drain terminal of the transistor 165 is electrically connected to the terminal tvsw, and the source terminal thereof is electrically connected to the terminal tvss. In addition, a ground signal is supplied to the terminal tvss.

[0185] As described above, the source terminal of transistor 165 and the drain terminal of transistor 166 are connected to each other, and the connection point between the source terminal of transistor 165 and the drain terminal of transistor 166 is electrically connected to terminal tvsw of integrated circuit 160a. Furthermore, when an H-level drive signal HDRV is supplied to switch circuit 164, conduction occurs between the drain terminal and the source terminal of transistor 165. When an H-level drive signal LDRV is supplied to switch circuit 164, conduction occurs between the drain terminal and the source terminal of transistor 166. Therefore, when an H-level drive signal HDRV is supplied to switch circuit 164, switch circuit 164 outputs voltage signal VDC as switching signal VSW from terminal tvsw. However, when an H-level drive signal LDRV is supplied to switch circuit 164, switching signal VSW, which is a ground signal, is output from terminal tvsw.

[0186] That is, by controlling the conduction states of transistors 165 and 166 based on the excitation signals HDRV and LDRV outputted from the excitation circuit 161, the switch circuit 164 outputs a switching signal VSW from the terminal tvsw, which is a connection point between the source terminal of transistor 165 and the drain terminal of transistor 166. In the following description, a state in which the drain and source terminals of transistors 165 and 166 are controlled to be conductive is sometimes referred to as "on," and a state in which the drain and source terminals of transistors 165 and 166 are controlled to be non-conductive is sometimes referred to as "off."

[0187] In addition, the excitation control circuit 162 outputs a boost control signal BC with an inverted logic level at a timing synchronized with at least one of the base excitation signal BDS and the excitation signal LDRV. The boost control signal BC is supplied to the gate terminal of transistor 167. Transistor 167 is a p-channel FET, with its source terminal electrically connected to terminal tvdd and its drain terminal electrically connected to terminal tvbt. When the gate terminal of transistor 167 is supplied with the boost control signal BC at an L level, the source and drain terminals of transistor 167 are conductive; however, when the gate terminal is supplied with the boost control signal BC at an H level, the source and drain terminals of transistor 167 become non-conductive. Therefore, when the gate terminal of transistor 167 is supplied with the boost control signal BC at an L level, transistor 167 supplies the voltage signal VDC to terminal tvbt; however, when the gate terminal of transistor 167 is supplied with the boost control signal BC at an H level, the supply of the voltage signal VDC to terminal tvbt is stopped. Here, in the following description, a state in which the source terminal and the drain terminal of the transistor 167 are controlled to be conductive is sometimes referred to as "on", and a state in which the drain terminal and the source terminal of the transistor 167 are controlled to be non-conductive is sometimes referred to as "off".

[0188] One end of coil 152a is electrically connected to terminal tvsw, and the other end is electrically connected to one end of capacitor 153a. A ground signal is also supplied to the other end of capacitor 153a. In other words, coil 152a and capacitor 153a form a low-pass filter circuit. The switching signal VSW output via terminal tvsw of integrated circuit 160a is smoothed by the low-pass filter circuit formed by coil 152a and capacitor 153a. The first step-down circuit 150a outputs the smoothed signal from this low-pass filter circuit as a voltage signal VHV.

[0189] One end of resistor 154a is electrically connected to the other end of coil 152a, and the other end is electrically connected to one end of resistor 155a. A ground signal is supplied to the other end of resistor 155a. Furthermore, the connection point between the other end of resistor 154a and one end of resistor 155a is electrically connected to terminal tvfb of integrated circuit 160a. In other words, resistors 154a and 155a divide the voltage value of voltage signal VHV and feed the divided signal back to integrated circuit 160a as feedback voltage signal VFB.

[0190] The excitation control circuit 162 controls at least one of the time when the basic excitation signal BDS becomes a high level, the time when the basic excitation signal BDS becomes a low level, the time when the excitation signal LDRV becomes a high level, and the time when the excitation signal LDRV becomes a low level, so that the voltage value of the input feedback voltage signal VFB becomes a predetermined value.

[0191] Specifically, when the voltage value of the input feedback voltage signal VFB is lower than a predetermined voltage value, the excitation control circuit 162 increases the value of the output basic excitation signal BDS. When the voltage value of the input feedback voltage signal VFB is higher than a predetermined voltage value, the excitation control circuit 162 increases the value of the output excitation signal LDRV. This controls the voltage value of the voltage signal VHV, which has been smoothed by the low-pass filter circuit formed by the coil 152a and the capacitor 153a.

[0192] Here, "duty" refers to the ratio of the time the output signal is output at an H level to the time the output signal changes from an H level to an L level and then changes back to an H level. For example, if the time the output signal changes from an H level to an L level and then changes back to an H level is 100 ms, and the time the signal is H level is 30 ms, then the duty is 30%. Furthermore, "increasing duty" means increasing the ratio of the time the output signal is output at an H level to the time the output signal changes from an H level to an L level and then changes back to an H level. For example, this can be achieved by fixing the time the output signal changes from an H level to an L level and then changes back to an H level, thereby increasing the time the signal stays at an H level. Alternatively, this can be achieved by fixing the time the output signal stays at an L level during the period after the output signal changes from an H level to an L level and then changes back to an H level, thereby increasing the time the signal stays at an H level. Alternatively, this can be achieved by fixing the time the output signal stays at an H level during the period after the output signal changes from an H level to an L level and then changes back to an H level, thereby shortening the time the signal stays at an L level.

[0193] One end of capacitor 156a is electrically connected to terminal tvsw, which outputs switching signal VSW, and the other end is electrically connected to terminal tvbt. Capacitor 156a accumulates a charge corresponding to the potential difference between one end and the other end. Capacitor 156a also generates a startup voltage signal VBT whose voltage value changes in response to the voltage value of switching signal VSW output from terminal tvsw, and outputs this startup voltage signal VBT from its other end.

[0194] As described above, the first step-down circuit 150a in this embodiment includes the integrated circuit 160a, the coil 152a, and the capacitor 153a, and generates and outputs the voltage signal VHV obtained by stepping down the voltage value of the voltage signal VDC according to the enable signal ENvh based on the step-down control signals VHVc1 to VHVc6 input from the drive signal output circuits 50-1 to 50-6.

[0195] Furthermore, the first step-down circuit 150a in this embodiment preferably has a so-called soft-start function. This soft-start function gradually increases the voltage value of the output voltage signal VHV toward a predetermined voltage value when the input enable signal ENvh switches from a state in which the output voltage signal VHV is not asserted to a state in which the output voltage signal VHV is asserted. In other words, the first step-down circuit 150a has a soft-start function that gradually increases the voltage value of the voltage signal VHV when the output of the voltage signal VHV is started.

[0196] Specifically, when the enable signal ENvh input to the first buck circuit 150a switches from a state in which the output voltage signal VHV is not asserted to a state in which the output voltage signal VHV is asserted, the excitation control circuit 162 gradually increases the value of the output basic excitation signal BDS regardless of the voltage value of the input feedback voltage signal VFB. As a result, the voltage value of the voltage signal VHV output by the first buck circuit 150a gradually increases.

[0197] Furthermore, when the voltage value of the voltage signal VHV output by the first step-down circuit 150a reaches a predetermined voltage value, for example, 42V, the voltage value of the feedback voltage signal VFB input to the excitation control circuit 162 also reaches a predetermined voltage value. When the voltage value of the feedback voltage signal VFB input to the excitation control circuit 162 reaches the predetermined value, the excitation control circuit 162 switches the control of the output base excitation signal BDS to control based on the voltage value of the feedback voltage signal VFB. As a result, the voltage value of the voltage signal VHV output by the first step-down circuit 150a is controlled to a predetermined and constant voltage value.

[0198] As described above, the first buck circuit 150a performs a soft start immediately after the enable signal ENvh input to the first buck circuit 150a switches from a state in which the output voltage signal VHV is not set to be valid to a state in which the output voltage signal VHV is set to be valid, thereby reducing the possibility of a surge current being generated immediately after the voltage signal VHV is started to be supplied.

[0199] As previously described, second step-down circuit 150b in this embodiment has the same configuration as first step-down circuit 150a. Therefore, in the following description, second step-down circuit 150b includes integrated circuit 160b corresponding to integrated circuit 160a, coil 152b corresponding to coil 152a, and capacitor 153b corresponding to capacitor 153a, and generates and outputs voltage signal VDD obtained by stepping down the voltage value of voltage signal VDC.

[0200] 3. Structure of the head unit

[0201] Next, the structure of the head unit 5 of this embodiment will be described. As described above, the head unit 5 includes a drive unit 10 and a discharge unit 20, and the drive unit 10 and the discharge unit 20 are electrically connected via a connection member 30. Below, an example of the structure of the drive unit 10 and the structure of the discharge unit 20 will be described.

[0202] 3.1 Structure of the ejection unit

[0203] First, an example of the structure of the discharge unit 20 included in the head unit 5 will be described. Figure 16 is a diagram illustrating the structure of the discharge unit 20. In the following description, the mutually orthogonal X1-axis, Y1-axis, and Z1-axis are used. In the following description, the tip side of the arrow along the illustrated X1-axis is sometimes referred to as the +X1 side, and the starting point side is sometimes referred to as the -X1 side. The tip side of the arrow along the illustrated Y1-axis is sometimes referred to as the +Y1 side, and the starting point side is sometimes referred to as the -Y1 side. The tip side of the arrow along the illustrated Z1-axis is sometimes referred to as the +Z1 side, and the starting point side is sometimes referred to as the -Z1 side.

[0204] like Figure 16 As shown, the ejection unit 20 includes a frame 31, an assembly substrate 33, a flow path structure 34, a head substrate 35, a distribution flow path 37, a fixing plate 39, and print heads 23-1 to 23-6. In the ejection unit 20, the flow path structure 34, the head substrate 35, the distribution flow path 37, and the fixing plate 39 are stacked in the order of the fixing plate 39, the distribution flow path 37, the head substrate 35, and the flow path structure 34, from the -Z1 side toward the +Z1 side, with the frame 31 positioned around the flow path structure 34, the head substrate 35, the distribution flow path 37, and the fixing plate 39 to support them. The collective substrate 33 is erected on the +Z1 side of the housing 31 while being held by the housing 31 , and the print heads 23 - 1 to 23 - 6 are positioned between the distribution flow path 37 and the fixing plate 39 with a portion thereof exposed to the outside of the ejection unit 20 .

[0205] When describing the structure of the ejection unit 20 , first, the structure of the print head 23 included in the ejection unit 20 will be described. Figure 17 : is a diagram showing an example of the structure of the print head 23. Figure 18 : is a diagram showing an example of a cross section of the print head 23. Here, Figure 18 Therefore Figure 17 The cross-sectional view of the print head 23 is shown along line Aa. Figure 17 The illustrated line Aa is a virtual line segment that passes through the introduction path 661 of the print head 23 and passes through the nozzle N1 and the nozzle N2.

[0206] like Figure 17 and Figure 18 As shown, the print head 23 has a plurality of nozzles N1 and a plurality of nozzles N2 arranged in parallel. The total number of nozzles N1 and nozzles N2 in the print head 23 is n, which is the same number as the ejection units 600 in the print head 23. It should be noted that the print head 23 is described as having the same number of nozzles N1 and nozzles N2. In other words, the print head 23 has n / 2 nozzles N1 and n / 2 nozzles N2. In the following description, when it is not necessary to distinguish between nozzles N1 and nozzles N2, they may be simply referred to as nozzles N.

[0207] The print head 23 includes a wiring member 388 , a housing 660 , a protective substrate 641 , a flow path forming substrate 642 , a communication plate 630 , a flexible substrate 620 , and a nozzle plate 623 .

[0208] In the flow channel forming substrate 642, a pressure chamber CB1, which is partitioned by a plurality of partition walls by anisotropic etching from one side, is arranged in parallel with the nozzle N1, and a pressure chamber CB2, which is partitioned by a plurality of partition walls by anisotropic etching from one side, is arranged in parallel with the nozzle N2. In the following description, when it is not necessary to distinguish between the pressure chambers CB1 and CB2, they may be simply referred to as pressure chambers CB.

[0209] The nozzle plate 623 is located on the -Z1 side of the flow channel substrate 642. The nozzle plate 623 is provided with a nozzle row Ln1 consisting of n / 2 nozzles N1 and a nozzle row Ln2 consisting of n / 2 nozzles N2. In the following description, the surface of the nozzle plate 623 on the -Z1 side, where the nozzles N are opened, is sometimes referred to as the liquid ejecting surface 623a.

[0210] The communication plate 630 is located on the -Z1 side of the flow channel substrate 642 and the +Z1 side of the nozzle plate 623. The communication plate 630 includes a nozzle communication path RR1 that connects the pressure chamber CB1 with the nozzle N1, and a nozzle communication path RR2 that connects the pressure chamber CB2 with the nozzle N2. Furthermore, the communication plate 630 includes pressure chamber communication paths RK1 and RK2 that connect the end of the pressure chamber CB1 with the manifold MN1 and the end of the pressure chamber CB2 with the manifold MN2, respectively, corresponding to and independently of the pressure chambers CB1 and CB2.

[0211] Manifold MN1 includes a supply communication passage RA1 and a connecting communication passage RX1. Supply communication passage RA1 extends through the connecting plate 630 along the Z1 axis. Connecting communication passage RX1 does not extend through the connecting plate 630 along the Z1 axis, but instead opens on the nozzle plate 623 side of the connecting plate 630 and extends midway along the Z1 axis. Similarly, manifold MN2 includes a supply communication passage RA2 and a connecting communication passage RX2. Supply communication passage RA2 extends through the connecting plate 630 along the Z1 axis, while connecting communication passage RX2 does not extend through the connecting plate 630 along the Z1 axis, but instead opens on the nozzle plate 623 side of the connecting plate 630 and extends midway along the Z1 axis. Furthermore, connecting communication passage RX1 in manifold MN1 communicates with the corresponding pressure chamber CB1 via pressure chamber communication passage RK1, while connecting communication passage RX2 in manifold MN2 communicates with the corresponding pressure chamber CB2 via pressure chamber communication passage RK2.

[0212] Here, in the following description, when there is no need to distinguish between the nozzle connecting path RR1 and the nozzle connecting path RR2, it is sometimes referred to as the nozzle connecting path RR, when there is no need to distinguish between the manifold MN1 and the manifold MN2, it is sometimes referred to as the manifold MN, when there is no need to distinguish between the supply connecting path RA1 and the supply connecting path RA2, it is sometimes referred to as the supply connecting path RA, and when there is no need to distinguish between the connecting connecting path RX1 and the connecting connecting path RX2, it is sometimes referred to as the connecting connecting path RX.

[0213] The vibration plate 610 is located on the +Z1 side surface of the flow channel forming substrate 642. Also, on the +Z1 side surface of the vibration plate 610, two rows of n piezoelectric elements 60 corresponding to the nozzles N1 and N2 are formed.

[0214] The piezoelectric element 60 includes a piezoelectric body 601 and a pair of electrodes 602 and 603 disposed so as to sandwich the piezoelectric body 601. Electrode 602 and piezoelectric body 601 are formed on the +Z1 side surface of the vibration plate 610 to correspond to pressure chambers CB. Electrode 603, on the +Z1 side surface of the vibration plate 610, serves as a common electrode common to the pressure chambers CB. The piezoelectric element 60 is driven by supplying a drive signal VOUT from the drive signal selection circuit 200 to electrode 602 and a reference voltage signal VBS to electrode 603, which serves as the common electrode, to displace the piezoelectric body 601 in the vertical direction.

[0215] A protective substrate 641 is bonded to the +Z1-side surface of the flow path-forming substrate 642. Protective substrate 641 defines a protective space 644 for protecting the piezoelectric element 60. Furthermore, a through-hole 643 extending along the Z1 axis is provided in protective substrate 641. Lead electrodes 611 extending from electrodes 602 and 603 of piezoelectric element 60 extend with their ends exposed inside through-hole 643. Wiring member 388 is electrically connected to lead electrodes 611 exposed inside through-hole 643.

[0216] Furthermore, a housing 660 is fixed to the protective substrate 641 and the connecting plate 630, defining a portion of the manifold MN that communicates with the multiple pressure chambers CB. The housing 660 is bonded to the protective substrate 641 and also to the connecting plate 630. Specifically, the housing 660 has a recess 665 on its surface on the -Z1 side, which accommodates the flow path-forming substrate 642 and the protective substrate 641. The recess 665 has a larger opening area than the surface of the protective substrate 641 bonded to the flow path-forming substrate 642. The flow path-forming substrate 642 and other components are accommodated in the recess 665. Furthermore, when the flow path-forming substrate 642 and other components are accommodated in the recess 665, the opening on the -Z1 side of the recess 665 is sealed by the connecting plate 630. Thus, the housing 660, the flow path-forming substrate 642, and the protective substrate 641 define the supply connecting path RB1 and the supply connecting path RB2 on the outer periphery of the flow path-forming substrate 642. Here, when there is no need to distinguish between the supply communication path RB1 and the supply communication path RB2 , they may be simply referred to as the supply communication path RB.

[0217] Furthermore, a flexible substrate 620 is provided on the surface of the communication plate 630 where the supply communication passage RA and the connection communication passage RX open. The openings of the supply communication passage RA and the connection communication passage RX are sealed by the flexible substrate 620. This flexible substrate 620 includes a sealing film 621 and a fixed substrate 622. The sealing film 621 is formed of a flexible film, etc., and the fixed substrate 622 is formed of a hard material such as a metal such as stainless steel.

[0218] The housing 660 is provided with an inlet passage 661 for supplying ink to the manifold MN. The housing 660 is also provided with a connection port 662 through which the wiring member 388 is inserted. The connection port 662 communicates with the through hole 643 of the protective substrate 641 and extends along the Z1 axis.

[0219] The wiring member 388 is a flexible member for electrically connecting the print head 23 and the head substrate 35. For example, an FPC can be used. The integrated circuit 201 is mounted on the wiring member 388 using a COF (Chip On Film) method. This integrated circuit 201 incorporates at least a portion of the aforementioned drive signal selection circuit 200.

[0220] In the print head 23 constructed as described above, the wiring member 388 transmits the voltage signal VHV, the drive signals COMA, COMB, COMC, the reference voltage signal VBS, the clock signal SCK, the print data signal SI, and the latch signal LAT. The voltage signal VHV, the drive signals COMA, COMB, COMC, the clock signal SCK, the print data signal SI, and the latch signal LAT are input to the drive signal selection circuit 200, which includes an integrated circuit 201 disposed in the wiring member 388. The drive signal selection circuit 200 then generates and outputs the drive signal VOUT by selecting or not selecting the drive signals COMA, COMB, and COMC based on the input voltage signal VHV, the clock signal SCK, the print data signal SI, and the latch signal LAT. The drive signal VOUT output by the drive signal selection circuit 200 propagates through the wiring member 388 and is supplied to the electrode 602 via the lead electrode 611. Furthermore, the reference voltage signal VBS propagates through the wiring member 388 and is supplied to the electrode 603 via the lead electrode 611. As a result, the piezoelectric body 601 deforms according to the potential difference between the drive signal VOUT supplied to the electrode 602 and the reference voltage signal VBS supplied to the electrode 603. In other words, the piezoelectric element 60 is driven. The driving of the piezoelectric element 60 then causes the vibration plate 610, on which the piezoelectric element 60 is mounted, to displace vertically. This causes the internal pressure of the corresponding pressure chamber CB to change, and the ink stored in the pressure chamber CB is ejected from the nozzle N in response to this change in pressure.

[0221] In the print head 23 configured as described above, the nozzles N, nozzle communication passages RR, pressure chambers CB, piezoelectric elements 60, and vibration plates 610 correspond to the aforementioned ejection unit 600. Specifically, the print head 23 includes a plurality of ejection units 600 that include piezoelectric elements 60 and eject ink in response to the driving of the piezoelectric elements 60.

[0222] That is, the ejection unit 20 includes: a print head 23-1, including a piezoelectric element 60 having one end supplied with a drive signal VOUT based on the drive signals COMA1, COMB1, and COMC1, and the other end supplied with a reference voltage signal VBS1 with a constant voltage value, and ink is ejected in response to the drive of the piezoelectric element 60; a print head 23-2, including a piezoelectric element 60 having one end supplied with a drive signal VOUT based on the drive signals COMA2, COMB2, and COMC2, and the other end supplied with a reference voltage signal VBS2 with a constant voltage value, and ink is ejected in response to the drive of the piezoelectric element 60; a print head 23-3, including a piezoelectric element 60 having one end supplied with a drive signal VOUT based on the drive signals COMA3, COMB3, and COMC3, and the other end supplied with a reference voltage signal VBS3 with a constant voltage value, and ink is ejected in response to the drive of the piezoelectric element 60. The ink is ejected; the print head 23-4 includes a piezoelectric element 60, one end of which is supplied with a drive signal VOUT based on the drive signals COMA4, COMB4, and COMC4, and the other end of which is supplied with a reference voltage signal VBS4 with a constant voltage value, and the ink is ejected corresponding to the drive of the piezoelectric element 60; the print head 23-5 includes a piezoelectric element 60, one end of which is supplied with a drive signal VOUT based on the drive signals COMA5, COMB5, and COMC5, and the other end of which is supplied with a reference voltage signal VBS5 with a constant voltage value, and the ink is ejected corresponding to the drive of the piezoelectric element 60; and the print head 23-6 includes a piezoelectric element 60, one end of which is supplied with a drive signal VOUT based on the drive signals COMA6, COMB6, and COMC6, and the other end of which is supplied with a reference voltage signal VBS6 with a constant voltage value, and the ink is ejected corresponding to the drive of the piezoelectric element 60.

[0223] Return to Figure 16 The fixing plate 39 is located on the -Z1 side of the print heads 23-1 to 23-6. The print heads 23-1 to 23-6 are fixed to the fixing plate 39. Specifically, the fixing plate 39 has six openings 391 extending along the Z1 axis and corresponding to the print heads 23-1 to 23-6. The print heads 23-1 to 23-6 are fixed to the fixing plate 39 so that the liquid ejection surfaces 623a are exposed through the six openings 391.

[0224] The distribution flow path 37 is located on the +Z1 side of the print heads 23-1 to 23-6. Four inlet portions 373 are provided on the +Z1 side of the distribution flow path 37. The four inlet portions 373 are flow path tubes that protrude from the -Z1 side of the distribution flow path 37 toward the +Z1 side along the Z1 axis, and are connected to flow path holes (not shown) formed on the -Z1 side of the flow path structure 34. In addition, the unillustrated flow path tubes connected to the four inlet portions 373 are located on the -Z1 side of the distribution flow path 37. The unillustrated flow path tubes located on the -Z1 side of the distribution flow path 37 are connected to the inlet path 661 provided in each of the print heads 23-1 to 23-6. In addition, the distribution flow path 37 has six openings 371 extending through it along the Z1 axis. The wiring components 388 provided in each of the print heads 23-1 to 23-6 are inserted through these six openings 371.

[0225] The head substrate 35 is located on the +Z1 side of the distribution channel 37. A wiring component FC is attached to the head substrate 35, which is electrically connected to the collective substrate 33 described later. Furthermore, the head substrate 35 has four openings 351 and cutouts 352 and 353. The wiring components 388 of the print heads 23-2 to 23-5 are inserted through the four openings 351 and electrically connected to the head substrate 35 using solder or the like. Furthermore, the cutout 352 allows the wiring component 388 of the print head 23-1 to pass through, and the cutout 353 allows the wiring component 388 of the print head 23-6 to pass through. The wiring components 388 of the print heads 23-1 and 23-6, respectively, passing through the cutouts 352 and 353, are electrically connected to the head substrate 35 using solder or the like.

[0226] In addition, four cutouts 355 are formed at the four corners of the head substrate 35. The introduction portions 373 pass through the four cutouts 355. The four introduction portions 373 passing through the cutouts 355 are connected to the flow path structure 34 located on the +Z1 side of the head substrate 35.

[0227] The flow path structure 34 includes a flow path plate Su1 and a flow path plate Su2. The flow path plates Su1 and Su2 are stacked along the Z1 axis, with the flow path plate Su1 located on the +Z1 side and the flow path plate Su2 located on the -Z1 side, and are bonded to each other using an adhesive or the like. Furthermore, the flow path structure 34 includes four inlet portions 341 on its surface on the +Z1 side, projecting along the Z1 axis toward the +Z1 side. The four inlet portions 341 communicate with flow path holes (not shown) formed on the -Z1 side of the flow path structure 34 through an ink flow path formed within the flow path structure 34. The flow path holes (not shown) formed on the -Z1 side of the flow path structure 34 communicate with the four inlet portions 373. Furthermore, a through hole 343 is formed in the flow path structure 34, extending through the Z1 axis. The wiring component FC, which is electrically connected to the head substrate 35, is inserted through the through hole 343.

[0228] Here, inside the flow path structure 34 , in addition to the ink flow path connecting the inlet portion 341 and the flow path hole (not shown) formed on the surface on the −Z1 side, a capture filter or the like for capturing foreign matter included in the ink flowing in the ink flow path may be provided.

[0229] The frame 31 is positioned to cover and support the flow path structure 34, the head substrate 35, the distribution flow path 37, and the fixing plate 39. The frame 31 has four openings 311, an assembly substrate insertion portion 313, and a holding member 315.

[0230] The four introduction portions 341 included in the flow path structure 34 are respectively inserted into the four openings 311. Ink is supplied from the liquid container 3 to the four introduction portions 341 inserted into the four openings 311 via a tube (not shown).

[0231] The holding component 315 clamps the collective substrate 33, which is partially inserted through the collective substrate insertion portion 313, between the holding component 315 and the frame 31. A connecting portion 330 is provided in the collective substrate 33. A connecting component 30 for transmitting various signals such as the voltage signal VHV, VDD, the data signal DATA, the drive signal COMA, COMB, COMC, the reference voltage signal VBS and other power supply voltages output by the driving unit 10 is attached to the connecting portion 330. In addition, the wiring component FC possessed by the head substrate 35 is electrically connected to the collective substrate 33. Thus, the integrated substrate 33 and the head substrate 35 are electrically connected. Here, a semiconductor device equivalent to the aforementioned restoration circuit 220 may also be provided in the integrated substrate 33. In addition, in Figure 16 3 , a case where one connection portion 330 is provided in the collective substrate 33 is shown in the figure, but the collective substrate 33 may include a plurality of connection portions 330 .

[0232] In the ejection unit 20 configured as described above, the liquid container 3 is connected to the inlet portion 341 via a tube (not shown), and the ink stored in the liquid container 3 is supplied to the ejection unit 20. The ink supplied to the ejection unit 20 is guided through the ink flow path formed within the flow path structure 34 to the flow path holes (not shown) formed on the -Z1 side of the flow path structure 34. Thereafter, the ink is supplied to the four inlet portions 373 of the distribution flow path 37. The ink supplied to the distribution flow path 37 is distributed within the ink flow paths (not shown) formed within the distribution flow path 37, corresponding to the print heads 23-1 to 23-6. The ink is then supplied to the inlet channels 661 of the corresponding print heads 23-1 to 23-6. The ink supplied to the print heads 23-1 to 23-6 via the inlet channels 661 is then stored in the pressure chambers CB included in the ejection unit 600.

[0233] Furthermore, various signals including the voltage signals VHV and VDD output by the driver unit 10, the drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, the reference voltage signals VBS1 to VBS6, and the data signal DATA propagate through the connection member 30 and are input to the ejection unit 20 through the connection portion 330. Various signals including the drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, the reference voltage signals VBS1 to VBS6, and the data signal DATA input to the ejection unit 20 propagate through the integrated substrate 33 and the head substrate 35. At this time, the restoration circuit 220 generates clock signals SCK1-SCK6, print data signals SI1-SI6, and latch signals LAT1-LAT6 corresponding to the print heads 23-1-23-6 based on the data signal DATA, and separates the generated clock signals SCK1-SCK6, print data signals SI1-SI6, and latch signals LAT1-LAT6 corresponding to the print heads 23-1-23-6. Then, the voltage signals VHV, VDD, drive signals COMA1-COMA6, COMB1-COMB6, COMC1-COMC6, reference voltage signals VBS1-VBS6, clock signals SCK1-SCK6, print data signals SI1-SI6, and latch signals LAT1-LAT6 are input to the wiring members 388 of the corresponding print heads 23-1-23-6. The voltage signals VHV and VDD, drive signals COMA, COMB, and COMC, reference voltage signal VBS, clock signal SCK, print data signal SI, and latch signal LAT supplied to the wiring member 388 propagate through the wiring member 388. At this point, the integrated circuit 201, which includes the drive signal selection circuit 200 provided in the wiring member 388, generates drive signals VOUT corresponding to each of the n ejection units 600 and supplies these drive signals VOUT to the electrodes 602 of the piezoelectric elements 60 included in the corresponding ejection units 600. Thus, the n piezoelectric elements 60 are individually driven according to the drive signals VOUT. As a result, ink stored in the pressure chambers CB corresponding to the piezoelectric elements 60 is ejected from the corresponding nozzles N.

[0234] 3.2 Structure of the drive unit

[0235] Next, the structure of the drive unit 10 included in the head unit 5 will be described. Figure 19 and Figure 20, the X2-axis, Y2-axis, and Z2-axis, which are perpendicular to each other, are illustrated as axes independent of the aforementioned X1-axis, Y1-axis, and Z1-axis. In the following description, the leading end side of an arrow along the illustrated X2-axis is sometimes referred to as the +X2 side, and the starting point side is sometimes referred to as the -X2 side. The leading end side of an arrow along the illustrated Y2-axis is sometimes referred to as the +Y2 side, and the starting point side is sometimes referred to as the -Y2 side. The leading end side of an arrow along the illustrated Z2-axis is sometimes referred to as the +Z2 side, and the starting point side is sometimes referred to as the -Z2 side.

[0236] Figure 19 1 is a diagram showing the structure of the drive unit 10. Figure 19 As shown, the driving unit 10 includes a base substrate B1 , a conversion circuit substrate B2 , and driving circuit modules DRV1 - DRV6 .

[0237] Base substrate B1 includes surface 801 and surface 802 located on the back side of surface 801, that is, opposite surface 801. Surfaces 801 and 802 of base substrate B1 extend along the Y2Z2 plane formed by the Y2-axis and the Z2-axis, with surface 801 located on the +X2 side and surface 802 located on the -X2 side. Details of base substrate B1 will be described later.

[0238] The conversion circuit board B2 is located on the +X2 side of surface 801 of the base substrate B1. Its mounting surface, where various electronic components are mounted, extends along the Y2Z2 plane. The conversion circuit board B2 is electrically connected to the base substrate B1 via a B-to-B connector on the -X2 side of the mounting surface. The conversion circuit board B2 is secured to the base substrate B1 with one or more screws.

[0239] A connector CN1 and an integrated circuit IC1 are provided on the +X2 side of the component mounting surface of the converter circuit board B2. Connector CN1 is located on the +Z2 side of the converter circuit board B2. A cable, such as an FFC, electrically connecting the drive unit 10 and the control unit 2 is attached to connector CN1. Integrated circuit IC1 is located on the -Z2 side of connector CN1. Integrated circuit IC1 incorporates at least a portion of the aforementioned control circuit 100 and converter circuit 120.

[0240] Various signals, including the image information signal IP, output by the control unit 2 are input to the drive unit 10 via the connector CN1. The various signals, including the image information signal IP, input to the drive unit 10 propagate through the conversion circuit board B2 and are then input to the integrated circuit IC1. Based on the input image information signal IP, the integrated circuit IC1 generates various signals, including the data signal DATA and the basic drive data signals dA1 to dA6, dB1 to dB6, and dC1 to dC6. Furthermore, the various signals, including the data signal DATA and the basic drive data signals dA1 to dA6, dB1 to dB6, and dC1 to dC6, generated by the integrated circuit IC1, propagate through the conversion circuit board B2 and are output to the base substrate B1 via a B2B connector electrically connected to the base substrate B1.

[0241] Drive circuit modules DRV1-DRV6 are located on the surface 801 side of base substrate B1 and on the -Z2 side of conversion circuit substrate B2. Specifically, drive circuit modules DRV1-DRV3 are located at positions spaced apart from each other, standing upright relative to base substrate B1, in the order of drive circuit module DRV1, drive circuit module DRV2, and drive circuit module DRV3, along the Y2 axis from the +Y2 side toward the -Y2 side. Furthermore, drive circuit modules DRV4-DRV6 are located at positions spaced apart from each other, standing upright relative to base substrate B1, in the order of drive circuit module DRV4, drive circuit module DRV5, and drive circuit module DRV6, along the Y2 axis from the +Y2 side toward the -Y2 side of drive circuit modules DRV1-DRV3, on the surface 801 of base substrate B1. At this time, the drive circuit modules DRV1-DRV6 are fixed to the base substrate B1 through corresponding BtoB connectors and are electrically connected to the base substrate B1. It should be noted that in addition to BtoB connectors, the drive circuit modules DRV1-DRV6 can also be fixed to the base substrate B1 using fixing components such as screws.

[0242] The driver circuit modules DRV1-DRV6 positioned as described above each include the aforementioned drive signal output circuits 50-1-50-6, respectively. Specifically, driver circuit module DRV1 includes drive signal output circuit 50-1, driver circuit module DRV2 includes drive signal output circuit 50-2, driver circuit module DRV3 includes drive signal output circuit 50-3, driver circuit module DRV4 includes drive signal output circuit 50-4, driver circuit module DRV5 includes drive signal output circuit 50-5, and driver circuit module DRV6 includes drive signal output circuit 50-6. Furthermore, driver circuit module DRV1 outputs the drive signals COMA1, COMB1, and COMC1 generated by drive signal output circuit 50-1, as well as the reference voltage signal VBS1, to base substrate B1 via corresponding B-to-B connectors. Similarly, driver circuit module DRVi outputs the drive signals COMAi, COMBi, and COMCi generated by drive signal output circuit 50-i, as well as the reference voltage signal VBSi, to base substrate B1 via corresponding B-to-B connectors.

[0243] Here, the drive circuit modules DRV1 through DRV6 all have the same configuration. Therefore, when there's no need to distinguish between these modules, they're sometimes simply referred to as the drive circuit module DRV. In this case, the drive circuit module DRV includes a drive signal output circuit 50, which serves as the drive signal output circuits 50-1 through 50-6. These outputs the drive signals COMA, COMB, and COMC, as well as the reference voltage signal VBS, to the base substrate B1 via corresponding B-to-B connectors.

[0244] Here, an example of the structure of the driving circuit module DRV will be described. Figure 20 FIG. 1 is a diagram showing an example of the structure of the driving circuit module DRV. Figure 20 As shown, the driving circuit module DRV includes driving circuits 52a, 52b, and 52c included in the driving signal output circuit 50, a connector CN3a, and a driving circuit substrate DRB on which the driving circuits 52a, 52b, and 52c and the connector CN3a are mounted.

[0245] The drive circuit board DRB is a circuit board on which various electronic components are mounted, and is located so that a component mounting surface extends along an X2Z2 plane formed by the X2 axis and the Z2 axis.

[0246] The drive circuits 52a, 52b, and 52c are located on the surface on the -Y2 side of the drive circuit substrate DRB so as to be aligned along the Z2 axis.

[0247] Specifically, in drive circuit 52a, the integrated circuit 500, amplifier circuit 550, and coil 561 included in drive circuit 52a are positioned along the X2 axis, from the -X2 side toward the +X2 side, in the order of coil 561, amplifier circuit 550, and integrated circuit 500. At this point, transistors 551 and 552 included in amplifier circuit 550 of drive circuit 52a are arranged side by side along the Z2 axis. Furthermore, in drive circuit 52b, the integrated circuit 500, amplifier circuit 550, and coil 561 included in drive circuit 52b are positioned along the -Z2 side of drive circuit 52a, in the order of coil 561, amplifier circuit 550, and integrated circuit 500, from the -X2 side toward the +X2 side, along the X2 axis. At this point, transistors 551 and 552 included in amplifier circuit 550 of drive circuit 52b are arranged side by side along the Z2 axis. Furthermore, in driver circuit 52c, the integrated circuit 500, amplifier circuit 550, and coil 561 included in driver circuit 52c are located on the -Z2 side of driver circuit 52a and the +Z2 side of driver circuit 52b, in the order of coil 561, amplifier circuit 550, and integrated circuit 500, from the -X2 side toward the +X2 side, along the X2 axis. In this case, transistors 551 and 552 included in amplifier circuit 550 of driver circuit 52c are arranged in parallel along the Z2 axis. That is, the driver circuits 52a, 52b, and 52c are located on the -Y2 side of the driver circuit substrate DRB, in the order of driver circuit 52a, driver circuit 52c, and driver circuit 52b, along the Z2 axis, from the +Z2 side toward the -Z2 side.

[0248] At this time, the integrated circuit 500 of the driving circuits 52a, 52b, and 52c is arranged in parallel along the Z2 axis, the amplifier circuit 550 of the driving circuits 52a, 52b, and 52c is arranged in parallel along the Z2 axis, and the coil 561 of the driving circuits 52a, 52b, and 52c is arranged in parallel along the Z2 axis.

[0249] As previously described, the voltage amplitudes of drive signals COMA and COMB are greater than the voltage amplitude of drive signal COMC. Therefore, the amount of current generated by the propagation of drive signals COMA and COMB is greater than the amount of current generated by the propagation of drive signal COMC. Consequently, the heat generated by drive circuit 52a, which outputs drive signal COMA, and drive circuit 52b, which outputs drive signal COMB, is greater than the heat generated by drive circuit 52c, which outputs drive signal COMC. By placing drive circuit 52c, which generates less heat, between these high-heating drive circuits 52a and 52b, drive circuits 52a and 52b are separated. This reduces the likelihood of heat generated in drive circuit 52a and drive circuit 52b interfering with each other and causing localized heat concentration in drive circuit module DRV.

[0250] Connector CN3a is located along the -X2-side edge of the drive circuit board DRB, on the -Y2-side surface of the drive circuit board DRB and on the -X2-side of the drive circuits 52a, 52b, and 52c. This connector CN3a engages with connector CN3b (described later) provided on the base substrate B1, thereby electrically connecting the drive circuit board DRB to the base substrate B1. In other words, connector CN3a and connector CN3b form a B2B connector that electrically connects the drive circuit module DRV to the base substrate B1. As a result, the drive signals COMA, COMB, and COMC and the reference voltage signal VBS output by the drive circuits 52a, 52b, and 52c are input to the base substrate B1. At this time, the terminal for propagation of the driving signals COMA, COMB, and COMC possessed by the connector CN3a and the terminal for propagation of the driving signals COMA, COMB, and COMC possessed by the connector CN3b are equivalent to the above-mentioned terminal COM-Out, and the terminal for propagation of the reference voltage signal VBS possessed by the connector CN3a and the terminal for propagation of the reference voltage signal VBS possessed by the connector CN3b are equivalent to the above-mentioned terminal VBS-Out.

[0251] In addition, if Figure 20 As shown, connector CN3a is located along the -X2 side of drive circuits 52a, 52b, and 52c, that is, along the -X2 side of drive circuit substrate DRB. Consequently, the shortest distance between coil 561 of drive circuit 52a and connector CN3a is shorter than the shortest distance between integrated circuit 500 of drive circuit 52a and connector CN3a. The shortest distance between coil 561 of drive circuit 52b and connector CN3a is shorter than the shortest distance between integrated circuit 500 of drive circuit 52b and connector CN3a. The shortest distance between coil 561 of drive circuit 52c and connector CN3a is shorter than the shortest distance between integrated circuit 500 of drive circuit 52c and connector CN3a. Consequently, the wiring length of the wiring pattern on drive circuit substrate DRB, through which drive signals COMA, COMB, and COMC and reference voltage signal VBS output by drive circuits 52a, 52b, and 52c propagate, can be shortened. As a result, the waveform accuracy of the drive signals COMA, COMB, COMC and the reference voltage signal VBS output from the drive circuit module DRV is improved.

[0252] That is, the driving unit 10 has a driving circuit module DRV, which includes: a driving signal output circuit 50-1, including driving circuits 52a, 52b, and 52c; a reference voltage signal output circuit 460, included in the driving circuits 52a, 52b, and 52c; a connector CN3a, electrically connected to the bottom substrate B1; and a driving circuit substrate DRB, which is provided with a driving signal output circuit 50 including driving circuits 52a, 52b, and 52c and a connector CN3a.

[0253] Return to Figure 19 A connector CN2 is provided on surface 801 of the base substrate B1. Connector CN2 is located along the -Z2 side of the base substrate B1. One end of the connecting component 30 is attached to connector CN2. Furthermore, the other end of the connecting component 30 is connected to the aforementioned connection portion 330. Thus, signals including the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6, as well as the data signal DATA, propagating through the base substrate B1 are supplied to the ejection unit 20.

[0254] That is, the driving unit 10 includes: a connector CN2 electrically connected to the ejection unit 20 having the print heads 23-1 to 23-6; and a base substrate B1 provided with the connector CN2 for transmitting driving signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6 and reference voltage signals VBS1 to VBS6.

[0255] In the drive unit 10 of this embodiment constructed as described above, the drive circuit module DRV, including the drive signal output circuit 50, is fixed upright relative to the base substrate B1 via a B-to-B connector. This eliminates the need to mount the drive signal output circuits 50-1 to 50-6 on the base substrate B1, enabling miniaturization of the base substrate B1. Consequently, both the drive unit 10 including the base substrate B1 and the head unit 5 incorporating the drive unit 10 can be miniaturized.

[0256] On the other hand, in this configuration, since the base substrate B1 is smaller, the area within the base substrate B1 where wiring patterns for various signal transmissions can be arranged is reduced. As a result, the various signals propagating through the base substrate B1 may interfere with each other. In particular, if distortion occurs in the signal waveforms of the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6 propagating through the base substrate B1, the driving characteristics of the multiple piezoelectric elements 60 included in the ejection unit 20 may change, resulting in a higher possibility of deteriorating the accuracy of ink ejection from the ejection unit 20.

[0257] Therefore, the following describes a configuration that can take into account both the miniaturization of the base substrate B1 and the reduction in the possibility of distortion in the signal waveforms of the propagated drive signals COMA1~COMA6, COMB1~COMB6, COMC1~COMC6, that is, an example of an optimal configuration of electronic components mounted on the base substrate B1, and an example of an optimal wiring pattern formed on the base substrate B1, that is, an example of an optimal wiring pattern for the drive signals COMA1~COMA6, COMB1~COMB6, COMC1~COMC6 and the reference voltage signals VBS1~VBS6 propagated in the base substrate B1.

[0258] When describing an example of optimal arrangement of electronic components mounted on the base substrate B1 and an example of optimal wiring patterns formed on the base substrate B1 , the structure of the base substrate B1 will be described first. Figure 21 : is a diagram showing an example of a cross-sectional structure of the base substrate B1. Figure 21 As shown, the base substrate B1 includes surface wiring layers 811 and 812 located between the aforementioned surface 801 and surface 802 , internal wiring layers 820 - 1 to 820 - m , and a plurality of insulating layers 810 .

[0259] Surface wiring layer 811 forms the wiring pattern on surface 801, while surface wiring layer 812 forms the wiring pattern on surface 802. Internal wiring layers 820-1 through 820-m are located between surface wiring layer 811 and surface wiring layer 812 along the X2 axis. They are inner layers within base substrate B1, forming the wiring pattern. From the +X2 side toward the -X2 side, internal wiring layers 820-1, 820-2, ..., 820-(m-1), and 820-m are stacked in this order. Wiring patterns for transmitting various signals are formed in surface wiring layers 811 and 812 and in the corresponding internal wiring layers 820-1 through 820-m by etching highly conductive copper foil or the like.

[0260] Multiple insulating layers 810 insulate the surface wiring layers 811 and 812 and the internal wiring layers 820-1 to 820-m from one another. Specifically, along the X2 axis, multiple insulating layers 810 are located between the surface wiring layer 811 and the internal wiring layer 820-1, between the internal wiring layer 820-1 and the internal wiring layer 820-2, between the internal wiring layer 820-j (j is any one from 1 to m-1) and the internal wiring layer 820-(j+1), and between the internal wiring layer 820-m and the surface wiring layer 812. These multiple insulating layers 810 are made of a material with excellent insulating properties, for example, epoxy glass formed by impregnating epoxy resin into glass fiber cloth. It should be noted that a solder resist film (not shown) for insulating the surface wiring layers 811 and 812 may also be applied to the surfaces 801 and 802.

[0261] As described above, the base substrate B1 of this embodiment includes a surface 801, a surface 802 located on the back side of surface 801, that is, at a position opposite to surface 801, and multiple internal wiring layers 820 located between surface 801 and surface 802. In other words, base substrate B1 is composed of a so-called multilayer substrate having multiple layers. In addition, multiple electronic components are mounted on at least one of surfaces 801 and 802 of base substrate B1. The multiple electronic components mounted on surfaces 801 and 802 are electrically connected to each other via wiring patterns formed on surface wiring layers 811 and 812 and internal wiring layers 820-1 to 820-m. Thus, base substrate B1 transmits various signals to the desired structure.

[0262] Next, an example of the optimal arrangement of electronic components mounted on the base substrate B1 as a multi-layer substrate will be described. Figure 22 FIG is a diagram showing an example of the arrangement of a plurality of electronic components mounted on the base substrate B1. Figure 22 In FIG. 1 , electronic components mounted on a surface 801 located on the +X2 side of the base substrate B1 are shown by solid lines, and electronic components mounted on a surface 802 located on the −X2 side of the base substrate B1 are shown by dotted lines.

[0263] like Figure 22 As shown, base substrate B1 includes sides 821, 822, 823, and 824. Side 821 and side 822 are positioned relative to each other, with side 821 on the +Z2 side along the Z2 axis and side 822 on the -Z2 side along the Z2 axis. Sides 823 and 824 are longer than sides 821 and 822, and are positioned relative to each other, with side 823 on the +Y2 side along the Y2 axis and side 824 on the -Y2 side along the Y2 axis. In other words, base substrate B1 has a generally rectangular shape, with sides 821 and 822 being the short sides and sides 823 and 824 being the long sides. It should be noted that the shape of base substrate B1 is not limited to a rectangle.

[0264] Connector CN2 , connectors CN3 b - 1 to CN3 b - 6 as the connector CN3 b described above, and two connectors CN4 b are mounted on surface 801 of base substrate B1 .

[0265] Connector CN2 is located at the -Z2-side end of base substrate B1. Specifically, connector CN2 has multiple terminals for transmitting signals including drive signals COMA1-COMA6, COMB1-COMB6, COMC1-COMC6, and data signal DATA. These multiple terminals are mounted on the -Z2-side end of base substrate B1 in a parallel arrangement along side 822.

[0266] Connectors CN3b-4, CN3b-5, and CN3b-6 are located on the +Z2 side of connector CN2, and are arranged in the order of connector CN3b-4, connector CN3b-5, and connector CN3b-6 along the Y2 axis from the +Y2 side toward the -Y2 side.

[0267] Connector CN3a of drive circuit module DRV4 is connected to connector CN3b-4. Specifically, connector CN3b-4 has multiple terminals for transmitting drive signals COMA4, COMB4, and COMC4, and reference voltage signal VBS4, output by drive signal output circuit 50-4. Connector CN3a of drive circuit module DRV5 is connected to connector CN3b-5. Specifically, connector CN3b-5 has multiple terminals for transmitting drive signals COMA5, COMB5, and COMC5, and reference voltage signal VBS5, output by drive signal output circuit 50-5. Connector CN3a of drive circuit module DRV6 is connected to connector CN3b-6. Specifically, connector CN3b-6 has multiple terminals for transmitting drive signals COMA6, COMB6, and COMC6, and reference voltage signal VBS6, output by drive signal output circuit 50-6. Furthermore, connectors CN3b-4, CN3b-5, and CN3b-6 are arranged on base substrate B1, with their respective terminals arranged side by side along the Z2 axis.

[0268] Connectors CN3b-1, CN3b-2, and CN3b-3 are on the +Z2 side of connectors CN3b-4, CN3b-5, and CN3b-6, and are arranged in the order of connector CN3b-1, connector CN3b-2, and connector CN3b-3 along the Y2 axis from the +Y2 side toward the -Y2 side.

[0269] Connector CN3a of drive circuit module DRV1 is connected to connector CN3b-1. Specifically, connector CN3b-1 has multiple terminals through which drive signals COMA1, COMB1, and COMC1, as well as reference voltage signal VBS1, output from drive signal output circuit 50-1, are transmitted. Connector CN3a of drive circuit module DRV2 is connected to connector CN3b-2. Specifically, connector CN3b-2 has multiple terminals through which drive signals COMA2, COMB2, and COMC2, as well as reference voltage signal VBS2, output from drive signal output circuit 50-2, are transmitted. Connector CN3a of drive circuit module DRV3 is connected to connector CN3b-3. Specifically, connector CN3b-3 has multiple terminals through which drive signals COMA3, COMB3, and COMC3, as well as reference voltage signal VBS3, output from drive signal output circuit 50-3, are transmitted. Furthermore, the connectors CN3b-1, CN3b-2, and CN3b-3 are provided on the base substrate B1 in such a manner that a plurality of terminals included in each connector are arranged in parallel along the Z2 axis.

[0270] As described above, on base substrate B1, connectors CN3b-1, CN3b-2, and CN3b-3 are located farther from connector CN2 than connectors CN3b-4, CN3b-5, and CN3b-6. In other words, on base substrate B1, the shortest distance between connectors CN3b-1, CN3b-2, and CN3b-3 and connector CN2 is longer than the shortest distance between connectors CN3b-4, CN3b-5, and CN3b-6 and connector CN2. Therefore, the drive signal output circuit 50-1 included in the drive circuit module DRV1 connected to the connector CN3b-1, the drive signal output circuit 50-2 included in the drive circuit module DRV2 connected to the connector CN3b-2, and the drive signal output circuit 50-3 included in the drive circuit module DRV3 connected to the connector CN3b-3 are located farther away from the connector CN2 than the drive signal output circuit 50-4 included in the drive circuit module DRV4 connected to the connector CN3b-4, the drive signal output circuit 50-5 included in the drive circuit module DRV5 connected to the connector CN3b-5, and the drive signal output circuit 50-6 included in the drive circuit module DRV6 connected to the connector CN3b-6. In other words, the shortest distance between the drive signal output circuits 50-1, 50-2, 50-3 and the connector CN2, and the shortest distance between the reference voltage signal output circuits 460 included in the drive signal output circuits 50-1, 50-2, 50-3 and the connector CN2 are longer than the shortest distance between the drive signal output circuits 50-4, 50-5, 50-6 and the connector CN2, and the shortest distance between the reference voltage signal output circuits 460 included in the drive signal output circuits 50-4, 50-5, 50-6 and the connector CN2.

[0271] The two connectors CN4b are located on the +Z2 side of connectors CN3b-1, CN3b-2, and CN3b-3, aligned along the Y2 axis. The two connectors CN4b mate with connectors (not shown) located on the component mounting surface on the -X2 side of the conversion circuit board B2, forming a B2B connector. This electrically connects the conversion circuit board B2 to the base board B1. Specifically, the two connectors CN4b have multiple terminals for transmitting various signals, including the data signal DATA and basic drive data signals dA1 to dA6, dB1 to dB6, and dC1 to dC6. Furthermore, the two connectors CN4b are mounted on the base board B1, with their multiple terminals arranged side by side along the Z2 axis.

[0272] In addition, if Figure 22 As shown, capacitors 110 - 1 to 110 - 6 , 190 - 1 to 190 - 6 , and a first step-down circuit 150 a and a second step-down circuit 150 b are provided on a surface 802 of the base substrate B1 .

[0273] When observing the base substrate B1 along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, capacitors 190-4 to 190-6 are located between the connector CN2 at the end on the -Z2 side of the base substrate B1 and the connectors CN3b-4, connector CN3b-5, and connector CN3b-6 located along the Y2 axis, and are located at positions arranged in the order of capacitor 190-4, capacitor 190-5, and capacitor 190-6 from the +Y2 side toward the -Y2 side along the Y2 axis.

[0274] At this time, capacitor 190-4 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 190-4 and connector CN3b-4 is shorter than the shortest distance between capacitor 190-5 and connector CN3b-4 and the shortest distance between capacitor 190-6 and connector CN3b-4, capacitor 190-5 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 190-5 and connector CN3b-5 is shorter than the shortest distance between capacitor 190-4 and connector CN3b-5 and the shortest distance between capacitor 190-6 and connector CN3b-5, and capacitor 190-6 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 190-6 and connector CN3b-6 is shorter than the shortest distance between capacitor 190-4 and connector CN3b-6 and the shortest distance between capacitor 190-5 and connector CN3b-6.

[0275] Furthermore, capacitor 190-4 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS4, i.e., the + terminal of the electrolytic capacitor serving as capacitor 190-4, is on the -Z2 side, and the other end, supplied with a ground signal, i.e., the - terminal of the electrolytic capacitor serving as capacitor 190-4, is on the +Z2 side, with these ends being located along the Z2 axis. Specifically, capacitor 190-4 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS4, is on the side of connector CN2, which outputs reference voltage signal VBS4 to ejection unit 20, and the other end, supplied with a ground signal, is on the side of connector CN3b-4, which supplies drive signals COMA4, COMB4, and COMC4.

[0276] Similarly, capacitor 190-5 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS5, i.e., the + terminal of the electrolytic capacitor serving as capacitor 190-5, is on the -Z2 side, and the other end, supplied with a ground signal, i.e., the - terminal of the electrolytic capacitor serving as capacitor 190-5, is on the +Z2 side, with these ends being located along the Z2 axis. Specifically, capacitor 190-5 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS5, is on the side of connector CN2, which outputs reference voltage signal VBS5 to ejection unit 20, and the other end, supplied with a ground signal, is on the side of connector CN3b-5, which supplies drive signals COMA5, COMB5, and COMC5.

[0277] Similarly, capacitor 190-6 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS6, i.e., the + terminal of the electrolytic capacitor serving as capacitor 190-6, is on the -Z2 side, and the other end, supplied with a ground signal, i.e., the - terminal of the electrolytic capacitor serving as capacitor 190-6, is on the +Z2 side, with these ends being located along the Z2 axis. Specifically, capacitor 190-6 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS6, is on the side of connector CN2, which outputs reference voltage signal VBS6 to ejection unit 20, and the other end, supplied with a ground signal, is on the side of connector CN3b-6, which supplies drive signals COMA6, COMB6, and COMC6.

[0278] When observing the base substrate B1 along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, capacitors 190-1 to 190-3 are located between connectors CN3b-4, connector CN3b-5, connector CN3b-6 located along the Y2 axis and connectors CN3b-1, connector CN3b-2, connector CN3b-3 located along the Y2 axis, and are arranged in the order of capacitor 190-1, capacitor 190-2, and capacitor 190-3 from the +Y2 side toward the -Y2 side along the Y2 axis.

[0279] At this time, capacitor 190-1 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 190-1 and connector CN3b-1 is shorter than the shortest distance between capacitor 190-2 and connector CN3b-1 and the shortest distance between capacitor 190-3 and connector CN3b-1, capacitor 190-2 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 190-2 and connector CN3b-2 is shorter than the shortest distance between capacitor 190-1 and connector CN3b-2 and the shortest distance between capacitor 190-3 and connector CN3b-2, and capacitor 190-3 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 190-3 and connector CN3b-3 is shorter than the shortest distance between capacitor 190-1 and connector CN3b-3 and the shortest distance between capacitor 190-2 and connector CN3b-3.

[0280] Furthermore, capacitor 190-1 is mounted on base substrate B1 such that one end, which receives reference voltage signal VBS1, i.e., the + terminal of the electrolytic capacitor serving as capacitor 190-1, is on the -Z2 side, and the other end, which receives a ground signal, i.e., the - terminal of the electrolytic capacitor serving as capacitor 190-1, is on the +Z2 side. These two ends are positioned along the Z2 axis. Specifically, capacitor 190-1 is mounted on base substrate B1 such that one end, which receives reference voltage signal VBS1, is on the side of connector CN2, which outputs reference voltage signal VBS1 to ejection unit 20, and the other end, which receives a ground signal, is on the side of connector CN3b-1, which receives drive signals COMA1, COMB1, and COMC1.

[0281] Similarly, capacitor 190-2 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS2, i.e., the + terminal of the electrolytic capacitor serving as capacitor 190-2, is on the -Z2 side, and the other end, supplied with a ground signal, i.e., the - terminal of the electrolytic capacitor serving as capacitor 190-2, is on the +Z2 side, with these ends being located along the Z2 axis. Specifically, capacitor 190-2 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS2, is on the side of connector CN2, which outputs reference voltage signal VBS2 to ejection unit 20, and the other end, supplied with a ground signal, is on the side of connector CN3b-2, which supplies drive signals COMA2, COMB2, and COMC2.

[0282] Similarly, capacitor 190-3 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS3, i.e., the + terminal of the electrolytic capacitor serving as capacitor 190-3, is on the -Z2 side, and the other end, supplied with a ground signal, i.e., the - terminal of the electrolytic capacitor serving as capacitor 190-3, is on the +Z2 side, with these ends being located along the Z2 axis. Specifically, capacitor 190-3 is mounted on base substrate B1 such that one end, supplied with reference voltage signal VBS3, is on the side of connector CN2, which outputs reference voltage signal VBS3 to ejection unit 20, and the other end, supplied with a ground signal, is on the side of connector CN3b-3, which supplies drive signals COMA3, COMB3, and COMC3.

[0283] That is, the shortest distance between the connector CN2 and the capacitors 190 - 1 to 190 - 3 is longer than the shortest distance between the connector CN2 and the capacitors 190 - 4 to 190 - 6 .

[0284] When observing the base substrate B1 along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, the capacitors 110-4 to 110-6 are located between the connectors CN3b-4, connector CN3b-5, and connector CN3b-6 located along the Y2 axis and the capacitors 190-1, capacitor 190-2, and capacitor 190-3 located along the Y2 axis, and are arranged in the order of capacitor 110-4, capacitor 110-5, and capacitor 110-6 from the +Y2 side toward the -Y2 side along the Y2 axis.

[0285] At this time, capacitor 110-4 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 110-4 and connector CN3b-4 is shorter than the shortest distance between capacitor 110-5 and connector CN3b-4 and the shortest distance between capacitor 110-6 and connector CN3b-4. Capacitor 110-5 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 110-5 and connector CN3b-5 is shorter than the shortest distance between capacitor 110-4 and connector CN3b-5 and the shortest distance between capacitor 110-6 and connector CN3b-5. Capacitor 110-6 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 110-6 and connector CN3b-6 is shorter than the shortest distance between capacitor 110-4 and connector CN3b-6 and the shortest distance between capacitor 110-5 and connector CN3b-6.

[0286] Furthermore, the capacitor 110-4 is mounted on the base substrate B1 in such a manner that one end supplied with a voltage signal VHV, i.e., the + pole of the electrolytic capacitor serving as capacitor 110-4, is on the -Z2 side, and the other end supplied with a ground signal, i.e., the - pole of the electrolytic capacitor serving as capacitor 110-4, is on the +Z2 side, and the one end and the other end are located along the Z2 axis. Similarly, capacitor 110-5 is mounted on the base substrate B1 in such a manner that one end supplied with a voltage signal VHV, i.e., the + pole of the electrolytic capacitor serving as capacitor 110-5, is on the -Z2 side, and the other end supplied with a ground signal, i.e., the - pole of the electrolytic capacitor serving as capacitor 110-5, is on the +Z2 side, and the one end and the other end are located along the Z2 axis. Capacitor 110-6 is mounted on the base substrate B1 in such a manner that one end supplied with a voltage signal VHV, i.e., the + pole of the electrolytic capacitor serving as capacitor 110-6, is on the -Z2 side, and the other end supplied with a ground signal, i.e., the - pole of the electrolytic capacitor serving as capacitor 110-6, is on the +Z2 side, and the one end and the other end are located along the Z2 axis.

[0287] When observing the base substrate B1 along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, the capacitors 110-1 to 110-3 are located between the connector CN3b-1, the connector CN3b-2, and the connector CN3b-3 located along the Y2 axis and the connector CN4b located along the Y2 axis, and are arranged in the order of capacitor 110-1, capacitor 110-2, and capacitor 110-3 along the Y2 axis from the +Y2 side toward the -Y2 side.

[0288] At this time, capacitor 110-1 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 110-1 and connector CN3b-1 is shorter than the shortest distance between capacitor 110-2 and connector CN3b-1 and the shortest distance between capacitor 110-3 and connector CN3b-1. Capacitor 110-2 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 110-2 and connector CN3b-2 is shorter than the shortest distance between capacitor 110-1 and connector CN3b-2 and the shortest distance between capacitor 110-3 and connector CN3b-2. Capacitor 110-3 is arranged on the base substrate B1 in such a manner that the shortest distance between capacitor 110-3 and connector CN3b-3 is shorter than the shortest distance between capacitor 110-1 and connector CN3b-3 and the shortest distance between capacitor 110-2 and connector 110-3.

[0289] Furthermore, the capacitor 110-1 is mounted on the base substrate B1 in such a manner that one end supplied with a voltage signal VHV, i.e., the + pole of the electrolytic capacitor serving as capacitor 110-1, is on the -Z2 side, and the other end supplied with a ground signal, i.e., the - pole of the electrolytic capacitor serving as capacitor 110-1, is on the +Z2 side, and the one end and the other end are located at positions along the Z2 axis. Similarly, capacitor 110-2 is mounted on the base substrate B1 in such a manner that one end supplied with a voltage signal VHV, i.e., the + pole of the electrolytic capacitor serving as capacitor 110-2, is on the -Z2 side, and the other end supplied with a ground signal, i.e., the - pole of the electrolytic capacitor serving as capacitor 110-2, is on the +Z2 side, and the one end and the other end are located along the Z2 axis. Capacitor 110-3 is mounted on the base substrate B1 in such a manner that one end supplied with a voltage signal VHV, i.e., the + pole of the electrolytic capacitor serving as capacitor 110-3, is on the -Z2 side, and the other end supplied with a ground signal, i.e., the - pole of the electrolytic capacitor serving as capacitor 110-3, is on the +Z2 side, and the one end and the other end are located along the Z2 axis.

[0290] When observing the base substrate B1 along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, the first step-down circuit 150a is located between the capacitors 110-1, 110-2, and 110-3 located along the Y2 axis and the connector CN4b located along the Y2 axis.

[0291] When viewing the base substrate B1 along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, the second step-down circuit 150b is located on the +Z2 side of the connector CN4b located along the Y2 axis.

[0292] As described above, base substrate B1 includes side 821, side 822 located opposite side 821, side 823, and side 824 located opposite side 823. Furthermore, connector CN2, connectors CN3b-1 to CN3b-6, and two connectors CN4b are provided on surface 801 of base substrate B1, while capacitors 110-1 to 110-6, 190-1 to 190-6, a first step-down circuit 150a, and a second step-down circuit 150b are provided on surface 802 of base substrate B1.

[0293] Furthermore, the connector CN3a of each of the drive circuit modules DRV1 to DRV6 engages with the connectors CN3b-1 to CN3b-6 provided on the surface 801 of the base substrate B1. Furthermore, by engaging the connector CN3a of the drive circuit module DRV1 with the connector CN3b-1 provided on the surface 801 of the base substrate B1, the drive circuit substrate DRB, on which the drive signal output circuit 50-1 of the drive circuit module DRV1 is mounted, is electrically connected to the base substrate B1. By engaging the connector CN3a of the drive circuit module DRVi with the connector CN3b-i provided on the surface 801 of the base substrate B1, the drive circuit substrate DRB, on which the drive signal output circuit 50-i of the drive circuit module DRVi is mounted, is electrically connected to the base substrate B1.

[0294] In other words, the driving circuit substrate DRB on which the driving signal output circuit 50-1 of the driving circuit module DRV1 is installed is electrically connected to the base substrate B1 through a BtoB connector composed of a connector CN3b-1 and a connector CN3a, and the driving circuit substrate DRB on which the driving signal output circuit 50-i of the driving circuit module DRVi is installed is electrically connected to the base substrate B1 through a BtoB connector composed of a connector CN3b-i and a connector CN3a.

[0295] Therefore, the driving signal output circuits 50 - 1 to 50 - 6 that output the driving signals COMA1 to COMA6 , COMB1 to COMB6 , and COMC1 to COMC6 and the reference voltage signals VBS1 to VBS6 are located on the surface 801 side of the base substrate B1 . That is, the shortest distance between the driving circuits 52a, 52b, 52c respectively possessed by the driving signal output circuits 50-1 to 50-6 and the surface 801 is shorter than the shortest distance between the driving circuits 52a, 52b, 52c respectively possessed by the driving signal output circuits 50-1 to 50-6 and the surface 802, and the shortest distance between the reference voltage signal output circuit 460 included in the driving circuits 52a, 52b, 52c respectively possessed by the driving signal output circuits 50-1 to 50-6 and the surface 801 is shorter than the shortest distance between the reference voltage signal output circuit 460 included in the driving circuits 52a, 52b, 52c respectively possessed by the driving signal output circuits 50-1 to 50-6 and the surface 802. In other words, the base substrate B1 is located between the driving signal output circuits 50 - 1 to 50 - 6 and the capacitors 110 - 1 to 110 - 6 , 190 - 1 to 190 - 6 , the first step-down circuit 150 a and the second step-down circuit 150 b .

[0296] In addition, the drive signals COMA1, COMB1, COMC1 and the reference voltage signal VBS1 output by the drive signal output circuit 50-1 of the drive circuit module DRV1 are supplied to the base substrate B1 through the BtoB connector formed by the connector CN3b-1 and the connector CN3a, and the drive signals COMAi, COMBi, COMCi and the reference voltage signal VBSi output by the drive signal output circuit 50-i of the drive circuit module DRVi are supplied to the base substrate B1 through the BtoB connector formed by the connector CN3b-i and the connector CN3a. That is, the base substrate B1 has a connection point of the power supply connection connector CN3b-1, that is, an electrode supplied with drive signals COMA1, COMB1, COMC1 and a reference voltage signal VBS1, a connection point of the power supply connection connector CN3b-2, that is, an electrode supplied with drive signals COMA2, COMB2, COMC2 and a reference voltage signal VBS2, a connection point of the power supply connection connector CN3b-3, that is, an electrode supplied with drive signals COMA3, COMB3, COMC3 and a reference voltage signal VBS3, a connection point of the power supply connection connector CN3b-4, that is, an electrode supplied with drive signals COMA4, COMB4, COMC4 and a reference voltage signal VBS4, a connection point of the power supply connection connector CN3b-5, that is, an electrode supplied with drive signals COMA5, COMB5, COMC5 and a reference voltage signal VBS5, and a connection point of the power supply connection connector CN3b-6, that is, an electrode supplied with drive signals COMA6, COMB6, COMC6 and a reference voltage signal VBS6.

[0297] In addition, when observed along the X2 axis orthogonal to the Z2 axis connecting the edge 821 and the edge 822 of the base substrate B1, the capacitor 190-1 is located between the connector CN2 and the connector CN3b-1, that is, between the connector CN2 and the electrode for electrically connecting the connector CN3b-1 and the base substrate B1, the capacitor 190-2 is located between the connector CN2 and the connector CN3b-2, that is, between the electrode for electrically connecting the connector CN2 and the connector CN3b-2 and the base substrate B1, and the capacitor 190-3 is located between the connector CN2 and the connector CN3b-3, that is, between the connector CN2 and the electrode for electrically connecting the connector CN3b-3 and the base substrate B1.

[0298] At this time, the capacitor 190-1 is arranged on the base substrate B1 in such a manner that the shortest distance between the connector CN2 and one end of the capacitor 190-1, that is, the + pole to which the reference voltage signal VBS1 is supplied, is shorter than the shortest distance between the connector CN2 and the other end of the capacitor 190-1, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-1 and one end of the capacitor 190-1, that is, the + pole to which the reference voltage signal VBS1 is supplied, is longer than the shortest distance between the connector CN3b-1 and the other end of the capacitor 190-1, that is, the - pole to which the ground signal is supplied. The capacitor 190-2 is arranged in such a manner that the shortest distance between the connector CN2 and one end of the capacitor 190-2, that is, the + pole to which the reference voltage signal VBS2 is supplied, is shorter than the shortest distance between the connector CN2 and the other end of the capacitor 190-2, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-1 and one end of the capacitor 190-1 ... longer than the shortest distance between the connector CN3b-1 and the other end of the capacitor 190-1, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-1 and one end of the capacitor 190-2, that is, the + pole to which the reference voltage signal VBS2 is supplied, is shorter than the shortest distance between the The shortest distance between connector CN3b-2 and one end of capacitor 190-2, i.e., the + pole to which the reference voltage signal VBS2 is supplied, is arranged on the base substrate B1 in such a manner that the shortest distance between connector CN3b-2 and the other end of capacitor 190-2, i.e., the - pole to which the ground signal is supplied, is longer than the shortest distance between connector CN3b-2 and the other end of capacitor 190-2, i.e., the - pole to which the ground signal is supplied. The capacitor 190-3 is arranged on the base substrate B1 in such a manner that the shortest distance between connector CN2 and one end of capacitor 190-3, i.e., the + pole to which the reference voltage signal VBS3 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-3, i.e., the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-3 and one end of capacitor 190-3, i.e., the + pole to which the reference voltage signal VBS3 is supplied, is longer than the shortest distance between connector CN3b-3 and the other end of capacitor 190-3, i.e., the - pole to which the ground signal is supplied.

[0299] Similarly, when observed along the X2 axis orthogonal to the Z2 axis connecting the edge 821 and the edge 822 of the base substrate B1, capacitor 190-4 is located between connector CN2 and connector CN3b-4, that is, between connector CN2 and the electrode for electrically connecting connector CN3b-4 and the base substrate B1, capacitor 190-5 is located between connector CN2 and connector CN3b-5, that is, between connector CN2 and the electrode for electrically connecting connector CN3b-5 and the base substrate B1, and capacitor 190-6 is located between connector CN2 and connector CN3b-6, that is, between connector CN2 and the electrode for electrically connecting connector CN3b-6 and the base substrate B1.

[0300] At this time, the capacitor 190-4 is arranged on the base substrate B1 in such a manner that the shortest distance between the connector CN2 and one end of the capacitor 190-4, that is, the + pole to which the reference voltage signal VBS4 is supplied, is shorter than the shortest distance between the connector CN2 and the other end of the capacitor 190-4, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-4 and one end of the capacitor 190-4, that is, the + pole to which the reference voltage signal VBS4 is supplied, is longer than the shortest distance between the connector CN3b-4 and the other end of the capacitor 190-4, that is, the - pole to which the ground signal is supplied, and the capacitor 190-5 is arranged in such a manner that the shortest distance between the connector CN2 and one end of the capacitor 190-5, that is, the + pole to which the reference voltage signal VBS5 is supplied, is shorter than the shortest distance between the connector CN2 and the other end of the capacitor 190-5, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-4 and one end of the capacitor 190-4 ... longer than the shortest distance between the connector CN3b-4 and the other end of the capacitor 190-4, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN2 and one end of the capacitor 190-5, that is, the + pole to which the reference voltage signal VBS5 is supplied, is shorter than the shortest distance between the connector CN The shortest distance between connector CN3b-5 and one end of capacitor 190-5, i.e., the + pole to which the reference voltage signal VBS5 is supplied, is arranged on the base substrate B1 in such a manner that the shortest distance between connector CN3b-5 and the other end of capacitor 190-5, i.e., the - pole to which the ground signal is supplied, is longer than the shortest distance between connector CN3b-5 and the other end of capacitor 190-5, i.e., the - pole to which the ground signal is supplied. The capacitor 190-6 is arranged on the base substrate B1 in such a manner that the shortest distance between connector CN2 and one end of capacitor 190-6, i.e., the + pole to which the reference voltage signal VBS6 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-6, i.e., the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-6 and one end of capacitor 190-6, i.e., the + pole to which the reference voltage signal VBS6 is supplied, is longer than the shortest distance between connector CN3b-6 and the other end of capacitor 190-6, i.e., the - pole to which the ground signal is supplied.

[0301] At this time, it is preferable that the capacitor 190-1 is located along the Z2 axis in such a manner that one end, that is, the + electrode to which the reference voltage signal VBS1 is supplied, is on the -Z2 side, and the other end, that is, the - electrode to which the ground signal is supplied, is on the +Z2 side. The capacitor 190-2 is located along the Z2 axis in such a manner that one end, that is, the + electrode to which the reference voltage signal VBS2 is supplied, is on the -Z2 side, and the other end, that is, the - electrode to which the ground signal is supplied, is on the +Z2 side. The capacitor 190-3 is located along the Z2 axis in such a manner that one end, that is, the + electrode to which the reference voltage signal VBS3 is supplied, is on the -Z2 side, and the other end, that is, the - electrode to which the ground signal is supplied, is on the +Z2 side. In the embodiment, capacitor 190-4 is located along the Z2 axis with one end, i.e., the + pole supplied with the reference voltage signal VBS4, on the -Z2 side and the other end, i.e., the - pole supplied with the ground signal, on the +Z2 side. Capacitor 190-5 is located along the Z2 axis with one end, i.e., the + pole supplied with the reference voltage signal VBS5, on the -Z2 side and the other end, i.e., the - pole supplied with the ground signal, on the +Z2 side. Capacitor 190-6 is located along the Z2 axis with one end, i.e., the + pole supplied with the reference voltage signal VBS2, on the -Z2 side and the other end, i.e., the - pole supplied with the ground signal, on the +Z2 side.

[0302] It should be noted that various electronic components other than the above-mentioned electronic components may be mounted on the base substrate B1.

[0303] Next, an example of an optimal wiring pattern formed on the base substrate B1 as a multilayer substrate, that is, an example of an optimal wiring pattern formed on the base substrate B1 for transmitting the drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6 and the reference voltage signals VBS1 to VBS6 will be described. Figure 23 1 is a diagram showing an example of a wiring pattern formed on the base substrate B1 for transmitting the drive signals COMA1 to COMA6. Figure 24 FIG. 1 is a diagram showing an example of a wiring pattern formed on the base substrate B1 for transmitting the driving signals COMB1 to COMB6. Figure 25 1 is a diagram showing an example of a wiring pattern formed on the base substrate B1 for transmitting the drive signals COMC1 to COMC6 and the reference voltage signals VBS1 to VBS3. Figure 26 1 is a diagram showing an example of a wiring pattern formed on the base substrate B1 for transmitting the reference voltage signals VBS4 to VBS6 .

[0304] like Figure 23 As shown, wirings Wca1 to Wca6 for propagating driving signals COMA1 to COMA6 are formed in an internal wiring layer 820 - k (k is any one of 1 to m-2).

[0305] Wiring Wca1 electrically connects a terminal for inputting a drive signal COMA1 to the base substrate B1 among a plurality of terminals of connector CN3b-1 electrically connected to the drive circuit module DRV1 and a terminal for supplying a drive signal COMA1 to the print head 23-1 among a plurality of terminals of connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMA1.

[0306] Wiring Wca2 is located on the -Y2 side of wiring Wca1, electrically connects a terminal for inputting a drive signal COMA2 to the base substrate B1 among a plurality of terminals of connector CN3b-2 electrically connected to the drive circuit module DRV2, and a terminal for supplying a drive signal COMA2 to the print head 23-2 among a plurality of terminals of connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMA2.

[0307] Wiring Wca3 is located on the -Y2 side of wiring Wca2, electrically connects the terminal for inputting the drive signal COMA3 to the base substrate B1 among the multiple terminals of connector CN3b-3 electrically connected to the drive circuit module DRV3, and the terminal for supplying the drive signal COMA3 to the print head 23-3 among the multiple terminals of connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMA3.

[0308] When observing the base substrate B1 from above, that is, observing the base substrate B1 along the X2 axis, the wiring Wca4 is located between the wiring Wca1 and the wiring Wca2, and electrically connects the terminal for inputting the drive signal COMA4 to the base substrate B1 among the multiple terminals of the connector CN3b-4 electrically connected to the drive circuit module DRV4 and the terminal for supplying the drive signal COMA4 to the print head 23-4 among the multiple terminals of the connector CN2 electrically connected to the ejection unit 20, thereby transmitting the drive signal COMA4.

[0309] When observing the base substrate B1 from above, that is, observing the base substrate B1 along the X2 axis, the wiring Wca5 is located between the wiring Wca2 and the wiring Wca3, electrically connecting the terminal for inputting the drive signal COMA5 to the base substrate B1 among the multiple terminals of the connector CN3b-5 electrically connected to the drive circuit module DRV5 and the terminal for supplying the drive signal COMA5 to the print head 23-5 among the multiple terminals of the connector CN2 electrically connected to the ejection unit 20, and transmitting the drive signal COMA5.

[0310] Wiring Wca6 is located on the -Y2 side of wiring Wca3, electrically connects the terminal for inputting the drive signal COMA6 to the base substrate B1 among the multiple terminals of connector CN3b-6 electrically connected to the drive circuit module DRV6, and the terminal for supplying the drive signal COMA6 to the print head 23-6 among the multiple terminals of connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMA6.

[0311] Specifically, internal wiring layer 820-k of base substrate B1 includes wiring Wca1 for propagating drive signal COMA1, wiring Wca2 for propagating drive signal COMA2, wiring Wca3 for propagating drive signal COMA3, wiring Wca4 for propagating drive signal COMA4, wiring Wca5 for propagating drive signal COMA5, and wiring Wca6 for propagating drive signal COMA6. Furthermore, within base substrate B1, wiring Wca1-Wca6 are positioned along the Y2 axis from the +Y2 side toward the -Y2 side in the order of wiring Wca1, wiring Wca4, wiring Wca2, wiring Wca5, wiring Wca3, and wiring Wca6, near connector CN2 electrically connected to ejection unit 20.

[0312] like Figure 24 As shown, wirings Wcb1 - Wcb6 for propagating driving signals COMB1 - COMB6 are formed in the inner wiring layer 820 -(k+2).

[0313] The wiring Wcb1 electrically connects a terminal for inputting a drive signal COMB1 to the base substrate B1 among a plurality of terminals of the connector CN3b-1 electrically connected to the drive circuit module DRV1 and a terminal for supplying a drive signal COMB1 to the print head 23-1 among a plurality of terminals of the connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMB1.

[0314] Wiring Wcb2 is located on the -Y2 side of wiring Wcb1, electrically connects a terminal for inputting a drive signal COMB2 to the base substrate B1 among a plurality of terminals of connector CN3b-2 electrically connected to the drive circuit module DRV2, and a terminal for supplying a drive signal COMB2 to the print head 23-2 among a plurality of terminals of connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMB2.

[0315] Wiring Wcb3 is located on the -Y2 side of wiring Wcb2, electrically connects a terminal for inputting a drive signal COMB3 to the base substrate B1 among a plurality of terminals of connector CN3b-3 electrically connected to the drive circuit module DRV3, and a terminal for supplying a drive signal COMB3 to the print head 23-3 among a plurality of terminals of connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMB3.

[0316] When observing the base substrate B1 from above, that is, observing the base substrate B1 along the X2 axis, the wiring Wcb4 is located between the wiring Wcb1 and the wiring Wcb2, and electrically connects the terminal for inputting the drive signal COMB4 to the base substrate B1 among the multiple terminals of the connector CN3b-4 electrically connected to the drive circuit module DRV4 and the terminal for supplying the drive signal COMB4 to the print head 23-4 among the multiple terminals of the connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMB4.

[0317] When observing the base substrate B1 from above, that is, observing the base substrate B1 along the X2 axis, the wiring Wcb5 is located between the wiring Wcb2 and the wiring Wcb3, electrically connecting the terminal for inputting the drive signal COMB5 to the base substrate B1 among the multiple terminals of the connector CN3b-5 electrically connected to the drive circuit module DRV5 and the terminal for supplying the drive signal COMB5 to the print head 23-5 among the multiple terminals of the connector CN2 electrically connected to the ejection unit 20, and transmitting the drive signal COMB5.

[0318] Wiring Wcb6 is located on the -Y2 side of wiring Wcb3, electrically connects a terminal for inputting a drive signal COMB6 to the base substrate B1 among a plurality of terminals of connector CN3b-6 electrically connected to the drive circuit module DRV6, and a terminal for supplying a drive signal COMB6 to the print head 23-6 among a plurality of terminals of connector CN2 electrically connected to the ejection unit 20, and transmits the drive signal COMB6.

[0319] That is, the base substrate B1 has a wiring Wcb1 for propagating the drive signal COMB1, a wiring Wcb2 for propagating the drive signal COMB2, a wiring Wcb3 for propagating the drive signal COMB3, a wiring Wcb4 for propagating the drive signal COMB4, a wiring Wcb5 for propagating the drive signal COMB5, and a wiring Wcb6 for propagating the drive signal COMB6, which are formed in the internal wiring layer 820-(k+2). The wirings Wcb1 to Wcb6 are located near the connector CN2 electrically connected to the ejection unit 20, along the Y2 axis from the +Y2 side toward the -Y2 side in the order of wiring Wcb1, wiring Wcb4, wiring Wcb2, wiring Wcb5, wiring Wcb3, and wiring Wcb6.

[0320] like Figure 25 As shown, wirings Wcc1-Wcc6 for propagating drive signals COMC1-COMC6 and wirings Wvb1-Wvb3 for propagating reference voltage signals VBS1-VBS3 are formed in internal wiring layer 820-(k+1). In other words, wirings Wcc1-Wcc6 for propagating drive signals COMC1-COMC6 and wirings Wvb1-Wvb3 for propagating reference voltage signals VBS1-VBS3 are formed in internal wiring layer 820-(k+1) located between internal wiring layer 820-k, which has wirings Wca1-Wca6 for propagating drive signals COMA1-COMA6, and internal wiring layer 820-(k+2), which has wirings Wcb1-Wcb6 for propagating drive signals COMB1-COMB6.

[0321] Wiring Wvb1 electrically connects a terminal for inputting a reference voltage signal VBS1 to the base substrate B1, among multiple terminals of connector CN3b-1 electrically connected to the drive circuit module DRV1, and a terminal for supplying the reference voltage signal VBS1 to the print head 23-1, among multiple terminals of connector CN2 electrically connected to the ejection unit 20, thereby propagating the reference voltage signal VBS1. Wiring Wvb1 is also electrically connected to the positive terminal of capacitor 190-1. Furthermore, when viewing base substrate B1 from above, i.e., along the X2 axis, within wiring Wvb1, within the range from the positive terminal of capacitor 190-1 to the terminal of connector CN2 for supplying the reference voltage signal VBS1, wiring Wvb1 overlaps with at least a portion of wiring Wca1 and at least a portion of wiring Wcb1.

[0322] Wiring Wvb2 is located on the -Y2 side of wiring Wvb1 and electrically connects a terminal for inputting a reference voltage signal VBS2 to base substrate B1, among multiple terminals of connector CN3b-2 electrically connected to drive circuit module DRV2, and a terminal for supplying reference voltage signal VBS2 to print head 23-2, among multiple terminals of connector CN2 electrically connected to ejection unit 20, thereby propagating reference voltage signal VBS2. Wiring Wvb2 is also electrically connected to the positive terminal of capacitor 190-2. Furthermore, when viewing base substrate B1 from above, i.e., when viewing base substrate B1 along the X2 axis, within wiring Wvb2, within the range from the positive terminal of capacitor 190-2 to the terminal of connector CN2 for supplying reference voltage signal VBS2, wiring Wvb2 overlaps with at least a portion of wiring Wca2 and at least a portion of wiring Wcb2.

[0323] Wiring Wvb3 is located on the -Y2 side of wiring Wvb2. It electrically connects a terminal for inputting a reference voltage signal VBS3 to the base substrate B1, among multiple terminals of connector CN3b-3 electrically connected to the drive circuit module DRV3, and a terminal for supplying the reference voltage signal VBS3 to the print head 23-3, among multiple terminals of connector CN2 electrically connected to the ejection unit 20, thereby propagating the reference voltage signal VBS3. Wiring Wvb3 is also electrically connected to the positive terminal of capacitor 190-3. Furthermore, when viewing base substrate B1 from above, i.e., when viewing base substrate B1 along the X2 axis, within wiring Wvb3, within the range from the positive terminal of capacitor 190-3 to the terminal of connector CN2 for supplying the reference voltage signal VBS3, wiring Wvb3 overlaps with at least a portion of wiring Wca3 and at least a portion of wiring Wcb3.

[0324] Wiring Wcc1 is located on the +Y2 side of wiring Wvb1 and electrically connects a terminal for inputting drive signal COMC1 to base substrate B1, among multiple terminals of connector CN3b-1 electrically connected to drive circuit module DRV1, and a terminal for supplying drive signal COMC1 to print head 23-1, among multiple terminals of connector CN2 electrically connected to ejection unit 20, thereby propagating drive signal COMC1. Wiring Wcc1 is located along wiring Wvb1, which propagates reference voltage signal VBS1.

[0325] Wiring Wcc2 is located on the -Y2 side of wiring Wvb1 and the +Y2 side of wiring Wvb2. It electrically connects the terminal for inputting drive signal COMC2 to base substrate B1, among the terminals of connector CN3b-2 electrically connected to drive circuit module DRV2, and the terminal for supplying drive signal COMC2 to print head 23-2, among the terminals of connector CN2 electrically connected to ejection unit 20, thereby transmitting drive signal COMC2. This wiring Wcc2 is located along wiring Wvb2, which transmits reference voltage signal VBS2.

[0326] Wiring Wcc3 is located on the -Y2 side of wiring Wvb2 and the +Y2 side of wiring Wvb3. It electrically connects the terminal for inputting drive signal COMC3 to base substrate B1, among the terminals of connector CN3b-3 electrically connected to drive circuit module DRV3, and the terminal for supplying drive signal COMC3 to print head 23-3, among the terminals of connector CN2 electrically connected to ejection unit 20, thereby transmitting drive signal COMC3. This wiring Wcc3 is located along wiring Wvb3, which transmits reference voltage signal VBS3.

[0327] Wiring Wcc4 is located on the -Y2 side of wiring Wvb1 and the +Y2 side of wiring Wcc2. It electrically connects the terminal for inputting drive signal COMC4 to base substrate B1, among the terminals of connector CN3b-4 electrically connected to drive circuit module DRV4, and the terminal for supplying drive signal COMC4 to print head 23-4, among the terminals of connector CN2 electrically connected to ejection unit 20, thereby transmitting drive signal COMC4. Wiring Wcc1 is located along wiring Wvb1, which transmits reference voltage signal VBS1.

[0328] Wiring Wcc5 is located on the -Y2 side of wiring Wvb2 and the +Y2 side of wiring Wcc3. It electrically connects the terminal for inputting drive signal COMC5 to base substrate B1, among the terminals of connector CN3b-5 electrically connected to drive circuit module DRV5, and the terminal for supplying drive signal COMC5 to print head 23-5, among the terminals of connector CN2 electrically connected to ejection unit 20, thereby transmitting drive signal COMC5. Wiring Wcc5 is located along wiring Wvb2, which transmits reference voltage signal VBS2.

[0329] Wiring Wcc6 is located on the -Y2 side of wiring Wvb3 and electrically connects a terminal for inputting drive signal COMC6 to base substrate B1, among multiple terminals of connector CN3b-6 electrically connected to drive circuit module DRV6, and a terminal for supplying drive signal COMC6 to print head 23-6, among multiple terminals of connector CN2 electrically connected to ejection unit 20, thereby propagating drive signal COMC6. Wiring Wcc6 is located along wiring Wvb3, which propagates reference voltage signal VBS3.

[0330] That is, the base substrate B1 has a wiring Wcc1 for propagating the driving signal COMC1, a wiring Wcc2 for propagating the driving signal COMC2, a wiring Wcc3 for propagating the driving signal COMC3, a wiring Wcc4 for propagating the driving signal COMC4, a wiring Wcc5 for propagating the driving signal COMC5, and a wiring Wcc6 for propagating the driving signal COMC6, as well as a wiring Wvb1 for propagating the reference voltage signal VBS1, a wiring Wvb2 for propagating the reference voltage signal VBS2, and a wiring Wcc3 for propagating the driving signal COMC3. Wiring Wvb2 for propagating quasi-voltage signal VBS2, wiring Wvb3 for propagating reference voltage signal VBS3, and wirings Wcc1 to Wcc6 and Wvb1 to Wvb3 are located near connector CN2, which is electrically connected to ejection unit 20, in the order of wiring Wcc1, wiring Wvb1, wiring Wcc4, wiring Wcc2, wiring Wvb2, wiring Wcc5, wiring Wcc3, wiring Wvb3, and wiring Wcc6, from the +Y2 side toward the -Y2 side along the Y2 axis. Furthermore, when viewing base substrate B1 from above, that is, when viewing base substrate B1 along the X2 axis, wiring Wvb1 overlaps at least partially with wiring Wca1 and wiring Wcb1, and wiring Wvb2 overlaps at least partially with wiring Wca2 and wiring Wcb2.

[0331] like Figure 26 As shown, wirings Wvb4 to Wvb6 for propagating reference voltage signals VBS4 to VBS6 and a wiring Wvhv for propagating voltage signal VHV are formed in the surface wiring layer 812 .

[0332] Wiring Wvb4 electrically connects a terminal for inputting a reference voltage signal VBS4 to the base substrate B1, among multiple terminals of connector CN3b-4 electrically connected to drive circuit module DRV4, and a terminal for supplying a reference voltage signal VBS4 to print head 23-4, among multiple terminals of connector CN2 electrically connected to ejection unit 20, thereby transmitting reference voltage signal VBS4. Wiring Wvb4 is also electrically connected to the positive terminal of capacitor 190-4.

[0333] Wiring Wvb5 is located on the -Y2 side of wiring Wvb4 and electrically connects a terminal for inputting a reference voltage signal VBS5 to the base substrate B1, among multiple terminals of connector CN3b-5 electrically connected to drive circuit module DRV5, and a terminal for supplying a reference voltage signal VBS5 to print head 23-5, among multiple terminals of connector CN2 electrically connected to ejection unit 20, thereby transmitting reference voltage signal VBS5. Wiring Wvb5 is also electrically connected to the positive terminal of capacitor 190-5.

[0334] Wiring Wvb6 is located on the -Y2 side of wiring Wvb5, electrically connects a terminal for inputting a reference voltage signal VBS6 to the base substrate B1 among a plurality of terminals of connector CN3b-6 electrically connected to the drive circuit module DRV6, and a terminal for supplying a reference voltage signal VBS6 to the print head 23-6 among a plurality of terminals of connector CN2 electrically connected to the ejection unit 20, and propagates the reference voltage signal VBS6.

[0335] One end of wiring Wvhv is electrically connected to coil 152a and capacitor 153a included in first step-down circuit 150a. Thus, wiring Wvhv propagates voltage signal VHV generated in first step-down circuit 150a. Furthermore, wiring Wvhv is electrically connected to the positive terminals of capacitors 110-1 to 110-6 and to connectors CN3b-1 to CN3b-6. Thus, the voltage signal VHV propagating through wiring Wvhv is supplied to drive circuit modules DRV1 to DRV6, respectively. Furthermore, wiring Wvhv bypasses the +Y2 side of wiring Wvb4 and is also electrically connected to connector CN2. Thus, the voltage signal VHV propagating through wiring Wvhv is also supplied to ejection unit 20.

[0336] That is, the surface wiring layer 812 of the base substrate B1 includes wiring Wvb4 for propagating the reference voltage signal VBS4, wiring Wvb5 for propagating the reference voltage signal VBS5, wiring Wvb6 for propagating the reference voltage signal VBS6, and wiring Wvhv for propagating the voltage signal VHV.

[0337] As described above, among the capacitors 190-1 to 190-6 provided on the base substrate B1, capacitors 190-1 to 190-3 are located farther from the connector CN2 electrically connected to the ejection unit 20 than capacitors 190-4 to 190-6. That is, the shortest distance between connector CN2 and capacitors 190-1 to 190-3 is longer than the shortest distance between connector CN2 and capacitors 190-4 to 190-6.

[0338] At this time, the wiring Wvb1 that electrically connects the capacitor 190-1 and the connector CN2 located at a position away from the connector CN2 and transmits the reference voltage signal VBS1 is set in the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, the wiring Wca1 for transmitting the drive signal COMA1 input to the print head 23-1 supplied with the reference voltage signal VBS1 is set in the internal wiring layer 820-(k+1) adjacent to the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, and the wiring Wcb1 for transmitting the drive signal COMB1 input to the print head 23-1 supplied with the reference voltage signal VBS1 is set in the internal wiring layer 820-(k+2) adjacent to the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820. When the base substrate B1 is observed along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, the wiring Wvb1 at least partially overlaps with the wiring Wca1 and the wiring Wcb1.

[0339] Similarly, the wiring Wvb2 that electrically connects the capacitor 190-2 and the connector CN2 located at a position away from the connector CN2 and transmits the reference voltage signal VBS2 is provided in the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, the wiring Wca2 for transmitting the drive signal COMA2 input to the print head 23-2 supplied with the reference voltage signal VBS2 is provided in the internal wiring layer 820-(k+1) adjacent to the internal wiring layer 820 among the multiple internal wiring layers 820, and the wiring Wcb2 for transmitting the drive signal COMB2 input to the print head 23-2 supplied with the reference voltage signal VBS2 is provided in the internal wiring layer 820-(k+2) adjacent to the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820. When the base substrate B1 is observed along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, the wiring Wvb2 overlaps with at least a portion of the wiring Wca2 and the wiring Wcb2.

[0340] Similarly, the wiring Wvb3 that electrically connects the capacitor 190-3 and the connector CN2 located at a position away from the connector CN2 and transmits the reference voltage signal VBS3 is provided in the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, the wiring Wca3 for transmitting the drive signal COMA3 input to the print head 23-3 supplied with the reference voltage signal VBS3 is provided in the internal wiring layer 820-(k+1) adjacent to the internal wiring layer 820 among the multiple internal wiring layers 820, and the wiring Wcb3 for transmitting the drive signal COMB3 input to the print head 23-3 supplied with the reference voltage signal VBS3 is provided in the internal wiring layer 820-(k+2) adjacent to the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820. When the base substrate B1 is observed along the normal direction of the surface 801 of the base substrate B1, that is, the X2 axis, the wiring Wvb3 overlaps with at least a portion of the wiring Wca3 and the wiring Wcb3.

[0341] That is, the wirings Wvb1 to Wvb3 for propagating the reference voltage signals VBS1 to VBS3 outputted through the capacitors 190-1 to 190-3 located at a position away from the connector CN2 are located adjacent to the wirings Wca1 to Wca3 for propagating the corresponding drive signals COMA1 to COMA3 and the wirings Wcb1 to Wcb3 for propagating the corresponding drive signals COMB1 to COMB3.

[0342] On the other hand, the wiring Wvb4 that electrically connects the capacitor 190-4 located near the connector CN2 and the connector CN2 and transmits the reference voltage signal VBS4 is set in the surface wiring layer 812 formed on the surface 802 where the capacitor 190-4 is provided, the wiring Wvb5 that electrically connects the capacitor 190-5 located near the connector CN2 and the connector CN2 and transmits the reference voltage signal VBS5 is set in the surface wiring layer 812 formed on the surface 802 where the capacitor 190-5 is provided, and the wiring Wvb6 that electrically connects the capacitor 190-6 located near the connector CN2 and the connector CN2 and transmits the reference voltage signal VBS6 is set in the surface wiring layer 812 formed on the surface where the capacitor 190-6 is provided.

[0343] Furthermore, a wiring Wvhv for propagating a voltage signal VHV is provided in the surface wiring layer 812 provided with wirings Wvb4 to Wvb6 for electrically connecting capacitors 190 - 4 to 190 - 6 located near connector CN2 and connector CN2 and propagating reference voltage signals VBS4 to VBS6 .

[0344] Here, print head 23-1 is an example of a first print head, piezoelectric element 60 included in print head 23-1 is an example of a first drive element, at least one of drive circuits 52a1, 52b1, and 52c1 is an example of a first drive circuit, reference voltage signal output circuit 460 included in at least one of drive circuits 52a1, 52b1, and 52c1 is an example of a first reference voltage signal output circuit, and drive circuit board DRB on which drive circuits 52a1, 52b1, and 52c1 are mounted is an example of a drive circuit board. Furthermore, print head 23-2 is an example of a second print head, piezoelectric element 60 included in print head 23-2 is an example of a second drive element, at least one of drive circuits 52a2, 52b2, and 52c2 is an example of a second drive circuit, and reference voltage signal output circuit 460 included in at least one of drive circuits 52a2, 52b2, and 52c2 is an example of a second reference voltage signal output circuit. Furthermore, base substrate B1 is an example of a wiring substrate, side 821 is an example of a first side, side 822 is an example of a second side, surface 801 is an example of a first surface, surface 802 is an example of a second surface, and electrodes formed on base substrate B1 of power supply connector CN3b-1, through which any one of drive signals COMA1, COMB1, and COMC1 propagates, are examples of first supply points. Electrodes formed on base substrate B1 of power supply connector CN3b-2, through which any one of drive signals COMA2, COMB2, and COMC2 propagates, are examples of second supply points. Any one of drive signals COMA1, COMB1, and COMC1 is an example of a first drive signal, reference voltage signal VBS1 is an example of a first reference voltage signal, any one of drive signals COMA2, COMB2, and COMC2 is an example of a second drive signal, and reference voltage signal VBS2 is an example of a second reference voltage signal. Connector CN2 is an example of an output connector, capacitor 190-1 is an example of a first capacitor, one end of the electrodes of capacitor 190-1, i.e., the electrode to which reference voltage signal VBS1 is supplied, is an example of a first electrode, the other end of the electrodes of capacitor 190-1, i.e., the electrode to which a ground signal is supplied, is an example of a second electrode, capacitor 190-2 is an example of a third capacitor, one end of the electrodes of capacitor 190-2, i.e., the electrode to which reference voltage signal VBS2 is supplied, is an example of a fifth electrode, and the other end of the electrodes of capacitor 190-2, i.e., the electrode to which a ground signal is supplied, is an example of a sixth electrode, and the Z2 axis is an example of a first axis, and the X2 axis is an example of a second axis.

[0345] 4. Effects

[0346] In the liquid ejection device 1 of this embodiment configured as described above, the drive unit 10 of the head unit 5 includes a first step-down circuit 150a that steps down an externally supplied voltage signal VDC to output a voltage signal VHV, and a second step-down circuit 150b that steps down the externally supplied voltage signal VDC to output a voltage signal VDD. Furthermore, the amplifier circuit 550 and demodulation circuit 560 of the drive circuit 52 output a drive signal COM corresponding to the voltage signal VHV stepped down by the first step-down circuit 150a. The integrated circuit 500 of the drive circuit 52 outputs amplification control signals Hgd and Lgd based on the voltage signal VDD stepped down by the second step-down circuit 150b, thereby controlling the drive of the amplifier circuit 550.

[0347] In such a head unit 5, since the drive unit 10 included in the head unit 5 generates the voltage signal VHV by stepping down the voltage signal VDC input from the outside, even if the voltage value of the voltage signal VDC input to the head unit 5 fluctuates along the propagation path of the voltage signal VDC, the accuracy of the voltage signal VHV input to the amplifier circuit 550 and the demodulation circuit 560 included in the drive circuit 52 can be improved. Therefore, even if the propagation path of the voltage signal VDC input to the head unit 5 becomes longer as the liquid ejection device 1 increases in size, and the voltage value of the voltage signal VDC input to the head unit 5 fluctuates, the likelihood of such voltage value fluctuations contributing to the signal waveform of the drive signal COM output by the amplifier circuit 550 and the demodulation circuit 560 included in the drive circuit 52 is reduced, thereby improving the accuracy of the signal waveform of the drive signal COM output by the amplifier circuit 550 and the demodulation circuit 560 included in the drive circuit 52. As a result, even when the liquid ejecting apparatus 1 is increased in size, the possibility of a decrease in the accuracy of ejecting ink from the ejecting unit 20 that ejects ink in response to the drive signal VOUT based on the drive signal COM is reduced.

[0348] In addition, in the liquid ejection device 1 of the present embodiment, since the possibility of a decrease in the accuracy of ink ejected from the ejection unit 20 that ejects ink according to the drive signal VOUT based on the drive signal COM is reduced even when the liquid ejection device 1 is enlarged, the possibility of a decrease in the accuracy of ink ejected from the ejection unit 20 is reduced even when the liquid ejection device 1 is a large machine in which the wiring length of the cable connecting the control unit 2 and the head unit 5 is more than 2 m, or when the liquid ejection device 1 is a line printer.

[0349] Furthermore, in the liquid ejection device 1 of this embodiment, the integrated circuit 500 provided in the drive unit 10 controls whether the first step-down circuit 150a outputs the voltage signal VHV obtained by stepping down the voltage signal VDC. In other words, the supply of the voltage signal VHV to the head unit 5 is controlled regardless of the control unit 2. Thus, even if the liquid ejection device 1 is enlarged and includes multiple head units 5, the supply of the voltage signal VHV, the drive signal COM, and the reference voltage signal VBS to the ejection unit 20 can be controlled at appropriate timing and in a short period of time.

[0350] Furthermore, in the liquid ejection device 1 of this embodiment, the first step-down circuit 150a includes a soft start function that gradually increases the voltage value of the output voltage signal VHV when it begins outputting the voltage signal VHV obtained by stepping down the voltage signal VDC. This reduces the likelihood of an inrush current being generated when the first step-down circuit 150a begins outputting the voltage signal VHV obtained by stepping down the voltage signal VDC. Therefore, even if the head unit 5 includes the first step-down circuit 150a that outputs the voltage signal VHV by stepping down the externally supplied voltage signal VDC, there is no need to provide an inrush current mitigation circuit within the head unit 5, enabling a more compact head unit 5.

[0351] Furthermore, in the head unit 5 of the liquid ejection device 1 of this embodiment, a drive signal VOUT based on the drive signals COMA1, COMB1, and COMC1 output by the drive circuits 52a1, 52b1, and 52c1 is supplied to one end of the piezoelectric element 60 of the print head 23-1, and a reference voltage signal VBS1 output by the reference voltage signal output circuit 460 is supplied to the other end of the piezoelectric element 60 of the print head 23-1. In such a liquid ejection device 1, when the piezoelectric element 60 of the print head 23-1 is driven, the current flowing from the drive circuits 52a1, 52b1, and 52c1 is output, passes through the piezoelectric element 60, and one end of the capacitor 190-1, and is fed back to the drive circuits 52a1, 52b1, and 52c1 via the other end of the capacitor 190-1, to which a ground signal is supplied.

[0352] In the liquid ejection device 1 of this embodiment, in the drive unit 10 including the drive circuits 52a1, 52b1, and 52c1 and the capacitor 190-1, the capacitor 190-1, which is supplied with a reference voltage signal VBS1 at one end and a ground signal at the other end, is arranged between the connector CN3b-1 for connecting the drive circuits 52a1, 52b1, and 52c1 and the connector CN2 electrically connected to the print head 23-1, with the end supplied with the reference voltage signal VBS1 on the connector CN2 side and the end supplied with the ground signal on the connector CN3b-1 side. This shortens the feedback path for the current flowing through the piezoelectric element 60 of the print head 23-1 when it is driven, from the other end of the capacitor 190-1 to the drive circuits 52a1, 52b1, and 52c1 via the wiring pattern for the ground signal. Consequently, the inductance component generated by the current flowing through the piezoelectric element 60 when it is driven is reduced. Therefore, the possibility of distortion in the signal waveforms of the drive signals COMA1, COMB1, and COMC1 that drive the piezoelectric element 60 due to the inductance component generated by the current flowing when the piezoelectric element 60 is driven is reduced. As a result, the waveform accuracy of the drive signal VOUT corresponding to the drive signals COMA1, COMB1, and COMC1 that drive the piezoelectric element 60 is improved.

[0353] At this time, by positioning one end and the other end of capacitor 190-1 along the Z2 axis connecting side 821 and side 822, the feedback path for the current flowing from the other end of capacitor 190-1 to the drive circuits 52a1, 52b1, and 52c1 when the piezoelectric element 60 of print head 23-1 is driven can be further shortened. This further reduces the inductance component generated by the current flowing through the piezoelectric element 60 when it is driven, further reducing the likelihood of distortion in the signal waveforms of the drive signals COMA1, COMB1, and COMC1 that drive the piezoelectric element 60 due to the inductance component. Consequently, the waveform accuracy of the drive signal VOUT corresponding to the drive signals COMA1, COMB1, and COMC1 that drive the piezoelectric element 60 is further improved.

[0354] In addition, as shown in the liquid ejection device 1 of the present embodiment, when the head unit 5 has print heads 23-2 to 23-6 in addition to the print head 23-1, by configuring the capacitors 190-2 to 190-6 in such a manner that one end of the capacitors 190-2 to 190-6 supplied with the corresponding reference voltage signals VBS2 to VBS6 is on the side of the connector CN2 electrically connected to the print heads 23-2 to 23-6, and one end of the capacitors 190-2 to 190-6 supplied with the ground signal is on the side of the corresponding connector CN3b-2 to CN3b-6, it is possible to shorten the feedback path for feeding back the current flowing through when the piezoelectric elements respectively possessed by the capacitors 190-2 to 190-6 are driven.

[0355] This also reduces the inductance component generated by the current flowing through the piezoelectric elements 60 of the print heads 23-2 to 23-6 when the piezoelectric elements 60 are driven. Consequently, the likelihood of distortion in the signal waveforms of the drive signals COMA2 to COMA6, COMB2 to COMB6, and COMC2 to COMC6 that drive the piezoelectric elements 60 of the print heads 23-2 to 23-6 is also reduced.

[0356] Furthermore, the head unit 5 of the liquid ejection device 1 of the present embodiment includes: a print head 23-1, including a piezoelectric element 60 having one end supplied with a drive signal VOUT based on drive signals COMA1, COMB1, and COMC1 and another end supplied with a reference voltage signal VBS1 having a constant voltage value, and ejecting ink in response to the driving of the piezoelectric element 60; a print head 23-4, including a piezoelectric element 60 having one end supplied with a drive signal VOUT based on drive signals COMA4, COMB4, and COMC4 and another end supplied with a reference voltage signal VBS4 having a constant voltage value, and ejecting ink in response to the driving of the piezoelectric element 60; and a drive unit 10, which supplies the drive signals COMA1, COMB1, and COMC1 and the reference voltage signal VBS1 to the print head 23-1 and outputs the drive signals COMA4, COMB4, and COMC4 and the reference voltage signal VBS4 to the print head 23-4, wherein the drive circuit 10 includes: drive circuits 52a1, 52b1 , 52c1, output drive signals COMA1, COMB1, COMC1; reference voltage signal output circuit 460, possessed by drive signal output circuit 50-1 that outputs reference voltage signal VBS1; capacitor 190-1, one end of which is supplied with reference voltage signal VBS1, and the other end of which is supplied with ground signal; drive circuits 52a4, 52b4, 52c4, output drive signals COMA4, COMB4, COMC4; reference voltage signal output circuit 460, possessed by drive signal output circuit 504 that outputs reference voltage signal VBS4; capacitor 190-4, one end of which is supplied with reference voltage signal VBS4, and the other end of which is supplied with ground signal; connector CN2, electrically connected to print head 23-1 and print head 23-4; and base substrate B1, provided with connector CN2, for transmission of drive signals COMA1, COMB1, COMC1, drive signals COMA1, COMB1, COMC1 and reference voltage signals VBS1, VBS4.

[0357] In the base substrate B1 of the head unit 5, wiring Wvb1, which electrically connects capacitor 190-1, located away from connector CN2, and connector CN2 and propagates reference voltage signal VBS1 supplied to print head 23-1, is provided in internal wiring layer 820-(k+1). Wiring Wca1, which propagates drive signal COMA1 supplied to print head 23-1, is provided in internal wiring layer 820-k, adjacent to internal wiring layer 820-(k+1). Wiring Wcb1, which propagates drive signal COMB1 supplied to print head 23-1, is provided in internal wiring layer 820-(k+2), adjacent to internal wiring layer 820-(k+1). Furthermore, when viewed from the normal to surface 801 of base substrate B1, wiring Wvb1 at least partially overlaps with wiring Wca1 and wiring Wcb1.

[0358] As previously described, when the piezoelectric element 60 of print head 23-1 is driven, the current flowing is output from the drive circuits 52a1, 52b1, and 52c1. This current is fed back to the drive circuits 52a1, 52b1, and 52c1 via the piezoelectric element 60, one end of capacitor 190-1, and the other end of capacitor 190-1, which is supplied with a ground signal. At this time, the current flowing in wiring Wvb1 is in the opposite direction to the current flowing in wiring Wca1 and wiring Wcb1. Therefore, the magnetic fields generated by the current flowing through the piezoelectric element 60 of print head 23-1 when it is driven cancel each other out. This reduces the effect of the inductance component on the drive signals COMA1 and COMB1 supplied to print head 23-1. As a result, the likelihood of distortion in the signal waveforms of the drive signals COMA1 and COMB1 supplied to print head 23-1 is reduced.

[0359] On the other hand, wiring Wvb4, which electrically connects capacitor 190-4 located near connector CN2 and connector CN2 and propagates reference voltage signal VBS4 supplied to print head 23-4, is provided in surface wiring layer 812 formed on surface 802 where capacitor 190-4 is provided. This reduces the number of through-holes provided in the propagation path for reference voltage signal VBS4. Near connector CN2, the wiring for signals propagating through connector CN2 is densely packed. If through-holes were provided near connector CN2, which has such dense wiring, a wiring pattern would need to be laid out for the propagation of signals input to connector CN2. This could hinder the miniaturization of base substrate B1 and complicate the layout of the wiring pattern, increasing the likelihood that noise, etc., would be superimposed on the signals input to connector CN2. That is, in the head unit 5 of this embodiment, by providing the wiring Wvb4 for electrically connecting the capacitor 190-4 located near the connector CN2 and the connector CN2 and for propagating the reference voltage signal VBS4 supplied to the print head 23-4 in the surface wiring layer 812 formed in the surface 802 on which the capacitor 190-4 is provided, the number of through holes provided in the propagation path for propagating the reference voltage signal VBS4 can be reduced. As a result, the base substrate B1 can be miniaturized and the possibility of noise and the like being superimposed on the signal input to the connector CN2 is reduced.

[0360] As described above, in the head unit 5 of the present embodiment, the wiring Wvb1 for electrically connecting the capacitor 190-1 located at a position away from the connector CN2 and the connector CN2 and for propagating the reference voltage signal VBS1 supplied to the print head 23-1, the wiring Wca1 for propagating the drive signal COMA1 supplied to the print head 23-1, and the wiring Wcb1 for propagating the drive signal COMB1 are arranged so as to at least partially overlap in adjacent wiring layers when viewed from the normal direction of the surface 801 of the base substrate B1, and the wiring Wvb4 for electrically connecting the capacitor 190-4 located near the connector CN2 and the connector CN2 and for propagating the reference voltage signal VBS4 supplied to the print head 23-4 is arranged in the same wiring layer as the capacitor 190-4, thereby achieving a balance between miniaturization of the base substrate B1 and improvement of signal accuracy.

[0361] 5. Modifications

[0362] In the liquid ejection device 1 and the head unit 5 of the present embodiment described above, the drive unit 10 may also have a capacitor 190-1a connected in parallel with the capacitor 190-1, a capacitor 190-2a connected in parallel with the capacitor 190-2, a capacitor 190-3a connected in parallel with the capacitor 190-3, a capacitor 190-4a connected in parallel with the capacitor 190-4, a capacitor 190-5a connected in parallel with the capacitor 190-5, and a capacitor 190-6a connected in parallel with the capacitor 190-6.

[0363] That is, the driving unit 10 may also include: a capacitor 190-1a, one end of which, i.e., the + pole, is supplied with a reference voltage signal VBS1, and the other end, i.e., the - pole, is supplied with a ground signal; a capacitor 190-2a, one end of which, i.e., the + pole, is supplied with a reference voltage signal VBS2, and the other end, i.e., the - pole, is supplied with a ground signal; 190-3a, one end of which, i.e., the + pole, is supplied with a reference voltage signal VBS3, and the other end, i.e., the - pole, is supplied with a ground signal; 190-4a, one end of which, i.e., the + pole, is supplied with a reference voltage signal VBS4, and the other end, i.e., the - pole, is supplied with a ground signal; 190-5a, one end of which, i.e., the + pole, is supplied with a reference voltage signal VBS5, and the other end, i.e., the - pole, is supplied with a ground signal; and 190-6a, one end of which, i.e., the + pole, is supplied with a reference voltage signal VBS6, and the other end, i.e., the - pole, is supplied with a ground signal.

[0364] In this case, when observing the base substrate B1 along the X2 axis, the capacitor 190-1a connected in parallel with the capacitor 190-1 is located between the connector CN2 and the connector CN3b-1, that is, between the connector CN2 and the electrode for electrically connecting the connector CN3b-1 and the base substrate B1, and is arranged on the base substrate B1 in such a manner that the shortest distance between the connector CN2 and one end of the capacitor 190-1a, that is, the + pole to which the reference voltage signal VBS1 is supplied, is shorter than the shortest distance between the connector CN2 and the other end of the capacitor 190-1a, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-1 and one end of the capacitor 190-1a, that is, the + pole to which the reference voltage signal VBS1 is supplied, is longer than the shortest distance between the connector CN3b-1 and the other end of the capacitor 190-1a, that is, the - pole to which the ground signal is supplied.

[0365] Similarly, when observing the base substrate B1 along the X2 axis, the capacitor 190-2a connected in parallel with the capacitor 190-2 is located between the connector CN2 and the connector CN3b-2, that is, between the connector CN2 and the electrode for electrically connecting the connector CN3b-2 and the base substrate B1, and is arranged on the base substrate B1 in such a manner that the shortest distance between the connector CN2 and one end of the capacitor 190-2a, that is, the + pole to which the reference voltage signal VBS2 is supplied, is shorter than the shortest distance between the connector CN2 and the other end of the capacitor 190-2a, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-2 and one end of the capacitor 190-2a, that is, the + pole to which the reference voltage signal VBS2 is supplied, is longer than the shortest distance between the connector CN3b-2 and the other end of the capacitor 190-2a, that is, the - pole to which the ground signal is supplied.

[0366] Similarly, when observing the base substrate B1 along the X2 axis, the capacitor 190-3a connected in parallel with the capacitor 190-3 is located between the connector CN2 and the connector CN3b-3, that is, between the connector CN2 and the electrode for electrically connecting the connector CN3b-3 to the base substrate B1, and is arranged on the base substrate B1 in such a manner that the shortest distance between the connector CN2 and one end of the capacitor 190-3a, that is, the + pole to which the reference voltage signal VBS3 is supplied, is shorter than the shortest distance between the connector CN2 and the other end of the capacitor 190-3a, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-3 and one end of the capacitor 190-3a, that is, the + pole to which the reference voltage signal VBS3 is supplied, is longer than the shortest distance between the connector CN3b-3 and the other end of the capacitor 190-3a, that is, the - pole to which the ground signal is supplied.

[0367] Similarly, when observing the base substrate B1 along the X2 axis, the capacitor 190-4a connected in parallel with the capacitor 190-4 is located between the connector CN2 and the connector CN3b-4, that is, between the connector CN2 and the electrode for electrically connecting the connector CN3b-4 to the base substrate B1, and is arranged on the base substrate B1 in such a manner that the shortest distance between the connector CN2 and one end of the capacitor 190-4a, that is, the + pole to which the reference voltage signal VBS4 is supplied, is shorter than the shortest distance between the connector CN2 and the other end of the capacitor 190-4a, that is, the - pole to which the ground signal is supplied, and the shortest distance between the connector CN3b-4 and one end of the capacitor 190-4a, that is, the + pole to which the reference voltage signal VBS4 is supplied, is longer than the shortest distance between the connector CN3b-4 and the other end of the capacitor 190-4a, that is, the - pole to which the ground signal is supplied.

[0368] Similarly, capacitor 190-5a connected in parallel with capacitor 190-5 is located between connector CN2 and connector CN3b-5, that is, between connector CN2 and the electrode for electrically connecting connector CN3b-5 to the base substrate B1, and is arranged on the base substrate B1 in such a manner that the shortest distance between connector CN2 and one end of capacitor 190-5a, that is, the + pole to which the reference voltage signal VBS5 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-5a, that is, the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-5 and one end of capacitor 190-5a, that is, the + pole to which the reference voltage signal VBS5 is supplied, is longer than the shortest distance between connector CN3b-5 and the other end of capacitor 190-5a, that is, the - pole to which the ground signal is supplied.

[0369] Similarly, capacitor 190-6a connected in parallel with capacitor 190-6 is located between connector CN2 and connector CN3b-6, that is, between connector CN2 and the electrode for electrically connecting connector CN3b-6 to the base substrate B1, and is arranged on the base substrate B1 in such a manner that the shortest distance between connector CN2 and one end of capacitor 190-6a, that is, the + pole to which the reference voltage signal VBS6 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-6a, that is, the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-6 and one end of capacitor 190-6a, that is, the + pole to which the reference voltage signal VBS6 is supplied, is longer than the shortest distance between connector CN3b-6 and the other end of capacitor 190-6a, that is, the - pole to which the ground signal is supplied.

[0370] Even the liquid ejecting device 1 and the head unit 5 configured as described above can achieve the same operational effects as those of the above-described embodiment.

[0371] Here, capacitor 190-1a is an example of a second capacitor, the electrode at one end of the electrodes of capacitor 190-1a, that is, the electrode supplied with the reference voltage signal VBS1, is an example of a third electrode, and the electrode at the other end of the electrodes of capacitor 190-1a, that is, the electrode supplied with the ground signal, is an example of a fourth electrode.

[0372] In addition, in the liquid ejection device 1 and the head unit 5 of the present embodiment described above, although it is described that the drive circuit modules DRV1~DRV6 generate the drive signals COMA1~COMA6, COMB1~COMB6, COMC1~COMC6 and the reference voltage signals VBS1~VBS6, and supply the generated drive signals COMA1~COMA6, COMB1~COMB6, COMC1~COMC6 and the reference voltage signals VBS1~VBS6 to the base substrate B1 through the BtoB connector, the drive signal output circuits 50-1~50-6 that generate and output the drive signals COMA1~COMA6, COMB1~COMB6, COMC1~COMC6 and the reference voltage signals VBS1~VBS6 can also be installed on the surface 801 of the base substrate B1.

[0373] Even in this case, the same operational effects as those of the above-described embodiment can be achieved.

[0374] In this case, the electrode at the other end of the coil 561 formed on the base substrate B1 and connected to any one of the driving circuits 52a1, 52b1, 52c1 and supplying power, or the electrode at one end of the capacitor 562 of any one of the driving circuits 52a1, 52b1, 52c1 is an example of a first supply point, and the electrode at the other end of the coil 561 formed on the base substrate B1 and connected to any one of the driving circuits 52a, 52b2, 52c2 and supplying power, or the electrode at one end of the capacitor 562 of any one of the driving circuits 52a2, 52b2, 52c2 is an example of a second supply point.

[0375] While the embodiments and modifications have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit and scope of the present invention. For example, the above embodiments can be appropriately combined.

[0376] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purpose and effects). Furthermore, the present invention includes configurations obtained by replacing non-essential portions of the configurations described in the embodiments. Furthermore, the present invention includes configurations that can achieve the same functions and effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. Furthermore, the present invention includes configurations obtained by adding known technologies to the configurations described in the embodiments.

[0377] The following can be derived from the above-mentioned embodiments.

[0378] One embodiment of the head unit comprises:

[0379] The first print head includes a first drive element having one end supplied with a first drive signal and the other end supplied with a first reference voltage signal having a constant voltage value, and ejects liquid in response to driving of the first drive element; and

[0380] a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head;

[0381] The driving unit comprises:

[0382] a first driving circuit, outputting the first driving signal;

[0383] A first reference voltage signal output circuit, outputting the first reference voltage signal;

[0384] an output connector electrically connected to the first print head;

[0385] a first capacitor, a first electrode of the first capacitor being supplied with the first reference voltage signal, and a second electrode of the first capacitor being supplied with a ground signal; and

[0386] A wiring substrate is provided with the output connector and is used for transmitting the first drive signal and the first reference voltage signal.

[0387] The wiring substrate includes a first side, a second side located opposite to the first side, and a first supply point to which the first drive signal is supplied.

[0388] The first capacitor is located between the output connector and the first supply point when viewed along a second axis orthogonal to a first axis connecting the first side and the second side,

[0389] The shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode.

[0390] The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

[0391] In this head unit, the feedback path through which the current generated by the first drive signal supplied by the first drive circuit to the first drive element is fed back to the first drive circuit can be shortened. As a result, the inductance component of the current generated by the first drive signal supplied by the first drive circuit to the first drive element in the current path is reduced, thereby reducing the likelihood of distortion in the signal waveform of the first drive signal supplied to the first drive element caused by this inductance component.

[0392] In one embodiment of the head unit, it may be possible that:

[0393] The first electrode and the second electrode are located at positions along the first axis.

[0394] In this head unit, the feedback path through which the current generated by the first drive signal supplied by the first drive circuit to the first drive element is fed back to the first drive circuit can be further shortened. As a result, the inductance component of the current generated by the first drive signal supplied by the first drive circuit to the first drive element in the current path is further reduced, further reducing the likelihood of distortion in the signal waveform of the first drive signal supplied to the first drive element caused by this inductance component.

[0395] In one embodiment of the head unit, it may be possible that:

[0396] The driving unit comprises:

[0397] a second capacitor, a third electrode of the second capacitor being supplied with the first reference voltage signal, and a fourth electrode of the second capacitor being supplied with a ground signal,

[0398] When viewed along the second axis, the second capacitor is located between the output connector and the first supply point,

[0399] The shortest distance between the output connector and the third electrode is shorter than the shortest distance between the output connector and the fourth electrode.

[0400] The shortest distance between the first supply point and the third electrode is longer than the shortest distance between the first supply point and the fourth electrode.

[0401] In this head unit, even when a second capacitor is provided in addition to the plurality of first capacitors in the current path of the current generated by the first drive signal supplied by the first drive circuit to the first drive element, the feedback path through which the current generated by the first drive signal supplied by the first drive circuit to the first drive element is fed back to the first drive circuit can be shortened. This reduces the inductance component of the current generated by the first drive signal in the current path, thereby reducing the likelihood of distortion in the signal waveform of the first drive signal supplied to the first drive element caused by this inductance component.

[0402] In one embodiment of the head unit, the head unit may include:

[0403] The second print head includes a second drive element having one end supplied with a second drive signal and the other end supplied with a second reference voltage signal having a constant voltage value, and ejects liquid in response to the driving of the second drive element.

[0404] The driving unit comprises:

[0405] a second driving circuit, outputting the second driving signal;

[0406] a second reference voltage signal output circuit, outputting the second reference voltage signal; and

[0407] a third capacitor, a fifth electrode of the third capacitor being supplied with the second reference voltage signal, and a sixth electrode of the third capacitor being supplied with a ground signal,

[0408] The output connector is electrically connected to the second print head,

[0409] The wiring substrate includes a second supply point to which the second drive signal is supplied and through which the second drive signal and the second reference voltage signal are transmitted.

[0410] When viewed along the second axis, the third capacitor is located between the output connector and the second supply point,

[0411] The shortest distance between the output connector and the fifth electrode is shorter than the shortest distance between the output connector and the sixth electrode.

[0412] The shortest distance between the second supply point and the fifth electrode is longer than the shortest distance between the second supply point and the sixth electrode.

[0413] Even when this head unit includes a second print head in addition to the first print head, the feedback path through which the current generated by the second drive signal supplied by the second drive circuit to the second drive element is fed back to the second drive circuit can be shortened. Consequently, the inductance component of the current generated by the second drive signal supplied by the second drive circuit to the second drive element in the current path is reduced, and the likelihood of distortion in the signal waveform of the second drive signal supplied to the second drive element due to this inductance component is also reduced.

[0414] In one embodiment of the head unit, it may be possible that:

[0415] The wiring substrate includes a first surface and a second surface located opposite to the first surface.

[0416] The first driving circuit is disposed on the first surface, and the first capacitor is disposed on the second surface.

[0417] In this head unit, the head unit can be miniaturized.

[0418] In one embodiment of the head unit, it may be possible that:

[0419] The driving unit includes a driving circuit substrate provided with the first driving circuit.

[0420] The wiring substrate includes a first surface and a second surface located opposite to the first surface.

[0421] The driving circuit substrate is electrically connected to the first surface via a BtoB connector, and the first capacitor is provided on the second surface.

[0422] In this head unit, the mounting area of ​​the first drive circuit is reduced, and the head unit can be miniaturized.

[0423] One embodiment of a liquid ejection device comprises:

[0424] Conveying unit, conveying medium;

[0425] The first print head includes a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, and ejects liquid onto the medium in response to driving of the first driving element; and

[0426] a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head;

[0427] The driving unit comprises:

[0428] a first driving circuit, outputting the first driving signal;

[0429] A first reference voltage signal output circuit, outputting the first reference voltage signal;

[0430] an output connector electrically connected to the first print head;

[0431] a first capacitor, a first electrode of the first capacitor being supplied with the first reference voltage signal, and a second electrode of the first capacitor being supplied with a ground signal; and

[0432] A wiring substrate is provided with the output connector and is used for transmitting the first drive signal and the first reference voltage signal.

[0433] The wiring substrate includes a first side, a second side located opposite to the first side, and a first supply point to which the first drive signal is supplied.

[0434] The first capacitor is located between the output connector and the first supply point when viewed along a second axis orthogonal to a first axis connecting the first side and the second side,

[0435] The shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode.

[0436] The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

[0437] In this liquid ejection device, the feedback path through which the current generated by the first drive signal supplied by the first drive circuit to the first drive element is fed back to the first drive circuit can be shortened. As a result, the inductance component of the current generated by the first drive signal supplied by the first drive circuit to the first drive element in the current path is reduced, thereby reducing the likelihood of distortion in the signal waveform of the first drive signal supplied to the first drive element caused by this inductance component.

[0438] In one embodiment of the liquid ejection device,

[0439] The first electrode and the second electrode are located at positions along the first axis.

[0440] In this liquid ejection device, the feedback path through which the current generated by the first drive signal supplied by the first drive circuit to the first drive element is fed back to the first drive circuit can be further shortened. As a result, the inductance component of the current generated by the first drive signal supplied by the first drive circuit to the first drive element in the current path is further reduced, further reducing the likelihood of distortion in the signal waveform of the first drive signal supplied to the first drive element caused by this inductance component.

[0441] In one embodiment of the liquid ejection device,

[0442] The driving unit comprises:

[0443] a second capacitor, a third electrode of the second capacitor being supplied with the first reference voltage signal, and a fourth electrode of the second capacitor being supplied with a ground signal,

[0444] When viewed along the second axis, the second capacitor is located between the output connector and the first supply point,

[0445] The shortest distance between the output connector and the third electrode is shorter than the shortest distance between the output connector and the fourth electrode.

[0446] The shortest distance between the first supply point and the third electrode is longer than the shortest distance between the first supply point and the fourth electrode.

[0447] In this liquid ejection device, even when a second capacitor is provided in addition to the plurality of first capacitors in the current path of the current generated by the first drive signal supplied by the first drive circuit to the first drive element, the feedback path through which the current generated by the first drive signal supplied by the first drive circuit to the first drive element is fed back to the first drive circuit can be shortened. Consequently, the inductance component of the current generated by the first drive signal in the current path is reduced, and the likelihood of distortion in the signal waveform of the first drive signal supplied to the first drive element due to this inductance component is reduced.

[0448] In one embodiment of the liquid ejecting device, the liquid ejecting device may include:

[0449] The second print head includes a second drive element having one end supplied with a second drive signal and the other end supplied with a second reference voltage signal having a constant voltage value, and ejects liquid in response to the driving of the second drive element.

[0450] The driving unit comprises:

[0451] a second driving circuit, outputting the second driving signal;

[0452] a second reference voltage signal output circuit, outputting the second reference voltage signal; and

[0453] a third capacitor, a fifth electrode of the third capacitor being supplied with the second reference voltage signal, and a sixth electrode of the third capacitor being supplied with a ground signal,

[0454] The output connector is electrically connected to the second print head,

[0455] The wiring substrate includes a second supply point to which the second drive signal is supplied and through which the second drive signal and the second reference voltage signal are transmitted.

[0456] When viewed along the second axis, the third capacitor is located between the output connector and the second supply point,

[0457] The shortest distance between the output connector and the fifth electrode is shorter than the shortest distance between the output connector and the sixth electrode.

[0458] The shortest distance between the second supply point and the fifth electrode is longer than the shortest distance between the second supply point and the sixth electrode.

[0459] In this liquid ejection device, even when a second print head is provided in addition to the first print head, the feedback path for feeding back the current generated by the second drive signal supplied by the second drive circuit to the second drive element to the second drive circuit can be shortened. Therefore, the inductance component of the current generated by the second drive signal supplied by the second drive circuit to the second drive element in the current path is also reduced, and the possibility of distortion in the signal waveform of the second drive signal supplied to the second drive element due to this inductance component is also reduced.

[0460] In one embodiment of the liquid ejection device,

[0461] The wiring substrate includes a first surface and a second surface located opposite to the first surface.

[0462] The first driving circuit is disposed on the first surface, and the first capacitor is disposed on the second surface.

[0463] In this liquid ejection device, the driving unit can be miniaturized.

[0464] In one embodiment of the liquid ejection device,

[0465] The driving unit includes a driving circuit substrate provided with the first driving circuit.

[0466] The wiring substrate includes a first surface and a second surface located opposite to the first surface.

[0467] The driving circuit substrate is electrically connected to the first surface via a BtoB connector, and the first capacitor is provided on the second surface.

[0468] In this liquid ejection device, the mounting area of ​​the first drive circuit is reduced, and the drive unit can be miniaturized.

Claims

1. A head unit, characterized in that: have: The first print head includes a first drive element having one end supplied with a first drive signal and the other end supplied with a first reference voltage signal of a constant voltage value, and ejects liquid in response to driving of the first drive element; as well as a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head; The driving unit comprises: a first driving circuit, outputting the first driving signal; A first reference voltage signal output circuit, outputting the first reference voltage signal; an output connector electrically connected to the first print head; a first capacitor, wherein the first reference voltage signal is supplied to a first electrode of the first capacitor and a ground signal is supplied to a second electrode of the first capacitor; as well as A wiring substrate is provided with the output connector and is used for transmitting the first drive signal and the first reference voltage signal. The wiring substrate includes a first side, a second side located opposite to the first side, and a first supply point to which the first drive signal is supplied. The first capacitor is located between the output connector and the first supply point when viewed along a second axis orthogonal to a first axis connecting the first side and the second side, The shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode. The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

2. The head unit according to claim 1, wherein: The first electrode and the second electrode are located at positions along the first axis.

3. The head unit according to claim 1, wherein: The driving unit comprises: a second capacitor, a third electrode of the second capacitor being supplied with the first reference voltage signal, and a fourth electrode of the second capacitor being supplied with a ground signal, When viewed along the second axis, the second capacitor is located between the output connector and the first supply point, The shortest distance between the output connector and the third electrode is shorter than the shortest distance between the output connector and the fourth electrode. The shortest distance between the first supply point and the third electrode is longer than the shortest distance between the first supply point and the fourth electrode.

4. The head unit according to claim 1, wherein: The head unit comprises: The second print head includes a second drive element having one end supplied with a second drive signal and the other end supplied with a second reference voltage signal having a constant voltage value, and ejects liquid in response to the driving of the second drive element. The driving unit comprises: a second driving circuit, outputting the second driving signal; A second reference voltage signal output circuit, outputting the second reference voltage signal; as well as a third capacitor, a fifth electrode of the third capacitor being supplied with the second reference voltage signal, and a sixth electrode of the third capacitor being supplied with a ground signal, The output connector is electrically connected to the second print head, The wiring substrate includes a second supply point to which the second drive signal is supplied, and propagates the second drive signal and the second reference voltage signal. When viewed along the second axis, the third capacitor is located between the output connector and the second supply point, The shortest distance between the output connector and the fifth electrode is shorter than the shortest distance between the output connector and the sixth electrode. The shortest distance between the second supply point and the fifth electrode is longer than the shortest distance between the second supply point and the sixth electrode.

5. The head unit according to claim 1, wherein: The wiring substrate includes a first surface and a second surface located opposite to the first surface. The first driving circuit is disposed on the first surface, and the first capacitor is disposed on the second surface.

6. The head unit according to claim 1, wherein: The driving unit includes a driving circuit substrate provided with the first driving circuit. The wiring substrate includes a first surface and a second surface located opposite to the first surface. The driving circuit substrate is electrically connected to the first surface via a BtoB connector, and the first capacitor is provided on the second surface.

7. A liquid ejection device, characterized in that: have: Conveying unit, conveying medium; The first print head includes a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, and ejects liquid onto the medium in response to driving of the first driving element; as well as a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head; The driving unit comprises: a first driving circuit, outputting the first driving signal; A first reference voltage signal output circuit, outputting the first reference voltage signal; an output connector electrically connected to the first print head; a first capacitor, wherein the first reference voltage signal is supplied to a first electrode of the first capacitor and a ground signal is supplied to a second electrode of the first capacitor; as well as A wiring substrate is provided with the output connector and is used for transmitting the first drive signal and the first reference voltage signal. The wiring substrate includes a first side, a second side located opposite to the first side, and a first supply point to which the first drive signal is supplied. The first capacitor is located between the output connector and the first supply point when viewed along a second axis orthogonal to a first axis connecting the first side and the second side, The shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode. The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

8. The liquid ejection device according to claim 7, wherein: The first electrode and the second electrode are located at positions along the first axis.

9. The liquid ejection device according to claim 7, wherein: The driving unit comprises: a second capacitor, a third electrode of the second capacitor being supplied with the first reference voltage signal, and a fourth electrode of the second capacitor being supplied with a ground signal, When viewed along the second axis, the second capacitor is located between the output connector and the first supply point, The shortest distance between the output connector and the third electrode is shorter than the shortest distance between the output connector and the fourth electrode. The shortest distance between the first supply point and the third electrode is longer than the shortest distance between the first supply point and the fourth electrode.

10. The liquid ejection device according to claim 7, wherein: The liquid ejection device comprises: The second print head includes a second drive element having one end supplied with a second drive signal and the other end supplied with a second reference voltage signal having a constant voltage value, and ejects liquid in response to the driving of the second drive element. The driving unit comprises: a second driving circuit, outputting the second driving signal; A second reference voltage signal output circuit, outputting the second reference voltage signal; as well as a third capacitor, a fifth electrode of the third capacitor being supplied with the second reference voltage signal, and a sixth electrode of the third capacitor being supplied with a ground signal, The output connector is electrically connected to the second print head, The wiring substrate includes a second supply point to which the second drive signal is supplied, and propagates the second drive signal and the second reference voltage signal. When viewed along the second axis, the third capacitor is located between the output connector and the second supply point, The shortest distance between the output connector and the fifth electrode is shorter than the shortest distance between the output connector and the sixth electrode. The shortest distance between the second supply point and the fifth electrode is longer than the shortest distance between the second supply point and the sixth electrode.

11. The liquid ejecting device according to claim 7, wherein: The wiring substrate includes a first surface and a second surface located opposite to the first surface. The first driving circuit is disposed on the first surface, and the first capacitor is disposed on the second surface.

12. The liquid ejection device according to claim 7, wherein: The driving unit includes a driving circuit substrate provided with the first driving circuit. The wiring substrate includes a first surface and a second surface located opposite to the first surface. The driving circuit substrate is electrically connected to the first surface via a BtoB connector, and the first capacitor is provided on the second surface.

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