Wafer three-dimensional model circuit connectivity test method, device, medium and program product

Abstract

The application provides a wafer three-dimensional model circuit connectivity test method, device, medium and program product. The wafer three-dimensional model includes a plurality of structure units. The method includes: establishing a material attribute mapping table to record conductive attribute information; identifying the constituent material of each structure unit based on the material attribute mapping table and adding a label reflecting the conductive attribute; setting at least two virtual probes to establish a contact relationship with different structure units of the wafer three-dimensional model; selecting one of the virtual probes as a starting probe, taking the structure unit where the starting probe is located as a starting point, acquiring a test result of the connectivity state between the virtual probes according to the conductive path propagation, and comparing the test result with a design expectation to determine whether the wafer three-dimensional model meets the circuit connectivity requirement. Through the establishment of the material conductive attribute mapping, the virtual probe layout and the connectivity judgment mechanism, the wafer three-dimensional model circuit connectivity can be accurately detected before wafer manufacturing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a wafer three-dimensional model circuit connectivity test method, device, medium and program product. BACKGROUND

[0002] In the manufacturing process of modern semiconductor devices, electrical testing is an important link to ensure the functional integrity and process stability of chips. It not only ensures product quality and reliability, but also provides valuable data support for the optimization of production process. Traditional electrical testing usually relies on test equipment with precision probes to establish contact with the pads or contacts on the wafer surface after wafer manufacturing is completed, and measures key electrical parameters such as connectivity, threshold voltage, leakage current, and gain to verify whether they meet the design specifications. Among these electrical testing items, circuit connectivity testing is particularly important, which is often used to determine whether the circuit path is disconnected, short-circuited or has other defects affecting the conduction performance.

[0003] However, the existing technology usually relies on actual production completed wafers as the object of electrical testing, and the detection behavior can only be carried out after wafer manufacturing is completed, so it is impossible to identify potential electrical defects in the design or process stage. Especially when the defect is caused by upstream design errors, such as process flow setting, mask layout or process recipe parameters, it is often not discovered until the physical wafer test stage, which is seriously lagging behind the source of the problem, resulting in lower yield and lower research and development efficiency.

[0004] Therefore, the current technology still lacks electrical connectivity simulation means for three-dimensional wafer models, making it difficult to implement virtual electrical testing in the modeling or simulation stage, further limiting the pre-optimization capability of the wafer manufacturing process. Once electrical abnormalities are found, it usually causes irreversible material waste, time loss and capacity loss. SUMMARY

[0005] In view of the deficiencies of the prior art, the present application provides a wafer three-dimensional model circuit connectivity test method, device, medium and program product to at least solve the problem that the prior art lacks electrical connectivity simulation and detection mechanism suitable for three-dimensional wafer models, and cannot carry out effective electrical verification in the virtual modeling stage.

[0006] In order to achieve the above-mentioned purposes and other advantages, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a wafer three-dimensional model circuit connectivity test method applied to a wafer three-dimensional model, the wafer three-dimensional model comprising a plurality of structure units, the method comprising:

[0008] establish a material attribute mapping table to record different materials and corresponding conductive attribute information;

[0009] identify the constituent materials of each structural unit based on the material attribute mapping table, and add a label reflecting the conductive attribute to each structural unit;

[0010] Set at least two virtual probes, respectively, with different structural units of the wafer three-dimensional model to establish a contact relationship;

[0011] Select one of the virtual probes as a starting probe, and take the structural unit where the starting probe is located as the starting point, and sequentially identify other structural units adjacent to the current structural unit along the conductive path, and mark the structural units with a circuit conduction as conductive state, and during the propagation of the conductive path, the structural units marked as conductive state are included in the set of conductive structural units;

[0012] After the propagation of the conductive path ends, determine whether the structural units where the remaining virtual probes are located are all included in the set of conductive structural units, if so, determine that there is a conduction relationship between all virtual probes, if not, determine that there is a break between at least part of the virtual probes;

[0013] Compare the test results of the connectivity state between the virtual probes with the design expectation to determine whether the wafer three-dimensional model meets the circuit connectivity requirement.

[0014] According to the wafer three-dimensional model circuit connectivity test method provided by the present application, the step of determining that there is a break between at least part of the virtual probes comprises:

[0015] The virtual probe pair formed by any two virtual probes, any virtual probe of the virtual probe pair is taken as a starting point to perform conductive path propagation, and a corresponding conductive structural unit subset is generated;

[0016] Determine whether the structural unit where one of the virtual probes is located is included in the conductive structural unit subset generated by the other virtual probe;

[0017] If included, it is determined that the virtual probe pair is conductive, and if not included, it is determined that there is a break between the virtual probe pair.

[0018] According to the wafer three-dimensional model circuit connectivity test method provided by the present application, the step of comparing the judgment result of the connectivity state between the virtual probes with the design expectation to determine whether the wafer three-dimensional model meets the circuit connectivity requirement comprises:

[0019] Obtain the expected connectivity relationship table between the virtual probes in the circuit design;

[0020] constructing an actual connectivity relationship table based on actual test results, and determining whether an actual conduction relationship between any two virtual probes conforms to the expected connectivity relationship table;

[0021] When there is a pair of virtual probes with inconsistent connectivity, tracing back the expected conduction path of the pair of virtual probes in the expected connectivity relationship table;

[0022] Based on the expected conduction path and the set of conduction structure units, determining an abnormal node causing inconsistent connectivity, and extracting process attribute information recorded in the structure unit to which the abnormal node belongs, the process attribute information including process flow number, process recipe number and mask number;

[0023] Based on the process attribute information and the corresponding manufacturing process steps, locating the source of the circuit connectivity abnormality, to determine whether the wafer three-dimensional model has design or manufacturing defects, and further determine whether the wafer three-dimensional model meets the circuit connectivity requirements.

[0024] According to the wafer three-dimensional model circuit connectivity test method provided by the application, the inconsistent connectivity includes: expected to be conduction but actually not conduction and expected to be disconnected but actually conduction;

[0025] For the case of expected to be conduction but actually not conduction, the step of determining the abnormal structure unit causing inconsistent connectivity based on the expected conduction path and the set of conduction structure units includes:

[0026] The structure units on the expected conduction path are compared with the set of conduction structure units in turn, and the first structure unit not appearing in the set of conduction structure units is determined as an abnormal node according to the propagation order of the conductive path, for determining the interruption position;

[0027] For the case of expected to be disconnected but actually conduction, the step of determining the abnormal structure unit causing inconsistent connectivity based on the expected conduction path and the set of conduction structure units includes:

[0028] The set of conduction structure units is compared with the expected conduction path for set difference, to identify a set of abnormal structure units not belonging to the expected conduction path;

[0029] According to the propagation order of the conductive path, the first structure unit belonging to the set of abnormal structure units is determined as an abnormal node, for indicating the starting point of the misconnection path.

[0030] According to the wafer three-dimensional model circuit connectivity test method provided in the application, the material attribute mapping table is constructed in the form of key-value pairs, the key of the key-value pair is used to represent the identification information of the material, and the value of the key-value pair is used to represent the conductive attribute of the material, and the conductive attribute is an attribute value representing whether the material has conductive capability.

[0031] According to the wafer three-dimensional model circuit connectivity test method provided in the application, during the conductive path propagation process, the structure unit marked as the conductive state is executed visual marking, and the visual marking includes:

[0032] The color attribute of the structure unit is changed to visually distinguish from the non-conductive structure unit; and / or,

[0033] The rendering material attribute of the structure unit is changed to visually enhance the conductive structure unit; and / or,

[0034] An additional label field representing the conductive state is embedded in the three-dimensional model data of the structure unit, and the additional label field includes a marking time, a conductive path source and a conductive state flag, and is used to support state recording, defect analysis or visual processing.

[0035] According to the wafer three-dimensional model circuit connectivity test method provided in the application, the wafer three-dimensional model is constructed, including the following steps:

[0036] An initial three-dimensional model of the target wafer is constructed, and the initial three-dimensional model is a thin cylindrical structure used to represent the base form of the wafer;

[0037] According to a preset process flow, each process step is read in sequence, and the adjustment mode and adjustment area of the wafer three-dimensional model are determined based on the process step;

[0038] The adjustment range of the wafer three-dimensional model is determined in combination with the process recipe parameters corresponding to the current process step and the historical measurement data;

[0039] Based on the adjustment mode, the adjustment area and the adjustment range, the structure of the wafer three-dimensional model is adjusted;

[0040] The process of reading the process step, determining the model adjustment mode and adjustment area, determining the adjustment range and adjusting the structure is executed in a loop until the process flow is completed, and the three-dimensional model structure of the target wafer is obtained.

[0041] In a second aspect, the application provides an electronic device, which includes:

[0042] One or more processors; and a memory storing computer program instructions which, when executed, cause the processors to perform the wafer three-dimensional model circuit connectivity test method of any of the above.

[0043] In a third aspect, the present application provides a computer-readable storage medium, which stores a computer program and / or instructions, and the computer program and / or instructions, when executed by a processor, implement the wafer three-dimensional model circuit connectivity test method of any of the above.

[0044] In a fourth aspect, the present application provides a computer program product, which includes a computer program and / or instructions, and the computer program and / or instructions, when executed by a processor, implement the wafer three-dimensional model circuit connectivity test method of any of the above.

[0045] The wafer three-dimensional model circuit connectivity test method, device, medium and program product provided by the present application are applied to a wafer three-dimensional model, and the wafer three-dimensional model includes a plurality of structure units. A material attribute mapping table is established to record different materials and corresponding conductive attribute information. Based on the material attribute mapping table, the constituent materials of each structure unit are identified, and a label reflecting the conductive attribute is added to each structure unit. At least two virtual probes are set up, and each virtual probe is in contact with a different structure unit of the wafer three-dimensional model. One of the virtual probes is selected as a starting probe, and the structure unit where the starting probe is located is taken as a starting point. Other structure units adjacent to the current structure unit are identified in sequence along a conductive path, and the structure units in which the circuit is connected are marked as conductive states. During the propagation of the conductive path, the structure units marked as conductive states are included in a connected structure unit set. After the propagation of the conductive path ends, it is determined whether the structure units where the remaining virtual probes are located are all included in the connected structure unit set. If yes, it is determined that there is a connection relationship between all the virtual probes. If no, it is determined that there is a disconnection between at least part of the virtual probes. The test result of the connectivity state between the virtual probes is compared with the design expectation to determine whether the wafer three-dimensional model meets the circuit connectivity requirement. The present application can accurately detect the circuit connectivity of the wafer three-dimensional model before wafer manufacturing by establishing a material conductive attribute mapping, a virtual probe layout and a connectivity judgment mechanism. In this way, the electrical problem is solved in the design simulation link, which helps to find design or process defects in advance, improves the closed-loop capability of the design verification link, helps to realize high consistency and high reliability from wafer design to manufacturing, reduces the risk of rework, and improves the yield and consistency of wafer production. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0047] Figure 1 is a flowchart of a wafer three-dimensional model circuit connectivity test method provided by the embodiments of the present application;

[0048] Figure 2 is a legend of an operation area of an amplified wafer three-dimensional model for circuit connectivity test provided by the embodiments of the present application;

[0049] Figure 3 is a virtual probe setting schematic diagram provided by the embodiments of the present application;

[0050] Figures 4a to 4e is a connectivity test schematic diagram under a defect-free condition provided by the embodiments of the present application;

[0051] Figures 5a to 5b is a connectivity test schematic diagram under a manufacturing defect condition provided by the embodiments of the present application;

[0052] Figure 6 is a structural schematic diagram of an electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0053] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the following preferred embodiments are described in detail in combination with the drawings, and the above and other purposes, characteristics and advantages of the present application can be more obvious and easy to understand.

[0054] It should be noted that those skilled in the art explicitly and implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict. Unless otherwise defined, the technical terms or scientific terms involved in the present application should be understood as the usual meaning by those skilled in the art in the technical field to which the present application belongs. The terms "one", "a", "an", "the" and similar words involved in the present application do not represent quantity limitation, which can represent singular or plural. The terms "include", "contain", "have" and any variations thereof involved in the present application are intended to cover non-exclusive inclusion; the terms "first", "second", "third" and the like involved in the present application only distinguish similar objects, and do not represent a specific order of the objects.

[0055] For the convenience of understanding the embodiments of the present application, the following is an introduction to the technical terms related in the present application:

[0056] Process Flow: In semiconductor production, the "Process Flow" refers to the design blueprint and execution sequence of all necessary processing steps in the entire manufacturing process from raw materials (usually silicon wafers) to finished chips. It is a detailed plan that specifies how to convert the designed circuit diagram into a physical integrated circuit. The process flow not only covers each individual process step, but also defines the relationship between these steps, the order, and their integration in the entire production process. It includes step definition, sequence arrangement, quality control points, equipment usage and material selection, etc.

[0057] Recipe: In semiconductor manufacturing, a recipe or process recipe refers to a set of specific parameters used to control each step in the production process. These parameters are carefully designed based on the desired final product characteristics and manufacturing process to ensure that each chip on a wafer meets the expected performance, reliability and yield. Parameters consist of the following indicators: temperature, pressure, gas flow, time, power, chemical concentration and mechanical parameters, etc.

[0058] Mask: Also known as a photomask or mask, it plays a crucial role in semiconductor manufacturing and microfabrication. It is a highly precise transparent substrate (usually quartz glass) covered with a layer of opaque chromium or other metal material patterns. These patterns correspond to specific geometric shapes in integrated circuit designs, used to define the position and size of circuit elements and interconnection lines formed on the waer.

[0059] Referring to Figure 1 The embodiments of the present application provide a wafer three-dimensional model circuit connectivity test method applied to a wafer three-dimensional model, which includes a plurality of structure units. The structure unit refers to a three-dimensional geometric object with a spatial range, material attribute and process source formed by modeling in the wafer three-dimensional model. It usually corresponds to a basic structure or local feature formed in a physical manufacturing process stage, such as metal wiring, via, silicon dioxide insulating layer, polysilicon gate, lithography opening area, etching residue, etc. The three-dimensional form of its spatial range can be a cuboid, cylinder, polyhedron, etc. The material attribute is composed of a certain process material, such as copper Cu, silicon dioxide , aluminum Al, etc. The process source can be mapped to a specific process step or mask layer.

[0060] The circuit connectivity test method includes:

[0061] Step S1: Establish a material attribute mapping table to record different materials and corresponding conductive attribute information.

[0062] As an example, the material attribute mapping table is constructed in the form of key-value pairs, the key of the key-value pair is used to represent the identification information of the material, and the value of the key-value pair is used to represent the conductive attribute of the material, which is an attribute value representing whether the material has conductive capability.

[0063] Specifically, the material attribute mapping table is constructed in the form of key-value pairs, the key is used to identify the unique information of the material, and the value is used to represent whether the material has conductive capability. The purpose of establishing the material attribute mapping table is to provide accurate material information for subsequent electrical analysis. By querying the mapping table, the system can quickly determine the conductivity of each structural unit and further determine the continuity or disconnection of the conductive path.

[0064] For example, copper, aluminum or tungsten is marked as "conductive". For silicon dioxide, silicon nitride or titanium dioxide, it is marked as "non-conductive".

[0065] Step S2: Based on the material attribute mapping table, identify the constituent material of each structural unit, and add a label reflecting the conductive attribute to each structural unit.

[0066] Specifically, each structural unit in the wafer three-dimensional model usually contains its corresponding material identification information. When the system traverses all the structural units, it calls the material attribute mapping table to read the material identification field of the structural unit, looks up the conductive attribute value corresponding to the material in the material attribute mapping table, and adds or embeds the conductive attribute as a label field to the geometric body metadata of the structural unit. The label field can adopt a Boolean value or an enumeration value, or a numerical value label to represent the electrical grade (such as electrical conductivity, resistance range, etc.).

[0067] For example, the structural unit A traversed is a section of interconnection metal line, and its constituent material is copper. In the material attribute mapping table, it is found that the conductive attribute of copper is "conductive", so the following label is added to the structural unit A:

[0068] {

[0069] "material": "Cu",

[0070] "conductive": true

[0071] }

[0072] For another example, the structural unit B is a section of dielectric layer, and its material is silicon dioxide. It is found that the conductive attribute of silicon dioxide is "non-conductive", and the added label is:

[0073] {

[0074] "material": "SiO2",

[0075] "conductive": false

[0076] }

[0077] In this way, the physical material properties and electrical behavior of the original three-dimensional geometry are associated, enabling the system to quickly and automatically determine whether the structural unit has the ability to conduct electricity when performing subsequent path propagation or electrical simulation. This avoids calling the mapping table and querying the material electrical properties of the structural unit every time during runtime, thus improving running efficiency and analysis accuracy.

[0078] Step S3: Set up at least two virtual probes to establish contact relationships with different structural units of the wafer 3D model.

[0079] like Figure 2 The enlarged view of a portion of the 3D wafer model shown illustrates the operational area for circuit connectivity testing in a 3D environment. In this step, specific structural units (such as top-level pads, power lines, and critical interconnects) can be automatically selected as probe contact points based on design rules or connectivity test plans. Each virtual probe records its location, the contacted structural unit number, probe ID, and expected connectivity object. Alternatively, target structural units can be manually selected in the user interface to place virtual probes at the corresponding spatial locations. Figure 3 As shown, virtual probes A and B are in contact with different structural units. The gold structure in the figure is made of copper, and the gray structure is made of aluminum.

[0080] Step S4: Select one from the virtual probes as the starting probe. Starting from the structural unit where the starting probe is located, identify other structural units adjacent to the current structural unit along the conductive path in sequence, and mark the structural units with the circuit connected as conductive. During the propagation of the conductive path, the structural units marked as conductive are included in the set of conductive structural units.

[0081] The system selects one of the multiple virtual probes set in step S3 as a starting probe, and takes the structure unit where the probe is located as the starting point of the conduction path, and performs a conduction path propagation operation. The system performs a traversal judgment on all its adjacent structure units. If the adjacent structure unit is in contact with the current structure unit in space and the conduction property of the adjacent structure unit is "conductive", the identification information (such as the unique identification ID of the structure unit) of the adjacent structure unit is stored in the set of conduction structure units. The conduction structure unit set can be a dictionary list or an object array, etc. In addition to at least including the unique identification information of each structure unit, it can also contain material information, spatial position, conduction state label and other attribute fields, which are used for subsequent probe connectivity judgment and path visualization analysis.

[0082] The propagation process of the conduction path can be realized based on algorithms such as breadth-first search (BFS) and depth-first search (DFS), to ensure complete coverage of all conductive paths from the starting point.

[0083] Illustratively, the starting probe establishes contact with structure unit A, and the system confirms that its material is copper and has conductivity, so the system adds the identification ID of structure unit A to the set of conduction structure units; structure unit A is adjacent to structure unit B, which is made of aluminum and is also a conductive material, so the system adds the identification ID of structure unit B to the set; structure unit B is adjacent to structure unit C, but C is made of silicon dioxide and is not conductive, so the conduction path ends in this direction; structure unit B is also connected to structure unit D, which is made of copper, so the system continues to propagate along the conductive path and adds the identification ID of structure unit D to the set.

[0084] Step S5: After the conduction path propagation ends, it is determined whether the structure units where the remaining virtual probes are located are all included in the set of conduction structure units. If yes, it is determined that there is a conduction relationship between all the virtual probes. If no, it is determined that there is a break between at least some of the virtual probes.

[0085] In this embodiment, when the system performs conduction path propagation with virtual probe A as the starting point to obtain the set of conduction structure units Set_A, and determines whether the structure unit where virtual probe B is located is included in the set Set_A, if yes, it means that the structure unit has been accessed and marked as conductive by the propagation, and it is considered that virtual probes A and B are conductive and have an electrical connection relationship between them.

[0086] Exemplarily, it is assumed that the structure unit contacted by the virtual probe A is U1, and the structure unit contacted by the virtual probe B is U6. The structure units in the three-dimensional model of the wafer propagate from U1 to U6 via U2, U3, U4 and U5 in sequence, each of which is a conductive material and forms a continuous contact relationship in space. The conductive structure unit set Set_A of the probe A is {U1, U2, U3, U4, U5, U6}, and the structure unit U6 where the probe B is located is included in the set Set_A, so it is determined that there is an electrical communication relationship between the virtual probes A and B.

[0087] In the embodiment, in step S5, the step of determining that there is a disconnection between at least part of the virtual probes includes:

[0088] Step S501: a virtual probe pair is formed by any two virtual probes, and a conductive path propagation is performed with any virtual probe of the virtual probe pair as a starting point to generate a corresponding conductive structure unit subset;

[0089] Step S502: determining whether the structure unit where one of the virtual probes is located is included in the conductive structure unit subset generated by the other virtual probe;

[0090] Step S503: if included, it is determined that the virtual probe pair is conductive, and if not included, it is determined that there is a disconnection between the virtual probe pair.

[0091] Specifically, for the case that there is a disconnection between at least part of the virtual probes, taking three virtual probes A, B and C as an example, the virtual probes are respectively arranged on three key interconnection structure units, which are denoted as structure units U1, U5 and U9. The system combines the three virtual probes in any two to obtain virtual probe pairs (A, B), (A, C) and (B, C). For each pair of probes, an optional one is selected as a starting point, and a conductive path propagation is performed to obtain a corresponding conductive structure unit subset. For example, starting from the probe A, the structure unit U5 where the probe B is located can be propagated to obtain the conductive structure unit subset subSet_A as {U1, U2, U3, U4, U5}. Or starting from the probe B, the structure unit U1 where the probe A is located can also be propagated, and the probes A and B are connected to each other through the conductive path. Starting from the probe C, the conductive structure unit subset subSet_C generated according to the conductive path propagation result is {U9, U10}. The structure unit U1 where the probe A is located is not included in the subset propagated by the probe C, and the structure unit U5 where the probe B is located is also not included in the subset. Therefore, the system determines that the virtual probes C and A are not connected, and the virtual probes C and B are also not connected.

[0092] Since the wafer three-dimensional model is often composed of multiple process layers, some electrical paths will branch out in multiple directions from a point. The depth or breadth first path diffusion can automatically identify the conduction of the bifurcation structure. Even if the end point is not one, but a group of structure units, it can still be determined whether there is any breakpoint or misconnection. In this way, not only can it be determined whether there is a break in the whole, but also the electrical connection state between each pair of virtual probes can be accurately identified. It is suitable for complex three-dimensional wafer models such as multi-probe, multi-layer interconnection, and multi-branch structure, and has good universality and scalability. It provides a path basis for subsequent structural tracing of connectivity abnormalities (such as interrupted paths and misconnected paths). The system can compare and analyze the set with the design expected connectivity path to determine the propagation interruption location or misconnection start location, thereby assisting in the accurate positioning and structural visualization marking of abnormal nodes.

[0093] Step S6: Compare the test results of the connectivity state between the virtual probes with the design expectation to determine whether the wafer three-dimensional model meets the circuit connectivity requirements.

[0094] In this embodiment, step S6 specifically includes:

[0095] Step S601: Obtain the expected connectivity relationship table between the virtual probes in the circuit design.

[0096] In this step, to determine whether the wafer three-dimensional model meets the circuit connectivity requirements, the system first extracts the expected connectivity relationship between the virtual probes from the circuit design file. For example, the design diagram specifies that probe A and probe B should be connected, probe A and probe C should also be connected, and probe B and probe C should be disconnected. The system generates the following expected connectivity relationship table accordingly: A-B should be conductive, A-C should be conductive, and B-C should be disconnected.

[0097] Step S602: Construct an actual connectivity relationship table based on the actual test results, and determine whether the actual conduction relationship between any two virtual probes conforms to the expected connectivity relationship table.

[0098] In this step, the system determines whether any two virtual probes are electrically connected or disconnected based on the virtual probe setting after the conductive path propagation. The actual electrical connection between each pair of probes is structurally represented to form an actual connectivity relationship table, which is used for comparison with the expected connectivity relationship table. For example, the virtual probe A propagation path includes the structure units {U1~U5}, the structure unit U5 where the probe B is located is included in Set_A, and it is determined that A-B is conductive; the structure unit U6 where the probe C is located is not included in Set_A, and it is determined that A-C is not conductive; the conductive path starting from the probe B includes the structure unit where the probe C is located, and it is determined that B-C is conductive. The actual result is compared with the design expectation in step S601, and it is identified that there is a connectivity inconsistency between A-C (expected to be conductive but actually not conductive) and B-C (expected to be disconnected but actually conductive).

[0099] Step S603: When there are virtual probe pairs with connectivity inconsistencies, backtrack the expected conductive path of the virtual probe pair in the expected connectivity relationship table;

[0100] Step S604: Based on the expected conductive path and the conductive structure unit set, determine the abnormal node causing the connectivity inconsistency, and extract the process attribute information recorded in the structure unit to which the abnormal node belongs, including process flow number, process recipe number, and mask number.

[0101] Specifically, the connectivity inconsistency includes: expected to be conductive but actually not conductive and expected to be disconnected but actually conductive.

[0102] For the case of expected to be conductive but actually not conductive, the step of determining the abnormal structure unit causing the connectivity inconsistency based on the expected conductive path and the conductive structure unit set includes:

[0103] The structure units on the expected conductive path are compared with the conductive structure unit set in turn, and the first structure unit not appearing in the conductive structure unit set is determined as the abnormal node according to the propagation order of the conductive path, which is used to determine the interruption position.

[0104] For example, the probe A and the probe C should be conductive in the design, but the actual test shows that they are not connected. The system extracts the expected conductive path from the design diagram, that is, according to the spatial adjacency and electrical conduction relationship formed by the three-dimensional layout, records the structure path sequence, such as U1 (probe A)→U2→U3→U4→U5→U6 (probe C). The backtracking process is to compare the structure units in the expected conductive path with the actual conductive structure unit set as the analysis object.

[0105] In the comparison, the system sequentially determines whether U1 is in Set_A, whether U2 is in Set_A, and so on according to the order of the designed path. If a certain structural unit (for example, U6) in the path does not appear in Set_A for the first time, it indicates that the electrical property propagation is interrupted after U5 and fails to continue to the subsequent structural units. The system determines that the structural unit U6 is an abnormal node, which is the actual position of the electrical property interruption.

[0106] For the case where conduction is expected to be interrupted but actually occurs, based on the expected conduction path and the conduction structural unit set, the step of determining the abnormal structural unit causing the connectivity inconsistency includes:

[0107] Comparing the conduction structural unit set with the expected conduction path by set difference, a set of abnormal structural units that do not belong to the expected conduction path is identified;

[0108] According to the propagation order of the conduction path, the first structural unit belonging to the set of abnormal structural units is determined as an abnormal node, which is used to indicate the starting point of the misconnection path.

[0109] Specifically, the conduction structural unit set starting from the virtual probe B is denoted as Set_B. The propagation path starting from the probe B is U5→U6→U7→U8→U9 (probe C), and Set_B is {U5, U6, U7, U8, U9}. In the design expectation, the propagation path starting from the probe B is U5→U6 (probe C), and the expected conduction path is limited to {U5, U6}. The system performs set difference comparison accordingly and identifies a set of abnormal structural units as {U7, U8, U9}. According to the propagation order of the conduction path, the system determines that U7 is the first structural unit belonging to the set of abnormal structural units in the propagation path, which is the starting node of the misconnection path.

[0110] Each structural unit in the wafer three-dimensional model has been attached with a process attribute information tag in the modeling stage. The process attribute information includes but is not limited to the process flow number in which the structural unit is located, the process recipe number used, and the corresponding reticle number. These information usually come from the process flow definition table and can be bound to each structural unit.

[0111] For example, in the scenario where the expected conduction between probe A and probe C is interrupted but actually occurs, the system identifies the path interruption node as structural unit U6. The system further accesses the attribute data bound to U6 to obtain the process flow number to which the structural unit belongs, which is "flow_012", the recipe number used, which is "recipe_025", and the corresponding reticle number, which is "reticle_036". This information indicates that the structural unit is formed in a specific etching process and is an electrical property structure controlled by a specific pattern mask.

[0112] Step S605: Based on the process attribute information and the corresponding manufacturing process step, the problem source of the circuit connectivity abnormality is located to determine whether the wafer three-dimensional model has design or manufacturing defects, and whether the wafer three-dimensional model meets the circuit connectivity requirement.

[0113] Based on the process attribute information of the abnormal structure unit, the system combines the manufacturing process knowledge base or the process modeling process to backtrack and locate the root cause of the conductive path abnormality. For example, if the structure unit U6 belongs to a metal interconnection formation area, and the corresponding mask "reticle_036" is not correctly windowed in the layer design, or the etching parameter configuration is interrupted, then the metal interconnection may not be formed or the connection may fail; or the etching depth controlled by the process recipe "recipe_025" is insufficient, which may also cause the physical connection to be discontinuous, thereby interrupting the conductive propagation.

[0114] In another abnormality of "expected to be disconnected but actually connected", according to the obtained process attribute information, the system further judges that the mask pattern is mis-set in the window in this area, or the material setting is mis-selected as a high-conductive metal, which causes the path that should be disconnected to be unexpectedly connected.

[0115] Through the above analysis, the structure-level abnormality recognition is further extended to the process attribute layer. Based on the process attribute information, the system can locate the node where the electrical abnormality occurs and perform cause analysis by combining the model configuration and the process execution process, thereby realizing a systematic analysis closed loop from connectivity abnormality to manufacturing defects. Thus, it is determined whether the wafer three-dimensional model has design or manufacturing defects.

[0116] In this embodiment, during the conductive path propagation process, the structure unit marked as a conductive state is executed visual marking, which includes:

[0117] changing the color attribute of the structure unit to visually distinguish it from the non-conductive structure unit; and / or,

[0118] changing the rendering material attribute of the structure unit to visually enhance the conductive structure unit; and / or,

[0119] embedding an additional label field representing the conductive state in the three-dimensional model data of the structure unit, the additional label field including a marking time, a conductive path source, and a conductive state flag, for supporting state recording, defect analysis, or visual processing.

[0120] Specifically, the system uses one or a combination of the following visual marking methods.

[0121] Color property change: For each structure unit marked as "conductive state" during the propagation process, change the rendering color of its 3D model to a specific color (such as green, blue, or custom highlight color) to visually distinguish it from the default neutral or gray "non-conductive" structure units. This approach is intuitive, fast, and suitable for interactive view display.

[0122] Figures 4a to 4e The complete process of electrical propagation, path marking, and connectivity determination is demonstrated when the model structure, material annotation, and process configuration are correct. The starting virtual probe A is powered on, starting the conductive path propagation process, as shown in Figure 4a . The contact in contact with probe A and its connected copper material are identified as conductive material and marked as already conductive (left green), as shown in Figure 4b . Probe A propagates the path to the aluminum segment, which is marked as conductive and marked as already conductive (middle green), as shown in Figure 4c . The aluminum segment continues to connect to the right copper segment, which is judged and marked as already conductive (right green), as shown in Figure 4d . The right copper segment connects to probe B, which is marked as already conductive, determining that the circuit between probes A and B is connected, as shown in Figure 4e .

[0123] Figures 5a to 5b The diagnosis process of connectivity testing on a wafer 3D model is demonstrated when a structure unit has a manufacturing defect, causing the electrical propagation to be interrupted, resulting in inconsistent connectivity. As shown in Figure 5a , the middle aluminum segment fails to connect to the left and right segments due to mask manufacturing defects, causing structural fracture. In the connectivity test, the conductive path of probe A cannot propagate to probe B, and A and B cannot form a conductive path, resulting in an open circuit, as shown in Figure 5b .

[0124] Adjusting material properties: The system can set special rendering material properties for the already connected structure units, such as adding highlight effects, glowing edges, transparency changes, etc., to make them more visually prominent in the 3D visualization model. This approach is often used in video frame rendering or complex level display to enhance the recognition of the connected path in the three-dimensional structure.

[0125] Embedding additional label fields: Embed metadata fields reflecting the electrical state in the model data structure of the connected structure units, such as the time of the connected state marker, the starting probe of the connected path, and the connected path number, etc. These information can be used for subsequent operations such as batch screening of connected structure units, path playback, process defect positioning, and historical comparison.

[0126] The visual marking operation is usually completed synchronously during the propagation of the conductive path execution process, that is, whenever a certain structure unit is identified to meet the conduction condition and is included in the conduction structure unit set, the system immediately performs marking and visual update on it. By quickly locating the breakpoint or misconnection section through color and attribute comparison, it is convenient for engineers or the system to automatically identify the path boundary, which can be used for design verification playback, process display or report screenshot.

[0127] In this embodiment, a three-dimensional model of the wafer is constructed, including the following steps:

[0128] Step A1: Construct an initial three-dimensional model of the target wafer, which is a thin cylindrical structure, used to represent the base form of the wafer;

[0129] Step A2: According to the preset process flow, read each process step in turn, and determine the adjustment mode and adjustment area of the wafer three-dimensional model based on the process step;

[0130] Step A3: Determine the adjustment amplitude of the wafer three-dimensional model in combination with the process recipe parameters corresponding to the current process step and the historical measurement data;

[0131] Step A4: Based on the adjustment mode, adjustment area and adjustment amplitude, adjust the structure of the wafer three-dimensional model;

[0132] The process of steps A2 to A4 is executed in a loop until the process flow is completed, and the three-dimensional model structure of the target wafer is obtained.

[0133] Specifically, the system supports voxel modeling or mesh modeling by loading a three-dimensional modeling engine module to construct an editable geometric model structure. The size (diameter and thickness) of the initial three-dimensional model can be set according to the specific wafer specifications (such as 8 inches, 12 inches, etc.) to represent the base of the bare wafer. The initial three-dimensional model does not contain any pattern information and represents the silicon wafer entity in the unprocessed state, which is the starting point of the entire virtual modeling process.

[0134] The modeling engine stretches a two-dimensional cross section with a circular bottom surface along the Z-axis direction in the three-dimensional coordinate system to generate a cylinder with a height of a set value. The spatial coordinate system of the three-dimensional model is established with the center point of the cylindrical bottom surface as the origin. Among them, the X-Y axis plane is the wafer surface, and the Z axis is the thickness direction. In this way, by constructing the initial three-dimensional model, the system can provide a unified geometric reference framework for accepting subsequent material stacking, etching, pattern division and attribute embedding structure adjustment operations in each process step, ensuring that all processing steps are superimposed and transformed in a unified coordinate system.

[0135] In Step A2, the process steps can include but not limited to deposition, oxidation, lithography, etching, doping, cleaning and planarization, etc. For different types of process steps, the system adopts the following processing strategy to determine the adjustment mode and adjustment area.

[0136] When the process step is oxidation step, if it is to generate a silicon dioxide layer directly on the exposed silicon surface, the system will set the adjustment mode as uniformly covering a layer of oxidation structure on the entire base surface of the wafer three-dimensional model.

[0137] When the process step is deposition step, the system will set the adjustment mode as adding material structure in the wafer three-dimensional model, and the adjustment area is determined according to the mask image or the photoresist protection area of the current step, usually referring to the surface area not covered by the photoresist.

[0138] When the process step is lithography step, the system will set the adjustment mode as removing or retaining the photoresist structure, and the adjustment area is determined according to the pattern information of the mask image and the type of photoresist used (positive or negative), to simulate the pattern structure of the photoresist after development.

[0139] When the process step is doping (ion implantation) step, the system will set the adjustment mode as introducing doping attribute information such as ion species, implantation dose and spatial distribution in the adjustment area, which is the area not covered by the photoresist to express the implantation window.

[0140] When the process step is etching step, the system will set the adjustment mode as removing material structure, and the adjustment area is determined according to the exposed area defined by the pattern in the loaded mask image, and the system will reduce the material volume in this area by a specified depth or proportion.

[0141] When the process step is cleaning step, the system will set the adjustment mode as removing residual photoresist structure, and the adjustment area is determined according to the photoresist pattern area formed in the previous lithography step, to represent the area where residual photoresist may exist, and perform thinning processing of the photoresist layer in the model.

[0142] When the process step is planarization step (such as CMP), the system will set the adjustment mode as uniformly adjusting the height of the top surface of the wafer three-dimensional model, and the adjustment area is the top area of the current model or the local area with thickness fluctuation, and the system will perform geometric reconstruction operation in this area to realize the height normalization processing of the structure.

[0143] In Step A3, the process recipe parameters of the current process step are read, which include but not limited to target thickness, etching time, deposition rate, doping attribute information, etc. The parameter values are the standard target values set by the process design stage or the production system. These parameters represent the physical structure changes that should be achieved by the process step under ideal conditions, and are the basic input for calculating the adjustment amplitude.

[0144] Meanwhile, the system obtains historical measurement data corresponding to the process step from a database or a production system, i.e. actual measurement results performed for the process step in a plurality of past batches of wafer processing, including but not limited to actual deposition thickness, etching depth, photoresist residual thickness, doping layer distribution, etc. Such data can reflect real execution errors and stability trends in the process, providing support for subsequent parameter correction.

[0145] On the basis of the process recipe parameters and historical measurement data, the system constructs a fitting model (such as linear regression, polynomial regression or correction function) for representing the numerical mapping relationship between the theoretical target value and the actual processing result. By means of the fitting model, the target value in the process recipe parameters is corrected to obtain an adjustment amplitude value closer to the actual situation, which is the spatial scale basis for subsequent execution of structure addition, removal or attribute embedding in the wafer three-dimensional model.

[0146] Taking the oxidation process step as an example, to predict the silicon dioxide growth rate and thickness, an oxidation thickness regression model can be constructed according to historical measurement data (such as furnace temperature, oxygen flow, deposition time, etc.):

[0147]

[0148] wherein, is the oxidation layer thickness, is the furnace temperature, is the oxygen flow, is the oxidation time, is the model error term.

[0149] The historical measurement data is real data measured to serve as the target value for training the regression model. It is also possible to search for the best parameter combination in the model through an optimization algorithm, so that the model output is as close as possible to the set thickness value. The final output film thickness value will serve as the amplitude value for adjusting the three-dimensional model structure in step A4, for generating a silicon dioxide structure layer matching the actual oxidation process in the model, so that the model is more consistent with the actual process errors.

[0150] Taking the photolithography process step as an example, the system can collect historical measurement data closely related to the pattern development result, including exposure dose, development time, photoresist thickness and other related parameters. Based on the above multi-dimensional process data, the system can construct a line width prediction model, preferably using advanced modeling techniques such as response surface method (RSM) to express the response relationship between line width and key process parameters. The system can predict the pattern line width value in the model through this modeling method. And make the final pattern structure more consistent with the actual measurement result, improve the consistency of photolithography pattern transfer and the accuracy of three-dimensional model restoration.

[0151] By introducing the recipe and historical metrology data, the fitting model can be continuously optimized according to real-time production data, so that the model is more consistent with the actual process error. The consistency between the model and the actual structure is significantly improved, and the reliability and engineering applicability of the simulation results are enhanced.

[0152] Step A4 specifically includes:

[0153] When the adjustment mode is material addition, a layer of three-dimensional structure corresponding to the target material attribute is constructed above the adjustment area according to the adjustment amplitude;

[0154] When the adjustment mode is material removal, the corresponding three-dimensional structure is removed from the wafer three-dimensional model with the adjustment amplitude as the depth in the adjustment area;

[0155] When the adjustment mode is to remove or retain the photoresist structure, a layer of thin cylinder structure is first covered on the surface of the current wafer three-dimensional model to simulate the initial thickness of the photoresist, and then the photoresist structure is removed in the adjustment area according to the adjustment amplitude to retain the photoresist structure in the non-adjustment area;

[0156] When the adjustment mode is to introduce doping attribute information, attribute markers representing ion species, concentration or distribution are added to the wafer three-dimensional model in the adjustment area;

[0157] When the adjustment mode is to normalize the height of the top surface of the wafer three-dimensional model, geometric reconstruction is performed on the local structure with height difference in the adjustment area, including cutting the structure volume higher than the target height or filling the area lower than the target height, to realize the normalization of the surface height of the wafer three-dimensional model.

[0158] The process of steps A2 to A4 is repeatedly executed until the process flow is completed, and the three-dimensional model structure of the target wafer is obtained. The generated wafer three-dimensional model contains the structure layer, pattern topography and doping attribute formed by each process step in the entire process flow, and expresses the structure evolution and attribute change of the wafer at each process stage in a three-dimensional visualization manner, to simulate the complete wafer manufacturing process. The model not only has three-dimensional geometric structure, but also integrates electrical, process and other attribute information, and can dynamically display the structure evolution process of the wafer at each process stage through three-dimensional visualization, realizing the virtual simulation and reconstruction of the entire wafer manufacturing process.

[0159] In summary, the wafer 3D model circuit connectivity testing method provided in this application, applied to wafer 3D models, enables accurate detection of wafer 3D model circuit connectivity before wafer manufacturing by establishing material conductivity property mapping, virtual probe deployment, and connectivity judgment mechanisms. This shifts electrical issues to the design simulation stage, helping to identify design or process defects early, improving the closed-loop capability of the design verification process, contributing to high consistency and reliability from wafer design to manufacturing, reducing rework risks, and improving wafer production yield and consistency.

[0160] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0161] Furthermore, some embodiments of this application also provide an electronic device. The electronic device can be various forms of digital computer, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, etc. The electronic device can also be various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices.

[0162] The electronic device includes: one or more processors; and a memory storing computer program instructions, which, when executed, cause the processor to perform the wafer three-dimensional model circuit connectivity testing method provided in any one or more of the above embodiments. Figure 6 An exemplary structural diagram of the electronic device is disclosed. For example... Figure 6 As shown, the electronic device includes one or more processors 1101, a memory 1102, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components are interconnected via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). The components, their connections and relationships, and their functions shown herein are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0163] The electronic device can further include an input device 1103 and an output device 1104. The processor 1101, the memory 1102, the input device 1103, and the output device 1104 can be connected through a bus or other means, Figure 6 The connection through the bus is taken as an example.

[0164] The input device 1103 can receive input digital or character information, and generate key signal input related to user settings and function control of the electronic device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, and the like input device. The output device 1104 can include a display device, an auxiliary lighting device (for example, an LED), and a tactile feedback device (for example, a vibration motor), and the like. The display device can include, but is not limited to, a liquid crystal display (LCD), a light-emitting diode (LED) display, and a plasma display. In some embodiments, the display device can be a touch screen.

[0165] To provide interaction with the user, the electronic device can be a computer. The computer has a display device (for example, a cathode-ray tube (CRT) or an LCD monitor) for displaying information to the user, and a keyboard and a pointing device (for example, a mouse or a trackball) through which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (for example, visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including voice input, speech input, or tactile input).

[0166] In the embodiments of the present application, the computer readable medium stores computer programs / instructions, and the computer programs / instructions are executed by the processor to implement the wafer three-dimensional model circuit connectivity test method provided by any one or more of the above embodiments. The computer readable medium can be included in the electronic device described in the above embodiments; or can exist separately and not be assembled into the device. The above computer readable medium carries one or more computer readable instructions.

[0167] The memory 1102 can be configured as a non-transitory computer-readable storage medium, and can be used to store a non-transitory program, a non-transitory computer-executable instruction, and a module. The processor 1101 can execute various functions of the server and data processing by running the non-transitory program, the instruction, and the module stored in the memory 1102, so as to implement the program instruction / module corresponding to the method provided by any one or more of the above embodiments.

[0168] The memory 1102 can include a program storage area and a data storage area. The program storage area can store an operating system, at least one application program required by a function, and the like. The data storage area can store data created according to use of the electronic device, and the like. In addition, the memory 1102 can include a high-speed random access memory, and can further include a non-transitory memory such as at least one of a disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 1102 can optionally include a memory disposed remotely from the processor 1101, and these remote memories can be connected to the electronic device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0169] It should be noted that more specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination thereof. In this application, the computer-readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in connection with an instruction execution system, apparatus, or device.

[0170] Computer-readable storage media includes permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM, Phase-Change Random-Access Memory), static random access memory (SRAM, Static Random-Access Memory), dynamic random access memory (DRAM, Dynamic Random-Access Memory), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), flash memory or other memory technologies, compact discs (CD-ROM), digital versatile discs (DVD) or other optical storage, magnetic cassette, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0171] Computer program code for carrying out operations of the present application can be written in one or more programming languages or combinations of languages including object oriented programming languages such as Java, Smalltalk, C++ or conventional procedural programming languages such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0172] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. For example, an Application Specific Integrated Circuit (ASIC), a general purpose computer or any other similar hardware device can be used. In some embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) can be stored in a computer readable recording medium, such as a RAM memory, a magnetic or optical drive or a soft disk and the like. In addition, some steps or functions of the present application can be implemented by hardware, for example, as a circuit cooperating with the processor to perform the respective steps or functions.

[0173] The computer program product provided by the embodiments of the present application includes one or more computer programs / instructions, which, when executed by a processor, generate all or part of the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center and the like integrated with one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk, SSD, solid state disk) and the like.

[0174] The flowcharts or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-specific system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0175] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily made by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims, and the above embodiments should be regarded as exemplary and non-limiting.

Claims

1. A method for testing the connectivity of a three-dimensional model circuit on a wafer, characterized in that, The method is applied to a wafer three-dimensional model comprising a plurality of structure units, and comprises the following steps: establishing a material attribute mapping table to record different materials and corresponding conductive attribute information; identifying the constituent materials of each structure unit based on the material attribute mapping table, and adding a label reflecting the conductive attribute to each structure unit; setting at least two virtual probes to establish a contact relationship with different structure units of the wafer three-dimensional model respectively; selecting one of the virtual probes as a starting probe, taking the structure unit where the starting probe is located as a starting point, sequentially identifying other structure units adjacent to the current structure unit along a conductive path, and marking the structure units with a circuit in a conductive state, and during the propagation of the conductive path, the structure units marked as the conductive state are included in a set of conductive structure units; after the propagation of the conductive path ends, judging whether the structure units where the remaining virtual probes are located are all included in the set of conductive structure units, if yes, it is determined that there is a conductive relationship between all the virtual probes, if not, it is determined that there is a disconnection between at least part of the virtual probes; comparing the test results of the connectivity state between the virtual probes with the design expectation to determine whether the wafer three-dimensional model meets the circuit connectivity requirement.

2. The wafer three-dimensional model electrical circuit connectivity test method of claim 1, wherein, The step of determining that there is a disconnection between at least part of the virtual probes comprises: forming a virtual probe pair with any two virtual probes, taking any virtual probe of the virtual probe pair as a starting point to perform conductive path propagation to generate a corresponding conductive structure unit subset; judging whether the structure unit where one of the virtual probes is located is included in the conductive structure unit subset generated by the other virtual probe; if yes, it is determined that the virtual probe pair is conductive, if not, it is determined that there is a disconnection between the virtual probe pair.

3. The wafer three-dimensional model electrical circuit connectivity test method of claim 1, wherein, The step of comparing the judgment results of the connectivity state between the virtual probes with the design expectation to determine whether the wafer three-dimensional model meets the circuit connectivity requirement comprises: obtaining an expected connectivity relationship table between the virtual probes in the circuit design; constructing an actual connectivity relationship table based on the actual test results, and judging whether the actual conductive relationship between any two virtual probes conforms to the expected connectivity relationship table; when there is a virtual probe pair with inconsistent connectivity, tracing back the expected conductive path of the virtual probe pair in the expected connectivity relationship table; based on the expected conductive path and the set of conductive structure units, determining an abnormal node causing the inconsistent connectivity, and extracting process attribute information recorded in the structure unit to which the abnormal node belongs, the process attribute information comprising process flow number, process recipe number and mask plate number; based on the process attribute information and the corresponding manufacturing process steps, locating the source of the circuit connectivity abnormality, to determine whether the wafer three-dimensional model has a design or manufacturing defect, and further determine whether the wafer three-dimensional model meets the circuit connectivity requirement.

4. The wafer three-dimensional model electrical circuit connectivity test method of claim 3, wherein, The inconsistent connectivity includes: expected to be conductive but actually not conductive, and expected to be disconnected but actually conductive. For the case that the expected conduction path should be on but actually not, the step of determining the abnormal structure unit causing the connectivity inconsistency based on the expected conduction path and the conduction structure unit set comprises: The structure units on the expected conduction path are compared with the conduction structure unit set in turn, and the first structure unit not present in the conduction structure unit set is determined as an abnormal node in the order of propagation of the conductive path, for determining the interruption position; For the case that the expected conduction path should be off but actually on, the step of determining the abnormal structure unit causing the connectivity inconsistency based on the expected conduction path and the conduction structure unit set comprises: The conduction structure unit set is compared with the expected conduction path in set difference, and an abnormal structure unit set not belonging to the expected conduction path is identified; In the order of propagation of the conductive path, the first structure unit belonging to the abnormal structure unit set is determined as an abnormal node, for indicating the start point of the misconnection path.

5. The wafer three-dimensional model electrical circuit connectivity test method of claim 1, wherein, The material attribute mapping table is constructed in the form of key-value pairs, the key of the key-value pair is used to represent the identification information of the material, and the value of the key-value pair is used to represent the conductive attribute of the material, which is an attribute value representing whether the material has conductive capability.

6. The wafer three-dimensional model electrical circuit connectivity test method of claim 1, wherein, In the conductive path propagation process, the structure units marked as conductive state are executed visual marking, the visual marking comprising: changing the color attribute of the structure unit to visually distinguish from the non-conductive structure unit; and / or, changing the rendering material attribute of the structure unit to visually enhance the conductive structure unit; and / or, embedding an additional label field representing the conductive state in the three-dimensional model data of the structure unit, the additional label field including the marking time, the conduction path source, and the conductive state flag, for supporting state recording, defect analysis, or visual processing.

7. The wafer three-dimensional model electrical circuit connectivity test method of claim 1, wherein, Constructing the wafer three-dimensional model comprises the following steps: constructing an initial three-dimensional model of the target wafer, the initial three-dimensional model being a thin cylindrical structure, for representing the base form of the wafer; reading each process step in turn according to a preset process flow, and determining the adjustment mode and adjustment area of the wafer three-dimensional model based on the process step; determining the adjustment amplitude of the wafer three-dimensional model in combination with the process recipe parameters corresponding to the current process step and the historical measurement data; performing structural adjustment on the wafer three-dimensional model based on the adjustment mode, the adjustment area, and the adjustment amplitude; cyclically performing the processes of reading the process step, determining the model adjustment mode and adjustment area, determining the adjustment amplitude, and performing structural adjustment, until the process flow is completed, to obtain the three-dimensional model structure of the target wafer.

8. An electronic device, comprising: The electronic device comprises: one or more processors; and a memory storing computer program instructions which, when executed, cause the processor to perform the wafer three-dimensional model circuit connectivity test method of any one of claims 1-7.

9. A computer readable storage medium having stored thereon a computer program and / or instructions, characterized in that, The computer program and / or instructions, when executed by the processor, implement the wafer three-dimensional model circuit connectivity test method of any one of claims 1-7.

10. A computer program product comprising computer programs and / or instructions, characterized in that, The computer program and / or instructions, when executed by a processor, implement the wafer three-dimensional model circuit connectivity test method as claimed in any one of claims 1-7.

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