Self-interference cancellation

Abstract

The invention relates to cancellation of self-interference in a radar transceiver. Exemplary embodiments include a radar transceiver (500) in which a correction module (510) is configured to combine an analog baseband receive signal with a digital correction signal to provide a corrected analog baseband signal, the correction module (510) comprising a sampling capacitor (Cs), a variable cancellation capacitor (Cc) controllable by the digital correction signal, an amplifier (519), and a switching arrangement (520), the switching arrangement (520) is configured to sample the baseband receive signal and sum a sampled charge across the sampling capacitor (Cs) and a charge across the variable cancellation capacitor (Cc) to provide a residual signal to the amplifier (519), the amplifier (519) is configured to amplify the residual signal to provide the corrected analog baseband signal to an ADC (511).

Description

Technical Field

[0001] The present disclosure relates to the cancellation of self-interference in radar transceivers. Background Art

[0002] Radar systems can be subject to self-interference, which manifests as a strong signal in the receiver resulting from direct detection at the receiver of the transmitted signal. This strong signal can limit the transceiver's ability to detect targets due to analog imperfections such as amplifier nonlinearities, which can create "ghost" targets and increase the transceiver's overall noise floor.

[0003] Figure 1 An exemplary radar transceiver 100 is shown, showing a single transmitter-receiver pair. Actual implementations may include multiple such transmitter-receiver pairs. On the transmitter side of the transceiver 100, a waveform generator 101 generates in-phase (I) and quadrature (Q) baseband radar transmit waveform signals, converts the signals from digital to analog, and up-converts the signals to be amplified by a power amplifier 105 for transmission via a transmit antenna 106. The I and Q digital signals are generated by a digital code generator 102 and provided to an IDAC 103. I and Q DAC 103 Q The analog signal is converted by the up-converter 104 I and Q upconverter 104 Q Perform up-conversion, the I up-converter 104 I and Q upconverter 104 Q The I and Q carrier signals are provided by a local oscillator generator (LO) 107. The baseband transmitter signal can be coded in various ways, such as phase coded, OFDM (Orthogonal Frequency Division Multiplexing), or frequency modulated. Upconverter 104 I 、104 Q The baseband transmitter signal is converted to a radar carrier frequency, which may be, for example, approximately 79 GHz in a typical vehicular radar application.

[0004] Reflections from one or more targets 108 are received by a receiver antenna 109. The received RF signal is amplified by a receiver RF amplifier 110 and downconverted using the same LO signal from LO 107 through an I downconverter 111. I and Q downconverter 111 Q After down-conversion to baseband, the received baseband signal is output by a variable gain amplifier (VGA) 112. I , 112 Q amplified and then passed through the analog-to-digital converter (ADC) 114 I 、114 Q The digital domain is converted and reassembled by the I / Q combiner 115 before being filtered by a low pass filter (LPF) 113.I , 113 Q The baseband amplification makes the ADC 114 I , the dynamic range and resolution requirements of 1140 can be relaxed.

[0005] Target estimation is performed using the digital baseband signal output by I / Q combiner 115. A range of digital signal processing techniques can be used to obtain target range, velocity, and azimuth or elevation. Range is typically obtained by applying a correlator filter for PMCW radars (FMCW radars use a Fourier transform). The output of correlator 116 is then processed by a Doppler FFT module 117, which performs Doppler processing, which may be followed by MIMO and direction-of-arrival processing steps. The output at the receiver is a range-Doppler map. Figure 2 An example extraction from a range-Doppler plot is shown in Figure 2, which plots power as a function of radial range at a given relative velocity, in this example, zero velocity. The plot will vary with velocity and can be represented in a three-dimensional graph with radial range and velocity on the x- and y-axes, and power on the z-axis. Peaks in the graph indicate the range and velocity of the target reflection.

[0006] For digitally encoded radars such as PMCW or OFDM, self-interference poses a major limitation to receiver performance and creates extremely stringent linearity, noise, and dynamic range requirements for the receiver amplifier and ADC, which can be prohibitive in terms of power dissipation and silicon area. Specifically, linear wideband amplification poses a major obstacle for digitally encoded radars. After downconversion, the baseband bandwidth in digital radars in the 76 to 81 GHz band can typically be as high as 4 GHz for short-range radar use cases, requiring up to 40 dB or more of amplification. To illustrate the challenge, a circuit consisting of 5 dB LNA gain, -9 dB mixer gain, 30 dB baseband gain with 13 dBm IIP3, and 10-bit ADC resolution can be used to receive polyphase digital codes.

[0007] The resulting effects from amplifier nonlinearity are shown in Figure 2 In the distance-cut (v=0) diagram, a self-interference signal 201 with -30dB coupling is visible at 0m, and targets 202, 204 are present at 3m (where RCS=10dBsm) and 30m (where RCS=0dBsm). In a real traffic situation, the close target 202 may be a truck, and the more distant missed target 204 may be a pedestrian. The nonlinear behavior of the variable gain amplifier, together with the strong self-interference, produces a noise ridge 203 at zero speed, making the detection of stationary pedestrians ( Figure 2 Missing detection in 204) is not possible.

[0008] Ghost targets 205 are also generated due to amplifier nonlinearity (in this case, LNA 110, which has an IIP3 of 5 dBm). These effects lead to false detection and ghost targets. In the case described above, with some specific codes (such as LFM codes), ghost targets 205 can be predetermined based on the distance and power of the target of the present invention. Ghost targets are generated by cross-modulation products of self-interference with strong targets and are generated in the millimeter wave front end in the carrier domain. After down-conversion, the cross-modulation products are completely new sequences that generate ghost targets. An analytical explanation of this effect is described in reference [7].

[0009] Due to the direct coupling between the transmit antenna 106 and the receive antenna 109, there is a strong self-interfering signal 201 (or overflow) at the input of the receiver. The self-interfering signal 201 may be substantially stronger than any target signal 202. Figure 2 In the example shown, self-interfering signal 201 is at a power of approximately 25 to 30 dBFS (dB relative to the full scale of the ADC), while the strongest target signal 202 at a distance of approximately 3 meters is at a power of approximately 12 dBFS. A noise ridge 203 at zero relative velocity is present in the received signal at approximately -11 dBFS, which can mask missed detection signal 203. A "ghost" target signal 205 is present at a level of approximately -7 dBFS, which is caused by amplifier nonlinearities due to the presence of strong self-interfering signal 201.

[0010] Self-interference signals can also be generated when the transmitted signal reflects from objects near the transmitter (e.g., a car bumper in the case of a typical vehicular radar implementation) and is received by the receiver. In the case of multiple-input, multiple-output (MIMO) radar applications that employ multiple transmitters emitting orthogonal transmit waveforms, each of the multiple receivers receives a superposition of reflected and coupled signals from the multiple transmitters, further complicating the self-interference problem.

[0011] Because of the above, self-interference can be a critical limitation for digitally decoded radar systems, which can lead to highly demanding requirements for millimeter wave and baseband circuits. One solution would be to design linear, wideband amplifiers and ADCs with very high dynamic range to mitigate the problem. However, this approach incurs a considerable power dissipation penalty and feasibility issues. Reducing the gain of the baseband amplifier to alleviate the nonlinearity can translate into more stringent requirements for the ADC. In the above example, using 13dB of gain instead of 30dB can allow the ridge to be eliminated below the noise floor. However, this translates into a need for a 17dB higher dynamic range for the ADC, so the 13 effective bits in this case have a 2GHz bandwidth. Such an ADC would require more than 1.2W of power, which may be too high for both single and MIMO receivers. Summary of the Invention

[0012] According to a first aspect, there is provided a radar transceiver comprising:

[0013] a digital signal generator configured to generate a digital baseband transmission signal;

[0014] a transmitter DAC configured to convert the digital baseband transmission signal into an analog baseband transmission signal;

[0015] A local oscillator (LO) module configured to generate a carrier signal;

[0016] an upconverter configured to mix the carrier signal with the analog baseband transmit signal to generate an RF transmit signal;

[0017] an RF amplifier configured to amplify the RF transmission signal;

[0018] a transmitting antenna configured to transmit the amplified RF transmission signal;

[0019] a receiving antenna configured to receive RF signals;

[0020] a receiving RF amplifier configured to amplify a received RF signal;

[0021] a downconverter configured to mix the carrier signal with the amplified receive RF signal to provide an analog baseband receive signal;

[0022] a correction module configured to combine the analog baseband received signal with a digital correction signal to provide a corrected analog baseband signal;

[0023] an ADC configured to receive the corrected analog baseband signal and provide a digital baseband signal; and

[0024] a correction signal generator configured to generate the digital correction signal based on the digital baseband transmission signal and the digital output signal of the transceiver and provide the correction signal to the correction module,

[0025] wherein the correction module includes a sampling capacitor, a variable cancellation capacitor controllable by the digital correction signal, an amplifier, and a switch arrangement, the switch arrangement being configured to sample the baseband receive signal and sum the sampled charge across the sampling capacitor with the charge across the variable cancellation capacitor to provide a residual signal to the amplifier, the amplifier being configured to amplify the residual signal to provide a corrected analog baseband signal to the ADC.

[0026] The radar transceiver may further include a clock signal generator configured to provide a clock signal to the switch arrangement and to a sampling switch connected to the sampling capacitor. The clock signal may include a first phase, in which the sampling switch is closed and charge is transferred to the sampling capacitor, and a second phase, in which the sampling switch is open and the charge is transferred to the input of the amplifier.

[0027] The correction module may include:

[0028] a first bias switch configured to connect a bias voltage to the summing node during a first clock phase and to be open during the second phase;

[0029] A second bias switch is configured to connect the bias voltage to an input node between the sampling capacitor and the sampling switch during a second clock phase and to be disconnected during the first clock phase.

[0030] The correction module may include:

[0031] an amplifier input switch configured to connect the summing node to an input of the amplifier during the second clock phase;

[0032] an amplifier feedback switch configured to connect the input and output of the amplifier during the first clock phase; and

[0033] An amplifier feedback capacitor is connected between the input and the output of the amplifier.

[0034] The clock signal may include a third phase in which charge from the output of the amplifier is transferred to the ADC.

[0035] The ADC may include an ADC sampling switch configured to connect the output of the amplifier to the ADC during a third clock phase.

[0036] The ADC may be a successive approximation register ADC.

[0037] The radar transceiver may include a correlator module configured to correlate the digital baseband signal from the ADC with an output from the digital signal generator to provide the digital output signal.

[0038] The radar transceiver may further include an FFT processing module configured to process the digital output signal to generate an output range-Doppler map.

[0039] The radar transceiver may be configured to operate as an FMCW, PMCW or OFDM radar transceiver.

[0040] According to a second aspect, there is provided a multiple-input multiple-output MIMO radar transceiver system comprising a plurality of radar transceivers according to the first aspect.

[0041] The LO module and the digital signal generator may be common to each of the plurality of radar transceivers.

[0042] According to a third aspect, there is provided a method of operating a radar transceiver according to the first aspect, the method comprising the steps of:

[0043] In a first calibration mode, the correction signal generator monitors a combined digital output signal and determines a signal to be cancelled from the analog baseband signal; and

[0044] In a second mode of operation, the correction signal generator provides the digital correction signal to the correction module to cancel the signal from the analog baseband signal.

[0045] In the first calibration mode, the gain of the amplifier may be reduced from a predetermined gain to reduce nonlinearity of the amplifier, and in the second operating mode, the gain of the amplifier may be increased to the predetermined gain.

[0046] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Embodiments will be described, by way of example only, with reference to the accompanying drawings, in which:

[0048] Figure 1 is a schematic diagram of an exemplary radar transceiver;

[0049] Figure 2 yes Figure 1 a graph of received signal power as a function of distance for an exemplary transceiver;

[0050] Figure 3 is a schematic diagram of an exemplary radar transceiver with received signal correction;

[0051] Figure 4a is a schematic diagram of exemplary modules for summing, canceling, amplifying, and sampling received baseband signals in a conventional radar transceiver;

[0052] Figure 4b is a schematic diagram of exemplary modules for summing, canceling, amplifying, and sampling received baseband signals in an exemplary radar transceiver according to the present disclosure;

[0053] Figure 5 is a schematic diagram of an exemplary radar transceiver having integrated sampler, cancellation, and amplification modules in the receiver side;

[0054] Figure 6 is used for Figure 5 A schematic diagram of an exemplary correlator module of a transceiver comprising a set of multipliers and summing blocks;

[0055] Figure 7 It is used for Figure 5 A schematic circuit diagram of an exemplary integrated sampler, cancellation, and amplification module of an ADC of a transceiver;

[0056] Figure 8 yes Figure 7 An exemplary signal timing diagram of a module;

[0057] Figure 9 is an exemplary graph of a received digital bit stream over time illustrating self-interference from an originally transmitted bit stream and a resulting residual bit stream after correction; and

[0058] Figure 10 is a schematic diagram of an exemplary multiple-input multiple-output (MIMO) transceiver arrangement.

[0059] It should be noted that the drawings are diagrammatic and not drawn to scale. For clarity and convenience in the drawings, the relative sizes and proportions of the various parts of these drawings have been shown by enlarging or reducing them in size. The same reference numerals are generally used to designate corresponding or similar features in modified and different embodiments. DETAILED DESCRIPTION

[0060] One way to reduce the linearity and dynamic range requirements of a receiver is to use active self-interference cancellation. Such methods are well established in cable Ethernet systems [1] and have gained attention in full-duplex communication systems [2] and more recently in phase-coded radar systems [4, 5]. In FMCW radar systems, the effects of self-interference can be reduced or even eliminated by using a high-pass filter, thereby utilizing analog demodulation of the receiver signal, which enables frequency selectivity as a function of distance (where nearby and strong targets appear at low frequencies, while the desired signal appears at higher frequencies). However, in general, this is not possible in digitally coded radar systems, where active cancellation needs to be robust (e.g., to withstand thickness, material, and paint variations in a car bumper), reliable (i.e., it needs to work all the time), and not degrade the noise performance of the receiver chain.

[0061] Figure 3The transceiver 300 shown in FIG. 3 shows two possible approaches for applying organic interference cancellation (i.e., cancellation at carrier and baseband). The transceiver 300 may actually include in-phase and quadrature paths in the transmitter and receiver paths, such as Figure 1 For clarity, a single path is shown in the exemplary transceiver 300, but it is understood that the components between the DAC and upconverter in the transmitter path and the LNA and correlator in the receiver path may include both I and Q paths. Figure 3 The corresponding reference numerals in Figure 1 Those reference numerals in may therefore indicate both I and Q paths.

[0062] In the first approach, a second digital waveform generator 301, a DAC 302, and an upconverter 303 are provided to generate a scaled replica of the transmit path, which is combined with the received signal in the millimeter wave front end to cancel the self-interfering signal, for example, in the electromagnetic domain with a coupler, at the output of the modulator 303. The generator 301, combined with the DAC 302 and the modulator 303, generates a cancellation signal that is a scaled replica of the transmitted radar signal. The resulting cancellation signal is then applied after the LNA 110 to cancel the self-interference. The rest of the receiver architecture is as described above with respect to FIG. Figure 1 The examples shown in FIG. 1 and FIG. 2 function as described above, with corresponding reference numerals. The cancellation signal may generally be applied before or after LNA 110. For example, before or after range Doppler processing, digital feedback using the demodulated radar signal may be used to measure and estimate the self-interference signal to determine the correct digital waveform for generator 301.

[0063] The second method uses digital feedback to measure and estimate self-interference in the baseband after the down-conversion mixer 111. This is based on the fact that the baseband amplifier suffers significantly more self-interference due to processing the weaker signal levels presented at the radar front end. The received signal is amplified and down-converted in the receiver as usual. After the mixer 111, a scaled replica of the transmitted signal is subtracted from the received signal in the analog domain by current or voltage summation. This is estimated by the digital output of the cancellation signal generator 304, which provides the digital signal to the DAC 305. The DAC 305 outputs an analog signal to the received baseband signal via the reconstruction filter 306, which is then subtracted from the received baseband signal. The remainder of the baseband signal is then ideally composed of only the desired target reflections and is then amplified and converted to the digital domain in the ADC 114, after which it is processed in the digital domain to provide an output range-Doppler map.

[0064] To estimate the cancellation signal in the digital feedback path, the gain setting of the variable gain amplifier 112 should be set low for several chirps to ensure that the ADC 114 is not saturated and a proper estimate can be obtained.

[0065] Other methods for organic interference cancellation are possible, but the above examples are considered to be the most relevant for radar applications.

[0066] The above two methods use a DAC to generate a continuous time signal to cancel the self-interference signal embedded in the incoming radar signal in the continuous time domain. Subtracting the signal in the continuous time domain introduces a severe trade-off. The cancellation method at the carrier causes considerable signal loss in the summing node and causes more noise to be added to the cancellation signal, resulting in a considerable reduction in the noise figure of the receiver. This can be seen, for example, in reference [8]. In addition, an additional replica transmitter is required at the millimeter wave carrier, which adds considerable complexity and area, and therefore increases cost. On the other hand, the cancellation in the continuous time domain in the baseband requires analog circuit summation, which introduces noise and also introduces new constraints on the impedance between the mixer 111, the DAC 305 and the VGA 112, voltage headroom limitations and nonlinearities, all of which can impair performance. In addition, this method requires very precise timing control of the two paths. In the baseband cancellation method, a DAC 305 with a reconstruction filter 306 is required. This filter 306 adds group delay to the cancellation signal, making it more difficult to time-align the cancellation signal with the continuous input signal that depends on process variations, frequency and temperature.

[0067] To overcome the above issues, cancellation can be performed in baseband in discrete time, allowing sampling and cancellation to be combined in a single block. In the first phase, the input baseband signal with interference is sampled to move the signal into the discrete time domain. In the second phase, cancellation is performed, and in the third and final phase, the discrete-time residual is amplified. This process eliminates the timing requirements stemming from the analog filter group delay and also removes the tradeoffs associated with analog addition of current or voltage at the mixer's output. Increased linearity can be achieved because the desired signal is sampled at a relatively small location, resulting in relaxed requirements for the sampling operation.

[0068] Figure 4a A conventional method of summing, canceling, and amplifying baseband signals for removing self-interference is shown. Figure 4b An example of the proposed method is shown in which sampling, summing and cancellation are integrated.

[0069] exist Figure 4a In the conventional method in , the summing and cancellation of the self-interference signal are performed first, then the residue is amplified by the VGA 112, and finally sampling and quantization are performed. As described above, this causes difficulties such as time alignment.

[0070] exist Figure 4b In the proposed method shown in , the sampling step is moved forward (with or without a buffer at the output of mixer 111). Since the signal after mixer 111 is relatively small and may be heavily contaminated by noise, it is possible to sample the input signal linearly despite the presence of the self-interfering signal. The second step is to eliminate the self-interfering signal. The residual signal is then amplified by VGA 112 and finally digitized by ADC.

[0071] Figure 5 An exemplary schematic block diagram of a complete radar transceiver 500 is shown in FIG. Figure 1 and 3 As shown in FIG, transceiver 500 may include both I and Q paths on the receiver and transmitter sides for clarity. Figure 5 A single path is shown in FIG. Radar transceiver 500 includes a digital signal generator 501 configured to generate a digital baseband transmission signal. Digital signal generator 501 may also provide the digital baseband transmission signal to other transceivers in a multi-transceiver implementation. Transmitter DAC 502 converts the digital baseband transmission signal into an analog baseband transmission signal. Local oscillator (LO) module 503 generates a carrier signal, which is mixed with the analog baseband transmission signal at upconverter 504. Upconverter 504 mixes the carrier signal with the analog baseband transmission signal to generate an RF transmission signal. LO module 503 may be configured to generate a chirped carrier signal, while the quadrature mixer and DAC may be configured to operate a phase shifter. RF amplifier 505 amplifies the RF transmission signal for transmission via transmit antenna 506.

[0072] The RF transmit signal reflects from one or more targets 518, providing a reflected signal received by the receiver antenna 507, as well as self-interfering signals received directly from the transmit antenna 506 and / or reflected from close-range static reflectors such as bumpers. The RF signal received by the receive antenna 507 is amplified by an RF amplifier 508. The amplified received RF signal is downconverted by mixing with a carrier signal from the LO 503 at a downconverter 509 to provide an analog baseband received signal.

[0073] The correction module 510 receives the analog baseband receive signal from the downconverter 509 and combines the analog baseband receive signal with the digital correction signal to provide a corrected analog baseband signal. The ADC or quantizer 511 receives the corrected analog baseband signal and converts it into a digital baseband signal, which is then processed by the correlator module 513, which combines the digital baseband signal with the output from the digital signal generator 501 to provide a combined digital output signal.

[0074] Correction signal generator 512 generates and provides a digital correction signal for use by correction module 510 to correction module 510 , the digital correction signal being based on the modulated baseband transmit signal and the combined digital output signal.

[0075] In the correction module 510, self-interference cancellation occurs after downconversion. Sampling capacitor Cs and sampling switch 522 are used to capture the incoming signal (including the desired signal and the self-interference signal), thereby moving subsequent signal processing operations into the discrete time domain. A variable cancellation capacitor Cc is used (e.g., using charge sharing principles) to subtract the self-interference signal. The value of the cancellation capacitor Cc is driven by the control logic switch arrangement 520, which is equipped with a pre-calculated digital equivalent of the self-interference signal generated by the correction signal generator 512.

[0076] Both the sampling capacitor Cs and the switch arrangement 520 that controls the value of the cancellation capacitor Cc are operated according to a clock signal CK provided by a clock signal generator 521, which provides separate clock signals to the sampling switch 522 and the switch arrangement 520, so that charge redistribution at Cs and Cc occurs simultaneously during the cancellation phase.

[0077] After performing the subtraction, the residual signal stored on capacitors Cs, Cc contains the desired signal and the remainder of the subtraction between the self-interference and its quantized equivalent. This residual is amplified by baseband amplifier 519 and passed to the output of correction module 510 for further processing. Figure 5 The output of the correction module is provided to the ADC or quantizer 511 for digitization. The digital baseband signal is then similar to the above description of Figure 1 5. The digital baseband signal is processed as described, which involves processing by a correlator module 513 that combines the digital baseband signal with the output from the digital signal generator 501 to provide a combined digital output signal. In a practical implementation, the correlator module 513 may include a set of multipliers and summing blocks. Figure 6 An exemplary arrangement of such a correlator module 513, comprising a set of multipliers and summing blocks, is schematically shown in FIG. Each individual combination of multipliers and summing blocks 601 receives one digital symbol input from the ADC 511 and one digital symbol input from the analog transmitter. If the ADC output is aligned with the transmitted sequence, then there is a strong correlation, and based on the number of delayed symbols, the target range can be estimated.

[0078] When the transceiver 500 is configured to operate with an FMCW MIMO waveform, such as where the LO module 503 generates a chirped carrier signal and the quadrature mixer and DAC are phase shifters or when the DAC directly synthesizes the FMCW waveform, the correlator function may be replaced by an FFT.

[0079] There are many advantages to introducing the sampling operation (rather than quantization of the signal) after the downconverter mixer 509 and before the receiver analog-to-digital conversion.

[0080] First, self-interfering signal cancellation is performed in the discrete time domain using sampled data, simplifying the timing requirements between the incoming receive path and the cancellation path. Because the cancellation signal remains in the discrete time domain, reconstruction filters at the DAC in the cancellation path are no longer required. Consequently, the effects of filter group delay and the associated timing resolution requirements are eliminated. Furthermore, the clock used for sampling and cancellation operations can be shared.

[0081] Second, the three main functions are integrated into one: sampling, cancellation, and amplification. Because sampling is a linear operation, it is feasible to move the sampler earlier in the receiver chain. In addition, the sampler processes small signals, which simplifies the linearity requirements.

[0082] Third, in conventional approaches, summing is performed on a resistor- or current-based DAC. This introduces voltage headroom, noise, and linearity tradeoffs at the summing point related to the need for the DAC to have high impedance with respect to the mixer output and the VGA input. Scaling up the resolution becomes extremely difficult. With current approaches, the DAC is part of the sampling function, alleviating the voltage headroom requirement. The switched capacitor architecture instead provides the ease of resolution scaling for elimination. The only remaining tradeoff is the thermal noise of the sampler (i.e., kT / C noise).

[0083] Fourth, the ADC 511 following the correction module 510 may have relaxed dynamic range requirements compared to existing implementations because it operates with smaller signals at the ADC input.

[0084] Fifth, the proposed correction module 510 can remove any (target) signal in the range-Doppler map, provided that the signal can be accurately detected in the range or range-Doppler FFT output. This can be applied, for example, to very strong nearby targets, such as constant bumper reflection signals.

[0085] Finally, in a Figure 5Implementing correction module 510 in transceiver 500 enables the integration of sampling and cancellation operations into a single integrated unit. This approach also enables the use of a switched capacitor feedback amplifier, which provides gain for the desired signal after removing the interfering signal. This enhances the receiver's noise performance. Amplifier 519 can be a variable gain amplifier that is tunable depending on the operating mode. Before self-interference cancellation is active, amplifier 519 can be in a low gain setting to ensure linear operation and avoid subsequent clipping of ADC 511. Once self-interference cancellation is active, amplifier 519 can be set to a higher gain depending on system requirements.

[0086] Figure 7 An exemplary schematic implementation of the correction module 510 and the ADC 511 is shown in FIG. Figure 8 The clock signal phase φ within one clock cycle is shown in 1a 、φ 1b , φ2, φ3 timing diagram. In the first phase of the clock cycle φ 1a 、φ 1b In the embodiment, the sampling switch 522 and the first bias switch 701 are closed, thereby connecting the baseband received signal and the bias voltage V bias During the first clock phase, the variable capacitor Cc is also connected between the digital correction signal and the bias voltage V bias Between. Figure 7 In the example of FIG, the variable capacitor Cc comprises a switchable array of capacitors controlled by the switch arrangement 520 such that a selected subset of the array of capacitors is connected in response to receiving the digital correction signal. Thus, the value of the variable capacitor Cc connected during the first clock phase is determined by the digital value of the digital correction signal.

[0087] In the first phase (φ 1a 、φ 1b ), the baseband input signal is sampled on the sampling capacitor Cs, and one plate of the sampling capacitor Cs is biased at a voltage V bias At the same time, the input and output of amplifier 519 are shorted by amplifier feedback switch 704 to reset the charge on amplifier feedback capacitor 705. First bias switch 701 is then opened at the end of the first clock phase, thereby allowing node 706 to float between sampling capacitor Cs and the input of amplifier 519 to capture charge on sampling capacitor Cs, and then sampling switch 522 is opened. Figure 8 As shown in FIG, the first phase includes a clock signal phase φ having a common rising edge 1a 、φ 1b , and the phase φ 1a The falling edge occurs at phase φ 1bAfter the falling edge of , the sampling switch 522 is disconnected after the first bias switch 701 .

[0088] In the second phase φ2, which begins after the end of the first phase φ1 (i.e., the first and second phases do not overlap), charge is moved from the sampling capacitor Cs to the feedback capacitor 705 connected across the input and output of the amplifier 519. First, the amplifier input switch 703, which protects the amplifier from self-interference, is closed to enable charge to be transferred from the input capacitors Cs and Cc to the feedback capacitor 705, and the second bias switch 702 connects the bias voltage Vbias to the input node 708 between the sampling capacitor Cs and the sampling switch 522. The charge on the sampling capacitor Cs is transferred to the input of the amplifier 519, and simultaneously provides a charge corresponding to the cancellation signal at the summing node 706. As a result, only the charge of the desired signal is pushed toward the amplifier 519, and the self-interference is cancelled.

[0089] In a third phase φ3, which begins at the end of and overlaps with the second phase φ2, the amplifier 519 is stable and analog-to-digital conversion is performed by the ADC 511. The ADC sampling switch 607 in the ADC 511 takes the charge from the amplifier 519 and stores it on a DAC of a successive approximation register (SAR) ADC, after which conversion occurs and a digital output signal is provided from the ADC 511. Alternatively, the ADC 511 may be another type, such as a pipeline ADC.

[0090] Figure 7 The specific example shown in FIG uses a separate sampling capacitor Cs and a switched capacitor DAC. In an alternative embodiment, these two functions can be integrated into a single capacitor, i.e., it is possible to sample on top of the DAC capacitor Cc, thereby requiring fewer capacitors and more switches. In terms of timing, this means that resetting the DAC capacitor Cc needs to be done before sampling, whereas in the embodiment shown, resetting the DAC can be done during sampling.

[0091] Figure 7The proposed architecture introduces a transition from continuous-time to discrete-time baseband processing after mixer 509, but does not perform quantization of the desired radar signal. Therefore, the resolution requirements of the correction module 510 are only related to the accuracy level required to suppress the interfering signal, not the requirements of the signal to be detected. This maintains the properties of the ADC or quantizer 511 following the correction module 510 or cancellation circuit. Furthermore, the digital representation of the interfering signal is added back to the signal at the output of ADC 511 in the digital domain, thereby restoring the interfering signal to its original level and eliminating residual quantization artifacts that typically cover the entire range-Doppler map. In the subsequent ADC function, there are no timing accuracy requirements other than those for resampling (the sampler in the cancellation stage becomes the speed / timing critical stage of the receiver), while the inherent gain function of the cancellation relaxes the dynamic range and quantization requirements of the main ADC function in conventional receivers. In practice, the cancellation capacitors can deviate from their ideal values ​​in silicon implementations. This can introduce second-order errors when the digital representation of the cancellation signal is added back to the digital domain. This error can be removed by estimating or measuring the actual capacitor values ​​and using these estimates when adding a digital representation of the cancellation signal.

[0092] Radar transceiver 500 operates in two modes. In the first calibration mode, correction signal generator 512 monitors the output from the receiver side and determines the signal to be cancelled, which may be a self-interference signal along with other ghost or reflection signals that need to be removed from the original baseband signal. In the second operating mode, correction signal generator 512 provides the cancellation signal to correction module 510 to remove the signal.

[0093] In the first calibration mode, noise ridges from baseband nonlinearity, which can originate from antenna leakage or bumper reflections that remain static during radar operation, can be eliminated. During this mode, several training chirp sequences can be transmitted. These chirp sequences are linearly received and amplified using the low gain setting of the VGA 519. In this way, after processing, the interference power typically residing in the first pair of range bins can be captured and estimated. After several chirp sequences, digital estimates of the signals at these bins are provided to the correction module 510. The gain of the VGA 519 can then be slowly increased toward the desired gain setting while repeatedly measuring the self-interference at the correlator output and feeding it back to the correction module 510.

[0094] In a second operating mode during normal radar operation, the correction signal generator can be operated to cancel targets in any range bin that may be dynamically generated during radar observations. While antenna leakage and bumper reflections will tend to generate self-interference that can always be canceled at baseband, as described above, other signals may still be present in the LNA and mixer circuits.

[0095] Figure 9Shows the use of short bit stream input with Figure 7 Simulation results of transceiver 500 with correction module 510. The input bit stream is filtered using a second-order low-pass filter. The same bit stream is applied to the cancellation DAC. Figure 9 A time domain graph showing a schematic simulation of a bitstream input signal is shown, showing a comparison between the original bitstream 901 and the cancelled bitstream 902, illustrating the difference in swing at the output of the quantizer when cancellation is not applied and when cancellation is applied. Due to the DAC resolution and the subsequent applied gain, the ADC output is reduced by 4 LSBs.

[0096] In summary, the present disclosure proposes a mixed-signal cancellation circuit that operates in the discrete time domain and is capable of removing self-interference in a digitally modulated radar transceiver with substantially better performance and flexibility than existing known implementations. The transceiver is able to cancel the effects of cross-modulation / nonlinearity of the millimeter-wave front-end amplifier within the baseband without the RF cancellation penalty of existing implementations.

[0097] The implementation of the transceiver may be within a MIMO radar system, i.e., where there are multiple transceivers. Each transceiver may be used as an FMCW, PMCW, or OFDM radar transceiver. Figure 10 An exemplary arrangement for a MIMO radar system is shown in FIG. Figure 5 MIMO radar system 1000 includes multiple transmitter channel modules 1001 1-n and corresponding multiple receiver channel modules 10021-n. The common processor (CPU) 1003 receives the range-Doppler map output from the receivers 10011-n and provides the transmission signal to the transmitter 1001 1-n and provides the cancellation signal to the receiver 1002 1-n A correction module is included in each receiver.

[0098] Multiple receivers 1002 1-n Each receiver in the Figure 7 The self-interference cancellation loop described above. Each receiver receives multiple self-interfering reflections from all available transmit antennas, resulting in multiple receive chirps that need to be cancelled. The information required for this is obtained from the corresponding range-Doppler processing of all receivers to obtain phase and amplitude information belonging to each sequence. This information is used in the CPU 1003 to process each corresponding sequence and estimate the cancellation signal for all reflections. The CPU 1003 then feeds back to each corresponding receiver 1002 based on the measured phase and amplitude of each transmit sequence. 1-n Elimination signal.

[0099] For other transceiver examples, the receive and transmit paths in the MIMO transceiver 1000 may include both in-phase and quadrature paths. Figure 10 A single path in each case is shown.

[0100] From reading this disclosure, other variations and modifications will be apparent to those skilled in the art.Such variations and modifications may involve equivalent and other features which are already known in the art of radar transceivers and which may be used instead of or in addition to features already described herein.

[0101] Although the appended claims refer to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any combination of novel features or any generalization of the novel features disclosed herein, whether or not the novel feature relates to the same invention as currently claimed in any claim or whether the novel feature alleviates any or all of the same technical problems as those alleviated by the present invention.

[0102] Features described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, individual features described in the context of individual embodiments for the sake of brevity may also be provided individually or in any suitable subcombination. Applicants hereby caution that new claims may be formulated based on such features and / or combinations of such features during the prosecution of this application or any further application derived therefrom.

[0103] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single processor or other unit may fulfil the functions of several components recited in the claims, and the reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A radar transceiver (500), characterized in that: include: A digital signal generator (501) configured to generate a digital baseband transmission signal; a transmitter DAC (502) configured to convert the digital baseband transmission signal into an analog baseband transmission signal; A local oscillator (LO) module (503) configured to generate a carrier signal; an upconverter (504) configured to mix the carrier signal with the analog baseband transmission signal to generate an RF transmission signal; an RF amplifier (505) configured to amplify the RF transmission signal; a transmitting antenna (506) configured to transmit the amplified RF transmission signal; a receiving antenna (507) configured to receive RF signals; a receiving RF amplifier (508) configured to amplify a receiving RF signal; a downconverter (509) configured to mix the carrier signal with the amplified receive RF signal to provide an analog baseband receive signal; a correction module (510) configured to combine the analog baseband received signal with a digital correction signal to provide a corrected analog baseband signal; an ADC (511) configured to receive the corrected analog baseband signal and provide a digital baseband signal; as well as a correction signal generator (512) configured to generate the digital correction signal based on the digital baseband transmission signal and the digital output signal of the transceiver (500) and provide the correction signal to the correction module (510), The correction module (510) includes a sampling capacitor (Cs), a variable cancellation capacitor (Cc) controllable by the digital correction signal, an amplifier (519), and a switch arrangement (520), wherein the switch arrangement (520) is configured to sample the baseband received signal and sum the sampled charge across the sampling capacitor (Cs) with the charge across the variable cancellation capacitor (Cc) to provide a residual signal to the amplifier (519), and the amplifier (519) is configured to amplify the residual signal to provide the corrected analog baseband signal to the ADC (511).

2. The radar transceiver (500) according to claim 1, characterized in that Furthermore, a clock signal generator (521) is included, which is configured to provide a clock signal (CK) to the switch arrangement (520) and to a sampling switch (522) connected to the sampling capacitor (Cs).

3. The radar transceiver (500) according to claim 2, characterized in that The clock signal (CK) includes a first phase (φ1) in which the sampling switch (522) is closed and charge is transferred to the sampling capacitor (Cs), and a second phase (φ2) in which the sampling switch (522) is open and the charge is transferred to the input of the amplifier (519).

4. The radar transceiver (500) according to claim 3, characterized in that The correction module (510) comprises: a first bias switch (701) configured to connect a bias voltage (Vbias) to a summing node (706) during a first clock phase (φ1) and to be open during the second phase (φ2); A second bias switch (702) is configured to connect the bias voltage (Vbias) to an input node (708) between the sampling capacitor (Cs) and the sampling switch (522) during a second clock phase (φ2) and to be disconnected during the first clock phase (φ1).

5. The radar transceiver (500) according to claim 4, characterized in that The correction module (510) comprises: an amplifier input switch (703) configured to connect the summing node (706) to the input of the amplifier (519) during the second clock phase (φ2); an amplifier feedback switch (704) configured to connect the input and output of the amplifier (519) during the first clock phase (φ1); and An amplifier feedback capacitor (705) is connected between the input and the output of the amplifier (519).

6. The radar transceiver (500) according to any one of claims 3 to 5, characterized in that: The clock signal (CK) includes a third phase (φ3) in which the charge from the output of the amplifier (519) is transferred to the ADC (511).

7. The radar transceiver (500) according to claim 6, characterized in that The ADC (511) includes an ADC sampling switch (607) configured to connect the output of the amplifier (519) to the ADC during a third clock phase (φ3).

8. The radar transceiver (500) according to any one of the preceding claims, characterized in that A correlator module (513) is included, the correlator module (513) being configured to correlate the digital baseband signal from the ADC (511) with the output from the digital signal generator (501) to provide the digital output signal.

9. A multiple-input multiple-output (MIMO) radar transceiver system (1100), characterized in that: Comprising a plurality of radar transceivers (500) according to any preceding claim.

10. A method of operating a radar transceiver according to any one of claims 1 to 8, characterized in that: The method comprises the following steps: In a first calibration mode, the correction signal generator (512) monitors a combined digital output signal and determines a signal to be cancelled from the analog baseband signal; and In a second mode of operation, the correction signal generator (512) provides the digital correction signal to the correction module (510) to cancel the signal from the analog baseband signal.

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