Test link anomaly locating apparatus, system, method, device, medium and program

Abstract

The application discloses a kind of test link exception positioning device, system, method, equipment, medium and program, it is related to computer technical field, including when testing link exception, processing component writes first enable bit to the first register of each node device, each node device enters low-power mode in response to first enable bit, to expose the position of unstable test link in low-power conversion process, each node device triggers link retraining in low-power mode, determines link exception position according to the flag bit state of second register, improves troubleshooting efficiency and abnormal positioning accuracy, saves time and labor cost.Therefore, the problems that the low work efficiency, high time and labor cost caused by the fact that the related art manual troubleshooting of link exception position cannot timely and effectively solve the abnormal problems are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and particularly relates to a test link exception positioning device, system, method, equipment, medium and program. BACKGROUND

[0002] Currently, a large number of servers produced by a factory end are equipped with GPU (Graphics Processing Unit, graphics processor) components, so the stress test of the GPU is also an important part before the servers are shipped.

[0003] In the process of the GPU stress test at the factory end, multiple error exceptions will be encountered, and in the numerous error exceptions, two types of exceptions can be roughly divided, one is GPU single fault, and the exception can be accurately pointed to the abnormal GPU in the error log. The other is an exception related to the GPU link, and the exception information cannot be directly indicated in the error log, and the production line staff needs to check it by himself. Since the GPU link is generally complex, there are many abnormal link positions and many abnormal situations, such as speed reduction, bandwidth fluctuation, ECC (Error Checking and Correcting, error checking and correction) error and the like, so the experience of the staff is required to be high, the work is very time-consuming and energy-consuming, and it is difficult to quickly find the abnormal position, which causes the production line to be congested, and the abnormal problems cannot be solved in time and effectively, which greatly affects the production capacity of the production line. SUMMARY

[0004] The present application provides a test link exception positioning device, system, method, equipment, medium and program to at least solve the problems that the manual checking of the link exception position cannot solve the abnormal problems in time and effectively, the work efficiency is low, the time and labor cost is high and the like.

[0005] The application provides a device for locating an abnormal position of a test link, the test link being composed of a graphic processor and a plurality of node devices, and the graphic processor and the plurality of node devices being in communication, wherein the device comprises: a first register and a second register of each node device; a processing component for writing a first enable bit into the first register of each node device when the test link is abnormal, and each node device entering a low-power mode in response to the first enable bit; the node device sending a first training sequence to the graphic processor in the low-power mode, the graphic processor returning a first response sequence, and the first response sequence being written into the second register when the node device and the graphic processor are in normal communication; and the processing component reading the second register of each node device and locating the abnormal position of the test link according to the reading result of the second register.

[0006] The application further provides a system for locating an abnormal position of a test link, comprising: a graphic processor and a plurality of node devices, the graphic processor and the plurality of node devices being composed of a test link, the test link being subjected to stress testing by a processing component, and the graphic processor and the plurality of node devices being in communication; and the device for locating an abnormal position of a test link as described in the above embodiment, which is used for locating the abnormal position of the test link.

[0007] The application further provides a method for locating an abnormal position of a test link, the method being applied to a processing component of the device for locating an abnormal position of a test link as described in the above embodiment, and comprising the following steps: writing a first enable bit into the first register of each node device when the test link is abnormal, each node device entering a low-power mode in response to the first enable bit, the node device sending a first training sequence to the graphic processor in the low-power mode, the graphic processor returning a first response sequence, and the first response sequence being written into the second register when the node device and the graphic processor are in normal communication; and reading the second register of each node device and locating the abnormal position of the test link according to the reading result of the second register.

[0008] The application further provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the methods for locating an abnormal position of a test link.

[0009] The application further provides a computer-readable storage medium, the computer-readable storage medium storing a computer program, and the computer program being executed by a processor to implement the steps of any of the methods for locating an abnormal position of a test link.

[0010] The application further provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the method for positioning a link exception as described above.

[0011] In the method for testing a link exception, the processing component writes a first enabling bit to a first register of each node device, each node device enters a low-power mode in response to the first enabling bit, and each node device triggers a link retraining in the low-power mode to expose a position of a link exception in a low-power conversion process. If the above embodiments cannot probe the position of the link exception, the control node device inserts an error cyclic redundancy check value in a data link layer packet sent by the control node device in the next time, and the position of the link exception is determined according to a flag bit state of a fourth register. The method improves the troubleshooting efficiency and the accuracy of the position of the link exception, and saves time and labor costs. Thus, the method solves the problems of low work efficiency and high time and labor costs caused by the fact that manual troubleshooting of the position of the link exception cannot timely and effectively solve the abnormal problem. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0013] Figure 1 A block schematic diagram of a device for testing a link exception provided by an embodiment of the application;

[0014] Figure 2 A block schematic diagram of a system for testing a link exception provided by an embodiment of the application;

[0015] Figure 3 A framework diagram of a system for testing a link exception provided by an embodiment of the application;

[0016] Figure 4 A flowchart of a method for testing a link exception provided by an embodiment of the application;

[0017] Figure 5 A whole logic schematic diagram of a system for testing a link exception provided by an embodiment of the application;

[0018] Figure 6 A whole architecture schematic diagram of a method for testing a link exception provided by an embodiment of the application;

[0019] Figure 7 A schematic diagram of a method for testing a link exception provided by an embodiment of the application.

[0020] Figure description: Test link anomaly location device 10 includes first register 110, second register 120, processing component 130, node device 140, graphics processor 150, and test link anomaly location system 20. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0022] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0023] After performing GPU stress testing, corresponding test logs are generated. The test logs contain a lot of error information. The test link anomaly localization system in this application only analyzes GPU-related link anomalies. Therefore, it is necessary to extract effective keywords from different log formats to determine whether the logs can clearly point to GPU anomalies.

[0024] Once the error message is identified as a GPU-related exception, some errors will automatically point to a problem with the GPU itself or have a clear exception. In these cases, there is no need to analyze the test path. However, if the error message is unclear, the test path needs to be analyzed to determine the specific location of the exception.

[0025] The traditional method of analyzing hardware links by viewing all PCI (Peripheral Component Interconnect) buses and connected device information is no longer sufficient to meet the requirements and cannot identify deeper problems.

[0026] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] An embodiment of this application provides a test link anomaly location device.

[0028] Specifically,Figure 1 A block diagram of a test link abnormality positioning device provided by an embodiment of the present application.

[0029] As shown in the figure, the test link is composed of a graphics processor 150 and a plurality of node devices 140, the test link uses a processing component to perform stress testing, and the graphics processor and the plurality of node devices communicate with each other, wherein the test link abnormality positioning device 10 comprises a first register 110, a second register 120, a processing component 130, a node device 140, and a graphics processor 150. Figure 1

[0030] Each node device 140 comprises the first register 110 and the second register 120, and the processing component 130 is configured to write a first enable bit to the first register 110 of each node device 140 when the test link is abnormal, each node device 140 enters a low-power mode in response to the first enable bit, the node device 140 sends a first training sequence to the graphics processor 150 in the low-power mode, the graphics processor 150 returns a first response sequence, and the first response sequence is written to the second register 120 when the communication between the node device 140 and the graphics processor 150 is normal; the processing component 130 reads the second register 120 of each node device 140 and locates the abnormal position of the test link according to the reading result of the second register 120.

[0031] It can be understood that, according to the embodiment of the present application, the processing component can write a first enable bit to the first register of the node device to force the node device to enter a low-power state and trigger link retraining in the low-power state. Since the low-power conversion process is more sensitive to signal integrity, it can effectively expose hidden link instability problems caused by poor contact, electromagnetic interference, circuit wiring defects, etc., improve fault detection rate, and based on the state feedback of the training sequence interaction, the abnormal position can be accurately located, the depth and reliability of abnormal detection are enhanced, and the dependence on the experience of technicians is reduced.

[0032] It should be noted that the processing component of the present application can be a BMC (Baseboard Management Controller), the first register is an LCR (Link Control Register), which is located in the configuration space of the node device, and the second register is a Link Status (link status register), and the node device can be a PCIe (Peripheral Component Interconnect Express) device, which is not limited.

[0033] ​The node device sends a first training sequence to the graphics processor in a low power state for negotiating link parameters, and the graphics processor returns a first response sequence indicating that the link training is completed and the parameters are confirmed. If the communication is normal, the success status will be written into a second register of the node device. The processing component reads the status of the second register of each node device. If there is any node device whose second register does not write a successful flag, it means that the link training between the node device and the graphics processor fails. The abnormal position can be determined in combination with the flag bit of the second register.

[0034] Specifically, the processing component writes a first enable bit to the LCR of each node device, where the LCR refers to a register for controlling and managing various parameters and states of network connection or communication link. In computer systems and network devices, LCR is usually used to set and adjust parameters such as working mode, speed, flow control, etc. of the link to ensure the stability and efficiency of network communication. The first enable bit is the (Extended Bit (Bit 4)) bit of the register, which represents the function of retraining the link in the link control register of the test link.

[0035] The test link needs to negotiate the following parameters by exchanging the first training sequence and the first response sequence when initializing or encountering communication problems: link speed, link width, equalization parameters, and polarity inversion, etc. This negotiation process is called link training. The link retraining between the node device and the graphics processor is used to detect the stability of the link, and to observe whether the link can successfully complete the training, so as to judge whether there is a problem of physical layer instability in the test link.

[0036] In the embodiment of the present application, a plurality of physical slots are arranged on the test link, and a node device 140 is arranged on each physical slot.

[0037] It can be understood that the embodiment of the present application can be arranged with a plurality of physical slots on the test link, and a node device is arranged on each physical slot, so that each slot corresponds to an independent node device. When a link abnormality occurs, the corresponding physical slot can be accurately positioned according to the abnormal position, so as to facilitate rapid troubleshooting and improve the fault identification efficiency.

[0038] In the embodiment of the present application, the test link abnormality positioning device 10 further comprises a third register and a fourth register.

[0039] Each node device comprises a third register and a fourth register; the processing component 130 is configured to write a third enable bit into the third register of each node device 140 when an abnormality of the test link is detected, and each node device 140 is responsive to the third enable bit to control the node device 140 to insert an erroneous cyclic redundancy check value in a data link layer packet to be sent next time; the processing component 130 reads the fourth register of each node device 140, and locates the abnormal position of the test link according to the reading result.

[0040] It can be understood that, by writing an enable bit into the third register, the embodiment of the present application can actively inject a CRC (Cyclic Redundancy Check) error, and locate the abnormal position of the test link according to the fourth register of the node device, thereby achieving active disturbance diagnosis and improving the detection rate of hidden faults.

[0041] It should be noted that the third register is configured to receive the third enable bit written by the processing component to trigger the node device to actively write an erroneous CRC value in a data link layer packet to be sent next time, thereby achieving "error injection", and the fourth register can be understood as a state register configured to record the response result of the link to the error. If the error is corrected, a corrected error flag bit is written, and it is proved that the tested link is normal. If the error is not corrected, an uncorrectable error flag bit is written, and it is proved that the tested link is unstable.

[0042] Specifically, if the abnormal position and abnormal information cannot be confirmed by the test link retraining, simulated abnormal disturbance test is performed. The processing component writes a bit0 bit of an EIR (Error Injection Register) to actively inject CRC error information in a data packet to be sent, and determines whether the link is stable by judging whether the link can correct the CRC error. If the link can correct the error, CE (Correctable Error) counting is recorded, the AER_CE_STATUS register is read, and the abnormal position information is located. If the link cannot correct the error, a UCE (Uncorrectable Error) interrupt is triggered, the AER_UE_STATUS register is read, and the abnormal position information is located. The AER_CE_STATUS register is a kind of error state register configured to report the state of correctable errors, and the AER_UE_STATUS register is configured to report the state of uncorrectable errors.

[0043] In the embodiment of the present application, the first register 110, the second register 120, the third register and the fourth register are all arranged in the configuration space of the node device 140.

[0044] It can be understood that the first register, the second register, the third register and the fourth register in the embodiments of the present application are all arranged in the configuration space of the node device, realizing unified control and diagnosis.

[0045] Specifically, the configuration space of the node device is a standardized register area built in each node device, used for storing device identity information, capability structure and control and state registers, without loading drivers or operating systems.

[0046] According to the test link exception positioning device provided in the embodiments of the present application, when testing the link exception, the processing component writes the first enable bit to the first register of each node device, each node device enters the low-power mode in response to the first enable bit, so as to expose the position of the unstable test link in the low-power conversion process, each node device triggers the link retraining in the low-power mode, and the position of the link exception is determined according to the flag bit state of the second register, thereby improving the troubleshooting efficiency and the exception positioning accuracy, and saving the time and labor cost. Therefore, the problem that the manual troubleshooting of the position of the link exception cannot effectively solve the abnormal problem in time, resulting in low work efficiency and high time and labor cost is solved.

[0047] Figure 2 The block diagram of the test link exception positioning system provided in the embodiments of the present application is shown.

[0048] As shown in Figure 2 , the test link exception positioning system 20 includes a graphics processor 150, a plurality of node devices 140 and a test link exception positioning device 10.

[0049] The test link is subjected to stress testing by using the processing component 130, and the graphics processor 150 and the plurality of node devices 140 communicate with each other; and the test link exception positioning device 10 is used for positioning the abnormal position of the test link.

[0050] It can be understood that the embodiments of the present application can realize the automatic and high-precision identification of the abnormal position in the PCIe test link by the cooperation of the graphics processor, the plurality of node devices and the test link exception positioning device.

[0051] Specifically, as shown in Figure 3 , the test link exception positioning system of the present application further includes a test link traversal module, an exception feature extraction module and a slot positioning module, and the three modules are sequentially executed in the process of analyzing the link exception, so as to position the abnormal position.

[0052] The test link traversal module actively probes and scans the entire test link to identify possible abnormal physical nodes, mainly including activating a low-power mode, triggering a link retraining function, and performing an error injection test. The activating low-power mode involves writing a first enable bit (Extended Bit (Bit 4)) to a first register of a node device, which is more likely to expose problems such as poor signal integrity and poor contact during power switching. The triggering link retraining function involves writing a second enable bit (Retrain Link Bit (Bit 5)) to the first register of each node device through a processing component, which forces the link to renegotiate and observes whether the training can be successfully completed. The performing error injection test involves actively injecting a CRC error in the data packet to test the error correction capability of the link if no problem is found through regular retraining. All node devices are traversed, and it is returned which devices fail, slow down, or narrow down during the retraining or error injection process.

[0053] The abnormal feature extraction module extracts identifiable abnormal types and characteristic values from the raw data obtained from the traversal module and reads key state registers. The LINK_STATUS register is used to determine whether the negotiated speed / width has decreased, the AER_CE_STATUS register is used to detect whether a correctable error has occurred, such as ERR_COR_Detect = 1 (Error Correctable Detection), and the AER_UE_STATUS register is used to detect whether an uncorrectable error has occurred, such as ERR_UNCOR_Detect = 1 (Error Uncorrectable Detection). The pre-set characteristic values are compared to distinguish the abnormal types and characteristic values.

[0054] The slot positioning module is used to determine the actual physical slot based on the characteristic values and provide standardized maintenance prompts based on the abnormal types.

[0055] The test link abnormal positioning system according to the embodiments of the present application cooperates with the graphics processor, the plurality of node devices, and the test link abnormal positioning device to realize automatic and high-precision identification of the abnormal position in the PCIe test link.

[0056] Figure 4 The test link abnormal positioning method provided by the embodiments of the present application is shown in the flowchart.

[0057] As shown in Figure 4 The test link abnormal positioning method is applied to the processing component of the test link abnormal positioning device, and the method includes the following steps:

[0058] In step S101, a first enable bit is written to a first register of each node device when testing a link exception, each node device enters a low-power mode in response to the first enable bit, the node device sends a first training sequence to the graphics processor in the low-power mode, the graphics processor returns a first response sequence, and the first response sequence is written to a second register when communication between the node device and the graphics processor is normal.

[0059] It can be understood that the embodiments of the present application can write a first enable bit to a first register of a node device when testing a link exception, force the node device to enter a low-power state, and trigger link retraining in the low-power state. Since the low-power conversion process is more sensitive to signal integrity, it can effectively expose hidden link instability problems caused by poor contact, electromagnetic interference, circuit wiring defects, etc., improve fault detection rate, and the state feedback based on training sequence interaction can accurately locate the abnormal position, enhance the depth and reliability of abnormal detection, and reduce the dependence on the experience of technical personnel.

[0060] It should be noted that the processing component of the present application can be connected to each node device to perform abnormal positioning operation on the test link between each node device and the graphics processor.

[0061] Specifically, in the factory end GPU stress test, the link exception detection includes implementing link retraining without interruption in the low-power state, as shown in Figure 6 Specifically:

[0062] The control processing component writes an Extended (Bit4) bit to the first register of all PCIe devices to activate the low-power conversion. In the process of power conversion, it is easier to expose the position of link instability, thereby determining whether the link has an exception.

[0063] The processing component writes a Retrain Link (Bit5) bit to the first register of all node devices to implement link retraining traversal without interruption. After the traversal is completed, the traversal result is registered to the Link Status (Bit0-Bit3). Whether the link has an exception is determined by reading whether there is a position return abnormal value in the second register after traversal.

[0064] The first register is a link control register, the second register is a link status register, the first enable bit is an Extended (Bit4) bit, the second enable bit is a Retrain Link (Bit5), the first training sequence is a TS1 (Training Sequence, training sequence) sequence, and the second response sequence is a TS2 sequence.

[0065] The link retraining is a handshake between all node devices and the graphic processor through the TS1 / TS2 ordered set, if the handshake fails or is degraded, an exception is exposed through the second register, and the link quality detection is realized without system restart, wherein the link retraining process comprises: writing the enable bit of the first register of the node device through the processing component to determine the trigger retraining request, at this time, the node device sends the TS1 sequence, wherein the TS1 sequence comprises: supported link speed, supported link width, whether to support equalization and polarity inversion information; the physical layer of the image processor parses the TS1, sends the TS2 sequence to the physical layer of the node device, confirms the common supported speed and width, if the equalization is supported, the equalization training is started, and the training state machine is set to enter the next stage; after both sides complete the training and reach an agreement, the result is written into the second register, wherein the second register records the training failure, speed reduction and other exception events, so as to determine the abnormal position.

[0066] In the embodiment of the application, after the first enable bit is written into the first register of each node device, the second enable bit is written into the first register of each node device, and each node device triggers the link retraining without interruption in response to the second enable bit.

[0067] It can be understood that the second enable bit can be written into the first register of each node device, and each node device triggers the link retraining without interruption in response to the second enable bit, so as to determine the link exception reason and ensure the consistency of the test condition and the reliability of the diagnostic result.

[0068] It should be noted that the second enable bit is Retrain Link (Bit5), which is used to trigger the link retraining without interruption.

[0069] In step S102, the second register of each node device is read, and the abnormal position of the test link is located according to the reading result of the second register.

[0070] It can be understood that the second register of each node device can be read, and the abnormal position of the test link is located according to the reading result of the second register, because the register reading delay is low (microsecond level), the state can be obtained immediately after the stress test, the fast feedback is realized, and the test effect and the accuracy of the abnormal result are improved.

[0071] In the embodiment of the application, the abnormal position of the test link is located according to the reading result of the second register, comprising: identifying the register state bit in the reading result; if the range of the register state bit is greater than or equal to a preset value, it is determined that the node device is normal; if the range of at least one register state bit is less than the preset value, the identifier of the node device is obtained, and the abnormal position of the test link is determined according to the identifier of the node device.

[0072] It can be understood that the embodiments of the present application can determine the abnormal reason of the test link based on the register state bit threshold, avoid subjective misjudgment, ensure the uniform, objective and repeatable judgment standard, and improve the abnormal positioning accuracy and maintenance efficiency.

[0073] It should be noted that if the speed and bandwidth are reduced abnormally, the abnormal information returned by the physical layer of the graphics processor can be read in the second register, and the corresponding characteristic value negotiated link width is less than the maximum width (negotiated link width < max width); the negotiated link speed is less than the maximum speed (negotiated link speed < max speed); the first points to the bandwidth reduction, and the second points to the speed reduction.

[0074] Specifically, the link abnormality existing in the link retraining process includes training failure, speed reduction and bandwidth reduction, wherein the first to seventh state bits in the second register are read, for example: if Bit0 = 0, it is determined that the training fails, if the values of Bit1-Bit3 are less than the nominal speed, it is determined that the speed is reduced abnormally, if the values of Bit4-Bit6 are less than the nominal bandwidth, it is determined that the bandwidth is reduced abnormally, and the fault position is located based on the abnormal type and device identification; if Bit0 = 1 (training is completed) and Bit1-Bit6 values are greater than the nominal value, it is determined that the node device is normal.

[0075] In the embodiments of the present application, if the read result carries the first response sequence, after it is determined that the node device is normal, further comprising: writing a third enable bit to the third register of each node device, each node device responding to the third enable bit; reading the fourth register of each node device, and locating the abnormal position of the test link according to the read result of the fourth register.

[0076] It can be understood that the embodiments of the present application can actively inject CRC errors by writing enable bits to the third register, locate the abnormal position of the test link according to the fourth register of the node device, realize active disturbance diagnosis, and improve the detection rate of hidden faults.

[0077] Specifically, by processing components deliberately inject error information in the outgoing data packet, by writing in the bit0 position of EIR, by judging whether the link can correct the error to determine whether the link is stable, if it can be corrected, the CE count record is made, the AER_CE_STATUS register is read to locate the abnormal position information; if it cannot be corrected, the UCE interrupt is triggered, and the AER_UE_STATUS register is read to locate the abnormal position information. If the link can correct the error, it can be understood that the tested link is normal and robust, and it is considered that the link has no exception; if the error cannot be corrected, it is considered that the link is unstable. Among them, CE and UCE have their own flag bits in the status register, and the state of the flag bit of CE or UCE is determined to determine the link exception.

[0078] In the embodiment of the application, the abnormal position of the test link is located according to the reading result of the fourth register, including: identifying the state of the cyclic redundancy check value in the reading result; if the cyclic redundancy check value returns to normal, it is determined that the node device has no exception; if the cyclic redundancy check value maintains error data, the identifier of the node device is obtained, and the abnormal position of the test link is determined according to the identifier of the node device.

[0079] It can be understood that the embodiment of the application can amplify the problem phenomenon by actively injecting CRC error and observing the recovery behavior, if it is judged that the CRC error is self-healing, it indicates that the node device has no exception, otherwise, the identifier of the node device is obtained, and the abnormal position of the test link is determined according to the identifier of the node device, to improve the objectivity and accuracy of diagnosis, to accurately locate the physical position, and to improve the efficiency of test.

[0080] It should be noted that the cyclic redundancy check is used for detecting the mechanism of data transmission error: each data packet contains a CRC check code, the receiving end recalculates the CRC according to the received data, and compares it with the CRC value carried in the packet, if it is inconsistent, it triggers the correctable error, wherein the common causes of CRC error: poor signal integrity, electromagnetic interference, poor gold finger contact, circuit board trace impedance mismatch, etc.

[0081] Specifically, as shown in Figure 7 If the CE is abnormal, the returned abnormal information can be read in the AER_CE_STATUS register, and the corresponding characteristic value is ERR_COR_Detect=1, if the UCE is abnormal, the returned abnormal information can be read in the AER_UE_STATUS register, and the corresponding characteristic value is ERR_UNCOR_Detect=1.

[0082] In the embodiment of the present application, the abnormal position is determined according to the identifier of the node device, comprising: obtaining a first correspondence relationship between the identifier of the node device and the arrangement position; taking the identifier of the node device as an index, querying the correspondence relationship to obtain the arrangement position of the node device, and determining the abnormal position of the test link according to the arrangement position of the node device.

[0083] It can be understood that, in the embodiment of the present application, the corresponding relationship between the node device identifier and the physical arrangement position can be queried to determine the abnormal position of the test link, thereby improving the troubleshooting and maintenance efficiency.

[0084] It should be noted that the first correspondence relationship between the identifier of the node device and the arrangement position is shown in Table 1, so as to display the corresponding specific slot information of the abnormal position, for the accurate positioning of the abnormal position by the operator.

[0085] Table 1: First correspondence relationship between identifier of node device and arrangement position

[0086]

[0087] For example, if the identifier of the node device is 81:00.0, the arrangement position is the switching board, and at this time, the oxidation of the switching uplink gold finger needs to be checked, and it is confirmed that the lock is in place.

[0088] In the embodiment of the present application, after the abnormal position of the test link is determined according to the identifier of the node device, comprising: obtaining a second correspondence relationship between the abnormal position and the abnormal type; taking the abnormal position as an index, querying the second correspondence relationship to obtain the abnormal type.

[0089] It can be understood that, in the embodiment of the present application, the second correspondence relationship between the abnormal position and the abnormal type can be obtained, and the abnormal type is queried by taking the abnormal position as an index, thereby improving the troubleshooting and maintenance efficiency.

[0090] It should be noted that the second correspondence relationship between the abnormal position and the abnormal type is shown in Table 2, and the node device can be determined according to the abnormal position, so as to query the key register characteristic value of the node device, and determine the abnormal type according to the characteristic value.

[0091] Table 2: Second correspondence relationship between abnormal position and abnormal type

[0092]

[0093] For example, if the abnormal position of the node device is queried, if the key register characteristic value of the node device negotiates the link width to be less than the maximum width, it indicates that the current abnormal type is speed reduction and bandwidth reduction.

[0094] In the embodiment of the present application, identifying whether the test link is abnormal comprises: obtaining error data of the graphic processor after stress testing; analyzing keywords in the error data to determine an abnormal result; if the abnormal result is a single fault of the graphic processor or a link abnormality, generating a maintenance suggestion report according to the abnormal position information of the single fault of the graphic processor or the link; and if the abnormal result does not show the fault reason, controlling a test link abnormality positioning system to locate the abnormal position.

[0095] It can be understood that, in the embodiment of the present application, after GPU stress testing, the type of abnormality can be determined by analyzing error data, if the reason for the abnormality is a single fault / link abnormality, a maintenance suggestion is generated, if the reason is unknown, the test link abnormality positioning system is controlled to locate the abnormal position, and the processing efficiency is improved.

[0096] Specifically, as shown in Figure 5 When the production line performs GPU stress testing, two error conditions can be encountered: one is a non-GPU related error, such as an alarm or error of other components caused during GPU stress testing, which is automatically ignored by the system; the other is a GPU related error, which automatically triggers the system. After the test item error, there is a corresponding error code, which can reflect the information of the abnormal component, such as SYS_BMC_001 pointing to BMC abnormality; SYS_GPU_001 points to the GPU component, and then triggers the system.

[0097] When the system encounters a GPU related error, the system analyzes the error log generated after GPU stress testing, and determines whether there is a clear abnormality direction by capturing keywords in the error log. If the log has a relatively clear abnormality direction, such as a fault of a certain GPU single body or a position of a GPU exchange board, the error information is reported, and the production line staff can directly repair or replace the abnormal position according to the error information; if the error log cannot point to a specific abnormal position, it will be processed in the test link abnormality positioning system. After running the automatic link analysis process, the system reports the abnormal position and abnormal information, and the production line staff can repair the abnormal position according to the information.

[0098] In the embodiment of the present application, a maintenance measure storage database is generated according to the abnormal position and the abnormal type.

[0099] Specifically, the corresponding specific slot information of the abnormal position is displayed to enable the operator to accurately locate the abnormal position, and the maintenance measures are fed back according to the abnormal information in the abnormal feature extraction module, for example: the abnormal information points to 73:00.0 card bandwidth reduction, the system will prompt the operator to check the GPU3 installation, whether the gold finger has dust, and check if there is no problem to try to reinstall the GPU3. After the production line operator performs the maintenance operation according to the system prompt, the maintenance action is prompted to input, and when the abnormal machine is retested, if the machine does not occur abnormal error, the system considers that the data analysis is effective, the maintenance suggestion is effective, and is recorded in the database. When similar abnormal conditions occur subsequently, the operator is prompted to perform the maintenance action. If the abnormal machine is retested, the same error still occurs, the system considers that the current maintenance suggestion is invalid, and discards this information and does not record it in the database.

[0100] In summary, the analysis time of the GPU pressure test abnormality of the production line is greatly reduced, the production efficiency of the production line is improved, compared with the traditional engineer analysis method, the accuracy of confirming abnormal problems is improved and the troubleshooting time is shortened, a large amount of manpower is liberated, the positioning of the abnormal position is more accurate, the replacement of parts in the traditional maintenance action is reduced, the material cost is greatly saved, the product quality is guaranteed, and the possibility of product quality problems after delivery is reduced.

[0101] It should be noted that the present application analyzes the possible test link abnormal problem, can be upgraded to classify and analyze all abnormal problems, and sorts all abnormal information and maintenance suggestions, and constantly improves the database to form an abnormal problem analysis system that is constantly learning and improving.

[0102] According to the test link abnormality positioning method provided by the embodiment of the present application, when the test link is abnormal, the processing component writes a first enable bit to the first register of each node device, each node device enters a low-power mode in response to the first enable bit, to expose the position of the unstable test link in the low-power conversion process, each node device triggers link retraining in the low-power mode, and determines the link abnormality position according to the flag bit state of the second register. If the above embodiments cannot probe the link abnormality position, the control node device inserts an error cyclic redundancy check value in the data link layer packet sent next time, to locate the abnormal position according to the flag bit state of the fourth register, improve the fault troubleshooting efficiency and abnormality positioning accuracy, and save time and labor cost. Therefore, the problem that manual troubleshooting of the link abnormality position cannot timely and effectively solve the abnormal problem, resulting in low work efficiency, high time and labor cost is solved.

[0103] The embodiments of the present application also provide an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps of any of the above-mentioned test link exception positioning methods.

[0104] In particular, the memory is used to store a computer program that can be run on the processor, and can include a high-speed RAM memory, and can also include a non-volatile memory such as at least one disk memory.

[0105] If the memory and the processor are implemented independently, the memory and the processor can be connected to each other through a bus and complete communication between each other, and the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The processor can be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0106] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program is configured to perform the steps of any of the above-mentioned test link exception positioning method embodiments when executed.

[0107] The embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of any of the above-mentioned test link exception positioning method embodiments.

[0108] Those skilled in the art will further realize that the mere concepts, teachings, and embodiments described herein are merely meant to provide an enabling description of the applications and are not intended to limit the scope of the applications. Therefore, embodiments or examples described herein are not meant to be limiting, but merely to aid in the understanding of the overall more complete disclosure of the applications. Accordingly, those skilled in the art will recognize that modifications and variations of the more complete description herein can be resorted to without departing from the spirit and scope of the applications. Therefore, it is intended that the applications encompass all such modifications and variations as fall within the scope of the applications. All articles, patents, and other publications that have been cited herein are incorporated herein by reference for the teachings relevant to the sentence and / or paragraph in which the article, patent, and / or publication is mentioned.

[0109] The above provides a display content acquisition method. The principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method and core idea of the present application. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application. These improvements and modifications also fall within the protection scope of the present application.

Claims

1. A test link anomaly location device, characterized in that, The test link consists of a graphics processor and multiple node devices. The test link utilizes processing components for stress testing. Communication occurs between the graphics processor and the multiple node devices. The device includes: Each node device has a first register, a second register, a third register, and a fourth register, wherein the first register is the link control register, the second register is the link status register, the third register is the error injection register, and the fourth register is the status register; A processing component is configured to, when the test link is abnormal, write a first enable bit to a first register of each node device, and each node device responds to the first enable bit to enter a low-power mode; write a second enable bit to the first register of each node device, and each node device responds to the second enable bit to trigger uninterrupted link retraining; in the low-power mode, the node device sends a first training sequence to the graphics processor; the graphics processor returns a first response sequence; when communication between the node device and the graphics processor is normal, the first response sequence is written to the second register; the processing component reads the second register of each node device and locates the abnormal position of the test link based on the reading result of the second register; The processing component is further configured to, when the test link is abnormal and the abnormal position of the test link is not located according to the reading result of the second register, write a third enable bit to the third register of each node device, and each node device responds to the third enable bit to control the node device to insert an erroneous cyclic redundancy check value in the next data link layer packet sent; the processing component reads the fourth register of each node device and locates the abnormal position of the test link according to the reading result.

2. The test link anomaly location device according to claim 1, characterized in that, The test link is equipped with multiple physical slots, and each physical slot is equipped with a node device.

3. The test link anomaly location device according to any one of claims 1-2, characterized in that, The first register, the second register, the third register, and the fourth register are all located in the configuration space of the node device.

4. A test link anomaly localization system, characterized in that, include: A graphics processor and multiple node devices are included, the graphics processor and multiple node devices forming a test link, the test link using the processing component to perform stress testing, and the graphics processor and multiple node devices communicating with each other. The test link anomaly location device according to any one of claims 1-3 is used to locate the abnormal position of the test link.

5. A method for locating anomalies in a test link, characterized in that, The method is applied to the processing component of the test link anomaly localization device according to any one of claims 1-3, wherein the method includes the following steps: When the test link is abnormal, a first enable bit is written to the first register of each node device. Each node device responds to the first enable bit and enters a low-power mode. In the low-power mode, the node device sends a first training sequence to the graphics processor. The graphics processor returns a first response sequence. When the communication between the node device and the graphics processor is normal, the first response sequence is written to the second register. Read the second register of each node device, and locate the abnormal position of the test link based on the reading result of the second register.

6. The test link anomaly localization method according to claim 5, characterized in that, After writing the first enable bit to the first register of each node device, the process includes: Write a second enable bit to the first register of each node device, and each node device responds to the second enable bit to trigger uninterrupted link retraining.

7. The test link anomaly localization method according to claim 5, characterized in that, The step of locating the abnormal location of the test link based on the read result of the second register includes: Identify the register status bits in the read result; If the range of the register status bits is greater than or equal to the preset value, then it is determined that the node device is not abnormal; If the range of at least one register status bit is less than a preset value, the identifier of the node device is obtained, and the abnormal location of the test link is determined based on the identifier of the node device.

8. The test link anomaly localization method according to claim 7, characterized in that, After confirming that the node devices are functioning normally, the following steps are also included: A third enable bit is written to the third register of each node device. In response to the third enable bit, each node device reads its fourth register and locates the abnormal position of the test link based on the reading result of the fourth register.

9. The test link anomaly localization method according to claim 8, characterized in that, The step of locating the abnormal location of the test link based on the reading result of the fourth register includes: Identify the status of the cyclic redundancy check value in the read result; If the cyclic redundancy check value returns to normal, it is determined that the node device is not abnormal; If the cyclic redundancy check value remains erroneous, the identifier of the node device is obtained, and the abnormal location of the test link is determined based on the identifier of the node device.

10. The test link anomaly localization method according to claim 7 or 9, characterized in that, Determining the abnormal location based on the identifier of the node device includes: Obtain the first correspondence between the identifier of the node device and its location; Using the identifier of the node device as an index, the corresponding relationship is queried to obtain the placement location of the node device, and the abnormal location of the test link is determined based on the placement location of the node device.

11. The test link anomaly localization method according to claim 7 or 9, characterized in that, After determining the abnormal location of the test link based on the identifier of the node device, the process includes: Obtain the second correspondence between the location of the exception and the type of the exception; Using the abnormal location as an index, the second correspondence is queried to obtain the abnormal type.

12. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the test link anomaly localization method as described in any one of claims 7 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the test link anomaly localization method as described in any one of claims 7 to 11.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the test link anomaly localization method as described in any one of claims 7 to 11.

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