Leakage treatment system and server

Abstract

The application discloses a liquid leakage processing system and a server, relates to the technical field of servers, and the system comprises a digital logic integrated unit and a latch unit. When receiving a liquid leakage abnormal signal, the digital logic integrated unit determines that power-off control needs to be performed on a host power supply of the server, generates a corresponding power-off control signal, and the latch unit performs signal latching on the power-off control signal according to a first voltage provided by a first power supply, so that the output of the first enable signal is maintained, so that the host power supply controller controls the host power supply to stop power supply according to the first enable signal, thereby completely shutting down the power supply of the server when the cooling liquid leaks, protecting the server board from impedance reduction or even short circuit caused by the dropping of the liquid cooling medium, effectively reducing the probability of device damage caused by the liquid leakage accident, solving the technical problem that the cooling liquid leakage easily causes damage to electronic equipment in the related art, and achieving the technical effect of improving the working reliability of the server.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to leakage control systems and servers. Background Technology

[0002] As computing demands increase, the power consumption of electronic devices is also rising, leading to a greater need for heat dissipation. To improve the heat dissipation efficiency of electronic devices, liquid cooling has been introduced.

[0003] In related technologies, the state of coolant is identified through leak detection, and an alarm is triggered when a coolant leak is confirmed, reminding staff to manually maintain the liquid cooling system in electronic equipment. However, this method has a long maintenance cycle, and the continuous dripping coolant can easily damage electronic equipment, reducing the reliability of server operation. Summary of the Invention

[0004] This application provides a leakage control system and a server to at least address the problem in the related art that coolant leakage can easily damage electronic equipment.

[0005] This application provides a leakage handling system for a server. The system includes: a digital logic integrated unit (DLU), whose input is connected to the server's baseboard management controller (BMD), for receiving a leakage abnormality signal output by the BMD and generating a power-off control signal based on the leakage abnormality signal; and a latching unit, whose first input is connected to the DLU, whose second input is connected to a first power supply, and whose output is connected to the server's host power controller. The latching unit is used to latch the power-off control signal based on a first voltage provided by the first power supply, generating a first enable signal so that the host power controller controls the host power supply to stop supplying power.

[0006] This application also provides a server that includes any of the above-described leakage handling systems.

[0007] Through this application, since the digital logic integrated unit can determine that the host power supply of the server needs to be powered off when it receives a leakage abnormality signal, it generates a corresponding power-off control signal according to the leakage abnormality signal. The latching unit latches the power-off control signal according to the first voltage provided by the first power supply, so that it maintains the output of the first enable signal before receiving other signals, so that the main power controller controls the host power supply to stop supplying power according to the first enable signal. In the event of coolant leakage, the power supply to the server is completely shut off, so as to protect the server boards from impedance reduction or even short circuit due to liquid cooling medium dripping, effectively reducing the probability of device damage caused by leakage accidents. Therefore, it can solve the technical problem that coolant leakage can easily damage electronic equipment, and achieve the technical effect of improving the working reliability of the server. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a connection diagram of a leakage control system provided in an embodiment of this application;

[0010] Figure 2 A schematic diagram illustrating the application of a leakage control system according to a specific embodiment of this application;

[0011] Figure 3 A connection diagram of a latching unit provided in a specific embodiment of this application;

[0012] Figure 4 A connection diagram of a leakage control system provided in one embodiment of this application;

[0013] Figure 5 This is a flowchart illustrating the leakage control system of a specific embodiment of this application;

[0014] Figure 6 This is a block diagram of a server provided in an embodiment of this application. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0016] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0017] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] With the introduction of liquid cooling systems, coolant circulation has become a concern in electronic devices, and coolant leakage has become a cause of damage. Current electronic devices use leak detection to confirm leaks and issue alarms, alerting staff to perform manual maintenance on the liquid cooling system. However, there is a time lag between the alarm and staff arrival at the site. During this time, coolant continues to drip, inevitably spilling onto electronic components and potentially causing damage.

[0019] To address the aforementioned technical issues, in related technologies, upon detecting a coolant leak, the Baseboard Management Controller (BMC) generates an alarm and sends it to maintenance personnel according to alarm push settings. Simultaneously, the controllable components of the BMC are powered off, shutting down the controlled power supply. However, this method only shuts down the controlled power supply and cannot disconnect the PSU (Power Supply Unit) power supply or standby power supply, inevitably causing damage to some electronic equipment and reducing the reliability of server operation.

[0020] To address the existing technical problems in related technologies, this application proposes a leakage handling system. Upon detecting a leakage anomaly, the system controls the host power supply of the server to shut down the power output through a digital logic integrated unit and a latching unit, thereby completely shutting down the power supply to the server. This allows for timely and effective overall power-off upon detecting leakage, protecting the server boards from damage caused by reduced impedance or even short circuits, thus maintaining the server's operational reliability.

[0021] The leakage control system of this application will now be described in detail with reference to the accompanying drawings.

[0022] Figure 1This is a connection diagram of a leakage control system provided in an embodiment of this application.

[0023] Reference Figure 1 As shown, the leakage handling system 100 of this application embodiment is applied to a server. The leakage handling system 100 includes: a digital logic integration unit 10 and a latching unit 20.

[0024] The digital logic integrated unit 10 has its input terminal connected to the baseboard management controller of the server. The digital logic integrated unit 10 is used to receive the leakage abnormality signal output by the baseboard management controller and generate a power-off control signal based on the leakage abnormality signal. The first input terminal of the latch unit 20 is adapted to be connected to the digital logic integrated unit 10, the second input terminal of the latch unit 20 is connected to the first power supply VCC, and the output terminal of the latch unit 20 is connected to the host power controller of the server. The latch unit 20 is used to latch the power-off control signal according to the first voltage provided by the first power supply VCC and generate a first enable signal so that the host power controller controls the host power supply to stop supplying power.

[0025] Specifically, the digital logic integrated unit 10 obtains leakage abnormality signals by establishing a connection with the server's baseboard management controller. Upon receiving the leakage abnormality signal, the digital logic integrated unit 10 identifies the signal and generates a corresponding power-off control signal. The digital logic integrated unit 10 can be implemented using an MCU (Microcontroller Unit), CPLD (Complex Programmable Logic Device), or similar devices.

[0026] The latch unit 20 latches the power-off control signal based on the first voltage provided by the first power supply VCC, maintaining the output of the first enable signal. The host power controller controls the host power supply to stop supplying power based on the first enable signal, completing the overall power-off control of the server. This protects the server boards from damage caused by impedance reduction or even short circuits due to liquid dripping, maintaining the server's operational reliability. The latch unit 20 effectively avoids false triggering caused by signal interference, ensuring that the host power supply will not automatically power on before the next AC power-on after being shut down, thus preventing equipment damage. The latch unit 20 can be implemented using logic state latches, analog latches, etc. The server's host power supply is the power unit that directly supplies power to the server motherboard and its core components (CPU (Central Processing Unit), memory, chipset, etc.), i.e., the server's PSU. It is responsible for converting alternating current (AC) to stable direct current (DC), providing the necessary voltage and current to the various hardware components inside the server.

[0027] This embodiment uses the digital logic integration unit 10 and the latch unit 20 to control the host power supply of the server to stop outputting power when a leakage event is detected, thus shutting down the entire server. At this time, even if coolant continues to drip onto electronic units such as the server motherboard, it will not cause damage to the devices, making it easy to maintain the reliability of the server's operation.

[0028] In some embodiments of this application, the digital logic integration unit 10 in the leakage handling system 100 can reuse the CPLD on the server motherboard, and the latch unit 20 can reuse the latch in the PSU, thereby reducing application costs and improving system integration.

[0029] Specifically, the server's BMC determines whether to send a leak event by analyzing the monitoring signals sent by the leak detection module. For example, the leak detection module can send high / low level signals to indicate a leak event, and the BMC can determine whether to send a leak event based on the level recognition; the leak detection module can also send the data it actually detects to the BMC, and the BMC can determine whether to send a leak event based on the data recognition, without any specific restrictions.

[0030] After detecting a leak, the BMC controls the interface signal between the server motherboard and the PSU, namely the PS_ON signal (power-off control signal), via the CPLD on the server motherboard to shut down the PSU. Upon receiving this signal, the PSU shuts off its power supply and latches the signal, thus keeping the PSU output off until maintenance personnel have handled the leak and reconnected the AC power supply. After re-initializing the latch, the PSU will start supplying power upon receiving the PSU_ON signal from the server motherboard.

[0031] For example, the latch in the PSU outputs a POWER_LATCH signal to the PSU control chip, so that the PSU control chip can switch the power supply state of the PSU based on the POWER_LATCH signal. After AC power-on, the latch defaults to latching a high-level signal (POWER_LATCH signal is high). At this time, the PSU control chip controls the PSU to be in the power supply output state, specifically supplying power to the server based on the AC power provided by the mains. At this time, the PSU supplies power to the server in two parts: continuous power supply (the power supply will not be interrupted even when the server is turned off, and it will usually only stop when the power cord is unplugged) and controlled power supply (referring to the power supply controlled by the internal chip of the server to power on and off). After a leakage event occurs, the latch receives a power-off control signal from the CPLD and latches a low-level signal (POWER_LATCH signal is low). At this time, the PSU control chip controls the PSU to be in the power-off state, that is, to stop supplying power to the server. At this time, both the continuous power supply part and the controlled power supply part of the server are in a de-energized state.

[0032] After power-on initialization, the PS_ON_CPLD signal controlled by the CPLD on the server motherboard is high by default. When a leakage event occurs, the CPLD controls the output of this signal to go low, that is, outputs a low-level signal (power-off control signal) to the latch in the PSU.

[0033] The PSU control chip detects the status of the POWER_LATCH signal. When the signal is high, it controls the PSU to be in power output mode; when the signal is low, it controls the PSU to be in power off mode.

[0034] In this embodiment, after the server detects a leakage anomaly, the latches in the motherboard CPLD and PSU control the PSU to shut down the power supply output, thereby shutting down all power to the server in the event of a coolant leak. This protects the server boards from impedance reduction or even short circuits caused by the dripping of liquid cooling medium, effectively reducing the probability of device damage caused by leakage accidents.

[0035] Combination Figure 2As shown, in some embodiments of this application, the leakage handling system 100 further includes a first resistor R21. One end of the first resistor R21 is connected to the output terminal of the digital logic integrated unit 10 and forms a first node. The other end of the first resistor R21 is connected to a second power supply P3V3_STBY. The second power supply P3V3_STBY is used to provide a second voltage. The first node is used to output a power-off control signal according to a first state signal and a second voltage. When the digital logic integrated unit 10 receives a leakage abnormality signal, it generates a low-level signal according to the leakage abnormality signal and uses the low-level signal as the power-off control signal. When no leakage abnormality signal is received, the output terminal of the digital logic integrated unit is in a high-impedance state.

[0036] Specifically, taking the CPLD of the server motherboard as an example, the server's baseboard management controller performs leakage detection through the leakage detection module connected to it. When a leakage event is detected, it transmits the PSU_OFF signal (i.e. leakage abnormal signal) that requires the PSU to be powered off to the motherboard CPLD.

[0037] When no leakage abnormality signal is received, the CPLD configures PS_ON_CPLD to a high-impedance state and uses the second power supply P3V3_STBY to pull the signal high through the first resistor R21. This ensures that the signal is high when AC power is on and no leakage event has occurred, thus maintaining the PSU's power-on state. When a leakage event occurs, the CPLD, based on the received leakage abnormality signal, pulls PS_ON_CPLD low (i.e., the first state signal), thereby outputting a low level to the latch to control the state of shutting off the PSU power supply output. Resistor R22 is a current-limiting resistor to improve system operational safety.

[0038] This embodiment uses the first resistor R21 in conjunction with the geothermal voltage provided by the second power source to switch the PS_ON_CPLD signal, thereby achieving power supply status control of the PSU and ensuring the accuracy of status control.

[0039] In some embodiments of this application, the first power supply VCC is the host power supply, and the second power supply P3V3_STBY is the motherboard power supply of the server. The leakage handling system 100 further includes a voltage isolation unit 30. The digital logic integrated unit 10 is connected to the latch unit 20 through the voltage isolation unit 30. The voltage isolation unit 30 is used to isolate the voltage of the first power supply VCC and the second power supply P3V3_STBY.

[0040] Specifically, the first voltage provided by the first power supply VCC is the output voltage of the PSU, and the second voltage provided by the second power supply P3V3_STBY is obtained by stepping down the output voltage of the PSU through a step-down module, and is used to power the server motherboard. The voltage isolation unit 30 transmits the isolated voltage of the PS_ON_CPLD signal to the PSU to isolate the motherboard power supply and the output voltage of the PSU, preventing the first power supply VCC from affecting the server motherboard and improving the server's operational stability. The voltage isolation unit 30 can be constructed using optocoupler isolation, capacitor isolation, or other methods, and there are no specific limitations.

[0041] Combination Figure 3 As shown, in some embodiments of this application, the latching unit 20 includes: a second resistor R5, one end of which is connected to a first power supply VCC; a third resistor R4, one end of which is connected to the first power supply VCC; a fourth resistor R3, one end of which is connected to the other end of the third resistor R4 and has a second node U1, and the other end of which is connected to the other end of the second resistor R5 and has a third node U2, wherein the third node U2 serves as the first input terminal of the latching unit 20; a first switch Q2, the first end of which is connected to the third node U2, and the second end of which is grounded; a second switch Q1, the first end of which is connected to the second node U1, the second end of which is connected to the third end of the second switch Q2 and has a fourth node U3, and the third end of which is connected to the third node U2; a fifth resistor R2, one end of which is connected to the third node U2; and a fourth resistor R4, one end of which is connected to the first power supply VCC; a fifth resistor R2, one end of which is connected to the first power supply VCC; a sixth resistor R4, one end of which is connected to the second power supply VCC; a seventh resistor R5, one end of which is connected to the second power supply VCC; a eighth resistor R4, one end of which is connected to the other end of the third resistor R4 and has a second node U1, and the other end of which is connected to the other end of the second resistor R5 and has a third node U3, and the third end of which is connected to the third node U2; a seventh resistor R2, one end of which is connected to the first power supply VCC; a truncation terminal, one end of which is connected to the first power supply VCC; a truncation terminal, one end of which is connected to the first power supply VCC; a truncation terminal R4, one end of which is connected to the other end of the third power supply VCC; a truncation terminal R5, one end of which is connected to the first power supply VCC; a The first switch Q3 is connected to the fourth node U3, and the other end of the fifth resistor R2 is grounded. The third switch Q3 has its first end connected to the second node U1 and its third end connected to the fourth node U3. The sixth resistor R7 has one end connected to the second end of the third switch Q3 and has a fifth node U4. The other end of the sixth resistor R7 is grounded. The fifth node U4 serves as the output of the latch unit 20. When the input of the latch unit 20 receives a power-off control signal, the first switch Q2 and the second switch Q1 are in the on state, the third switch Q3 is in the off state, and the output of the latch unit 20 outputs a low-level signal to enable the host power controller to control the host power supply to stop supplying power. When no power-off control signal is received, the first switch Q2 and the second switch Q1 are in the off state, the third switch Q3 is in the on state, and the output of the latch unit outputs a high-level signal.

[0042] Specifically, the first switch Q2, the second switch Q1, and the third switch Q3 can be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), IGBTs (Insulated-Gate Bipolar Transistors), etc. The following describes the operation of the latch unit 20 in detail, taking the first switch Q2, the second switch Q1, and the third switch Q3 as examples of using MOSFETs.

[0043] When the PSU is powered on via AC, the VCC voltage gradually rises from 0 level until it reaches the preset voltage state.

[0044] During the VCC voltage rise, VCC pulls up the voltage at the second node U1 through the third resistor R4, and pulls up the voltage at the third node U2 through the parallel connection of resistors (R4+R3) and R5. During power-up, the voltage values ​​of U1 and U2 are equivalent, ensuring that the voltage difference of Vgs of the second switch Q1 is approximately 0, controlling the second switch Q1 to be in the off state. When the second switch Q1 is in the off state, the voltage of the fourth node U3 is obtained at a 0 level through the pull-down resistor, thereby controlling the voltage difference of Vgs of the first switch Q2 to be 0, making Q2 in the off state. At this time, the node voltages U1=U2=VCC, and U3=0. When the VCC voltage continues to rise and VCC exceeds the threshold voltage Vth of Q3, Q3 is turned on, and the node voltages U4=U1=VCC, thus latching the POWER_LATCH signal to a high level VCC.

[0045] When PS_ON is pulled low, the node voltage U2 at the third node U2 is 0. Through resistor selection, the Vgs of Q1 is made to be less than its threshold voltage Vth, so Q1 is turned on. At this time, the node voltage U3 = U1 = VCC*R2 / (R4+R2). Through resistor selection, U3 is made to be greater than the threshold voltage Vth of Q2, so Q2 is turned on, thus making PS-ON latched to a 0 level. At this time, the node voltage U1 = U3, so the Vgs voltage difference of Q3 is 0, thus turning off Q3, so that the node voltage U4 obtains a 0 level through R7 ground, and POWER_LATCH is latched to a low level, that is, the first enable signal is output to the host power controller to control the host power supply PSU to stop supplying power.

[0046] This embodiment uses a latching unit 20 composed of a switching transistor and a resistor to meet the control accuracy requirements.

[0047] In some embodiments of this application, the latch unit 20 further includes: a first filtering subunit, used to filter the input signal of the latch unit so as to output the filtered input signal to the third node U2; and a second filtering subunit, used to filter the output signal of the latch unit so as to send the filtered output signal to the host power controller.

[0048] In other words, by constructing a first filtering subunit and a second filtering subunit at the first input and output terminals of the latch unit 20 respectively, the input signal is filtered by the first filtering subunit, which improves the working quality of the latch unit 20 and avoids adverse effects of external interference on the controllable effect; the output signal of the latch unit 20 is filtered by the second filtering subunit to improve the quality of the output signal and ensure the working stability of the host power supply.

[0049] In some embodiments of this application, the first filtering subunit includes: a filtering resistor, one end of which is connected to the third node U2; and a filtering capacitor, one end of which is connected to the other end of the filtering resistor, the other end of which is grounded. The filtering capacitor is configured to be in a low-impedance state when the frequency of the input signal is higher than the cutoff frequency, so as to bypass the high-frequency components in the input signal to ground. The cutoff frequency is determined based on the capacitance value of the filtering capacitor and the resistance value of the filtering resistor.

[0050] Specifically, the second filter subunit can adopt the same circuit structure as the first filter subunit, such as... Figure 3 As shown, this embodiment uses an RC filter constructed from the seventh resistor R6 and the first capacitor C1 as the first filtering unit to preprocess the PS_ON signal input to the latch unit 20, thereby suppressing high-frequency noise and interference in the PS_ON signal and improving signal quality. This embodiment also uses an RC filter constructed from the eighth resistor R1 and the second capacitor C2 as the second filtering unit to filter out high-frequency noise and interference from the POWER_LACTH signal output from the latch unit 20, thereby improving signal quality.

[0051] In some embodiments of this application, the latch unit 20 further includes: a ninth resistor R24, one end of which is connected to the first power supply VCC, and the other end of which is adapted to be connected to the third node U2; a tenth resistor R25, one end of which is connected to the first power supply VCC, and the other end of which is adapted to be connected to the fifth node U4, wherein the resistance value of the tenth resistor R25 is greater than the resistance value of the sixth resistor R7, and the resistance difference between the tenth resistor R25 and the sixth resistor R7 is greater than a preset resistance value; wherein, when the input terminal of the latch unit 20 does not receive a power-off control signal, the third node U2 is at a high level based on the ninth resistor R24, and the fifth node U4 is at a high level based on the tenth resistor R25, so that the output terminal of the latch unit continuously outputs a high-level signal.

[0052] Specifically, in the case where the latch unit 20 reuses the latch in the host power supply, Figure 3 for Figure 2 The circuit diagram of the latch shows that latch unit 20 consists of a latch, a ninth resistor R24, and a tenth resistor R25. The ninth and tenth resistors R24 and R25 serve as pull-up resistors for the input and output terminals of the latch, respectively. The input terminal of the latch is connected to the first power supply VCC through the ninth resistor R24, and the output terminal is connected to the first power supply VCC through the tenth resistor R25. To ensure that both the input and output terminals of the latch are high-level signals during initialization, the ninth and tenth resistors R24 and R25 are used with relatively large resistance values. For example, when the resistance value of the pull-up resistor, i.e., the tenth resistor R25, is several times larger than the resistance value of the sixth resistor R7, it ensures that during initialization, the output level of the POWER_LATCH signal is less than 0.2*VCC. This indicates that the POWER_LATCH signal output is a low level, thus controlling the host power supply. The resistors R23 and R26 at the input and output terminals of the latch are used as current-limiting resistors. Relatively small resistance values ​​can be used to prevent large currents from appearing on the signal lines when the latch or chip malfunctions.

[0053] During application, the latch's input PS_ON and output POWER_LATCH are connected to VCC through resistors R24 and R25. After power-on, the latch's input and output are high-level signals by default to ensure that the PSU maintains its power supply output state after the AC source is powered on. When PS_ON is pulled low, the signal can be latched, so that the PS_ON input and POWER_LATCH output signals are latched to low level before the AC power is restored, thus keeping the PSU in a power-off state.

[0054] Combination Figure 3 As shown, during the leak detection process, Figure 2 The functions and working status of each unit are as follows:

[0055] The baseboard management controller detects leakage through its connected leakage detection module; when a leakage event is detected, it transmits the PSU_OFF signal, which requires the PSU to be powered off, to the digital logic integrated unit 10 (mainboard CPLD).

[0056] The digital logic integrated unit 10 controls the transmission of the PS_ON_CPLD signal to the voltage isolation unit. The CPLD configures the signal to a high-impedance state and uses the second power supply P3V3_STBY to pull the signal high through resistor R21 to ensure that the signal is high when AC power is on and no leakage event occurs, that is, to keep the host power supply on. When a leakage event occurs, the digital logic integrated unit pulls the signal low, that is, to shut down the power supply output of the host power supply.

[0057] The voltage isolation unit 30 transmits the PS_ON_CPLD signal to the host power supply after isolating the voltage. The function of the voltage isolation unit 30 is to isolate the motherboard power supply and the host power supply, so as to prevent the host power supply from affecting the safety of the motherboard.

[0058] The input PS_ON and output POWER_LATCH of the host power supply latch are connected to the first power supply VCC through resistors R24 and R25 respectively. After power-on, their input and output are high-level signals by default, ensuring that the host power supply output is maintained after AC power-on. When PS_ON is pulled low, the signal can be latched, so that the PS_ON input and POWER_LATCH output signals are latched to low level before AC power-on again, that is, the host power supply output is turned off.

[0059] The host power controller controls the power supply status of the host based on the POWER_LATCH signal status provided by the latch.

[0060] In some embodiments of this application, the leakage handling system 100 further includes: a process control unit 40, configured to control the server process to shut down and store data based on the leakage anomaly signal, and generate a feedback signal after determining that the process shutdown and data storage operations are completed; the digital logic integration unit 10 is further configured to generate a power-off control signal based on the leakage anomaly signal when the feedback signal is received.

[0061] In other words, the process control unit 40 is used to control the server processes and can be built based on the server's BIOS (Basic Input / Output System).

[0062] For example, taking the process control unit 40 as the server's BIOS and the digital logic integrated unit as the server motherboard's VPLD as an example, combined with... Figure 2As shown, the baseboard management controller detects whether a leakage event has occurred through the leakage detection module. If no leakage event is detected, it checks again after a preset delay. Once the baseboard management controller determines that a leakage event has occurred, it notifies the BIOS and CPLD to initiate the shutdown process. The BIOS, based on the server's current state, instructs the OS (Operating System) to close processes and store any necessary data. Upon receiving feedback that process closure and data storage are complete, the CPLD generates a power-off control signal based on the leakage anomaly signal.

[0063] In this embodiment, after detecting a leakage event, the process control unit 40 can notify the server to perform orderly shutdown and data storage. After the process shutdown and data storage are completed, the digital logic integration unit 10 controls the host power supply to stop supplying power, so as to avoid data loss caused by sudden shutdown.

[0064] In some embodiments of this application, the digital logic integration unit 10 is further configured to, upon receiving a feedback signal, control the server load to be powered off in a preset sequence, and after determining that the server load has been powered off, generate a power-off control signal based on the leakage abnormality signal.

[0065] Specifically, continuing with the example of the process control unit 40 being the server's BIOS and the digital logic integrated unit being the server motherboard's CPLD, and combining... Figure 2 As shown, the baseboard management controller detects whether a leakage event has occurred through the leakage detection module. If no leakage event is detected, it checks again after a preset delay. After the baseboard management controller determines that a leakage event has occurred, it sends a PSU_OFF signal, which requires the host power to be turned off, to both the BIOS and the motherboard CPLD. This allows the BIOS to perform the following process control operations based on the PSU_OFF signal; the motherboard CPLD remains in a waiting state.

[0066] The BIOS performs process control operations, specifically: when the BIOS receives the PSU_OFF signal, it notifies the OS to close the process and store the data that needs to be stored; after the BIOS determines that the OS has completed the process closure and data storage, it generates a feedback signal to the baseboard management controller.

[0067] After receiving the feedback signal, the baseboard management controller forwards it to the CPLD. The CPLD then determines that the server's data storage is complete based on the feedback signal and controls the server to enter an ordered power-off shutdown state. In other words, the CPLD controls all controlled power supplies, and during shutdown, it sequentially controls the power supply shutdown according to the stored shutdown power-off sequence.

[0068] After the CPLD confirms that the server has completed the orderly shutdown process, it controls the PS_ON_CPLD to output a low level based on the PSU_OFF signal, and controls the host power supply to stop supplying power through the latch unit 20.

[0069] In this embodiment, after the process is closed and data is stored, the digital logic integration unit 10 controls the server to shut down in an orderly manner to avoid server malfunctions due to abnormal power-down sequence.

[0070] Furthermore, leakage detection can be performed by different areas. When a leakage event occurs in a certain component area, the power to that area is cut off. This reduces the impact of leakage events on server operation while minimizing the impact on server reliability and preventing damage to electronic equipment.

[0071] Specifically, the server can be divided into multiple independent detection units, such as computing and storage areas, and a leakage detection sensor can be deployed in each area. Each leakage detection sensor sends a monitoring signal to the baseboard management controller. The baseboard management controller can then determine whether a leakage event has occurred in the corresponding area based on the monitoring signals sent by each leakage detection sensor. When a leakage event is determined to have occurred in a certain area, a leakage anomaly signal for that area is generated and sent to the digital logic integrated unit 10 (such as the motherboard CPLD) and the process control unit 40 (BIOS). The process control unit 40 can identify the processes associated with that area by recognizing the leakage anomaly signal and send a signal to the OS to control the associated processes to shut down and save data, generating a corresponding feedback signal to the baseboard management controller. After the baseboard management controller sends the feedback signal to the digital logic integrated unit 10, the digital logic integrated unit 10 can control the area to perform an orderly power-off shutdown to prevent damage to components caused by contact between live equipment and leaking coolant, thus ensuring the operational stability of the server.

[0072] As a specific embodiment of this application, the leakage handling system is as follows: Figure 2 , Figure 3 and Figure 4 As shown, based on this leakage handling system, the leakage handling workflow in the server is as follows: Figure 5 As shown, the following steps may be included:

[0073] S101: After the server powers on and initializes, it initializes the PS_ON_CPLD signal to a high-impedance state to keep the host power supply (PSU) in a power output state.

[0074] S102, the substrate management controller receives monitoring information from the leakage detection module to determine whether a leakage event has occurred. If no leakage event has occurred, step S103 is executed; if a leakage event has occurred, step S104 is executed.

[0075] For example, a leak detection module can be built based on intelligent sensing devices. These devices can employ fiber optic liquid sensors, which are densely distributed in areas such as server trays, motherboard interface slots, and power supply units. When continuous liquid coverage occurs for 5 seconds, an alarm is triggered. Alternatively, point-type pressure sensors can be used, which are placed at pipe interface locations to detect whether coolant leaks occur at the interface. Or, a conductivity induction array can be used, with 24 alloy contacts covering high-risk areas. A liquid impedance analysis algorithm can be used to distinguish between alcohol volatiles and actual liquid leaks, with a false alarm rate of less than 0.3%.

[0076] S103, delay for a preset time. Then, return to step S102 to check for a leak again. The preset time is the leak detection cycle, which can be set according to the control accuracy requirements.

[0077] S104, the baseboard management controller notifies the process control unit and the digital logic integrated unit to enter the shutdown process. The process control unit can be the server's BIOS, and the digital logic integrated unit reuses the CPLD on the server motherboard to reduce hardware costs.

[0078] S105, the process control unit notifies the operating system to close the process and store the data that needs to be stored according to the state of the server, and generates a feedback signal after the process is closed and the data is stored.

[0079] S106, the substrate management controller forwards the feedback signal to the digital logic integration unit.

[0080] S107: After receiving the feedback signal, the digital logic integrated unit controls the server to enter an orderly power-off shutdown state.

[0081] In other words, the digital logic integration unit remains in standby mode during steps S105 and S106, and only takes action after receiving a feedback signal.

[0082] S108, after the server's orderly shutdown process is completed, the digital logic integrated unit controls the PS_ON_CPLD signal to be low, and after transmission through the voltage isolation unit and latch, makes the POWER_LATCH signal low.

[0083] In other words, after detecting a liquid leakage event, the board management controller notifies the BIOS and the digital logic integrated unit (CPLD) to enter a sequential power-off process, and shuts down the power supply output of the power supply unit (PSU) after shutdown. The power-off sequence in the sequential power-off process can be preset.

[0084] The digital logic integrated unit controls the PS_ON_CPLD signal to be high by default after power-on initialization. When a leakage event occurs, the digital logic integrated unit controls the PS_ON_CPLD signal to be low.

[0085] The circuit design of the latch is as follows Figure 3 As shown, the system latches a high-level signal by default after AC power-on. Upon receiving a low-level signal from the digital logic integration unit, it latches both the input and output as low-level signals until AC power-on is resumed, at which point the signal state cannot be changed.

[0086] S109, after the host power controller receives a low level POWER_LATCH signal, it controls the host power supply to shut off the power output to the server.

[0087] In other words, the host power controller detects the status of the POWER_LATCH signal. When the signal is high, it controls the host power supply to be in the power output state; when the signal is low, it controls the PSU to be in the power off state.

[0088] Therefore, the leakage control system 100 can bring the following technical effects:

[0089] 1. When the server detects a liquid leak, the baseboard management controller can directly control the host power supply (PSU) to cut off the power through the digital logic integrated unit 10 to avoid damage to the equipment;

[0090] 2. After the baseboard management controller detects a leakage event, the process control unit 40 can realize the orderly shutdown of the server and data storage control to avoid data loss caused by sudden shutdown;

[0091] 3. The digital logic integration unit 10 can control the orderly power-off of the server to avoid server malfunctions due to abnormal power-off sequence;

[0092] 4. The latching unit 20 latches the power off signal, effectively avoiding false triggering caused by signal interference, and ensuring that the host power will not automatically power on before the next AC power-on after being turned off, thus avoiding damage to the equipment.

[0093] Therefore, in the leakage handling system of this application embodiment, the digital logic integrated unit can determine that the host power supply of the server needs to be cut off when a leakage abnormal signal is received. The system generates a corresponding power-off control signal based on the leakage abnormal signal. The latching unit latches the power-off control signal based on the first voltage provided by the first power supply, so that it maintains the output of the first enable signal before receiving other signals. This allows the main power controller to control the host power supply to stop supplying power based on the first enable signal, thereby shutting off all power to the server when coolant leakage occurs. This protects the server boards from impedance reduction or even short circuits caused by liquid cooling media dripping, effectively reducing the probability of device damage caused by leakage accidents. Therefore, it can solve the technical problem that coolant leakage can easily damage electronic equipment and achieve the technical effect of improving the operational reliability of the server.

[0094] Embodiments of this application also provide a server. For example... Figure 6 As shown, the server 1000 in this embodiment of the application includes any of the above-described leakage handling systems 100.

[0095] The leakage control system and server provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A leakage control system, characterized in that, The system, applied to a server, includes: A digital logic integrated unit, the input of which is connected to the baseboard management controller of the server, is used to receive the leakage abnormality signal output by the baseboard management controller and generate a power-off control signal based on the leakage abnormality signal. A latching unit, wherein a first input terminal of the latching unit is adapted to be connected to the digital logic integrated unit, a second input terminal of the latching unit is connected to a first power supply, and an output terminal of the latching unit is connected to the host power controller of the server, wherein the latching unit is used to latch the power-off control signal according to the first voltage provided by the first power supply, and generate a first enable signal so that the host power controller controls the host power supply to stop supplying power. The system also includes: A first resistor, one end of which is connected to the output terminal of the digital logic integrated unit to form a first node, and the other end of which is connected to a second power supply, wherein the second power supply is used to provide a second voltage, and the first node is used to output the power-off control signal according to the power-off control signal and the second voltage; When the digital logic integrated unit receives the leakage abnormality signal, it generates a low-level signal based on the leakage abnormality signal and uses the low-level signal as the power-off control signal. When the leakage abnormality signal is not received, the output terminal of the digital logic integrated unit is in a high-impedance state.

2. The leakage control system according to claim 1, characterized in that, The first power supply is the host power supply, the second power supply is the server motherboard power supply, and the system further includes: A voltage isolation unit is provided, through which the digital logic integrated unit is connected to the latch unit. The voltage isolation unit is used to isolate the first power supply and the second power supply from voltage.

3. The leakage handling system according to claim 1, characterized in that, The latch unit includes: The second resistor, one end of which is connected to the first power source; A third resistor, one end of which is connected to the first power source; A fourth resistor, one end of which is connected to the other end of the third resistor and has a second node, and the other end of which is connected to the other end of the second resistor and has a third node, wherein the third node serves as the first input terminal of the latch unit; A first switch transistor, the first end of which is connected to the third node, and the second end of which is grounded; The second switch has a first end connected to the second node, a second end connected to the third end of the second switch and has a fourth node, and the third end of the second switch is connected to the third node. The fifth resistor has one end connected to the fourth node and the other end grounded. The third switch is connected to the second node at its first end and to the fourth node at its third end. A sixth resistor, one end of which is connected to the second end of the third switching transistor and has a fifth node, and the other end of which is grounded, wherein the fifth node serves as the output terminal of the latch unit; When the power-off control signal is received at the input terminal of the latch unit, the first and second switching transistors are in the on state, the third switching transistor is in the off state, and the output terminal of the latch unit outputs a low-level signal so that the host power controller controls the host power supply to stop supplying power. In the absence of the power-off control signal, the first and second switching transistors are in the off state, the third switching transistor is in the on state, and the output terminal of the latch unit outputs a high-level signal.

4. The leakage control system according to claim 3, characterized in that, The latch unit further includes: The first filtering subunit is used to filter the input signal of the latch unit so as to output the filtered input signal to the third node; The second filtering subunit is used to filter the output signal of the latch unit so as to send the filtered output signal to the host power controller.

5. The leakage control system according to claim 4, characterized in that, The first filtering subunit includes: A filter resistor, one end of which is connected to the third node; A filter capacitor, one end of which is connected to the other end of the filter resistor, and the other end of which is grounded, is configured to be in a low-impedance state when the frequency of the input signal is higher than the cutoff frequency, so as to bypass the high-frequency components in the input signal to ground, wherein the cutoff frequency is determined based on the capacitance value of the filter capacitor and the resistance value of the filter resistor.

6. The leakage control system according to claim 3, characterized in that, The latch unit further includes: A ninth resistor, one end of which is connected to the first power source, and the other end of which is adapted to be connected to the third node; The tenth resistor has one end connected to the first power source and the other end adapted to be connected to the fifth node. The resistance value of the tenth resistor is greater than that of the sixth resistor, and the resistance difference between the tenth resistor and the sixth resistor is greater than a preset resistance value. Wherein, if the power-off control signal is not received at the input terminal of the latch unit, the third node is at a high level based on the ninth resistor, and the fifth node is at a high level based on the tenth resistor, so that the output terminal of the latch unit continuously outputs a high-level signal.

7. The leakage control system according to any one of claims 1-6, characterized in that, Also includes: The process control unit is used to control the server's processes to shut down and store data based on the leakage anomaly signal, and to generate a feedback signal after determining that the process shutdown and data storage operations are completed. The digital logic integration unit is also used to generate the power-off control signal based on the leakage anomaly signal when the feedback signal is received.

8. The leakage control system according to claim 7, characterized in that, The digital logic integration unit is also used for, Upon receiving the feedback signal, the server load is controlled to be powered off in a preset sequence, and after confirming that the server load has been powered off, the power-off control signal is generated based on the leakage anomaly signal.

9. A server, characterized in that, Includes the leakage treatment system according to any one of claims 1 to 8.

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