FPGA daisy chain communication structure and communication system

Abstract

The application discloses a kind of FPGA daisy chain communication structure and communication system, it is related to communication technical field, it solves the problem that interface and protocol are not standardized, development and debugging are difficult in the prior art FPGA inside star topology structure is connected each sub-function module, its technical scheme main point is: it is proposed that communication structure adopts UART interface as the physical interface between host computer and FPGA, each sub-function module in FPGA is connected in the mode of daisy chain;The communication structure used in the application can communicate directly between host computer and each sub-function module through standardized interface and protocol, each sub-function module can be independently developed, debuged, and is suitable for FPGA design in the field of electronic product testing.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, more particularly, it relates to a FPGA daisy chain communication structure and a communication system. BACKGROUND

[0002] As shown in the prior art FPGA internal function module and host computer communication topology diagram. The prior art FPGA internal function module and host computer generally adopt the topology communication structure of "host computer-center module-multiple sub-function modules". The host computer is interconnected with the only center module in the FPGA through a serial port or a network port and the like physical link. The center module is responsible for the reception of host computer data, the transmission of sub-function module response data, the analysis and packaging of communication data packets, the pairing of sub-function module bus interfaces and the like functions. The remaining sub-function modules are hung on the center module through an internal bus to complete the transmission of host computer instructions and response information. Figure 1 Figure 1 The star topology structure of "center module-multiple sub-function modules" adopted by the prior art FPGA has the following disadvantages:

[0003] 1. Non-standardized interface and protocol: the communication protocol between the host computer and the FPGA is not calibrated, and there are differences between different projects, which leads to the fact that the protocol analysis part in the center module cannot be solidified and needs to be reprogrammed according to the specific protocol of the project; the bus between the center module and each sub-function module is not calibrated, and there are differences in the requirements between different sub-modules, which leads to the fact that the interface part of the center module also needs to be adapted according to the interface situation of the sub-module; due to the differences in functional requirements between different projects, each sub-function module has different interface requirements, which leads to the fact that the program code of the center module and the sub-function module needs to be restructured, the development cycle is long, and a lot of manpower is consumed.

[0004] 2. High coupling between the center module and the sub-function module causes development and debugging difficulties: the center module is a bridge between the host computer and the sub-function module, and the correctness of the center module needs to be ensured when the sub-function module is tested; the center module and the sub-function module are mutually dependent, and the program can only be tested and debugged as a whole, which is difficult and time-consuming; due to the tight coupling relationship between the functional modules, the program code has poor repeatability, and the sustainable optimization ability of the module is lost; if the sub-function modules and the center module are not in the same clock domain, there is cross-clock domain processing, which is very time-consuming and laborious when the number of interfaces is large, and it is also difficult to troubleshoot when problems occur.

[0005] 2. High coupling between the center module and the sub-function module causes development and debugging difficulties: the center module is a bridge between the host computer and the sub-function module, and the correctness of the center module needs to be ensured when the sub-function module is tested; the center module and the sub-function module are mutually dependent, and the program can only be tested and debugged as a whole, which is difficult and time-consuming; due to the tight coupling relationship between the functional modules, the program code has poor repeatability, and the sustainable optimization ability of the module is lost; if the sub-function modules and the center module are not in the same clock domain, there is cross-clock domain processing, which is very time-consuming and laborious when the number of interfaces is large, and it is also difficult to troubleshoot when problems occur.

[0006] ​In the field of electronic product testing, each sub-function module needs to complete a specific interface test or business test function, and the communication between the host computer and each sub-function module does not have high requirements on the rate and real-time performance. If the star topology structure is used inside the FPGA for interconnection between sub-function modules, there will be multiple communication protocols between the host computer and the sub-function modules, and complex bus interfaces between the sub-function modules, which are difficult to reconcile. Designers can only program and implement according to different projects and different needs, and the inheritance is poor, the program code reliability cannot be guaranteed, and the same module needs to be repeatedly designed or tested.

[0007] Therefore, the present application provides a FPGA daisy chain communication structure and communication system to solve the above problems. SUMMARY

[0008] The purpose of the present application is to provide a FPGA daisy chain communication structure and communication system to solve the problem that the star topology structure is used inside the existing FPGA to connect each sub-function module, resulting in non-standardized interfaces and protocols, and difficult development and debugging. The communication structure proposed by the present application uses a UART interface as the physical interface between the host computer and the FPGA, and each sub-function module inside the FPGA is connected in a daisy chain manner. The communication structure adopted by the present application enables the host computer and each sub-function module to communicate directly through standardized interfaces and protocols, and each sub-function module can be developed and debugged independently, which is suitable for FPGA design in the field of electronic product testing.

[0009] The present application first provides a FPGA daisy chain communication structure, comprising: a plurality of FPGA internal function modules, the plurality of FPGA internal function modules are connected in series in a daisy chain topology and communicate externally through a UART interface, wherein the transmitting port of a previous FPGA internal function module is connected with the receiving port of a subsequent FPGA internal function module; each FPGA internal function module comprises: a TMIP interface module and a sub-function module, the TMIP interface module and the sub-function module communicate through a TMI interface, the TMIP interface module is configured to generate and analyze data frames according to a TMIP protocol; the sub-function module is configured to execute the function configured in the register in response to the instruction of the data frame; wherein the TMIP protocol provides that each FPGA internal function module forwards the data frame that does not match the ID itself, and responds to the data frame that matches the ID itself and updates the forwarding content.

[0010] In a possible implementation, the data frame comprises: a frame header, a module ID, a command word, a data length, a register address, a data packet, and a frame tail; wherein the frame header is a data frame start flag, the module ID is an ID of a sub-function module in a daisy chain, the command word is an operation instruction represented by different values, at least including: a NOP operation, a read operation, a write operation, and a command response, the data length is a number of data packets in the read operation and the write operation, the register address is a register start address of the sub-function module in the read operation and the write operation, the data packet is required data in the read operation and the write operation, all data words in the data packet are filled with 0 in the read operation, all data words in the data packet are filled with write-in data by default in the write operation, and the frame tail is a data frame end flag.

[0011] In a possible implementation, the module ID occupies a bit width to determine an upper limit number of sub-function modules mounted in the daisy chain topology.

[0012] In a possible implementation, the TMIP protocol further provides that: when each FPGA internal function module responds to a data frame corresponding to an ID of the module and updates forwarding content, the data packet is updated to response data generated by a response operation instruction of a sub-function module, and the command word representing the read operation and the write operation is updated to a command word representing the command response.

[0013] In a possible implementation, the TMIP interface module is specifically used for: receiving input data and converting the input data into parallel data; receiving a frame header and performing frame header detection until a correct frame header is detected; receiving a module ID and detecting whether the module ID is consistent with a corresponding sub-function module ID; in a case where the module ID is consistent with the corresponding sub-function module ID, sequentially receiving a command word, a data length, a register address, a data packet, and a frame tail, wherein data in the data packet is received one by one according to the data length; sending the command word, the register address, and the data packet to a sub-function module, and receiving response data returned by the sub-function module; taking the frame header, the module ID, the command word, the data length, the register address, and the frame tail as forwarding data, wherein the command word is modified to a command response when the command word represents the read operation or the write operation; updating the data packet according to the response data, and converting the forwarding data and the response data into a serial data frame and outputting the serial data frame.

[0014] In a possible implementation, the TMIP interface module comprises a data transceiving module, a protocol analysis module and a data buffering module; the data transceiving module is configured to convert received input data into parallel data and send the parallel data to the protocol analysis module, and convert data sent by the data buffering module into serial data and output the serial data; the protocol analysis module is configured to analyze data frames in the input data, and in the case that a module ID of the data frames matches a sub-function module ID, send a command word, a register address and a data packet to the sub-function module, and forward other contents of the data frames to the data buffering module; and the data buffering module is configured to receive forwarded contents of the protocol analysis module and response data of the sub-function module in the case that the module ID of the data frames matches the sub-function module ID, and forward the contents and the response data to the data transceiving module.

[0015] In a possible implementation, the protocol analysis module is further configured to generate a handshake signal, and send the handshake signal to the sub-function module together with the command word, the register address and the data packet.

[0016] In a possible implementation, the sub-function module comprises a register mapping module and a function implementation module; the register mapping module is configured to map the register address to a specific register; and the function implementation module is configured to execute parameters of the register configuration, and implement corresponding functions of the sub-function module.

[0017] In a possible implementation, the sub-function module receives, through the TMI interface, a handshake signal i_valid, a command word i_cmd, a register address i_addr and a data packet i_data, and when the handshake signal i_valid is high, the other three signals are valid inputs; the sub-function module outputs, through the TMI interface, a handshake signal o_valid and response data o_data, and when the handshake signal o_valid is high, the response data o_data is a valid output; and the handshake signals i_valid and o_valid only remain high in one clock cycle.

[0018] The application also provides an FPGA daisy chain communication system, which comprises the FPGA daisy chain communication structure as described above.

[0019] Compared with the prior art, the application has the following beneficial effects: the daisy chain communication structure is adopted to replace the original central module star topology structure, the host computer and each FPGA internal function module can directly communicate through a standard interface and a protocol, and each FPGA internal function module can be connected to an external host computer through a UART interface to perform independent debugging and running. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the principles of the present application. In the drawings:

[0021] Figure 1 A topology structure diagram for communication between an existing FPGA internal function module and a host computer;

[0022] Figure 2 A schematic diagram of an FPGA daisy chain communication structure provided by the embodiments of the present application;

[0023] Figure 3 A schematic diagram of an FPGA daisy chain communication structure provided by the embodiments of the present application;

[0024] Figure 4 A schematic diagram of a TMIP data frame provided by the embodiments of the present application;

[0025] Figure 5 A work flow diagram of a TMIP interface module provided by the embodiments of the present application;

[0026] Figure 6 A functional block diagram of a TMIP interface module and a sub-function module provided by the embodiments of the present application;

[0027] Figure 7 A definition code diagram of an external clock test function module provided by the embodiments of the present application. DETAILED DESCRIPTION

[0028] Hereinafter, the term "include" or "may include" used in the various embodiments of the present application indicates the existence of the applied function, operation, or element, and does not limit one or more functions, operations, or elements to be added. Also, as used in the various embodiments of the present application, the terms "include", "have", and their conjugates merely indicate the presence of the specific features, numbers, steps, operations, elements, components, or combinations thereof, and should not be understood as excluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0029] In the various embodiments of the present application, the expression "or" or "at least one of B or / and C" includes any combination of the listed terms or all combinations thereof. For example, the expression "B or C" or "at least one of B or / and C" can include B, can include C, or can include both B and C.

[0030] The terminology used in the various embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the present application. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present application belong. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0031] For the purposes of the present application, the technical solutions and advantages will be more clearly apparent from the following detailed description of embodiments and drawings, which are provided by way of example only, and are not intended to limit the present application.

[0032] Please refer to Figure 2 as shown, Figure 2 The schematic diagram of the FPGA daisy chain communication structure provided by the embodiments of the present application is shown in FIG. 1. The structure includes: a plurality of FPGA internal function modules, which are connected in series in a daisy chain topology and communicate externally through a UART interface, wherein the transmitting port of a previous FPGA internal function module is connected with the receiving port of a subsequent FPGA internal function module; each FPGA internal function module includes: a TMIP interface module and a sub-function module, which communicate through a TMI interface, the TMIP interface module is configured to generate and parse data frames according to the TMIP protocol; the sub-function module is configured to execute the function configured in the register in response to the instruction of the data frame; wherein the TMIP protocol provides that: each FPGA internal function module forwards the data frame that does not match its own ID, and responds to the data frame that matches its own ID and updates the forwarding content.

[0033] Specifically, as Figure 2As shown, each FPGA internal function module contains a TMIP interface module and a sub-function module, and the sub-function module is interconnected with the TMIP interface module through the TMI interface (i.e. TMI_S and TMI_M). The rxd interface of the first TMIP interface module receives the external input signal i_rxd through the UART interface, the rxd interface of the second TMIP interface module is connected to the txd interface of the previous TMIP interface module, and the txd interface of the last TMIP interface module sends the output signal o_txd to the outside through the UART interface, thereby realizing the topology of the daisy chain. The TMIP interface module is mainly responsible for parsing the data packet of the external control terminal. If the data frame instruction obtained by parsing is consistent with the ID of the associated sub-function module, the TMIP interface module communicates with the sub-function module through the TMI interface, so as to prompt the sub-function module to execute the corresponding function and return the response data; if the data frame instruction obtained by parsing is inconsistent with the ID of the associated sub-function module, the TMIP interface module directly forwards the data frame.

[0034] Please refer to Figure 3 As shown, Figure 3 A schematic diagram of the application of the FPGA daisy chain communication structure provided by the embodiment is shown in the figure. In the figure, the host computer is connected with FPGA1 through the UART interface, the sub-function modules of FPGA1 include: DDR3 module, SPI_S module, RST module, FGIO module, UART test module, logic version module, XADC module, DAC module, and ADC module, each sub-function module is sequentially mounted on the communication chain through the TMIP interface module, FPGA1 is also connected with external FPGA2 and DSP through the UART interface, the sub-function modules inside FPGA2 and DSP can also be mounted on the daisy chain communication link through the TMIP interface module to expand the daisy chain, and finally return to FPGA1 to form a closed loop and communicate with the host computer, thereby realizing the daisy chain communication between the multiple sub-function modules inside FPGA and the external control terminal (host computer, other FPGA, ARM, DSP, PS, etc.). It should be noted that the commonly used modules in other FPGA designs are also exemplarily shown in the figure, such as GPIO_SCAN module, and the like, which will not be described here. In the figure, FPGA1_RXD represents the input of FPGA1, FPGA1_TXD represents the output of FPGA1, FPGA2_RXD represents the input of FPGA2, FPGA2_TXD represents the output of FPGA2, DSP_RXD represents the input of DSP, and DSP_TXD represents the output of DSP.

[0035] The improvement of the present application is that a daisy chain topology is designed inside the FPGA instead of the original star topology, and the daisy chain communication between a plurality of sub-function modules and an external control end (a host computer, other FPGA, ARM, DSP, PS, etc.) is realized through a TMIP interface module, the interface and protocol standardization are realized, and the coupling of the central module is avoided. The TMIP interface module can directly communicate externally through a UART interface (universal asynchronous receiver transmitter), the sub-function modules are described in a register manner, the function of each sub-function module can be customized according to the requirement, the development and debugging of each sub-function module are independently completed, and the development and debugging difficulty is reduced.

[0036] Referring to Figure 4 , a schematic diagram of a TMIP data frame provided by an embodiment of the present application is shown. Figure 4 In a possible implementation, the data frame comprises a frame header, a module ID, a command word, a data length, a register address, a data packet, and a frame tail. The frame header is a data frame start flag, the module ID is an ID of a sub-function module on the daisy chain, the command word is an operation instruction represented by different values, at least including: a NOP operation, a read operation, a write operation, and a command response, the data length is a number of data packets in the read and write operations, the register address is a register start address of the sub-function module in the read and write operations, the data packet is required data in the read and write operations, all data words in the data packet are filled with 0 in the read operation, all data words in the data packet are filled with write-in data by default in the write operation, and the frame tail is a data frame end flag.

[0037] Specifically, as Figure 4 shown, the schematic diagram of the data frame under the NOP operation (NOP), the read operation (READ), the write operation (WRITE), and the command response (RESPONSE) is given in the figure. The data frame comprises a frame header (0x5A55), a module ID (DADD[7:0]), a command word (CMD[7:0]), a data length (DLEN[15:0]), a register address (RADD[15:0]), a data packet (n×DATA[15:0]), and a frame tail (0xA5AA). The module ID and the command word each occupy a bit width of 8 bits, the frame header, the data length, the register address, and the frame tail each occupy a bit width of 16 bits, and the data packet occupies a bit width of n×16 bits.

[0038] As shown in Table 1, Table 1 is TMIP data frame structure. Frame header: 2 bytes 16 bits, using fixed 0x5A55 to represent the beginning of the data frame; module ID: 1 byte 8 bits, which can represent the ID of each sub-function module to be tested on the daisy chain; command word: 1 byte 8 bits, 0 represents NOP operation, 1 represents read operation, 2 represents write operation, 3 represents command response, and other operation instructions can be extended; data length: 2 bytes 16 bits, representing the number of data packets in read and write operations, the maximum is 65535 16-bit data; register address: 2 bytes 16 bits, representing the starting address of the device register in read and write operations; data packet: 2-131070 bytes, representing the data required in read and write operations, all data in read operation is filled with 0, and all data in write operation is filled with write data by default, and the sub-function module to be tested can also redefine these data; frame tail: 2 bytes 16 bits, using fixed 0xA5AA to represent the end of the data frame.

[0039] Table 1 TMIP data frame structure

[0040]

[0041] Further, the module ID occupies the bit width to determine the upper limit number of sub-function modules mounted on the daisy chain topology.

[0042] Specifically, in the case that the module ID occupies 8 bits, the range that can be represented is 0x00-0xFF, 0x00 is generally not used, and the daisy chain can be connected with 255 sub-function modules at most.

[0043] It should be noted that the more devices on the daisy chain, the greater the communication delay, and therefore the FPGA daisy chain communication structure provided by the application is more suitable for scenarios with low real-time communication requirements, such as FPGA design in the field of electronic product testing.

[0044] Further, the TMIP protocol further provides that: when each FPGA internal function module responds to the data frame corresponding to its own ID and updates the forwarding content, the data packet is updated to the response data generated by the sub-function module response operation instruction, and the command word representing the read operation and the write operation is updated to the command word representing the command response.

[0045] Specifically, when updating the forwarding content, the data packet in the data frame is updated to the response data generated by the corresponding sub-function module processing, the command word representing the read operation and the write operation is updated to the command word representing the command response, and the remaining part of the data frame is directly forwarded after being registered.

[0046] Please refer to Figure 5 shown, Figure 5A workflow diagram of the TMIP interface module is provided in the embodiments of the present application. In a possible implementation, the TMIP interface module is specifically configured to: receive input data, and convert the input data into parallel data; receive a frame header, and perform frame header detection until a correct frame header is detected; receive a module ID, and detect whether the module ID is consistent with a corresponding sub-function module ID; in the case where the module ID is consistent with the corresponding sub-function module ID, sequentially receive a command word, a data length, a register address, a data packet, and a frame tail, wherein the data in the data packet is received one by one according to the data length; send the command word, the register address, and the data packet to a sub-function module, and receive response data returned by the sub-function module; take the frame header, the module ID, the command word, the data length, the register address, and the frame tail as forwarding data, wherein the command word is modified as a command response when the command word indicates a read operation or a write operation; update the data packet according to the response data, and convert the forwarding data and the response data into a serial data frame for output.

[0047] Specifically, as shown in Figure 5 , the TMIP interface module only responds to a data frame with the same sub-function module ID as itself, and does not process a data frame with a non-self sub-function module ID, but directly forwards the data.

[0048] Please refer to Figure 6 , and Figure 6 A functional block diagram of the TMIP interface module and the sub-function module is provided in the embodiments of the present application. Further, the TMIP interface module comprises a data transceiver module, a protocol analysis module, and a data buffer module; the data transceiver module is configured to convert received input data into parallel data and send the parallel data to the protocol analysis module, and convert data sent by the data buffer module into serial data for output; the protocol analysis module is configured to analyze a data frame in the input data, and in the case where a module ID of the data frame is consistent with a sub-function module ID, send a command word, a register address, and a data packet to a sub-function module, and forward other contents of the data frame to the data buffer module; and the data buffer module is configured to, in the case where the module ID of the data frame is consistent with the sub-function module ID, receive forwarding contents of the protocol analysis module and response data of the sub-function module, and forward the contents and the response data to the data transceiver module.

[0049] Further, the protocol analysis module is further configured to generate a handshake signal, and send the handshake signal to the sub-function module together with the command word, the register address, and the data packet.

[0050] Specifically, as shown in Figure 6As shown in the figure, each FPGA internal function module comprises a TMIP interface module and a sub-function module, and the TMIP interface module and the sub-function module realize data transmission through a TMI interface. The TMI interface is called TMI_M at the TMIP interface module end and called TMI_S at the sub-function module end. The signals transmitted by the TMI interface include a command word i_cmd, a register address i_addr, a data packet i_data, handshake signals i_valid and o_data, and response data o_valid. The TMIP interface module is composed of a transceiver module (serial-to-parallel UART_RX, parallel-to-serial UART_TX), a protocol analysis module tmip_parse, a data buffer module data_fifo, and the like. The TMIP interface module can directly connect a UART interface to receive input data i_rxd and send output data o_txd.

[0051] Please refer to Figure 6 As shown in the figure, Figure 6 The functional block diagram of the TMIP interface module and the sub-function module provided for the embodiments of the present application is shown. In a possible implementation, the sub-function module comprises a register mapping module and a function implementation module; the register mapping module is configured to map a register address to a specific register; and the function implementation module is configured to execute parameters of the register configuration to realize the corresponding function of the sub-function module.

[0052] Specifically, please refer to Figure 7 As shown in the figure, Figure 7 The definition code diagram of the external clock test function module provided for the embodiments of the present application is shown. The definition mode of the sub-function module is illustrated by taking an external clock test function module as an example. As shown in the figure, Figure 7 The define macro definition in the external clock test function module comprises register definitions and a command list that can be supported and are visible to the external clock test function module. In the figure, four register definitions (EXT_CLK1_REGL, EXT_CLK2_REGL, EXT_CLK3_REGL, and EXT_CLK4_REGL) and read and write command definitions (CMD_READ and CMD_WRITE) are provided.

[0053] Further, the sub-function module receives handshake signals i_valid, command words i_cmd, register addresses i_addr, and data packets i_data through the TMI interface, and when the handshake signals i_valid are high, the other three signals are valid inputs; the sub-function module outputs handshake signals o_valid and response data o_data through the TMI interface, and when the handshake signals o_valid are high, the response data o_data are valid outputs; and the handshake signals i_valid and o_valid only maintain high levels in one clock cycle.

[0054] Specifically, the TMI interface of the external clock test function module needs to transmit 4 input signals and 2 output signals, which are consistent in any sub-function module. The 4 input signals are i_valid, i_cmd, i_addr and i_data, and when i_valid is high, the other 3 input signals are valid inputs; the 2 output signals include o_valid and o_data, and when o_valid is high, o_data is a valid output. It should be noted that i_valid and o_valid only maintain one clock cycle in the same data case. In order to guarantee the determinacy of interface delay, it is required to output data as soon as possible after input is valid.

[0055] Exemplarily, the register definition of the external clock test function module is shown in Table 2.

[0056] Table 2: Register definition example of external clock test function module

[0057]

[0058] In order to facilitate those skilled in the art to fully understand the FPGA daisy chain communication structure provided in the present application, the computer accesses the data flow with 4 sub-function modules as an example to illustrate the FPGA daisy chain communication structure of the present application. The output data of the computer enters from the sub-function module 1, and the input data is output from the sub-function module 4, and the specific steps are as follows:

[0059] Step 1: The computer sends a read operation data frame: 0x5A55 0x0301 0x0002 0x0000 0x0000 0x0000 0xA5AA;

[0060] Step 2: After the data enters the sub-function module with ID=0x01, it is not responded and directly transmitted, and the output data of the sub-function module with ID=0x01 is as follows: 0x5A55 0x0301 0x0002 0x0000 0x0000 0x0000 0xA5AA;

[0061] Step 3: After the data enters the sub-function module with ID=0x02, it is not responded and directly transmitted, and the output data of the sub-function module with ID=0x02 is as follows: 0x5A55 0x0301 0x0002 0x0000 0x0000 0x0000 0xA5AA;

[0062] Fourth step: the data enters the sub-function module with ID=0x03, and the response is read out 2 words of data, and the output data is as follows: 0x5A55 0x0303 0x0002 0x0000 0x55AA 0x1234 0xA5AA (the command word and the data packet are changed);

[0063] Fifth step: the data enters the sub-function module with ID=0x04, and no response is made, and the output data of the sub-function module with ID=0x04 is as follows: 0x5A55 0x0303 0x0002 0x0000 0x55AA 0x1234 0xA5AA;

[0064] Sixth step: the computer receives the read operation response frame: 0x5A55 0x0303 0x0002 0x0000 0x55AA 0x1234 0xA5AA.

[0065] It can be understood that the FPGA daisy chain communication structure provided by the application comprises:

[0066] 1. Modularization and interface standardization are realized: the external communication interface of the sub-function module is defined as a combination of a plurality of registers, the meaning of the registers is defined by the function module, the independence and flexibility of the module are ensured, the TMI interface is used as a parallel interface for accessing the registers, becomes a general interface of the sub-function module, the standardization of the interface is realized, and the communication and integration between modules are facilitated; the modular design not only simplifies the system architecture, but also improves the scalability and maintainability of the system;

[0067] 2. Independent debugging and convenient development are realized: after the sub-function module is connected with the TMIP interface module, the RXD / TXD of the TMIP interface module is only connected with the external RXD / TXD, and the product module level function debugging can be independently completed; in the development process, the sub-function module does not need to consider the communication interface and protocol of the upper computer, and only needs to focus on the function development and register definition of itself; the same sub-function module can be easily transplanted in different projects, only needs to be simply port called, and the development efficiency and module reusability are greatly improved;

[0068] 3. The communication link design is optimized: after a plurality of modules are connected in a daisy chain mode, each TMIP interface module can receive the response data of the upper computer or the previous stage module, the communication link and the number of signal lines are simplified; the size of the communication data packet is variable, which can meet the fast transmission of small packet data and support the complete transmission demand of large packet data; the TMIP interface module adopts an asynchronous communication mode, and each sub-function module can work in different clock domains, and the problem of cross-clock domain does not need to be considered; the UART interface is not only suitable for FPGA internal modules, but also can be extended to DSP, ARM, PS and other processor modules, and the scalability and compatibility of the system are further enhanced.

[0069] The embodiment of the present application also provides an FPGA daisy chain communication system, which comprises the FPGA daisy chain communication structure as shown in the figure. Figure 2

[0070] The above detailed description of the specific embodiments has further explained the purposes, technical solutions and beneficial effects of the present application. It should be understood that the above description is only the specific embodiments of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application should be included in the protection scope of the present application.​

Claims

1. An FPGA daisy chain communication structure, characterized by, The application relates to a TMIP (Trans-Module Interface Protocol) communication system based on a daisy chain topology. The TMIP communication system comprises a plurality of FPGA internal function modules which are connected in series in a daisy chain topology and communicate with the outside through a UART interface, wherein a transmitting port of a previous FPGA internal function module is connected with a receiving port of a subsequent FPGA internal function module to form a daisy chain topology. Each FPGA internal function module comprises a TMIP interface module and a sub-function module, and the TMIP interface module and the sub-function module communicate through a TMI interface. The TMIP interface module comprises a data transceiver module, a protocol analysis module and a data buffer module. The data transceiver module is used for converting received input data into parallel data and sending the parallel data to the protocol analysis module and converting data output from the data buffer module into serial data. The protocol analysis module is used for analyzing a data frame in the input data, and when the module ID of the data frame is consistent with the ID of the sub-function module, the protocol analysis module sends a command word, a register address and a data packet to the sub-function module and forwards other contents of the data frame to the data buffer module. The data buffer module is used for receiving forwarding contents of the protocol analysis module and response data of the sub-function module when the module ID of the data frame is consistent with the ID of the sub-function module and forwarding the contents to the data transceiver module. The TMIP protocol stipulates that each FPGA internal function module forwards a data frame with an inconsistent ID and responds to and updates forwarding contents of a data frame with a consistent ID; when each FPGA internal function module responds to and updates forwarding contents of a data frame with a consistent ID, the data packet is updated to response data generated by a response operation instruction of the sub-function module, and a command word indicating a read operation and a write operation is updated to a command word indicating a command response. The data frame comprises a frame header, a module ID, a command word, a data length, a register address, a data packet and a frame tail; the frame header is a data frame start flag, the module ID is an ID of a sub-function module in the daisy chain, the command word is an operation instruction with different values and at least comprises a NOP operation, a read operation, a write operation and a command response, the data length is a number of data packets in the read operation and the write operation, the register address is a starting address of a register of the sub-function module in the read operation and the write operation, the data packet is required data in the read operation and the write operation, all data words in the data packet are filled with 0 in the read operation, all data words in the data packet are filled with default write-in data in the write operation, and the frame tail is a data frame end flag.

2. The FPGA daisy chain communication structure of claim 1, wherein, The module ID occupies a bit width to determine an upper limit number of the sub-function modules mounted in the daisy chain topology.

3. The FPGA daisy chain communication structure of claim 1, wherein, The TMIP interface module is specifically used for receiving input data, converting the input data into parallel data, sending the parallel data to the protocol analysis module, converting data output from the data buffer module into serial data and outputting the serial data. ​ receiving a frame header, performing frame header detection until a correct frame header is detected; receiving a module ID and detecting whether the module ID matches a corresponding sub-function module ID; in the case where the module ID matches the corresponding sub-function module ID, sequentially receiving a command word, a data length, a register address, a data packet, and a frame tail, wherein the data in the data packet is received one by one according to the data length; sending the command word, the register address, and the data packet to the sub-function module and receiving response data returned by the sub-function module; taking the frame header, the module ID, the command word, the data length, the register address, and the frame tail as forwarding data, wherein the command word is modified as a command response when the command word indicates a read operation or a write operation; updating the data packet according to the response data and converting the forwarding data and the response data into a serial data frame for output.

4. The FPGA daisy chain communication structure of claim 1, wherein, The protocol analysis module is further configured to generate a handshake signal and send the handshake signal to the sub-function module together with the command word, the register address, and the data packet.

5. The FPGA daisy chain communication structure of claim 1, wherein, The sub-function module includes: a register mapping module and a function implementation module; the register mapping module is configured to map the register address to a specific register; the function implementation module is configured to execute a parameter of the register configuration and implement a corresponding function of the sub-function module.

6. The FPGA daisy chain communication structure of claim 5, wherein, The sub-function module receives, through the TMI interface, a handshake signal i_valid, a command word i_cmd, a register address i_addr, and a data packet i_data, wherein when the handshake signal i_valid is high, the other three signals are valid inputs; The sub-function module outputs, through the TMI interface, a handshake signal o_valid and response data o_data, wherein when the handshake signal o_valid is high, the response data o_data is a valid output; The handshake signals i_valid and o_valid only remain high in one clock cycle.

7. An FPGA daisy chain communication system, characterized by, The communication system includes the FPGA daisy chain communication structure according to any one of claims 1 to 6.

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