A semiconductor device etching structure prediction method and device, storage medium

Abstract

The application discloses a semiconductor device etching structure prediction method and equipment, and a storage medium. The application obtains three-dimensional etching evolution simulation data of a semiconductor structure to be etched under different etching process conditions; extracts a two-dimensional cross-sectional image from the three-dimensional etching evolution simulation data; generates an etching morphology evolution sequence under high time resolution based on the two-dimensional cross-sectional image; and obtains a target profile image of the semiconductor structure after etching from the etching morphology evolution sequence under high time resolution. A profile prediction model based on deep learning is constructed, and the profile prediction model is trained by using a data set; input of the profile prediction model based on deep learning includes etching process conditions and an initial profile image of the semiconductor structure before etching, and output is a predicted profile image after etching evolving with etching time. The application combines physical modeling and a data-driven method, realizes high-precision prediction and intelligent optimization control of the etching process, and improves process stability and product yield.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor device etching structure prediction method and device and storage medium, which are applied to etching process optimization in a wafer manufacturing process. BACKGROUND

[0002] With the continuous development of semiconductor devices towards miniaturization, high performance and complexity, the precise control of etching process, as a key process step in microelectronic manufacturing, is particularly important. At present, with the device size shrinking to the nanometer level, small changes in the etching process may lead to significant differences in device performance, and even cause device failure. With the continuous evolution of process nodes, from the traditional 0.18 μm, 0.13 μm to 16 nm, 7 nm or even 5 nm, the acceptable morphology deviation in the etching process is becoming smaller and smaller. With the continuous reduction of integrated circuit feature size, the traditional prediction method relying on artificial experience, static parameters or simple data driving has gradually been difficult to meet the high requirements of etching precision and real-time performance for advanced process nodes. At present, the existing technology still has the following shortcomings: on the one hand, the pure physical model method has high computational complexity and is difficult to realize real-time control; on the other hand, the pure data-driven method relies on a large amount of experimental data and lacks the guidance of physical mechanism, and the prediction accuracy is low when facing complex structures or new process conditions.

[0003] Therefore, there is an urgent need for a hybrid modeling strategy that combines physical models and data-driven methods, and realizes prediction control of etching process based on the model, to improve the accuracy, reliability and efficiency of the etching process. SUMMARY

[0004] The purpose of the present application is to solve the problems existing in the prior art, and to provide a semiconductor device etching structure prediction method and device and storage medium, which realize high-precision prediction and real-time control of the etching process by combining physical modeling based on kinetic Monte Carlo and data-driven method based on deep learning.

[0005] To achieve the above-mentioned purpose, in a first aspect, the present application provides a semiconductor etching process prediction method, which comprises:

[0006] Obtaining three-dimensional etching evolution simulation data of a semiconductor structure to be etched under different etching process conditions; the three-dimensional etching evolution simulation data includes three-dimensional profile images of the semiconductor structure at different etching time points in the etching process;

[0007] Two-dimensional cross-sectional images are extracted from three-dimensional etching evolution simulation data; the two-dimensional cross-sectional images include multiple longitudinal cross-sectional images and multiple transverse cross-sectional images; an etching morphology evolution sequence at high temporal resolution is generated based on the above two-dimensional cross-sectional images; and the etching target contour image of the semiconductor structure after etching is obtained from the etching morphology evolution sequence at high temporal resolution.

[0008] The dataset consists of the initial contour image of the semiconductor structure before etching and the corresponding target contour image after etching.

[0009] A deep learning-based contour prediction model is constructed and trained using a dataset. The input of the deep learning-based contour prediction model includes etching process conditions and an initial contour image of the semiconductor structure before etching, and the output is a predicted contour image after etching that evolves with etching time.

[0010] The etching process conditions and the initial contour image of the semiconductor structure before etching are input into a trained deep learning-based contour prediction model to obtain the predicted contour image of the semiconductor structure after etching.

[0011] Preferably, the process of obtaining three-dimensional etching evolution simulation data of the semiconductor structure to be etched under different etching process conditions includes:

[0012] A three-dimensional lattice model is established to discretize the semiconductor structure surface into a three-dimensional lattice structure;

[0013] A surface reaction event library is constructed; the surface reaction event library includes multiple surface reaction events of different etching processes, and each surface reaction event is adsorption, desorption, migration or ion bombardment;

[0014] Define the probability equation and reaction rate for each surface reaction event, where the reaction rate is related to the etching process conditions;

[0015] The etching process of the current semiconductor structure is iteratively simulated using a dynamic Monte Carlo algorithm. The next surface reaction event is randomly selected and executed according to the reaction rate, and the state of the three-dimensional semiconductor structure is updated at the same time.

[0016] Record the three-dimensional contour image of the semiconductor structure at the current stage at the preset etching time point to form a three-dimensional etching evolution simulation dataset;

[0017] By changing the etching process conditions, a new three-dimensional lattice model is established, ultimately generating a three-dimensional etching evolution simulation dataset covering various etching process conditions.

[0018] More preferably, the updating the state of the three-dimensional semiconductor structure comprises: updating the material type of the etched lattice sites, and recalculating the local environment parameters and future surface reaction event probabilities of the neighboring lattice sites affected by the current step surface reaction event.

[0019] Preferably, the implementation process of extracting two-dimensional cross-sectional images from the three-dimensional etching evolution simulation data comprises:

[0020] extracting a plurality of longitudinal cross-sectional images along the lateral coordinates of the key feature region or fixed intervals; extracting a plurality of transverse cross-sectional images along the different depths of the key feature region or preset region; and converting the extracted longitudinal cross-sectional images and transverse cross-sectional images into binary images or grayscale images.

[0021] More preferably, the key feature region comprises the center line of the trench, the edge of the trench, the center axis of the high aspect ratio hole, and the interface of different material layers.

[0022] Preferably, the implementation process of generating the etching morphology evolution sequence at high time resolution based on the above two-dimensional cross-sectional images comprises:

[0023] obtaining a sequence of two-dimensional cross-sectional images at different etching time points, and extracting contour evolution features therefrom; the contour evolution features are a set of time sequence parameters for quantitatively describing the contour morphology;

[0024] based on the contour evolution features, generating a two-dimensional cross-sectional image representing the contour morphology at an intermediate time as an intermediate contour;

[0025] introducing a smoothing process based on physical constraints to ensure that the generated intermediate contour conforms to the physical evolution law;

[0026] extracting multi-scale features of the contour evolution from the intermediate contour;

[0027] based on the multi-scale features of the contour evolution, generating the etching morphology evolution sequence at high time resolution.

[0028] Preferably, the method further comprises:

[0029] performing defect detection on the etched post-prediction contour image of the semiconductor structure to identify the potential defect type and severity in the etched post-prediction semiconductor structure;

[0030] adjusting the etching process conditions of the current semiconductor structure according to the etched post-prediction contour image and the potential defect type and severity, to realize closed-loop optimization.

[0031] More preferably, the implementation process of performing defect detection on the etched post-prediction contour image of the semiconductor structure to identify the potential defect type and severity in the etched post-prediction semiconductor structure comprises:

[0032] establishing a library of defect types;

[0033] extracting key geometric features from the post-etch predicted profile image of the semiconductor structure;

[0034] constructing a defect recognition classifier to determine potential defect types based on the extracted key geometric features;

[0035] obtaining the severity of potential defects based on the post-etch predicted profile image of the semiconductor structure and the potential defect types.

[0036] In a second aspect, the present application provides an electronic device comprising a memory, a processor and an industrial interface, wherein the memory stores a computer program, and the program executes the method when running on the processor.

[0037] In a third aspect, the present application provides a computer readable storage medium storing a computer program, wherein the program realizes the method when executed by a processor.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] 1) The present application combines physical-based KMC simulation with data-driven deep learning methods, fully utilizing the advantages of both, ensuring the physical reasonableness of the model, and improving the computational efficiency and adaptability.

[0040] 2) By constructing a high time-resolution etching morphology evolution sequence, the present application can capture the transient characteristics and subtle changes in the etching process, providing a new perspective for in-depth understanding of the etching mechanism.

[0041] 3) The present application establishes a deep learning-based profile prediction model, which can quickly and accurately predict the etching results under different process parameters, greatly reducing the need for experimental verification and reducing development costs.

[0042] 4) The present application can automatically identify potential etching defects and their positions, providing early warning of possible quality problems.

[0043] 5) The present application realizes intelligent optimization and closed-loop control of the etching process based on the feedback mechanism of reinforcement learning or model predictive control strategy, significantly improving the process stability and product yield. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0045] Figure 1 A flowchart of the overall process for intelligent prediction of etching structures for semiconductor devices.

[0046] Figure 2 A flowchart of the process for physical modeling based on kinetic Monte Carlo (KMC).

[0047] Figure 3 Examples of two-dimensional cross-sectional images of a structure of a semiconductor device, where (a) is a lateral cross-sectional image and (b) is a longitudinal cross-sectional image.

[0048] Figure 4 A simulated structure of a semiconductor device and two-dimensional cross-sectional images, where (a) is a schematic diagram of a three-dimensional simulated structure and (b) is a two-dimensional cross-sectional dimension marker diagram.

[0049] Figure 5 A flowchart of the process for generating a sequence of etching topography evolution.

[0050] Figure 6 A schematic diagram of the timing prediction results for different structures.

[0051] Figure 7 A deep learning prediction model architecture diagram based on a U-Net architecture.

[0052] Figure 8 A deep learning prediction model architecture diagram with hierarchical perception. DETAILED DESCRIPTION

[0053] In order to make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0054] The terms “comprise” and “have” and any variations thereof, as referred to in the embodiments of the present application, are intended to cover the non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include other steps or units not listed, or can optionally include other steps or units inherent to the process, method, product, or device.

[0055] The embodiment provides a semiconductor etching process prediction method. In the embodiment, the semiconductor structure refers to a micro or nanometer level three-dimensional morphology formed on a semiconductor wafer through photolithography, etching and other processes in an integrated circuit manufacturing process. These structures are basic units of devices such as transistors, capacitors and interconnection lines. Specifically, but not limited to, the structures include shallow trench isolation (STI) structures for device isolation, gate structures of transistors, fin structures in FinFET, high aspect ratio storage holes in 3D NAND memory, contact hole and via structures for conductive connection and the like.

[0056] Specifically, referring to the accompanying drawings Figure 1 The semiconductor etching process prediction method comprises the following steps.

[0057] S1. Obtain three-dimensional etching evolution simulation data of a semiconductor structure to be etched under different etching process conditions through a physical modeling module based on a kinetic Monte Carlo (KMC) method; the three-dimensional etching evolution simulation data comprises three-dimensional profile images of the semiconductor structure at different etching time points in the etching process.

[0058] S2. Extract two-dimensional cross-sectional images from the three-dimensional etching evolution simulation data; the two-dimensional cross-sectional images comprise a plurality of longitudinal cross-sectional images and a plurality of transverse cross-sectional images; the extraction positions of the cross-sectional images can be flexibly selected according to the structure characteristics to fully characterize the etching characteristics.

[0059] S3. Generate an etching morphology evolution sequence under high time resolution based on the above-mentioned two-dimensional cross-sectional images; obtain a target profile image of the semiconductor structure after etching from the etching morphology evolution sequence under high time resolution. The above-mentioned operation can generate continuous or more intensive time sequence data from limited discrete time point data, and increase the data richness.

[0060] A data set is formed by an initial profile image of the semiconductor structure before etching and a corresponding target profile image after etching.

[0061] S4. Construct a profile prediction model based on deep learning, and train the profile prediction model by using the data set;

[0062] The input of the profile prediction model based on deep learning comprises etching process conditions and an initial profile image of the semiconductor structure before etching, and the output is a predicted profile image after etching evolved with etching time. The model can adopt various network structures and learning strategies, and is not limited to a specific architecture type.

[0063] S5. Input the etching process conditions and the initial profile image of the semiconductor structure before etching into the trained profile prediction model based on deep learning to obtain a predicted profile image of the semiconductor structure after etching.

[0064] In one embodiment, the method further comprises:

[0065] S6. Defect detection is performed on the post-etch predicted profile image of the semiconductor structure to identify potential defect types and severities in the post-etch predicted semiconductor structure.

[0066] S7. The etching process conditions of the current semiconductor structure can be adjusted based on the post-etch predicted profile image, as well as the potential defect types and severities, through a feedback mechanism based on reinforcement learning, model predictive control, or other optimization algorithms, to achieve closed-loop optimization. The specific implementation of reinforcement learning, model predictive control, or other optimization algorithms can be flexibly selected according to the application scenario.

[0067] It should be noted that the execution order of the above steps can be adjusted according to actual needs, and there can be interaction and iteration between steps. The present application is not limited to a fixed linear process.

[0068] In one embodiment, as shown in Figure 2 Step S1 specifically includes:

[0069] S11. A three-dimensional lattice model is established to discretize the surface of the semiconductor structure to be etched into a three-dimensional lattice structure. The lattice type can be selected according to the material properties, and the parameters can be set according to the actual material properties.

[0070] S12. A surface reaction event library is constructed. The surface reaction event library includes a plurality of surface reaction events for different etching processes. Each surface reaction event is a basic etching process such as adsorption, desorption, migration, or ion bombardment. For different etching systems, a corresponding set of surface reaction events can be defined, and the types and quantities of surface reaction events can be flexibly set according to the complexity of the etching chemistry.

[0071] S13. The probability equation and reaction rate of each surface reaction event are defined, wherein the reaction rate is associated with the etching process conditions (temperature, gas flow, radio frequency power, pressure, etc.). The relationship between the reaction rate and the etching process conditions can be a function relationship based on physical and chemical principles, or an empirical relationship based on experimental data fitting. The present application is not limited to a specific function form.

[0072] S14. The etching process of the current semiconductor structure is iteratively simulated using a kinetic Monte Carlo (KMC) algorithm. The next surface reaction event is randomly selected and executed based on the reaction rate, and the state of the three-dimensional semiconductor structure is updated. The time step of iteration can be adaptively adjusted to balance the calculation efficiency and simulation accuracy.

[0073] In particular, the updating of the state of the three-dimensional semiconductor structure includes updating the material type of the etched lattice site (e.g., changing from semiconductor material to vacuum), and recalculating the local environment parameters and future surface reaction event probabilities of the neighboring lattice sites affected by the current step surface reaction event.

[0074] S15. Record the three-dimensional profile image of the semiconductor structure at the preset etching time point of the current stage, to form a three-dimensional etching evolution simulation dataset. The recording frequency can be flexibly set according to the complexity and variation rate of the etching process, to capture key evolution characteristics.

[0075] S16. Repeat steps S11 to S15 by changing the etching process conditions, to generate a three-dimensional etching evolution simulation dataset covering multiple etching process conditions. For example, the etching process parameters include temperature, gas flow, radio frequency power, and pressure. The parameter selection can use various experimental design methods to effectively cover the parameter space in a limited number of simulations.

[0076] It can be understood that the physical modeling method is not limited to kinetic Monte Carlo (KMC), and various simulation methods such as molecular dynamics, Monte Carlo, continuum method, or a combination thereof can also be selected.

[0077] As shown in FIG. 1, step S1 can further include a parameter optimization loop, which continuously adjusts the physical model parameters by comparing the model predictions with the experimental results, to improve the accuracy of the model. Figure 2

[0078] In one embodiment, step S2 specifically includes:

[0079] Before performing step S2, a unified three-dimensional Cartesian coordinate system is first established for the three-dimensional etching evolution simulation dataset to be analyzed. In a preferred embodiment, the XY plane is the plane on which the surface of the semiconductor wafer is located, and the Z axis is the direction perpendicular to the wafer surface and pointing to the interior of the substrate. The value of the Z axis represents the etching depth. The coordinate origin (0, 0, 0) can be set at the center or a certain corner point of the pattern to be etched. All two-dimensional cross-section extraction is based on this coordinate system.

[0080] S21. Extract a plurality of longitudinal cross-section images along the key feature region or fixed interval transverse coordinates; wherein the key feature region is a specific region selected to comprehensively characterize the non-uniformity of the etching morphology in three-dimensional space, including but not limited to: the center line of the trench, the edge of the trench, the center line of the high aspect ratio hole, and the interface between different material layers, etc.

[0081] In one embodiment, the key feature region includes but is not limited to one or a combination of the following:

[0082] ​For trench or line array structure: select the line at the center of the array, the line at the edge of the array, and the line at the junction of dense and sparse regions as key features.

[0083] For single structure (such as trench, fin): select the geometric center line of the structure, the edge contour line of the structure, and the corner of the structure (such as the corner of L-shaped or T-shaped structure) as key features.

[0084] For high aspect ratio hole structure: select the center region of the hole as the key feature.

[0085] For structures containing different materials: select the interface region of two or more materials as the key feature to analyze the etching selectivity.

[0086] Region based on physical effect prediction: select the region where significant loading effect, micro-loading effect or sidewall angle critical dimension (CD) change is likely to occur, which is predicted by preliminary physical analysis, as the key feature.

[0087] S22. Extract multiple transverse cross-sectional images along different depths of the key feature region or the preset region;

[0088] S23. Convert the extracted longitudinal cross-sectional images and transverse cross-sectional images into binary images or grayscale images to facilitate subsequent topographic feature extraction.

[0089] As an example, for the same extraction region, the transverse cross-sectional image and the longitudinal cross-sectional image of the semiconductor device structure are shown in Figure 3 (a) of the drawings, Figure 3 (b) of the drawings.

[0090] The transverse cross-sectional image observes the etching structure from the direction perpendicular to the wafer surface, showing the contour and distribution of the planar pattern. By comparing the top view before and after etching, the accuracy and consistency of pattern transfer can be evaluated, and the change of critical dimension can be measured.

[0091] The longitudinal cross-sectional image cuts the structure along a certain direction, showing the topographic profile perpendicular to the cutting plane. This figure is used to evaluate key parameters such as etching depth, sidewall angle, bottom shape, etc. The cutting position can be flexibly selected according to the structure characteristics to fully characterize the etching characteristics.

[0092] The above transverse cross-sectional image and longitudinal cross-sectional image reveal various etching characteristics, including but not limited to: etching depth, sidewall angle, sidewall roughness, bottom shape, etching under mask, interface features, etc. These features constitute a multi-dimensional index system for evaluating etching quality.

[0093] As Figure 4(b) is a cross-section taken along the lateral direction of (a), resulting in a 2D XY cross-section. Similarly, all cross-sections in FIG. 6 are longitudinal xz cross-sections and their predicted results. Figure 4 (b) is a cross-section taken along the lateral direction of (a), resulting in a 2D XY cross-section. Similarly, all cross-sections in FIG. 6 are longitudinal xz cross-sections and their predicted results.

[0094] The 3D schematic part is based on simulated lattice data to construct a 3D model of the etched structure. The data representation can be in the form of voxels, surface meshes, or other appropriate data structures to effectively characterize the 3D features. The 3D topography formed by etching, such as trenches, holes, or composite structures, can be displayed, and the positions and directions of cross-section extraction can be marked.

[0095] The cross-section part shows the 2D cross-section images extracted from the 3D model, including but not limited to:

[0096] Longitudinal cross-section: extracted along a specific lateral coordinate, showing the structural changes in the depth direction;

[0097] Lateral cross-section: extracted along a specific depth, showing the structural distribution in the plane direction.

[0098] As shown in Figure 4 , the extracted cross-section images can be subjected to appropriate image processing to highlight the structural contours, facilitating feature extraction and quantitative analysis. The processing method can be flexibly selected according to specific application requirements, and the present application is not limited to a specific image processing technique.

[0099] As shown in Figure 6 , the method of the present application can be applied to the prediction of etching topography of different structure types, including but not limited to simple trenches, trench arrays, hole arrays, line structures, and composite structures, etc.

[0100] For each structure, the profiles of the initial state, intermediate state, and final state can be predicted, forming a complete etching evolution sequence. The prediction results can show key feature changes during etching, such as depth increase, sidewall angle evolution, bottom shape change, etc.

[0101] As shown in Figure 6 , for different types of structures, the prediction results can reveal different etching characteristics:

[0102] Trench structures can exhibit changes in depth over time and evolution of sidewall angles;

[0103] Array structures can exhibit the effects of density, reflecting the interaction between adjacent units;

[0104] High aspect ratio structures can exhibit changes in etching characteristics with increasing depth;

[0105] Composite structures can exhibit changes in etching behavior at different material interfaces.

[0106] One embodiment is shown in FIG. 1, which includes the following steps: Figure 5 As shown in FIG. 3, step S3 specifically includes:

[0107] S31. Obtain a sequence of two-dimensional cross-sectional images at different etching time points, and extract contour evolution features therefrom; the contour evolution features are a set of time series parameters used to quantitatively describe the contour morphology, including but not limited to: etching depth, sidewall angle, critical dimension (CD), curvature of the trench bottom, sidewall roughness, and lateral etching amount under the mask.

[0108] S32. Based on the contour evolution features, generate a two-dimensional cross-sectional image representing the contour morphology at an intermediate time point using curve fitting or time series interpolation algorithms, as an intermediate contour. The algorithm selection can be determined flexibly according to the data characteristics to balance the calculation efficiency and interpolation accuracy.

[0109] S33. Introduce a smoothing process based on physical constraints to ensure that the generated intermediate contour conforms to the physical evolution law; the physical constraints can include but are not limited to material removal monotonicity, contour continuity, etching rate variation law, etc., to ensure the physical reasonableness of the generated data.

[0110] S34. Extract multi-scale features of the contour evolution using methods such as wavelet transform or Fourier analysis; the multi-scale features of the contour evolution include: low-frequency components representing the overall change in the contour morphology, and high-frequency components representing the local details (such as sidewall roughness, micro-trench) of the contour.

[0111] These signal analysis methods such as wavelet transform or Fourier analysis can decompose the morphology changes into components of different frequencies or scales, facilitating the understanding and modeling of the evolution characteristics at different scales.

[0112] S35. Based on the multi-scale features of the contour evolution, generate an etching morphology evolution sequence at high time resolution, the specific implementation process is:

[0113] Based on the multi-scale features of the contour evolution, construct a parameterized evolution model with time as input and contour geometric parameters as output, and by evaluating the parameterized evolution model at dense time points and reconstructing two-dimensional cross-sectional images, an etching morphology evolution sequence at high time resolution is generated; the two-dimensional cross-sectional images are the etched target contour images of the semiconductor structure.

[0114] The parameterized evolution model can describe the evolution trajectory of the contour points over time, enabling morphology prediction at any time point.

[0115] Through the above steps, the time series data generation module of the present application can expand the original data with low time resolution into a high-resolution sequence, increase the data richness, and at the same time ensure the physical rationality of the generated data. It should be noted that the above steps can be flexibly adjusted according to specific application scenarios, and the present application is not limited to a specific data generation method or processing order.

[0116] In one embodiment, the specific method of constructing the contour prediction model based on deep learning in step S4 includes:

[0117] S41. Design a deep neural network structure with multiple input channels, including an etching process condition channel and an initial contour image channel before etching;

[0118] The deep neural network structure selects a suitable network structure as a basic framework, which can be a U-Net, a convolutional LSTM, a Transformer, or a combination thereof;

[0119] S42. Define a multi-task learning objective to simultaneously optimize the accuracy of topography prediction and the precision of key feature parameter prediction;

[0120] S43. Use a physical constraint loss function to ensure that the prediction results conform to the physical laws and topological consistency;

[0121] S44. Use the data generated in steps S1 to S3 for model training and verification;

[0122] S45. Apply a transfer learning strategy to fine-tune the model using experimental data to improve the prediction accuracy under actual etching process conditions.

[0123] The etching process condition channel can receive one or more combinations of temperature, gas flow, radio frequency power, pressure, and other etching process parameters; the initial contour image channel before etching can receive the structure topography image before etching. Through this multi-channel design, the model can simultaneously learn the relationship between process parameters and etching results and the relationship between initial topography and etching results.

[0124] As an example, the deep neural network structure can use an encoder-decoder structure combined with a time series modeling module. In the encoder part, convolutional layers, attention mechanisms, or other feature extraction methods can be used to extract feature representations of the input data. Features from different sources can be integrated through a feature fusion module to form a unified feature representation.

[0125] The time series modeling module can use recurrent neural networks, attention mechanisms, or other sequence modeling methods to learn the time evolution law of etching topography. This module can capture the dynamic characteristics of the etching process and predict the etching state at different time points.

[0126] The decoder part can convert the timing features back to the spatial domain, reconstructing the etching profile images at different time points. The decoder can use transposed convolution, upsampling or other image generation methods to gradually restore the spatial resolution of the features. A skip connection mechanism can be introduced to pass the features from the encoder directly to the corresponding layer of the decoder, preserving the detailed information.

[0127] The model training can use a multi-objective learning method, and the optimized loss function can include:

[0128] Profile prediction loss: measures the difference between the predicted profile and the actual profile;

[0129] Feature parameter loss: prediction accuracy for key parameters;

[0130] Physical constraint loss: regularization term designed based on the physical laws of the etching process.

[0131] The total loss function can be a weighted combination of the above losses, and the weights can be flexibly adjusted according to the specific application scenario. The training data can come from physical simulation and time series data generation steps, and appropriate data division methods and learning strategies can be used.

[0132] It should be noted that the above network structure and training method are only examples, and the deep learning prediction model of the present application is not limited to a specific network architecture, loss function or learning algorithm, and can be flexibly selected and combined according to the specific application requirements.

[0133] In one embodiment, step S6 specifically includes:

[0134] S61. Establish a defect type library, including Bridge, Necking, Under-etching, Over-etching, Roughness, CD Variation, etc.

[0135] S62. Extract key geometric features from the predicted profile image of the semiconductor structure after etching; the key geometric features include but are not limited to: the distance between adjacent key regions, the final depth of the trench or hole, the deviation value of the side wall angle, the quantitative indicators of line width roughness (LWR), etc., as well as the radius of curvature at the bottom or corner, etching depth, side wall angle, critical dimension (CD), trench bottom curvature, side wall roughness, and lateral etching amount under the mask.

[0136] S63. Construct a defect recognition classifier to determine the potential defect type based on the extracted key geometric features; specifically including:

[0137] Determine the potential defect area based on the key geometric features in combination with the preset mapping rules;

[0138] For the potential defect area, a support vector machine classifier is used to determine the potential defect type.

[0139] S64. According to the post-etch predicted profile image of the semiconductor structure and the potential defect type, the severity of the potential defect is obtained; specifically:

[0140] S641. A defect spatial distribution map is established according to the post-etch predicted profile image of the semiconductor structure and the potential defect type, and a high-risk area in the predicted profile is located; specifically, by assigning a defect risk index to each pixel point or each local area on the predicted profile image according to the closeness of its key geometric features to the preset defect standard, a defect risk heat map (Heatmap) that is registered with the predicted profile image is generated. In the heat map, the area with a higher risk index is identified as a high-risk area.

[0141] S642. The defect risk index is calculated to quantitatively evaluate the defect risk level under the current process parameters.

[0142] In one embodiment, the step S7 specifically includes:

[0143] S71. A process parameter-structure quality mapping model is constructed to establish the relationship between process parameter adjustment and structure improvement;

[0144] S71. A parameter optimization framework based on deep learning is designed, and the negative value of the defect risk index is taken as a reward function;

[0145] S73. Alternatively, a model predictive control (MPC) framework is established to minimize the weighted sum of defect risk and parameter adjustment cost as the target;

[0146] S74. The process parameter adjustment constraint condition is set to ensure that the parameter change is within a feasible range;

[0147] S75. The parameter optimization calculation is performed, and the optimal process parameter adjustment suggestion is output;

[0148] S76. The optimized parameters are applied to the actual etching process or the next round of simulation to form a closed-loop control.

[0149] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the present application can have many different forms, and the following examples should not be construed as limiting the present application.

[0150] Example 1, Trench Etching Process Optimization: This embodiment applies the semiconductor etching process prediction method of the present application to optimize the fin trench etching process of the FinFET device of the advanced technology node.

[0151] (1) Initial conditions:

[0152] Initial structure: pre-deposited hard mask on silicon substrate, patterned to form a line grating array. As an example, the initial structure is a pre-deposited SiO2 hard mask (thickness 50 nm) on a silicon substrate, patterned to form a line grating array with line width 40 nm and pitch 40 nm.

[0153] Etching target: form a fin-trench with specific depth, width, and sidewall angle, requiring control of sidewall roughness and CD variation. As an example, the etching target is to form a fin-trench with depth 120 nm, width 30 nm (± 2 nm), and sidewall angle 89° (± 1°), while minimizing sidewall roughness and CD variation.

[0154] Etching process conditions: fluorine-containing mixed gas, ICP etching, with initial parameter settings. As an example, the etching process conditions are CF4 / O2 / Ar mixed gas, ICP etching, with initial parameters of radio frequency power 500 W, bias power 100 W, pressure 10 mTorr, gas flow ratio CF4:O2:Ar = 60:10:30, and substrate temperature 60°C.

[0155] (2) Implementation steps:

[0156] Step 1: Establish a physical model of fin-trench etching based on the kinetic Monte Carlo method. Consider the surface reaction mechanism of Si in fluorine-containing plasma, simulate under multiple sets of different process parameters, and generate an etching morphology database covering the parameter space. Each set of parameter simulation records three-dimensional structure data every 5 seconds within 0-200 seconds.

[0157] Step 2: Extract two-dimensional cross-sections of key positions from three-dimensional simulation data, including longitudinal cross-sections along the fin length direction and transverse cross-sections at different depths. Extract 20 uniformly distributed time point data to form an initial time sequence, then apply a time sequence data generation module to increase the time resolution to one data point every 0.5 seconds.

[0158] Step 3: Use a deep learning prediction model based on the U-Net architecture to predict the post-etching prediction profile image.

[0159] The input channels of the deep learning prediction model based on the U-Net architecture include process parameters (radio frequency power, bias power, pressure, and three gas flow rates) and initial profile images (size 128x128 pixels, resolution 1 nm / pixel). The output is a sequence of etching profiles at 40 time points (0-200 seconds, interval 5 seconds). Use 80% of the simulation data for training and 20% for validation. Additionally, use 10 sets of experimental data for transfer learning to fine-tune the model to adapt to actual etching process conditions.

[0160] In one embodiment, the deep learning prediction model based on U-Net architecture takes U-Net network as the basic framework, see FIG. 1 Figure 7 which includes an encoder, a bottleneck layer, a decoder, a process parameter processing module, and an output layer.

[0161] The process parameter processing module, Figure 5 the input end of which is configured to receive a parameter vector containing at least one etching process condition parameter, and the process parameter processing module is configured to convert the parameter vector into a set of parameter features.

[0162] In an optional implementation, the process parameter processing module contains at least one fully connected layer.

[0163] The input end of the encoder is configured to receive an initial contour image before etching, which includes multiple encoding layers for extracting a set of multi-scale spatial features from the initial contour image; and each encoding layer is followed by a down-sampling unit.

[0164] In an optional implementation, each encoding layer includes at least one convolutional layer and one pooling layer.

[0165] The bottleneck layer adopts a time evolution module, the input end of which is connected with the output end of the last encoding layer and the output end of the process parameter processing module, and the time evolution module is configured to:

[0166] (a) fuse the spatial features output by the last encoding layer and the parameter features output by the process parameter processing module to form an initial state feature map;

[0167] (b) based on the initial state feature map, generate a hidden state sequence containing multiple hidden states through a recurrent neural network unit, wherein each hidden state corresponds to a future prediction time point.

[0168] Further, the recurrent neural network unit is a convolutional long short-term memory (ConvLSTM) unit or a gated recurrent unit (GRU).

[0169] The input end of the decoder is connected with the output end of the time evolution module, which includes the same number of decoding layers as the encoding layers, is configured to receive the hidden state sequence, and decode each hidden state in the sequence to generate a corresponding predicted contour image, thereby forming a predicted contour image sequence; each decoding layer is followed by an up-sampling unit, and the encoding layer and the decoding layer in the same layer adopt skip connections.

[0170] The multi-scale spatial features are received and fused in the decoding process through the skip connection to improve the detail accuracy of the predicted contour image.

[0171] The output layer fuses the feature map transmitted by the last decoding layer upsampling unit with the initial contour feature map to obtain the next frame contour image.

[0172] Step 4: Defect detection is performed on the post-etch predicted contour image of the semiconductor structure to identify potential defect types and severity in the post-etch predicted semiconductor structure. Potential defect types include insufficient / over-etching, sidewall angle deviation, abnormal trench bottom shape, etc. For the detected defects, a model predictive control (MPC) strategy is used to optimize the process parameters.

[0173] Step 5: The optimized process parameters are applied to the actual etching equipment, and the test sample is etched and the contour is measured by SEM / TEM. The measurement results are fed back to the system to update the prediction model, forming a closed-loop optimization. Through 3-5 rounds of iteration, the optimal process window is converged.

[0174] The process parameters obtained by the above method are optimized to improve the etching quality and stability. The deep learning prediction model based on the U-Net architecture in this embodiment shows high precision, with a key dimension prediction error within an acceptable range. The process window is widened, enhancing process robustness, and key indicators such as uniformity and roughness are improved, solving specific defect problems, improving subsequent process success rate, significantly shortening development cycle, and reducing silicon wafer consumption.

[0175] Embodiment 2, 3D NAND memory hole etching control: This embodiment applies the semiconductor etching process prediction method of the present application to optimize the high aspect ratio hole etching process in the manufacturing of 3D NAND flash memory.

[0176] Initial conditions:

[0177] Initial structure: 48 layers of SiO2 / Si3N4 alternating stack (each layer thickness of 30 nm), with a 200 nm thick SiO2 hard mask on top, patterned to form a circular opening with a diameter of 90 nm.

[0178] Etching target: Form a through-hole with a total depth of 3000 nm, a diameter of 80 nm (±5 nm), and a sidewall angle of 88°-90°, while minimizing interlayer step effect and sidewall roughness.

[0179] Etching process conditions: C4F8 / O2 / CO / Ar composite gas, dual-frequency ICP etching, initial parameters: high-frequency power 1200 W, low-frequency power 400 W, pressure 25 mTorr, gas flow ratio C4F8:O2:CO:Ar=20:10:40:100, substrate temperature 20℃.

[0180] Implementation steps:

[0181] Step 1: Adopt a hierarchical KMC physical modeling strategy to establish micro-reaction models for SiO2 etching and Si3N4 etching, respectively, focusing on the selectivity changes and transition behaviors at the interface. Consider factors such as reactant diffusion limitations, ion bombardment angle distribution changes with depth, and charged effects. Simulate the etching process for 0-600 seconds for each set of parameters, recording three-dimensional structure data every 15 seconds.

[0182] Step 2: Extract key information from three-dimensional simulation data, including: longitudinal cross-section along the hole depth direction, transverse cross-section at different depths (especially focusing on SiO2 / Si3N4 interface position), hole diameter change curve with depth, etc. Apply time series data generation module to generate high time resolution (one data point every 3 seconds) morphology evolution sequence, and introduce diffusion limitation type rate decay model and other physical constraints for deep area morphology prediction.

[0183] Step 3: Use a hierarchical deep learning prediction model to predict the post-etching prediction profile image.

[0184] The hierarchical deep learning prediction model uses an attention-enhanced U-Net architecture. Input channels include: process parameters (dual-frequency power, pressure, four gas flow rates, temperature), initial profile image, and material layer marker map (identifying different material layer positions). The output is a sequence of 40 etching profiles covering the complete 0-600 second process. The model uses a hierarchical weighted loss function to give higher weights to deep regions and material interfaces.

[0185] In another embodiment, the hierarchical deep learning prediction model is embodied as a device or system for semiconductor etching profile prediction, as shown in Figure 8 The U-Net network is used as the basic framework, which includes a multi-modal input processing unit, an encoder, a bottleneck layer, a decoder, a process parameter processing module, and an output layer.

[0186] The multi-modal input processing unit is configured to receive an initial profile image and a material layer marker map registered therewith, and combine them into a multi-channel input feature map.

[0187] Here, the material layer mask is a digital map that is spatially registered with the initial contour image and encodes key prior knowledge about the chemical composition and physical properties of the etch target. The digital map assigns a unique numerical label to each different material in the initial structure at the pixel level. In a typical shallow trench isolation (STI) etch process, the map explicitly identifies regions such as photoresist, oxide, nitride hardmask layers, and the silicon (Si) substrate to be etched.

[0188] By merging the geometric contour image and the material mask into a multi-channel input (e.g., one channel for geometry and another channel for material labels), the neural network is ensured to perceive both the "topography" and "composition" of the structure at every step of feature extraction, thereby learning a more accurate and physically consistent etch dynamics.

[0189] The process parameter processing module has an input configured to receive a parameter vector comprising at least one etch process condition parameter, and is configured to convert the parameter vector into a set of parameter features.

[0190] In an optional embodiment, the process parameter processing module comprises at least one fully connected layer.

[0191] The encoder has an input configured to receive an initial contour image before etching, and comprises multiple encoding layers for extracting a set of multi-scale spatial features from the initial contour image; each encoding layer is followed by a down-sampling unit.

[0192] In an optional embodiment, each encoding layer comprises at least one convolutional layer and one pooling layer.

[0193] The bottleneck layer employs a temporal evolution module having inputs connected to the output of the last encoding layer and the output of the process parameter processing module, and is configured to:

[0194] (a) fuse the spatial features output by the last encoding layer and the parameter features output by the process parameter processing module to form an initial state feature map;

[0195] (b) based on the initial state feature map, generate a sequence of hidden states comprising multiple hidden states through a recurrent neural network unit, where each hidden state corresponds to a future prediction time point.

[0196] Further, the recurrent neural network unit is a Convolutional Long Short-Term Memory (ConvLSTM) unit or a Gated Recurrent Unit (GRU).

[0197] The input end of the decoder is connected with the output end of the time evolution module, and the decoder includes the same number of decoding layers as the encoding layers, is configured to receive the hidden state sequence, and decode each hidden state in the sequence to generate a corresponding predicted contour image, thereby forming a predicted contour image sequence; each decoding layer is connected in series with an up-sampling unit, and a skip connection is used between the encoding layer and the decoding layer at the same layer. An attention gate unit is connected in series on each skip connection. The attention gate unit is configured to: according to high-level semantic features transmitted from the current decoding layer through the up-sampling unit, adaptively adjust and filter low-level spatial features from the encoding layer, so that the current decoding layer can focus on the key area (such as the material interface or the deep area) most relevant to the current task when reconstructing the predicted contour image.

[0198] The output layer receives the feature map transmitted by the up-sampling unit of the last decoding layer and the initial contour feature map, and obtains the next frame of contour image.

[0199] Further, the loss function used to train the device / system is a hierarchical weighted loss function, and the loss function is configured to: when calculating the error between the predicted contour image and the real contour image, higher weights are applied to the error of the preset key area (including but not limited to the deep area and the material interface area), so as to guide the model to preferentially optimize the prediction accuracy of the key area.

[0200] Step 4: Develop a detection system for defects unique to 3D NAND, focusing on aperture variation, sidewall tilt, interface step, and abnormal hole bottom shape. Based on the detection results, use reinforcement learning strategy to optimize process parameters, and realize adaptive adjustment in the etching process.

[0201] Step 5: According to the model prediction and reinforcement learning optimization results, design a segmented etching strategy, divide the entire deep hole etching process into 3-5 segments, and use optimized parameter combinations in each segment. For example, high selectivity formula is used in the shallow area, etching rate and uniformity are balanced in the middle area, and reactant transport and product discharge capacity are enhanced in the deep area. Through experimental verification and model feedback, the parameters of each segment and the switching points are optimized.

[0202] The etching process optimized by the method realizes high-quality high-aspect-ratio structures, effectively controls the critical dimension variation, keeps the key structure parameters in the target range, and meets the requirements of subsequent processes. Apparently, the application of the method of the application improves the etching efficiency, shortens the process time, improves the characteristics at the interface, improves the structure quality, significantly reduces the defect rate, especially the deep key defects, improves the yield of finished products, reduces the manufacturing cost, enhances the process stability, and improves the adaptability to material and equipment variations.

[0203] The above examples show that the intelligent prediction method for etching structures of semiconductor devices provided by the application can be effectively applied to optimization of different types of semiconductor etching processes, improve process stability and product yield. Those skilled in the art should understand that the above embodiments are only examples, and the protection scope of the application should be subject to the claims.

[0204] The electronic device provided by the embodiment of the application specifically includes a memory and a processor, the memory stores executable code, and the processor executes the executable code to implement the method of any one of the embodiments.

[0205] The memory can include a high-speed random access memory (RAM) and can also include a non-volatile memory such as at least one disk memory. The communication connection between the system network element and at least one other network element can be achieved through at least one communication interface (which can be wired or wireless), and the Internet, a wide area network, a local area network, a metropolitan area network, etc. can be used.

[0206] The bus can be an ISA bus, a PCI bus, an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0207] The memory is used to store programs, and the processor executes the programs after receiving execution instructions. The method executed by the device defined by the flow process disclosed in any one of the embodiments of the application can be applied to the processor or implemented by the processor.

[0208] The processor can be an integrated circuit chip with a signal processing capability. In implementation, the steps of the above method can be completed by an integrated logic circuit or an instruction in the form of software in the processor. The processor mentioned above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc. It can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed by the processor. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, or other mature storage media in the art. The storage medium is located in the storage memory, and the processor reads the information in the storage memory and combines the hardware to complete the steps of the above method.

[0209] The computer program product of the readable storage medium provided by the embodiments of the present application includes a computer readable storage medium storing program codes, and the program codes include instructions for executing the method described in the foregoing method embodiments. The specific implementation can be referred to the foregoing method embodiments, and will not be described here.

[0210] When the function is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0211] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present application, and are used to illustrate the technical solutions of the present application, but are not intended to limit the present application. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some of the technical features, within the technical scope disclosed by the present application. These modifications, changes or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for predicting semiconductor etching processes, characterized in that, The method includes: Obtain three-dimensional etching evolution simulation data of the semiconductor structure to be etched under different etching process conditions; the three-dimensional etching evolution simulation data includes three-dimensional contour images of the semiconductor structure at different etching time points during the etching process; Two-dimensional cross-sectional images are extracted from three-dimensional etching evolution simulation data; the two-dimensional cross-sectional images include multiple longitudinal cross-sectional images and multiple transverse cross-sectional images; an etching morphology evolution sequence at high temporal resolution is generated based on the above two-dimensional cross-sectional images; and the etching target contour image of the semiconductor structure after etching is obtained from the etching morphology evolution sequence at high temporal resolution. The dataset consists of the initial contour image of the semiconductor structure before etching and the corresponding target contour image after etching. A deep learning-based contour prediction model is constructed and trained using a dataset. The input of the deep learning-based contour prediction model includes etching process conditions and an initial contour image of the semiconductor structure before etching, and the output is a predicted contour image after etching that evolves with etching time. The etching process conditions and the initial contour image of the semiconductor structure before etching are input into a trained deep learning-based contour prediction model to obtain the predicted contour image of the semiconductor structure after etching.

2. The method according to claim 1, characterized in that, The process of obtaining three-dimensional etching evolution simulation data of the semiconductor structure to be etched under different etching process conditions includes: A three-dimensional lattice model is established to discretize the semiconductor structure surface into a three-dimensional lattice structure; A surface reaction event library is constructed; the surface reaction event library includes multiple surface reaction events of different etching processes, and each surface reaction event is adsorption, desorption, migration or ion bombardment; Define the probability equation and reaction rate for each surface reaction event, where the reaction rate is related to the etching process conditions; The etching process of the current semiconductor structure is simulated iteratively using a dynamic Monte Carlo algorithm. The next surface reaction event is randomly selected and executed according to the reaction rate, while the state of the semiconductor structure of the three-dimensional lattice structure is updated. Record the three-dimensional contour image of the semiconductor structure at the current stage at the preset etching time point to form a three-dimensional etching evolution simulation dataset; By changing the etching process conditions, a new three-dimensional lattice model is established, ultimately generating a three-dimensional etching evolution simulation dataset covering various etching process conditions.

3. The method according to claim 2, characterized in that, The updated state of the three-dimensional semiconductor structure includes: updating the material type of the etched lattice sites, and recalculating the local environmental parameters of neighboring lattice sites affected by the current step surface reaction event and the probability of future surface reaction events.

4. The method according to claim 1, characterized in that, The process of extracting two-dimensional cross-sectional images from three-dimensional etching evolution simulation data includes: Extract multiple longitudinal cross-sectional images along the key feature region or at fixed intervals of horizontal coordinates; extract multiple transverse cross-sectional images at different depths along the key feature region or preset region; convert the extracted longitudinal and transverse cross-sectional images into binary or grayscale images.

5. The method according to claim 4, characterized in that, The key feature areas include the centerline of the trench, the edge of the trench, the central axis of the high aspect ratio hole, and the interface between different material layers.

6. The method according to claim 1, characterized in that, The process of generating an etching morphology evolution sequence at high temporal resolution based on the above-mentioned two-dimensional cross-sectional image includes: Two-dimensional cross-sectional image sequences at different etching time points are obtained, and contour evolution features are extracted from them; the contour evolution features are a set of time series parameters used to quantitatively describe the contour morphology; Based on the contour evolution features, a two-dimensional cross-sectional image representing the contour shape at an intermediate moment is generated as the intermediate contour. A smoothing process based on physical constraints is introduced to ensure that the generated intermediate contours conform to the laws of physical evolution; Extract multi-scale features of contour evolution from intermediate contours; Based on the multi-scale features of contour evolution, an etch morphology evolution sequence with high temporal resolution is generated.

7. The method according to claim 1, characterized in that, The method further includes: Defect detection is performed on the post-etching predicted contour image of a semiconductor structure to identify the type and severity of potential defects in the post-etching predicted semiconductor structure. Based on the predicted contour image after etching and the type and severity of potential defects, the etching process conditions of the current semiconductor structure are adjusted to achieve closed-loop optimization.

8. The method according to claim 7, characterized in that, The process of performing defect detection on the post-etching predicted contour image of the semiconductor structure to identify the potential defect types and severity in the post-etching predicted semiconductor structure includes: Establish a defect type library; Extract key geometric features from the predicted contour image of the semiconductor structure after etching; Construct a defect identification classifier to determine the type of potential defects based on the extracted key geometric features; The severity of potential defects is obtained by predicting the contour image of the semiconductor structure after etching and the type of potential defects.

9. An electronic device comprising a memory, a processor, and an industrial interface, wherein the memory stores a computer program that, when executed on the processor, performs the method of any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, the program, when executed by a processor, implementing the method of any one of claims 1 to 8.

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