Circuit design method, circuit design assistance device, storage medium, and program product

Abstract

Provided are a circuit design method, a circuit design auxiliary device, a computer readable storage medium, and a computer program product. The circuit design method comprises: in response to an operation of a user, acquiring a position at which a circuit element in a target circuit is configured; determining a voltage region in which the circuit element is located according to the position at which the circuit element is configured; adjusting a parameter constraint condition of the circuit element according to the voltage region, the parameter constraint condition being used to constrain a range of a parameter value in the circuit element; and adjusting the parameter value of the circuit element according to the voltage region, the adjusted parameter value of the circuit element satisfying the parameter constraint condition. The present application can improve the efficiency of circuit design.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a circuit design method, a circuit design auxiliary device, a computer readable storage medium and a computer program product. BACKGROUND

[0002] In a semiconductor circuit, a plurality of voltage levels of operating voltages are generally used. Therefore, in the design of a semiconductor circuit, a chip region in a semiconductor substrate is divided into a plurality of regions according to operating voltages. Each region divided is referred to as a high-voltage region, a low-voltage region, and the like. Only circuit elements operating at a corresponding operating voltage are configured within each region. Therefore, even the same kind of circuit elements need to be parameterized according to the voltage region in which they are configured. This is the same in the case where a method called Pcell (Parameterized cell) is used to achieve design efficiency.

[0003] In the conventional art, the parameter configuration of circuit elements in each voltage region is generally optimized manually. This method is time-consuming and inefficient. SUMMARY

[0004] Therefore, it is necessary to provide a circuit design method, a circuit design auxiliary device, a computer readable storage medium and a computer program product capable of improving the efficiency of circuit design to solve the above technical problems.

[0005] A circuit design method for assisting the configuration of circuit elements in a semiconductor circuit, the circuit design method comprising:

[0006] In response to an operation of a user, a position in which a circuit element in a target circuit is configured is acquired;

[0007] According to the position in which the circuit element is configured, a voltage region in which the circuit element is located is determined;

[0008] According to the voltage region, a parameter constraint condition of the circuit element is adjusted, the parameter constraint condition being used to constrain a range of a parameter value in the circuit element;

[0009] According to the voltage region, a parameter value of the circuit element is adjusted, the adjusted parameter value of the circuit element satisfying the parameter constraint condition.

[0010] In one of the embodiments, the determination of the voltage region in which the circuit element is located according to the position in which the circuit element is configured comprises:

[0011] According to the position where the circuit element is configured, layer structure information at the position is acquired, the layer structure information including a kind of a well region and a layer, the layer being a set of layers formed by element layers used in the circuit element;

[0012] Based on the layer structure information, the voltage region is determined.

[0013] In one embodiment, the determination of the voltage region based on the layer structure information includes:

[0014] When the layer structure information is applicable to only one voltage region, the voltage region is determined based on the layer structure information.

[0015] Further, the circuit design method further includes:

[0016] When the layer structure information is applicable to more than one voltage region, the voltage region is determined according to a set voltage region, the set voltage region being variable.

[0017] In one embodiment, after the determination of the voltage region in which the circuit element is located according to the position where the circuit element is configured, the method further includes:

[0018] According to the voltage region, the layer of the circuit element is adjusted.

[0019] In one embodiment, after the adjustment of the parameter value of the circuit element according to the voltage region, the method further includes:

[0020] According to the position where the circuit element is configured and the adjusted parameter value of the circuit element, a layout of the circuit element in the target circuit is generated.

[0021] A circuit design assistance device for assisting configuration of a circuit element in a semiconductor circuit, the circuit design assistance device including:

[0022] A position specifying unit configured to acquire a position where a circuit element in a target circuit is configured in response to an operation of a user;

[0023] A region determining unit configured to determine a voltage region in which the circuit element is located according to the position where the circuit element is configured;

[0024] A constraint condition output unit configured to adjust a parameter constraint condition of the circuit element according to the voltage region, the parameter constraint condition being used to constrain a range of a parameter value in the circuit element; and

[0025] A parameter rewriting unit configured to adjust a parameter value of the circuit element according to the voltage region, the adjusted parameter value of the circuit element satisfying the parameter constraint condition.

[0026] In one embodiment, the circuit design assistance device includes:

[0027] a layer information output section configured to acquire layer structure information at the position where the circuit element is to be arranged, the layer structure information including a type of a well region and a layer, the layer being a set of layers formed by a layer of elements used in the circuit element, based on the position where the circuit element is to be arranged;

[0028] The region determination section determines the voltage region based on the layer structure information.

[0029] In one embodiment, the circuit design assistance device includes:

[0030] a layout generation section configured to generate a layout of the circuit element in the target circuit based on the position where the circuit element is to be arranged and the adjusted parameter value of the circuit element.

[0031] A computer-readable storage medium having stored thereon a computer program, the computer program, when executed by a processor, implementing the steps of the method of any one of the above.

[0032] A computer program product comprising a computer program, the computer program, when executed by a processor, implementing the steps of the method of any one of the above.

[0033] The above circuit design method, circuit design assistance device, computer-readable storage medium, and computer program product can automatically determine which voltage region a position where a circuit element is to be arranged belongs to based on a specified position of a user, and adjust a parameter value of the circuit element based on the determination result. Thus, in the design of a semiconductor circuit divided into a plurality of different voltage regions, layout design of circuit elements can be performed more easily and efficiently. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a schematic diagram showing division of a high voltage region and a low voltage region in a semiconductor circuit.

[0035] Figure 2 is a plan view showing a polysilicon resistor arranged in a low voltage region.

[0036] Figure 3 is a plan view showing a polysilicon resistor arranged in a high voltage region.

[0037] Figure 4 is a block diagram showing a structure of a circuit design assistance device in the present application.

[0038] Figure 5 is a flowchart showing a circuit design method in the present application.

[0039] Figure 6is a block diagram showing the system configuration of a design of a semiconductor circuit.

[0040] Figure 7 is a flowchart showing a flow of a circuit design to which the present application is applied.

[0041] Figure 8 is a diagram showing a parameter set of a polysilicon resistor.

[0042] Figure 9 is a diagram showing layers of different voltage regions.

[0043] Figure 10 is a diagram showing an example of a constraint condition set of a region to be configured.

[0044] Explanation of Reference Signs:

[0045] 1 - circuit design assistance device; 2 - position specifying section; 3 - region determining section; 4 - parameter rewriting section; 5 - parameter output section; 6 - layout generating section; 7 - layer information output section; 8 - constraint condition output section; 9 - generated result recording section. DETAILED DESCRIPTION

[0046] An embodiment in which the present application is embodied will be described below. In the present application, for example Figure 1 is shown, a design of a semiconductor circuit in which a region as a whole is divided into a high voltage region and a low voltage region is targeted. The high voltage region is a region in which circuit elements that operate at a high voltage (for example, around 6 to 18 V) are arranged. The low voltage region is a region in which circuit elements that operate at a low voltage (for example, around 1.5 to 1.0 V) are arranged. On the specifications of the semiconductor circuit to be designed, the kind, the number, the connection relationship, and the like of the circuit elements that should be arranged are specified for each of the high voltage region and the low voltage region. The purpose of the present application is to assist determination of the specific arrangement of the circuit elements in each region.

[0047] The kind of the circuit element includes various kinds such as a transistor and a resistor. A circuit element in which a plurality of circuit elements are set as one set for a specific purpose, like a Pcell, can also be handled as one circuit element here. Figure 1 The "region as a whole" in the above-mentioned "region as a whole" can be the entirety of a region that becomes one chip in a semiconductor substrate, or the entirety of a repeating unit contained therein.

[0048] For example, if it is considered that the circuit element includes a polysilicon resistor, as Figure 2 Figure 3 ​As shown, in the case of being arranged in the low voltage region and the case of being arranged in the high voltage region, the minimum values that should be satisfied in design differ with respect to various parameters of the circuit element. As the parameters appearing in the figure, the line width a of the resistance pattern PO, the line interval b of the resistance patterns PO from each other, the gap c between the edge of the resistance pattern PO and the via CT, and the gap d between the edge of the arranged well region and the edge of the resistance pattern PO can be cited. In Figure 2 , Examples of connecting two polysilicon resistance lines in series by the metal wiring Ml are shown in Figure 3 .

[0049] The matters that must be adjusted according to the region are not limited to the size. The layer structure can also be included. In the example of Figure 2 , In the example of Figure 3 , with respect to the silicon substrate below the polysilicon resistance line, the case of having to be a well 1 region in the low voltage region and a well 2 region in the high voltage region is also shown. In the well 1 region and the well 2 region, the impurity doping concentration or the doping depth differs. In addition, with respect to the element recognition layer, the case of having to be a recog 1 layer in the low voltage region and a recog 2 layer in the high voltage region is also shown. The element recognition layer is not a physical layer formed by a photomask, but a layer for recognizing the element when verifying whether the determined layout matches the circuit Figure 1 .

[0050] In one embodiment, referring to Figure 4 , a circuit design assistance device 1 is provided. Assistance in the arrangement of a circuit element can be performed by the circuit design assistance device 1 shown in Figure 4 . The circuit design assistance device 1 of Figure 4 has a position specifying section 2, a region determining section 3, a constraint condition output section 8, and a parameter rewriting section 4. Exemplarily, the circuit design assistance device 1 can also include a parameter output section 5.

[0051] The position specifying section 2 is used to acquire the position at which a circuit element in a target circuit is arranged in response to the operation of a user. The target circuit is a semiconductor circuit that is currently designed.

[0052] The region determining section 3 is used to determine the voltage region in which the circuit element is located according to the position at which the circuit element is arranged, for example, to determine which one of the high voltage region and the low voltage region the position specified by the user belongs to.

[0053] The constraint condition output section 8 can output the constraint condition when the arrangement of the circuit element is determined. The constraint condition output section 8 is used to adjust the parameter constraint condition of the circuit element according to the voltage region, the parameter constraint condition being used to constrain the range of the parameter value in the circuit element.

[0054] The parameter rewriting section 4 can change the parameters of the circuit element. The parameter rewriting section 4 is configured to adjust the parameter value of the circuit element according to the voltage region, and the adjusted parameter value of the circuit element satisfies the parameter constraint condition.

[0055] The parameter output section 5 outputs the parameters of the circuit element.

[0056] In one embodiment, the circuit design assistance device 1 further includes a layer information output section 7. The layer information output section 7 can output layer structure information at a position where the circuit element is to be placed.

[0057] The layer information output section 7 is configured to acquire layer structure information at a position where the circuit element is to be placed, the layer structure information including a kind of a well region and a layer, the layer being a set of layers formed by a layer of elements used in the circuit element.

[0058] Meanwhile, the region determination section determines the voltage region based on the layer structure information.

[0059] In one embodiment, the circuit design assistance device 1 further includes a layout generation section 6. The layout generation section 6 can generate a layout of the circuit element.

[0060] The layout generation section 6 generates a layout of the circuit element in the target circuit according to the position where the circuit element is to be placed and the adjusted parameter value of the circuit element.

[0061] Exemplarily, the circuit design assistance device 1 further includes a generation result recording section 9. The generation result recording section 9 can record the layout generated by the layout generation section 6.

[0062] The position specifying section 2, the region determination section 3, the parameter rewriting section 4, the parameter output section 5, the layout generation section 6, the layer information output section 7, the constraint condition output section 8, and the generation result recording section 9 can all be functional modules installed on a computer.

[0063] In one embodiment, referring to Figure 5 A circuit design method is also provided, including the following steps:

[0064] In step S10, a position where a circuit element in a target circuit is to be placed is acquired in response to an operation of a user;

[0065] In step S20, a voltage region where the circuit element is to be placed is determined according to the position where the circuit element is to be placed;

[0066] In step S30, a parameter constraint condition of the circuit element is adjusted according to the voltage region, the parameter constraint condition being configured to constrain a range of a parameter value in the circuit element;

[0067] Step S40, according to the voltage region, adjusting the parameter value of the circuit element, the adjusted parameter value of the circuit element meets the parameter constraint condition.

[0068] In step S10, in the screen of the computer can display Figure 1 That area overall map. The user can specify the position of the circuit element to be placed in the target circuit in the screen. Exemplarily, the user can make the specification of the kind of circuit element and the specification based on the position of the coordinate input device.

[0069] Based on this, the computer can obtain the coordinate value of the specified position in response to the user's operation, thereby obtaining the position of the circuit element configured in the target circuit. This step can be performed by Figure 4 the position specification unit 2.

[0070] In step S20, the coordinate value of the specified position can be obtained according to step S10, and the voltage region where the circuit element is located is determined. Step S20 can be performed by Figure 4 the region determination unit 3.

[0071] In step S30, after determining the voltage region where the circuit element is located, the corresponding parameter constraint condition of the circuit element can be automatically switched according to the voltage region. The parameter constraint condition is used to constrain the range of the parameter value in the circuit element.

[0072] The parameter constraint condition (constraint) can be initially specified by the manufacturing equipment, but it may need to be changed according to the determined voltage region. In this case, the parameter constraint condition is changed according to the requirements of the voltage region. Exemplarily, the changed parameter constraint condition can be applicable when further adding the circuit element within this voltage region. The information of the parameter constraint condition required for this processing can be provided by Figure 4 the constraint condition output unit 8.

[0073] For example, Figure 10 Examples of parameter constraint conditions of different voltage regions are shown. Specifically, in Figure 10 , the circuit element includes a polysilicon resistor. The parameters of the polysilicon resistor include the line width (a of Figure 2 , Figure 3 ), the same line spacing (b of Figure 2 , Figure 3 ), the gap between the edge of the resistance pattern and the via (c of Figure 2 , Figure 3 ), and the gap between the resistance pattern and the edge of the well (d of Figure 2 , Figure 3 ). At the same time Figure 10The respective minimum values of the respective parameters of the polysilicon resistor are shown. The set of constraint conditions of the parameters in the case of the low voltage region and the set of constraint conditions of the parameters in the case of the high voltage region are shown. When the voltage region in which the circuit element is present is switched, the parameter constraint conditions are automatically changed. At the same time, Figure 10 The contents shown do not necessarily need to be displayed on the screen of the computer.

[0074] In step S40, adjustment of the parameter values of the circuit elements is performed. The adjustment of the parameter values refers to changing the parameter values of the circuit elements of the target circuit according to the voltage region determined in step S20.

[0075] The adjustment processing of the parameter values can be implemented by the parameter rewriting section 4. In this processing, the parameter values to be assigned to the circuit elements can be provided from the parameter output section 5 in the Figure 4 . In addition, the parameter values of the circuit elements after adjustment need to satisfy the parameter constraint conditions can be provided from the constraint condition output section 8 in the Figure 4 .

[0076] As an example, in the case where the circuit elements of the target circuit include a polysilicon resistor (including the case where included in a Pcell), Figure 2 , Figure 3 The dimensions of the respective parts noted in the illustration in

[0077] In the illustration in Figure 2 , Figure 3 For any one of the four parameters of the line width a, the line interval b, the gap c, and the gap d of the polysilicon resistor (circuit element), the values (a2, b2, c2, d2) required in the high voltage region ( Figure 3 ) are all larger than the values (al, bl, cl, dl) required in the low voltage region ( Figure 2 ).

[0078] When the adjustment of the parameter values is performed, the parameter set for the low voltage can be switched to the parameter set for the high voltage or vice versa.

[0079] Therefore, in the case where the originally assigned parameter values are the parameter values for the low voltage region and the determined voltage region is the high voltage region, the parameter values for the low voltage region can be changed to the parameter values for the high voltage region. This is the adjustment of the parameter values. The adjustment is automatically performed by the computer in the case of compliance. With respect to the Pcell, by changing the parameter values thereof, an element satisfying the constraints can also be automatically generated.

[0080] On the contrary, the adjustment of the parameter values can also be performed in the case where the originally assigned parameter values are the parameter values for the high voltage region and the determined voltage region is the low voltage region.

[0081] Exemplarily, the user can also be enabled to select whether to perform the adjustment of the parameter values or not by a relevant setting.

[0082] As an example, the parameter set of a polysilicon resistor (circuit element) can also be as shown. Figure 8 Figure 8 is a display example in the screen of the computer. Figure 8 The parameters of the polysilicon resistor seen in the above are "Segment W", "Segment L", "Segment number", and "Segment Connection". If corresponding to Figure 2 Figure 3 , Segment W is the line width a. Segment L is the length in the up-down direction of the resistor pattern PO, although no label is added in Figure 2 Figure 3 . Segment number is the number of the resistor patterns PO, which is "2" in the example of Figure 2 Figure 3 . Segment Connection is the distinction of whether the plurality of resistor patterns are connected in series or in parallel. These can be manually set by the user on the screen of Figure 8

[0083] "Placement Area" in the above is a parameter of setting the kind of the well region in which the polysilicon resistor is arranged. Figure 8 The example shown is of the case of N well in the low voltage region. This parameter can be determined by the coordinates of the arranged position and automatically switched. Figure 8 Meanwhile, even if each of the above parameters can be manually set, if there is a parameter that does not satisfy the parameter constraint condition corresponding to the determined voltage region, this parameter can be automatically corrected.

[0084] In one embodiment, step S20 comprises:

[0085] Step S21, according to the position in which the circuit element is arranged, acquiring layer structure information at the position, the layer structure information including the kind of the well region and the layers, the layers being a set of layers formed by the element layers used in the circuit element;

[0086] Step S22, determining the voltage region based on the layer structure information;

[0087] In step S21, the layer structure information at the position specified by the user can be acquired.

[0088]

[0089] ​​​​​The layer structure information includes a kind of the well region and a layer, which is a set of layers formed by an element layer used in the circuit element. The kind of the well region may be, for example, a kind of the well region formed in the silicon substrate. The layer may be, for example, a set of element layers used in the Pcell.

[0090] The layer structure information in the region as a whole can be set in advance based on a standard specification of a manufacturing apparatus. The layer structure information can be provided by the layer information output section 7 in the manufacturing apparatus. Figure 4 In this step, the computer can read out the layer structure information in which the coordinate values acquired in step S10 are located, from the layer information output section 7.

[0091] In step S22, it can be determined which of the high voltage region and the low voltage region the voltage region belongs to, based on the content of the layer structure information acquired in step S21.

[0092] It can be determined in advance that the voltage region determination is performed using the information of which layer in the layer structure information, and then the voltage region is determined based on the kind of the layer. For example, it is determined in advance that the voltage region determination is performed using the information of the well region in the layer structure information. As for the well region, there are NW, PW, HVNW, and HVPW. If it is known which of them the well region at the user-specified position (the position at which the circuit element is to be arranged) is, then the voltage region can also be determined.

[0093] In one embodiment, step S22 includes:

[0094] In step S221, when the layer structure information can be applied to only one voltage region, the voltage region is determined based on the layer structure information.

[0095] Meanwhile, the circuit design method further includes:

[0096] In step S23, when the layer structure information can be applied to more than one voltage region, the voltage region is determined according to a set voltage region, which is variable.

[0097] In step S221, when the layer structure information includes a layer (such as NW or PW) that can be used only in the low voltage region, the voltage region can be determined to be the low voltage region. When the layer structure information includes a layer (such as HVNW or HVPW) that can be used only in the high voltage region, the voltage region can be determined to be the high voltage region.

[0098] Meanwhile, in step S23, in some cases, the layer included in the layer structure information can be used in both the low voltage region and the high voltage region. In this case, the layer structure information can be applied to more than one voltage region. In this case, the voltage region can be determined according to a set voltage region. The set voltage region is a temporary setting, which can be manually changed later as needed.

[0099] In one embodiment, after step S20, further comprising:

[0100] Step S50, adjusting the layers of the circuit element according to the voltage region.

[0101] Figure 9 Examples of layers of circuit elements in different voltage regions are shown. In Figure 9 , the layers are a set of layers formed by a well region, a polysilicon conductive layer, an element identification layer, a via, and a metal conductive layer. Figure 9 Layers in a low voltage region and layers in a high voltage region are shown. When the voltage region in which the circuit element is located is different, the layers of the circuit element of the target circuit are automatically changed. Figure 9 The content shown does not necessarily need to be displayed on the screen of the computer.

[0102] Exemplarily, when executed in step S20 according to step S23, the voltage region in which the circuit element is located is determined according to the set voltage region, instead of depending on the layer structure information. In such a case, if the set voltage region is subsequently manually changed, the layer structure information (including the layers) can also be adjusted and changed accordingly. Also, if the manually changed set voltage region is subsequently changed, the parameter constraint conditions of the circuit element and the parameter values of the circuit element, etc. can also be adjusted and changed accordingly.

[0103] In one embodiment, after step S40, further comprising:

[0104] Step S60, generating the layout of the circuit element in the target circuit according to the position in which the circuit element is configured and the adjusted parameter values of the circuit element.

[0105] Basically, the circuit element of the target circuit is configured at the position specified by the user in S10. However, through the adjustment of the parameter values of the circuit element in S40, there can be a case that the circuit element is slightly deviated from the specified position. Therefore, the layout of the circuit element in the target circuit is generated. The adjustment of the position can be automatically performed by the computer. As for the Pcell, the layout can be automatically adjusted by changing its parameter set. This processing can be performed by Figure 4 the layout generation part 6 in. The determined circuit configuration can be recorded in the generation result recording part 9.

[0106] In summary, the above processing described in the present application can be performed by causing the computer to perform the following steps: in response to the operation of the user, acquiring the position in which the circuit element in the target circuit is configured; determining the voltage region in which the circuit element is located according to the position in which the circuit element is configured; adjusting the parameter constraint conditions of the circuit element according to the voltage region, the parameter constraint conditions being used to constrain the range of the parameter values in the circuit element; adjusting the parameter values of the circuit element according to the voltage region, the adjusted parameter values of the circuit element satisfying the parameter constraint conditions.Figure 4 The circuit design aid 1 may include a computer with programs installed thereon.

[0107] Semiconductor circuit design generally uses Figure 6 The process design kit, design tools, and design data shown are used for this purpose. In this application, the following can be added: Figure 6 The Pcell development tool is located on the left side of the middle section. Therefore, parameters are automatically adjusted as described above, resulting in high design efficiency. The Pcell can be included in a process design kit provided by manufacturing equipment; however, in this application, its parameters can be automatically adjusted according to the relevant voltage region (the voltage region where the circuit elements are located), as mentioned above.

[0108] Below, refer to Figure 7 Describe the advantages of using this application. Figure 7 The diagram schematically illustrates a summary of the steps for determining the circuit element configuration in this application. Automatic adjustment of the parameters used in this application is performed during the "layout design" stage of this process. In this application, even if the execution parameters change, it is not necessary to return to the previous step. Figure 7 This is the stage preceding the "layout design" in the design process. Under current technology, manual parameter changes are required, thus requiring a return to... Figure 7 The "circuit design" stage in the previous method requires redesigning. However, if this application is used, such a redesign is unnecessary, making it much more convenient.

[0109] According to the embodiments of this application, the voltage region to which the location of the circuit element to be configured belongs is automatically determined, and the parameters of the circuit element are adjusted appropriately based on the determination result. Therefore, in the design of semiconductor circuits divided into multiple different voltage regions, the layout design of circuit elements can be performed more easily and efficiently.

[0110] Furthermore, it is understood that the above embodiments are merely exemplary embodiments of this application and do not limit this application in any way. Therefore, this application can certainly be modified and varied in various ways without departing from its spirit. For example, the voltage level of the voltage region is not limited to the two levels of high voltage region and low voltage region, but can also be three or more levels. In addition, the determination of the voltage region is not limited to the determination based on layer information. When the division of the voltage region is predefined, it can also be determined based on the information of that division.

Claims

1. A method of circuit design, characterized by, A method for assisting configuration of circuit elements in a semiconductor circuit, the circuit design method comprising: acquiring, in response to an operation of a user, a position at which a circuit element in a target circuit is to be configured; determining a voltage region in which the circuit element is located, based on the position at which the circuit element is to be configured; adjusting a parameter constraint condition of the circuit element, based on the voltage region, the parameter constraint condition being used to constrain a range of a parameter value in the circuit element; adjusting the parameter value of the circuit element, based on the voltage region, the adjusted parameter value of the circuit element satisfying the parameter constraint condition; determining the voltage region in which the circuit element is located, based on the position at which the circuit element is to be configured, comprising: determining which voltage region of the semiconductor circuit the position at which the circuit element is to be configured belongs to; the semiconductor circuit including at least two voltage regions having different voltage levels.

2. The circuit design method of claim 1, wherein, the determining the voltage region in which the circuit element is located, based on the position at which the circuit element is to be configured, comprising: acquiring layer structure information at the position at which the circuit element is to be configured, based on the position at which the circuit element is to be configured, the layer structure information including a type of a well region and a layer, the layer being a set of layers formed by a component layer used in the circuit element; determining the voltage region based on the layer structure information.

3. The circuit design method of claim 2, wherein, the determining the voltage region based on the layer structure information, comprising: determining the voltage region based on the layer structure information when the layer structure information can only be applicable to one voltage region; and the circuit design method further comprising: determining the voltage region according to a set voltage region when the layer structure information is applicable to more than one voltage region, the set voltage region being variable.

4. The circuit design method according to claim 1 or 2, wherein, after the determining the voltage region in which the circuit element is located, based on the position at which the circuit element is to be configured, further comprising: adjusting a layer of the circuit element, based on the voltage region.

5. The circuit design method according to claim 1 or 2, wherein, after the adjusting the parameter value of the circuit element, based on the voltage region, comprising: generating a layout of the circuit element in the target circuit, based on the position at which the circuit element is to be configured and the adjusted parameter value of the circuit element.

6. A circuit design aid device, characterized by comprising: A circuit design assistance device for assisting configuration of circuit elements in a semiconductor circuit, the circuit design assistance device comprising: a position specifying unit configured to acquire, in response to an operation of a user, a position at which a circuit element in a target circuit is to be configured; a region determining unit configured to determine a voltage region in which the circuit element is located, based on the position at which the circuit element is to be configured; a constraint condition output unit configured to adjust a parameter constraint condition of the circuit element, based on the voltage region, the parameter constraint condition being used to constrain a range of a parameter value in the circuit element; and a parameter rewriting unit configured to adjust the parameter value of the circuit element, based on the voltage region, the adjusted parameter value of the circuit element satisfying the parameter constraint condition; the determining the voltage region in which the circuit element is located, based on the position at which the circuit element is to be configured, comprising: determining which voltage region of the semiconductor circuit the position at which the circuit element is to be configured belongs to; the semiconductor circuit including at least two voltage regions having different voltage levels.

7. The circuit design aid of claim 6, wherein the circuit design assistance device comprising: A layer information output section configured to acquire layer structure information at a position where the circuit element is to be arranged, the layer structure information including a kind of a well region and a layer, the layer being a set of layers formed by a layer of elements used in the circuit element; The region determination section determines the voltage region based on the layer structure information.

8. The circuit design aid of claim 6 or 7, wherein, The circuit design assistance device includes: A layout generation section configured to generate a layout of the circuit element in the target circuit based on the position where the circuit element is to be arranged and the adjusted parameter value of the circuit element.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 5.

10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 5.

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