Semiconductor device unit structure modeling method and device, equipment and storage medium

Abstract

The invention provides a semiconductor device unit structure modeling method and device, equipment and a storage medium, and belongs to the technical field of data processing. The semiconductor device unit structure comprises a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device are connected and are metal oxide semiconductor field effect transistors; comprising the steps of obtaining test data of a first semiconductor device and a second semiconductor device; determining a resistance value of the first semiconductor device according to the test data; creating a combined model according to the resistance value; determining a second characteristic parameter corresponding to the second semiconductor device according to the combined model and the test data; determining a first characteristic parameter corresponding to the first semiconductor device model according to the second characteristic parameter and the test data; and creating a semiconductor device unit structure model according to the first characteristic parameter and the second characteristic parameter. According to the invention, the problem that a semiconductor device unit formed by two MOS devices connected in series cannot be modeled at present is solved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a method, apparatus, device and storage medium for modeling a semiconductor device unit structure. Background Art

[0002] Circuit design is one of the most important factors affecting circuit performance. Good circuit design can reduce circuit energy consumption, stability, and size.

[0003] Currently, circuit design in the prior art involves the application of MOS (Metal-Oxide-Semiconductor) devices. In order to study the characteristics of MOS devices, it is usually necessary to perform modeling analysis on the MOS devices.

[0004] However, the inventors have discovered that the prior art has at least the following technical problems: when two MOS devices are connected in series to form a semiconductor device unit, it is impossible to perform overall modeling analysis. Summary of the Invention

[0005] The present application provides a semiconductor device unit structure modeling method, apparatus, equipment and storage medium to solve the problem of low accuracy of currently acquired device characteristics.

[0006] In a first aspect, the present application provides a method for modeling a semiconductor device unit structure, wherein the semiconductor device unit structure includes a first semiconductor device and a second semiconductor device, the first semiconductor device being connected to the second semiconductor device, wherein the first semiconductor device and the second semiconductor device are both metal oxide semiconductor field effect transistors; the method includes: obtaining test data of the first semiconductor device and the second semiconductor device; determining the resistance value of the first semiconductor device based on the test data; creating a combination model based on the resistance value; determining a second characteristic parameter corresponding to the second semiconductor device based on the combination model and the test data; determining a first characteristic parameter corresponding to the first semiconductor device model based on the second characteristic parameter and the test data; and creating a semiconductor device unit structure model based on the first characteristic parameter and the second characteristic parameter.

[0007] In one possible implementation, the test data includes: a first current-voltage curve showing that the drain current of the second semiconductor device changes with the gate voltage of the first semiconductor device when the gate voltage of the second semiconductor device is a constant, and a second current-voltage curve showing that the drain current of the second semiconductor device changes with the drain voltage of the second semiconductor device when the gate voltage of the second semiconductor device is a constant; a third current-voltage curve showing that the drain current of the second semiconductor device changes with the gate voltage of the second semiconductor device when the gate voltage of the first semiconductor device is a constant, and a fourth current-voltage curve showing that the drain current of the second semiconductor device changes with the drain voltage of the second semiconductor device.

[0008] In one possible implementation, the drain voltage of the first semiconductor device corresponding to the first current-voltage curve and the third voltage curve is less than a preset voltage value, and the maximum value of the gate voltage of the first semiconductor device corresponding to the first current-voltage curve is greater than the turn-on voltage of the first semiconductor device, and the maximum value of the gate voltage of the second semiconductor device corresponding to the third current-voltage curve is greater than the turn-on voltage of the second semiconductor device.

[0009] In one possible implementation, determining the resistance value of the first semiconductor device based on test data includes: selecting at least four groups of data to be input in the first current-voltage curve; inputting the data to be input into preset resistance equations respectively to obtain a group of equations to be solved; and solving the group of equations to be solved to obtain the resistance value of the first semiconductor device.

[0010] In one possible implementation, it also includes: determining model performance data of the semiconductor device unit structure model; determining a performance error based on the model performance data and test data; if the performance error is less than a preset value, determining the semiconductor device unit structure model as the target semiconductor device unit structure model; if the performance error is greater than or equal to the preset value, changing the model parameters of the semiconductor device unit structure model based on the performance error to obtain a new semiconductor device unit structure model; using the new semiconductor device unit structure model, re-executing the steps of determining the model performance data to changing the parameters until the performance error is less than the preset value.

[0011] In one possible implementation, model parameters of a semiconductor device unit structure model are changed according to a performance error to obtain a new semiconductor device unit structure model, including: searching for a type correspondence according to a data type of the performance error to obtain a parameter type to be changed; searching for a difference calculation formula corresponding to the parameter type to be changed and the data type; inputting the performance error into the difference calculation formula to obtain a changed difference; determining new model parameters according to each changed difference and the parameter value corresponding to each changed difference; and creating a model using the new model parameters to obtain a new semiconductor device unit structure model.

[0012] In one possible implementation, a combination model is created based on the resistance value, including: generating first model parameters corresponding to the second semiconductor device, second model parameters corresponding to the resistance value, and connection relationship parameters; inputting the first model parameters, second model parameters, and connection relationship parameters into model fitting software to obtain the combination model.

[0013] In a second aspect, the present application provides a semiconductor device unit structure modeling device, wherein the semiconductor device unit structure includes a first semiconductor device and a second semiconductor device, the first semiconductor device is connected to the second semiconductor device, wherein the first semiconductor device and the second semiconductor device are both metal oxide semiconductor field effect transistors; the device includes: a data acquisition module for acquiring test data of the first semiconductor device and the second semiconductor device; a resistance determination module for determining the resistance value of the first semiconductor device according to the test data; a first creation module for creating a combination model according to the resistance value; a first determination module for determining the second characteristic parameter corresponding to the second semiconductor device according to the combination model and the test data; a second determination module for determining the first characteristic parameter corresponding to the first semiconductor device model according to the second characteristic parameter and the test data; and a second creation module for creating a semiconductor device unit structure model according to the first characteristic parameter and the second characteristic parameter.

[0014] In a third aspect, the present application provides an electronic device comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory, so that the processor executes the semiconductor device unit structure modeling method described in the first aspect.

[0015] In a fourth aspect, the present application provides a computer-readable storage medium, in which computer execution instructions are stored. When the computer execution instructions are executed by a processor, they are used to implement the semiconductor device unit structure modeling method described in the first aspect.

[0016] The semiconductor device unit structure modeling method, apparatus, equipment and storage medium provided in the present application obtain test data of the semiconductor device, determine the characteristic parameters including the resistance value of one of the semiconductor devices based on the test data, use the resistance value of this semiconductor device, replace one of the semiconductor devices with a resistor, and use the semiconductor device model for the other semiconductor device to create a combined model, obtain the second characteristic parameter corresponding to the second semiconductor device, and create a semiconductor device unit structure model based on the first characteristic parameter and the second characteristic parameter to achieve modeling of a unit including two semiconductor devices connected in series. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an application scenario of the semiconductor device unit structure modeling method provided in an embodiment of the present application;

[0019] Figure 2A schematic flow chart of a semiconductor device unit structure modeling method provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a combination model provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of test voltages for dual semiconductor devices provided in an embodiment of the present application;

[0022] Figure 5 A schematic structural diagram of a semiconductor device unit structure modeling apparatus provided in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0024] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0025] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0026] Circuit design plays a crucial role in circuit performance. Through careful circuit design, we can effectively reduce energy consumption, enhance stability and optimize size.

[0027] In existing technologies, when two MOS devices are connected in series, it is usually necessary to build a model and perform simulation tests to obtain the device characteristics. However, the current simulation test results are not good.

[0028] In response to the above technical problems, the inventors proposed the following technical concept: by obtaining test data of semiconductor devices, determining the resistance value of one of them, treating this semiconductor device as a resistor to create a model containing two devices, and determining the model performance data corresponding to the model, continuously changing the model according to the model performance data and test data to obtain the target semiconductor device unit structure model.

[0029] Figure 1 Schematic diagram of the application scenario of the semiconductor device unit structure modeling method provided in the embodiment of the present application. Figure 1In this scenario, it includes: terminal device 101, server 102, and data acquisition device 103.

[0030] In a specific implementation process, the terminal device 101 may include a computer, a server, a tablet, a mobile phone, a PDA (Personal Digital Assistant), a notebook, etc., which can input data.

[0031] The server 102 can be implemented using a server or a cluster of multiple servers with more powerful processing capabilities and higher security. If possible, a computer or laptop with stronger computing power can be used as a replacement.

[0032] The data acquisition device 103 can be an experimental instrument, a memory, etc.

[0033] The connection between the server 102 and the terminal device 101 and the data acquisition device 103 can be a wired connection or a wireless connection.

[0034] The server 102 is used to receive instructions from the terminal device 101, obtain test data from the data acquisition device 103, establish a semiconductor model, optimize the semiconductor model, and obtain a target semiconductor device unit structure model.

[0035] It is understood that the structure illustrated in the embodiments of this application does not constitute a specific limitation on the method for modeling the unit structure of a semiconductor device. In other feasible embodiments of this application, the above architecture may include more or fewer components than shown, or combine or split certain components, or arrange the components differently. The specific configuration can be determined based on the actual application scenario and is not limited here. Figure 1 The components shown can be implemented by hardware, software, or a combination of software and hardware.

[0036] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0037] Figure 2 A flow chart of a semiconductor device unit structure modeling method provided in an embodiment of the present application. The execution subject of the embodiment of the present application may be Figure 1The server 102 may also be a computer and / or a mobile phone, etc., and this embodiment does not impose any particular restrictions on this. The semiconductor device unit structure includes a first semiconductor device and a second semiconductor device, the first semiconductor device is connected to the second semiconductor device, wherein the first semiconductor device and the second semiconductor device are both metal oxide semiconductor field effect transistors. Figure 2 As shown, the method includes:

[0038] S201: Acquire test data of a first semiconductor device and a second semiconductor device.

[0039] This step may include controlling the test equipment to test the first semiconductor device and the second semiconductor device to obtain test data; may also include reading the test data obtained by the test; and may also include receiving the test data sent by the terminal device.

[0040] S202: Determine the resistance value of the first semiconductor device according to the test data.

[0041] This step may include solving a set of equations according to test data to obtain the resistance value of the first semiconductor device.

[0042] S203: Create a combination model based on the resistance value.

[0043] This step may include inputting the basic model into model fitting software to obtain a second semiconductor device model corresponding to the second semiconductor device, and connecting the second semiconductor device model in series with a resistor having a resistance value to obtain a combined model, wherein the basic model may be a preset model corresponding to a metal oxide semiconductor field effect transistor. The process of creating the combined model may also include receiving a model setting file sent by a staff member, inputting the model setting file and the resistance value into the simulation software, thereby implementing the modeling of the combined model.

[0044] Figure 3 This is a schematic diagram of the combined model provided in the embodiment of the present application. Figure 3 As shown, the left side is the second semiconductor device model, and the right side is the resistor (equivalent resistor of the first semiconductor device). The resistance value of the resistor is the resistance value obtained in step S202 above. In the figure, d represents the drain terminal, g represents the gate terminal, s represents the source terminal, b represents the ground terminal, and n0 represents the connection point between the first semiconductor device model and the second semiconductor device model. n0 is both the source terminal of the second semiconductor device model and the drain terminal of the first semiconductor device model.

[0045] S204: Determine a second characteristic parameter corresponding to the second semiconductor device according to the combined model and the test data.

[0046] In this step, it includes running model fitting software using the combined model to obtain fitting data, sending the fitting data to the terminal device so that the terminal device outputs the fitting data, receiving model parameters input by the staff, replacing the model parameters of the combined model with the input model parameters, obtaining a new combined model, and performing this step again using the new combined model until receiving confirmation information sent by the staff through the terminal device. It can also include inputting the model setting file, test data and resistance value into the simulation software to obtain the second characteristic parameter corresponding to the second semiconductor device optimized by the simulation software. It can also include inputting the combined model into the model fitting software to obtain fitting data, calculating the error between the fitting data and the test data, optimizing the combined model based on the error, obtaining a new combined model, and repeating this step using the new combined model until the error is less than a preset threshold.

[0047] The second characteristic parameter may include resistance, electron mobility, gate oxide capacitance, and a turn-on voltage of the second semiconductor device. "Second" and "first" are used to distinguish the characteristic parameters of the second semiconductor device from the characteristic parameters of the first semiconductor device.

[0048] S205: Determine the first characteristic parameter corresponding to the first semiconductor device model according to the second characteristic parameter and the test data;

[0049] In this step, similar to the above-mentioned steps S203 and S204, the steps include combining the second characteristic parameter and the preset metal oxide semiconductor field effect transistor model parameters to obtain the semiconductor device unit structure model data to be optimized, inputting the semiconductor device unit structure model data to be optimized into the model fitting software to obtain fitting data of the model performance output by the model fitting software, adjusting the metal oxide semiconductor field effect transistor model parameters according to the fitting data and the test data to obtain new semiconductor device unit structure model data to be optimized, and again performing the step of inputting the data into the model fitting software to adjust the parameters until the error between the fitting data and the test data is less than a preset error threshold; it may also include using the preset metal oxide semiconductor field effect transistor model parameters to replace the resistance part of the combined model in the above step (the combined model created in the above step S203 and processed in the above step S204) to obtain the semiconductor device unit structure model data to be optimized, inputting the semiconductor device unit structure model data to be optimized into the model fitting software to obtain fitting data, and optimizing the semiconductor device unit structure model data to be optimized using the fitting data and the test data to obtain the first characteristic parameters corresponding to the first semiconductor device.

[0050] Among them, in the step of using fitting data and test data to optimize the semiconductor device unit structure model data to be optimized, in addition to the software automatically adjusting according to the difference between the fitting data and the test data, the fitting data can also be output so that the staff can adjust the semiconductor device unit structure model data to be optimized according to the fitting data and the test data.

[0051] S206: Creating a semiconductor device unit structure model according to the first characteristic parameter and the second characteristic parameter.

[0052] In this step, the MOS device model architecture of the simulation software may be used to create two MOS device models, and the first characteristic parameter and the second characteristic parameter may be used as parameters used in the model to obtain a semiconductor device unit structure model.

[0053] From the description of the above embodiments, it can be seen that the embodiments of the present application obtain test data of semiconductor devices, determine the characteristic parameters including resistance value of one of the semiconductor devices based on the test data, use the resistance value of this semiconductor device, replace one of the semiconductor devices with resistance, and use the semiconductor device model for the other semiconductor device to create a combined model, obtain the second characteristic parameter corresponding to the second semiconductor device, and create a semiconductor device unit structure model based on the first characteristic parameter and the second characteristic parameter to achieve modeling of a unit including two semiconductor devices connected in series.

[0054] In a possible implementation, the test data includes:

[0055] When the gate voltage of the second semiconductor device is constant, a first current-voltage curve shows that the drain current of the second semiconductor device changes with the gate voltage of the first semiconductor device, and a second current-voltage curve shows that the drain current of the second semiconductor device changes with the drain voltage of the second semiconductor device.

[0056] When the gate voltage of the first semiconductor device is constant, a third current-voltage curve shows that the drain current of the second semiconductor device changes with the gate voltage of the second semiconductor device, and a fourth current-voltage curve shows that the drain current of the second semiconductor device changes with the drain voltage of the second semiconductor device.

[0057] The first current-voltage curve can be measured by controlling the gate voltage of the second semiconductor device to a constant value, the drain voltage of the second semiconductor device to a low voltage, and the gate voltage of the first semiconductor device to a scanning voltage, and measuring the drain current of the second semiconductor device and the gate voltage of the first semiconductor device. The second current-voltage curve can be measured by controlling the gate voltage of the second semiconductor device to a constant value, the drain voltage of the second semiconductor device to a scanning voltage, inputting different voltages of equal step lengths to the voltage of the first semiconductor device, and measuring the drain voltage of the second semiconductor device and the drain current of the second semiconductor device. The third current-voltage curve can be measured by controlling the gate voltage of the first semiconductor device to a constant value, the drain voltage of the second semiconductor device to a low voltage, inputting a scanning voltage to the gate of the second semiconductor device, and measuring the drain current of the second semiconductor device and the gate voltage of the second semiconductor device. The fourth current-voltage curve can be measured by controlling the gate voltage of the first semiconductor device to a constant value, the drain voltage of the second semiconductor device to a scan voltage, inputting voltages of equal steps to the gate of the second semiconductor device, and measuring the drain current and drain voltage of the second semiconductor device. Each current-voltage curve includes various voltage data input during the test.

[0058] The detailed parameters of different test processes can be seen in Table 1.

[0059] Table 1 Test process diagram

[0060]

[0061] The turn-on voltage V th1 and V th2 Can be measured, V dd1 and V dd2 Can be pre-set.

[0062] It can be seen from the description of the above embodiments that the embodiments of the present application facilitate subsequent calculation of characteristic parameters of semiconductor devices and optimization of semiconductor device unit structure models by testing current-voltage curves under different conditions.

[0063] Figure 4 This is a schematic diagram of the test voltage of the dual semiconductor device provided in the embodiment of the present application. Figure 4 As shown, the first semiconductor device is the semiconductor device in the right dashed box, and the second semiconductor device is the semiconductor device in the left dashed box. The voltage applied to the gate of the second semiconductor device is defined as V g2 , the drain voltage is defined as V d2 , the ground voltage is defined as V subThe node at the source of the second semiconductor device is considered as n0; the voltage applied to the gate of the first semiconductor device is defined as V g1 , the source voltage is defined as V s1 , the ground voltage is the same as the second semiconductor device V sub , n0 node is also the drain terminal of the first semiconductor device. Taking N-type semiconductor device as an example, at V g2 is a fixed value and V g1 When the drain voltage is constant, two sets of data are measured on the device: the drain current and gate voltage curve measurement (when the drain voltage is constant, the drain current is measured along with the gate voltage sweeping curve) and the drain current and drain voltage curve measurement (when the gate voltage is constant, the drain current is measured along with the drain voltage sweeping curve). Define the standard operating voltage of semiconductor device 1 as V dd1 , the device turn-on voltage is V th1 ; The standard operating voltage of semiconductor device 2 is V dd2 , the device turn-on voltage is V th2 .

[0064] For example, when performing the first set of tests, the drain voltage V d2 Controlled to 0.1V, V dd2 Test the gate voltage V g2 Controlled from 0 to V dd2 The scanning voltage of the first semiconductor device is V s1 Controlled to 0, the gate voltage V g1 Controlled by V dd1 .

[0065] In one possible implementation, the drain voltage of the first semiconductor device corresponding to the first current-voltage curve and the third voltage curve is less than a preset voltage value, and the maximum value of the gate voltage of the first semiconductor device corresponding to the first current-voltage curve is greater than the turn-on voltage of the first semiconductor device, and the maximum value of the gate voltage of the second semiconductor device corresponding to the third current-voltage curve is greater than the turn-on voltage of the second semiconductor device.

[0066] The preset voltage value may be a maximum voltage that enables the first semiconductor device to operate in a linear region. The gate voltage of the first semiconductor device corresponding to the first current-voltage curve and the gate voltage of the second semiconductor device corresponding to the third current-voltage curve are scan voltages, and thus have a maximum voltage value. The maximum value can ensure that both the first semiconductor device and the second semiconductor device are fully turned on.

[0067] It can be seen from the description of the above embodiments that the embodiments of the present application control the voltage range input when measuring the current-voltage curve so that the measured data can reflect the characteristics of the device.

[0068] In a possible implementation, the step S202 of determining the resistance value of the first semiconductor device according to the test data includes:

[0069] S2021: Select at least four sets of data to be input from the first current-voltage curve.

[0070] In this step, it may include randomly selecting four sets of data from the first current-voltage curve as the data to be input; it may also include selecting at least four sets of data in the first current-voltage curve where the gate voltage of the first semiconductor device is greater than the turn-on voltage of the first semiconductor device as the data to be input.

[0071] The data to be input includes test data used in the process of obtaining the first current-voltage curve through testing, such as the voltage data in Table 1.

[0072] S2022: Input the data to be input into the preset resistance equation respectively to obtain a set of equations to be solved.

[0073] In this step, since four groups of data to be input are selected in the above step S2021, each group of data to be input can be input into the preset resistance equation to obtain an equation to be solved, and the equations to be solved can be combined to obtain a group of equations to be solved.

[0074] S2023: Solve the set of equations to obtain the resistance value of the first semiconductor device.

[0075] In this step, a preset program or script may be used to solve the set of equations to obtain the resistance value.

[0076] From the description of the above embodiments, it can be seen that the embodiment of the present application obtains the resistance value of the first semiconductor device by using the data in the first current-voltage curve to solve the equation, which facilitates the subsequent use of this characteristic parameter to model and optimize the semiconductor device unit.

[0077] In a possible implementation, the resistance equation is preset in step S2022 as follows:

[0078]

[0079] Where R total Represents the total resistance, u n represents electron mobility, C ox represents the gate oxide capacitance, W and L are constants, representing the width and length of the MOS device respectively, V g2represents the gate voltage of the second semiconductor device, R g1 represents the resistance value of the first semiconductor device, I d2 Represents the drain current of the second semiconductor device, V th2 represents the turn-on voltage of the second semiconductor device.

[0080] Among them, R total Equal to R g1 With R g2 The sum of R g2 represents the equivalent resistance of the second semiconductor device, When the first semiconductor device is regarded as a linear resistor R g1 In the case when V d2 =0.1V and V g2 -V th2 >>V d2 -V n0 When the first semiconductor device and the second semiconductor device can be regarded as a linear resistor, the above resistance equation can be used. In the above resistance equation, the V gs V g2 -V n0 At this time, the channel between the source and drain of the first semiconductor device is regarded as a linear resistor, and the current passing through the source and drain of the first semiconductor device or the second semiconductor device is I d2 , so V n0 -V S1 =V n0 -0=R g1 *I d2 , so the V of the second semiconductor device gs V g2 -R g1 *I d2 , the equivalent resistance of the first semiconductor device or the second semiconductor device presents the above preset resistance equation. d2 =0.1V, I d2 With V g2 The corresponding value can be obtained by scanning u n 、C ox 、R g1 、V th2 is considered as the quantity to be solved. When multiple groups of V g2 with I d2 When the value of R is g1 The numerical value of .

[0081] From the description of the above embodiment, it can be seen that in the embodiment of the present application, when the voltage Vd2 is a constant small voltage during the test, due to the first semiconductor device V s1 is 0, the second semiconductor device has a voltage divider, Vn0 Less than V d2 , and the voltage V between the drain and source terminals of the first semiconductor device ds1 =V n0 -V S1 , V d2 -0=V d2 , so V ds1 Less than V d2 At this time, for the first semiconductor device, V g1 Apply voltage V dd1 , the first semiconductor device is fully turned on, V dd1 Generally much larger than the device turn-on voltage V th1 , that is, V of the first semiconductor device gs1 -V th1 >V d2 >V ds1 , where V gs1 Represents the voltage between the gate and source of the first semiconductor device. According to the characteristics of the semiconductor device, the channel between the source and drain can be represented by a linear resistor, and the resistance is:

[0082]

[0083] Where R on Represents the resistance between source and drain, u n represents electron mobility, C ox represents the gate oxide capacitance, W and L are constants, V gs Represents the voltage between the gate and source terminals, V th Indicates the turn-on voltage.

[0084] Therefore, the first semiconductor device can be regarded as a linear resistor. By regarding the first semiconductor device as a resistor, the characteristic parameters of the second semiconductor device can be solved.

[0085] In a possible implementation, after creating the semiconductor device unit structure model according to the first characteristic parameter and the second characteristic parameter in step S206, the method further includes:

[0086] S207: Determine model performance data of the semiconductor device unit structure model.

[0087] This step may include running simulation software to obtain model performance data output by the simulation software.

[0088] The model performance data may include parameter data such as current-voltage curve, resistance value, electron mobility, and turn-on voltage.

[0089] S208: Determine the performance error based on the model performance data and the test data.

[0090] In this step, it may include calculating the difference between the model performance data and the test data to obtain the performance error; it may also include using the area between the curve of the test data and the curve of the model performance data as the performance error; in the case where the model performance data and the test data contain at least one parameter type, it may also include determining the performance error corresponding to each parameter type based on the model performance data and test data of each parameter type.

[0091] The parameter types include, for example, turn-on voltage and mobility.

[0092] S209: If the performance error is less than a preset value, the semiconductor device unit structure model is determined as a target semiconductor device unit structure model.

[0093] In this step, the preset value may be a value set by the staff based on experimental data or experience parameters.

[0094] S210: If the performance error is greater than or equal to a preset value, the model parameters of the semiconductor device unit structure model are changed according to the performance error to obtain a new semiconductor device unit structure model; using the new semiconductor device unit structure model, the steps of determining the model performance data to change the parameters are re-executed until the performance error is less than the preset value.

[0095] This step may include multiplying the performance error by a preset coefficient to obtain a parameter modification, and adding the parameter modification to the model parameters to obtain a new semiconductor device unit structure model. If the model performance data and the test data contain at least one parameter type, the model parameters may be modified based on the type of model parameter using a corresponding performance error to obtain a new semiconductor device unit structure model. The steps of determining the model performance data to modify the parameters may be steps S205 to S206 above.

[0096] From the description of the above embodiments, it can be seen that the embodiments of the present application obtain a performance error by combining model performance data and measured data. When the performance error is less than a preset value, the semiconductor device model is determined as the target semiconductor device unit structure model. When the performance error is greater than or equal to the preset value, the semiconductor device unit structure model is adjusted according to the performance error until the performance error is less than the preset value, thereby achieving continuous optimization of the semiconductor device unit structure model and ultimately approaching the actual measurement results.

[0097] In a possible implementation, in step S210, the model parameters of the semiconductor device unit structure model are changed according to the performance error to obtain a new semiconductor device unit structure model, including:

[0098] S2101: According to the data type of the performance error, the type correspondence is searched to obtain the parameter type to be changed.

[0099] In this step, the type correspondence may store a correspondence between the data type of the performance parameter and the data type of the parameter to be changed.

[0100] The type correspondence relationship may be pre-set by the staff based on experimental data or experience, and may be stored in a table, key-value pair, or other format.

[0101] S2102: Find the difference calculation formula corresponding to the parameter type and data type to be changed.

[0102] In this step, the difference calculation formula corresponding to the parameter type and data type to be changed can be obtained by looking up the table. The difference calculation formula can be preset by the staff.

[0103] S2103: Input the performance error into the difference calculation formula to obtain the change difference.

[0104] In this step, the performance error may be used as an independent variable of the difference calculation formula, and the dependent variable of the obtained difference calculation formula may be used as the change difference.

[0105] S2104: Determine new model parameters based on each change difference and the parameter value corresponding to each change difference.

[0106] In this step, the change difference corresponding to the same parameter type is added to the corresponding parameter value to obtain a new model parameter corresponding to this parameter type; it can also include subtracting each change difference from the corresponding parameter value to obtain a new model parameter.

[0107] S2105: Create a model using new model parameters to obtain a new semiconductor device unit structure model.

[0108] This step may include inputting new model parameters into simulation software to obtain a new semiconductor device unit structure model.

[0109] From the description of the above embodiments, it can be seen that the embodiments of the present application find the parameter type to be changed that needs to be modified based on the data type corresponding to the performance error, and use the difference calculation formula corresponding to the performance error and the parameter type to be changed to calculate the change difference, combine the change difference with the corresponding parameter value, and obtain new model parameters. The new model parameters are used to create a model, thereby realizing automatic updating of the model and increasing the speed of model determination.

[0110] In a possible implementation, after the above step S207, the method further includes: determining a target semiconductor device unit structure model based on the test data, the model performance data, and the semiconductor device unit structure model. Specifically, the method includes:

[0111] S224: Send the test data and the model performance data to the terminal device, so that the terminal device outputs the test data and the model performance data.

[0112] In this step, the test data and model performance data may be sent in a message, data packet or other format, and the terminal device may output the test data and model performance data by displaying the output.

[0113] S225: Receive a parameter change instruction sent by the terminal device, wherein the parameter change instruction includes at least one replacement parameter, which corresponds to a model parameter of the semiconductor device unit structure model and is input by the staff based on the test data and model performance data output by the terminal device.

[0114] In this step, the parameter change instruction may be received by receiving a message, a data packet, or the like.

[0115] S226: Substituting the corresponding model parameters with the replacement parameters to obtain a new semiconductor device unit structure model.

[0116] In this step, the original model parameters corresponding to the replacement parameters may be deleted, and the replacement parameters may be used as new model parameters. After all the replacement parameters are used to replace the model parameters, a new semiconductor device unit structure model is obtained.

[0117] S227: Using the new semiconductor device unit structure model, re-execute the steps of determining model performance data and sending data until a confirmation instruction sent by the terminal device is received, and determine the new semiconductor device unit structure model as the target semiconductor device unit structure model.

[0118] In this step, the steps of determining the model performance data and sending the data may be steps S207 to S224 of this embodiment. The confirmation instruction may also be received by receiving a message, data packet, etc. The confirmation instruction may be input by a staff member on the terminal device, or may be generated by the terminal device after the staff member triggers a related button on the terminal device.

[0119] From the description of the above embodiments, it can be seen that the embodiments of the present application send test data and model performance data to the terminal device, so that the model can be manually adjusted according to the test data and model performance data, so that the model is continuously optimized, and finally an effect that is basically consistent with the test data is achieved, thereby realizing model improvement and increasing the accuracy of the model.

[0120] In a possible implementation, in step S203, creating a combination model according to the resistance value includes:

[0121] S2031: Generate first model parameters corresponding to the second semiconductor device, second model parameters corresponding to the resistance value, and connection relationship parameters.

[0122] This step may include using a preset program or script to generate first model parameters, second model parameters corresponding to the resistance value, and connection relationship parameters.

[0123] S2032: Input the first model parameters, the second model parameters and the connection relationship parameters into the model fitting software to obtain a combined model.

[0124] The connection relationship parameter may be data indicating the position and connection relationship between the second semiconductor device and the resistor. In the resulting combined model, the source terminal of the second semiconductor device model is connected to one end of the resistor model, the drain terminal of the second semiconductor device model serves as the drain terminal of the combined model, and the other end of the resistor model serves as the source terminal of the combined model.

[0125] From the description of the above embodiments, it can be seen that the embodiments of the present application generate model parameters corresponding to semiconductor devices, model parameters corresponding to resistors, and connection relationship parameters, and input the three parameters into the model fitting software to obtain a combined model, thereby increasing the efficiency of model creation.

[0126] Figure 5 A schematic diagram of a semiconductor device unit structure modeling apparatus provided in an embodiment of the present application. The semiconductor device unit structure includes a first semiconductor device and a second semiconductor device, wherein the first semiconductor device is connected to the second semiconductor device, wherein the first semiconductor device and the second semiconductor device are both metal oxide semiconductor field effect transistors; Figure 5 As shown, the semiconductor device unit structure modeling device 500 includes: a data acquisition module 501, a first parameter determination module 502, a first creation module 503, a second parameter determination module 504 and a second creation module 505.

[0127] The data acquisition module 501 is configured to acquire test data of the first semiconductor device and the second semiconductor device.

[0128] The resistance determination module 502 is configured to determine the resistance value of the first semiconductor device according to the test data.

[0129] The first creating module 503 is used to create a combination model according to the resistance value.

[0130] The first determining module 504 is configured to determine a second characteristic parameter corresponding to the second semiconductor device according to the combined model.

[0131] A second determining module 505 is configured to determine a first characteristic parameter corresponding to the first semiconductor device model based on the second characteristic parameter and the test data;

[0132] The second creation module 506 is configured to create a semiconductor device unit structure model according to the first characteristic parameter and the second characteristic parameter.

[0133] The device provided in this embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0134] In one possible implementation, the test data includes: a first current-voltage curve showing that the drain current of the second semiconductor device changes with the gate voltage of the first semiconductor device when the gate voltage of the second semiconductor device is a constant, and a second current-voltage curve showing that the drain current of the second semiconductor device changes with the drain voltage of the second semiconductor device when the gate voltage of the second semiconductor device is a constant; a third current-voltage curve showing that the drain current of the second semiconductor device changes with the gate voltage of the second semiconductor device when the gate voltage of the first semiconductor device is a constant, and a fourth current-voltage curve showing that the drain current of the second semiconductor device changes with the drain voltage of the second semiconductor device.

[0135] In one possible implementation, the drain voltage of the first semiconductor device corresponding to the first current-voltage curve and the third voltage curve is less than a preset voltage value, and the maximum value of the gate voltage of the first semiconductor device corresponding to the first current-voltage curve is greater than the turn-on voltage of the first semiconductor device, and the maximum value of the gate voltage of the second semiconductor device corresponding to the third current-voltage curve is greater than the turn-on voltage of the second semiconductor device.

[0136] In one possible implementation, the resistance determination module 502 is specifically used to: select at least four groups of data to be input in the first current-voltage curve; input the data to be input into a preset resistance equation respectively to obtain a set of equations to be solved; and solve the set of equations to be solved to obtain the resistance value corresponding to the first semiconductor device.

[0137] The device provided in this embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0138] In one possible implementation, a resistance equation is preset as follows:

[0139]

[0140] Where R total Represents the total resistance, u n represents electron mobility, C ox represents the gate oxide capacitance, W and L are constants, representing the width and length of the MOS device respectively, Vg2 represents the gate voltage of the second semiconductor device, R g1 represents the resistance value of the first semiconductor device, I d2 Represents the drain current of the second semiconductor device, V th2 represents the turn-on voltage of the second semiconductor device.

[0141] The device provided in this embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0142] In a possible implementation, the semiconductor device unit structure modeling apparatus 500 further includes: a model optimization module 507 .

[0143] The model optimization module 507 is used to determine the model performance data of the semiconductor device unit structure model; determine the performance error based on the model performance data and the test data; if the performance error is less than a preset value, determine the semiconductor device unit structure model as the target semiconductor device unit structure model; if the performance error is greater than or equal to the preset value, change the model parameters of the semiconductor device unit structure model based on the performance error to obtain a new semiconductor device unit structure model; use the new semiconductor device unit structure model to re-execute the steps of determining the model performance data to changing the parameters until the performance error is less than the preset value.

[0144] The device provided in this embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0145] In one possible implementation, the model optimization module 507 is specifically used to find the type correspondence based on the data type of the performance error to obtain the parameter type to be changed; find the difference calculation formula corresponding to the parameter type to be changed and the data type; input the performance error into the difference calculation formula to obtain the change difference; determine the new model parameters based on each change difference and the parameter value corresponding to each change difference; use the new model parameters to create a model to obtain a new semiconductor device unit structure model.

[0146] The device provided in this embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0147] In one possible implementation, the first creation module 503 is specifically used to generate first model parameters corresponding to the second semiconductor device, second model parameters corresponding to the resistance value, and connection relationship parameters; the first model parameters, the second model parameters, and the connection relationship parameters are input into the model fitting software to obtain a combined model.

[0148] The device provided in this embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0149] In order to implement the above embodiment, the embodiment of the present application also provides an electronic device.

[0150] refer to Figure 6 , which shows a schematic structural diagram of an electronic device 600 suitable for implementing an embodiment of the present application. The electronic device 600 may be a terminal device or a server. The terminal device may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (Portable Android Devices, PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 6 The electronic device shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0151] like Figure 6 As shown, the electronic device 600 may include a processor (such as a central processing unit, a graphics processing unit, etc.) 601, and a memory 602 connected to the processor in communication, which can perform various appropriate actions and processes according to the program stored in the memory 602, the computer execution instruction, or the program loaded from the storage device 608 into the random access memory (Random Access Memory, referred to as RAM) 603 to implement the semiconductor device unit structure modeling method in any of the above embodiments, wherein the memory can be a read-only memory (Read Only Memory, referred to as ROM). In RAM 603, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 601, the memory 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0152] Typically, the following devices may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 608 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 6 The electronic device 600 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed instead.

[0153] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network via the communication device 609, or installed from the storage device 608, or installed from the memory 602. When the computer program is executed by the processing device 601, the above-mentioned functions defined in the method of the embodiment of the present application are performed.

[0154] It should be noted that the computer-readable storage medium mentioned above in this application can be a computer-readable signal medium or a computer storage medium, or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this application, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal can take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable storage medium other than a computer-readable storage medium that can transmit, propagate, or convey a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable storage medium may be conveyed using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0155] The computer-readable storage medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0156] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes the method shown in the above embodiment.

[0157] The computer program code for performing the operations of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect via the Internet).

[0158] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0159] The modules described in the embodiments of the present application may be implemented in software or hardware. In some cases, the name of a unit does not necessarily limit the module itself. For example, the data acquisition module 501 may also be described as a "test data acquisition module 501."

[0160] The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0161] The present application also provides a computer-readable storage medium, which stores computer execution instructions. When the processor executes the computer execution instructions, the technical solution of the semiconductor device unit structure modeling method in any of the above-mentioned embodiments is implemented. Its implementation principle and beneficial effects are similar to the implementation principle and beneficial effects of the semiconductor device unit structure modeling method. Please refer to the implementation principle and beneficial effects of the semiconductor device unit structure modeling method, and no further details will be given here.

[0162] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0163] The present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the technical solution of the semiconductor device unit structure modeling method in any of the above-mentioned embodiments. Its implementation principle and beneficial effects are similar to the implementation principle and beneficial effects of the semiconductor device unit structure modeling method. Please refer to the implementation principle and beneficial effects of the semiconductor device unit structure modeling method, and no further details will be given here.

[0164] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the above-mentioned disclosed concepts. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

[0165] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0166] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor device unit structure modeling method, characterized in that: The semiconductor device unit structure includes a first semiconductor device and a second semiconductor device, wherein the first semiconductor device is connected to the second semiconductor device, wherein the first semiconductor device and the second semiconductor device are both metal oxide semiconductor field effect transistors; the method includes: Acquiring test data of the first semiconductor device and the second semiconductor device; determining a resistance value of the first semiconductor device according to the test data; creating a combination model based on the resistance values; determining a second characteristic parameter corresponding to the second semiconductor device according to the combined model and the test data; determining a first characteristic parameter corresponding to the first semiconductor device model according to the second characteristic parameter and the test data; A semiconductor device unit structure model is created according to the first characteristic parameter and the second characteristic parameter.

2. The method according to claim 1, characterized in that The test data includes: a first current-voltage curve showing a change in drain current of the second semiconductor device as the gate voltage of the first semiconductor device changes when the gate voltage of the second semiconductor device is constant, and a second current-voltage curve showing a change in drain current of the second semiconductor device as the drain voltage of the second semiconductor device changes; When the gate voltage of the first semiconductor device is constant, a third current-voltage curve shows that the drain current of the second semiconductor device changes with the gate voltage of the second semiconductor device, and a fourth current-voltage curve shows that the drain current of the second semiconductor device changes with the drain voltage of the second semiconductor device.

3. The method according to claim 2, characterized in that The drain voltage of the first semiconductor device corresponding to the first current-voltage curve and the third voltage curve is less than a preset voltage value, and the maximum value of the gate voltage of the first semiconductor device corresponding to the first current-voltage curve is greater than the turn-on voltage of the first semiconductor device, and the maximum value of the gate voltage of the second semiconductor device corresponding to the third current-voltage curve is greater than the turn-on voltage of the second semiconductor device.

4. The method according to claim 2, characterized in that Determining the resistance value of the first semiconductor device according to the test data includes: In the first current-voltage curve, at least four groups of data to be input are selected; Inputting the data to be input into the preset resistance equation respectively to obtain a set of equations to be solved; Solve the set of equations to obtain the resistance value of the first semiconductor device.

5. The method according to any one of claims 1 to 4, characterized in that Also includes: determining model performance data of the semiconductor device unit structure model; determining a performance error based on the model performance data and the test data; If the performance error is less than a preset value, determining the semiconductor device unit structure model as a target semiconductor device unit structure model; If the performance error is greater than or equal to a preset value, the model parameters of the semiconductor device unit structure model are changed according to the performance error to obtain a new semiconductor device unit structure model; using the new semiconductor device unit structure model, the steps of determining the model performance data to the changed parameters are re-executed until the performance error is less than the preset value.

6. The method according to claim 5, characterized in that The step of changing the model parameters of the semiconductor device unit structure model according to the performance error to obtain a new semiconductor device unit structure model includes: According to the data type of the performance error, the type correspondence is searched to obtain the parameter type to be changed; Find the difference calculation formula corresponding to the parameter type and data type to be changed; Inputting the performance error into the difference calculation formula to obtain a change difference; Determine new model parameters according to each change difference and the parameter value corresponding to each change difference; A model is created using the new model parameters to obtain a new semiconductor device unit structure model.

7. The method according to any one of claims 1 to 4, characterized in that The step of creating a combination model according to the resistance value includes: generating first model parameters corresponding to the second semiconductor device, second model parameters corresponding to the resistance value, and connection relationship parameters; The first model parameters, the second model parameters and the connection relationship parameters are input into model fitting software to obtain the combined model.

8. A semiconductor device unit structure modeling device, characterized in that: The semiconductor device unit structure includes a first semiconductor device and a second semiconductor device, wherein the first semiconductor device is connected to the second semiconductor device, wherein the first semiconductor device and the second semiconductor device are both metal oxide semiconductor field effect transistors; the device includes: A data acquisition module, configured to acquire test data of the first semiconductor device and the second semiconductor device; a resistance determination module, configured to determine a resistance value of the first semiconductor device according to the test data; A first creation module is used to create a combination model according to the resistance value; a first determining module, configured to determine a second characteristic parameter corresponding to the second semiconductor device according to the combined model and the test data; a second determining module, configured to determine a first characteristic parameter corresponding to the first semiconductor device model according to the second characteristic parameter and the test data; The second creation module is used to create a semiconductor device unit structure model according to the first characteristic parameter and the second characteristic parameter.

9. An electronic device, characterized in that: include: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the semiconductor device unit structure modeling method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the semiconductor device unit structure modeling method according to any one of claims 1 to 7 when executed by a processor.

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