Method and electronic device for determining board card redundancy lines

Abstract

Embodiments of the present application provide a method for determining redundant lines of a board card and an electronic device, which can be applied to the technical field of board card detection. The method for determining redundant lines of the board card comprises: constructing a network topology graph for a target board card based on the layout positions of the end points of each of a plurality of lines laid in the target board card; determining effective nodes from a plurality of nodes of the network topology graph based on design reference data of the target board card; determining edges between the effective nodes that meet predetermined conditions as invalid edges from a plurality of edges included in the network topology graph; and determining lines corresponding to the invalid edges as redundant lines.

Description

Technical Field

[0001] This invention relates to the field of circuit board testing technology, and more specifically to a method and electronic device for determining redundant circuits on a circuit board. Background Technology

[0002] During the design process of printed circuit boards (PCBs), due to manual or automatic routing errors, designer oversights, or the removal of certain components during the design process, some redundant lines are often left behind. These lines can cause adverse consequences such as signal reflection and electromagnetic interference, so it is necessary to detect them.

[0003] The detection methods in related technologies mostly involve engineers visually inspecting PCB design drawings to find redundant lines. This is not only inefficient and time-consuming, but also prone to missing some redundant lines when dealing with complex PCB circuits, resulting in low detection accuracy. Summary of the Invention

[0004] In view of the above problems, the present invention provides a method and electronic device for determining redundant circuits on a circuit board.

[0005] According to a first aspect of the present invention, a method for determining redundant circuits on a circuit board is provided, comprising:

[0006] Based on the location of the endpoints of the multiple lines deployed in the target board, a network topology diagram for the target board is constructed. In the network topology diagram, the nodes represent the endpoints of the lines, and the edges used to connect the nodes represent the lines.

[0007] Based on the design reference data of the target board, valid nodes are determined from multiple nodes in the network topology diagram, where the lines between valid nodes are designed as path states.

[0008] Among the multiple edges included in the network topology graph, edges whose connections to valid nodes meet predetermined conditions are identified as invalid edges;

[0009] The lines corresponding to invalid edges are identified as redundant lines.

[0010] A second aspect of the present invention provides an apparatus for determining redundant circuits on a circuit board, comprising a construction module, a first determining module, a second determining module, and a third determining module.

[0011] The construction module is used to construct a network topology diagram for the target board based on the deployment positions of the endpoints of the multiple lines deployed in the target board. In the network topology diagram, the nodes represent the endpoints of the lines, and the edges used to connect the nodes represent the lines.

[0012] The first determining module is used to determine the effective nodes from multiple nodes in the network topology based on the design reference data of the target board, wherein the lines between the effective nodes are designed to be in a path state.

[0013] The second determining module is used to determine the edges in the network topology graph whose connections to valid nodes meet predetermined conditions as invalid edges.

[0014] The third determination module is used to determine the lines corresponding to invalid edges as redundant lines.

[0015] A third aspect of the present invention provides an electronic device comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0016] A fourth aspect of the present invention also provides a computer-readable storage medium having a computer program or instructions stored thereon, wherein the computer program or instructions, when executed by a processor, implement the steps of the above-described method.

[0017] A fifth aspect of the present invention also provides a computer program product, including a computer program or instructions that, when executed by a processor, implement the steps of the above-described method.

[0018] According to embodiments of the present invention, by constructing a network topology diagram and based on defined valid nodes, automated and rapid detection of redundant lines can be achieved through automated processing of the network topology diagram. This improves the efficiency of PCB design engineering and the standardization and manufacturability of PCB design. It not only quickly detects redundant lines but also achieves high accuracy, accurately identifying extra line segments not connected to valid network nodes, avoiding the problem of omissions easily encountered in traditional manual inspection. Furthermore, this method relies only on the actual line distribution data and board design data of the board under test, without the need for pre-defined detection rules. This reduces the adverse effects of rule sets not fully covering the actual situation. The detection is highly accurate and flexible, adaptable to the detection of various boards, especially non-standard boards. The method of the present invention can promptly detect and correct redundant line segments to prevent potential design errors, such as signal interference or electrical short circuits, thereby improving the reliability of the final product. Attached Figure Description

[0019] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 An application scenario diagram of the method for determining redundant circuits on a circuit board according to an embodiment of the present invention is shown;

[0021] Figure 2 A flowchart of a method for determining redundant circuits on a circuit board according to an embodiment of the present invention is shown;

[0022] Figure 3 A schematic diagram illustrating the detection results of redundant lines according to an embodiment of the present invention is shown;

[0023] Figure 4 An example of a network topology diagram according to an embodiment of the present invention is shown;

[0024] Figure 5 An example of a network topology diagram according to another embodiment of the present invention is shown;

[0025] Figure 6 An example is shown of obtaining multiple connected subgraphs by subgraph partitioning a network topology graph according to an embodiment of the present invention;

[0026] Figure 7 An example of multiple topology subgraphs and cross-layer association subgraphs obtained based on a network topology graph in a multi-layer board scenario according to an embodiment of the present invention is shown.

[0027] Figure 8 Another example of a cross-layer association subgraph according to an embodiment of the present invention is shown;

[0028] Figure 9 Another example of a cross-layer associated subgraph is shown according to an embodiment of the present invention;

[0029] Figure 10 A structural block diagram of an apparatus for determining redundant circuits on a circuit board according to an embodiment of the present invention is shown;

[0030] Figure 11 A block diagram of an electronic device suitable for implementing a method for determining redundant circuitry on a circuit board, according to an embodiment of the present invention, is shown. Detailed Implementation

[0031] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0033] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0034] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0035] The method of this invention is applied to the detection of redundant lines in PCBs. During PCB design, due to manual routing, misoperation of automatic routing tools, designer negligence, or the removal of certain components, redundant lines often remain, such as unconnected ends branching off from the main signal path but not connected to any component or network. The presence of these lines can cause problems, such as signal reflection. In high-frequency signal transmission, redundant lines can act as impedance mismatch points, leading to signal reflection and thus signal integrity issues. They can also cause electromagnetic interference (EMI): these floating lines may act like antennas, emitting or receiving unwanted EMI, affecting circuit performance. Furthermore, they can cause electrostatic discharge (ESD) sensitivity; floating lines easily accumulate static charge, increasing the risk of ESD damage to sensitive components. They can also increase manufacturing costs, affect wiring density, and increase material waste. Finally, they can lead to non-standard designs that do not meet industry standards or customer requirements, affecting delivery quality. Therefore, it is necessary to detect these redundant lines.

[0036] Existing inspection methods mostly involve engineers visually inspecting PCB designs to find redundant traces that are not connected to any networks. This is time-consuming and labor-intensive, especially when dealing with complex multi-layer PCB designs, and is prone to omissions. Due to human factors, some small but critical redundant traces may be overlooked, making it difficult to guarantee 100% accuracy, especially when dealing with dense wiring.

[0037] While the following detection tools can achieve automated detection, their implementation typically relies on predefined rule sets, which may not cover all situations, especially non-standard designs, lacking flexibility. They also lack support for specific project requirements or special cases, have limited customization capabilities, poor adaptability to dynamic changes, and incur high costs for full rescanning when designs change. Furthermore, they are inefficient; even minor design modifications require a complete rescan, wasting significant computational resources and time. They also lack the ability to scan only the affected parts after design changes, reducing overall work efficiency. Therefore, there is an urgent need for a method that can automatically, quickly, and accurately detect redundant circuits.

[0038] An embodiment of the present invention provides a method for determining redundant lines on a circuit board, comprising: constructing a network topology diagram for the target circuit board based on the deployment positions of the endpoints of multiple lines deployed in the target circuit board, wherein nodes in the network topology diagram represent endpoints of lines, and edges in the network topology diagram used to connect nodes represent lines; determining valid nodes from multiple nodes in the network topology diagram based on design reference data of the target circuit board, wherein lines between valid nodes are designed as pathways; determining invalid edges from multiple edges in the network topology diagram whose connections to valid nodes meet predetermined conditions; and determining the lines corresponding to invalid edges as redundant lines.

[0039] Figure 1 The diagram illustrates an application scenario of a method for determining redundant circuits on a circuit board according to an embodiment of the present invention.

[0040] like Figure 1 As shown, the application scenario 100 according to this embodiment may include a PCB board 101, a computing device 102, and a display device 103.

[0041] In the application scenario of this invention embodiment, redundant circuits can be detected on the PCB board 101. The PCB board 101 can be any type of board, such as a single-sided board, double-sided board, single-layer board, multi-layer board, etc.

[0042] The computing device 102 can execute the method for determining redundant circuits on a PCB according to the embodiments of the present invention. For example, it can acquire design data of the PCB board 101, such as the layout positions of the line endpoints in the PCB board 101, the component mounting positions in the PCB board 101, the measurement point positions set in the PCB board 101, the signal line types of the lines in the PCB board 101, and construct a network topology diagram for the PCB board 101 based on the layout positions of the line endpoints in the PCB board 101.

[0043] Furthermore, the computing device 102 can determine the effective nodes (the lines between effective nodes are designed as a path) from multiple nodes in the network topology diagram based on information such as the component installation position in the PCB board 101, the measurement point position set in the PCB board 101, and the signal line type of the lines in the PCB board 101. It can also determine the edges in the network topology diagram whose connection with the effective nodes meets the predetermined conditions as invalid edges. In this way, the lines corresponding to the invalid edges can be determined as redundant lines, and the redundant line information in the PCB board 101 can be output.

[0044] Finally, the test results can be displayed to the user through the display device 103, for example, in the form of a list or in the form of an image.

[0045] The following will be based on Figure 1 The described scene, through Figures 2-9 The method for determining redundant circuits on a circuit board according to the embodiments of the invention will be described in detail.

[0046] Figure 2 A flowchart of a method for determining redundant circuits on a circuit board according to an embodiment of the present invention is shown.

[0047] like Figure 2 As shown, the method for determining redundant circuits on a board in this embodiment includes operations S201 to S204, which can be executed by a processor.

[0048] In operation S201, based on the location of the endpoints of the multiple lines deployed in the target board, a network topology diagram for the target board is constructed. In the network topology diagram, the nodes represent the endpoints of the lines, and the edges used to connect the nodes represent the lines.

[0049] In operation S202, valid nodes are determined from multiple nodes in the network topology based on the design reference data of the target board, wherein the lines between valid nodes are designed to be in a path state.

[0050] In operation S203, among the multiple edges included in the network topology graph, edges whose connections to valid nodes meet predetermined conditions are identified as invalid edges.

[0051] In operation S204, the line corresponding to the invalid edge is identified as a redundant line.

[0052] According to an embodiment of the present invention, the target board can be a board to be tested, which can be a single-layer or multi-layer PCB board.

[0053] Before performing the above operation S201, the PCB design data of the target board can be obtained first. Data related to all circuits of the target board can be obtained and analyzed to detect all circuits, or only data related to a portion of the target board's circuits can be extracted and analyzed to target specific circuits.

[0054] A parser can be used to extract the endpoint locations of multiple traces on a target board from a PCB design file, as well as the target board's design reference data. This design reference data can include information on components, power supplies, signal line types, and testing procedures. Since this design data determines that the relevant traces must be designed as open circuits for normal functionality, it's possible to determine which traces are valid and which are redundant.

[0055] After the data preparation is completed, the above operation S201 can be used to construct a network topology diagram for the target board based on the location of the endpoints of the multiple lines deployed in the target board, and the PCB wiring structure can be abstracted into an undirected graph to analyze the connection relationship between the line segments.

[0056] A network topology diagram includes multiple nodes and multiple edges. Nodes represent the endpoints of lines, and edges connecting nodes represent lines. Each edge represents a direct physical connection between two line endpoints. For multilayer PCBs, considering the presence of vias, the via locations must also be considered as nodes.

[0057] Each node in the graph can be identified. To uniquely identify each node, you can use its position coordinates (x, y) or coordinates that include layer information (x, y, layer). In this way, even two points with the same coordinates but on different layers can be distinguished.

[0058] The process of constructing a network topology graph may include the following operations.

[0059] First, initialize the graph structure. Create an empty graph structure to store all nodes and edges. This graph structure can be in the form of an adjacency list, where each node is associated with a list containing all other nodes directly connected to it.

[0060] Next, the operations of adding nodes and edges are performed. All extracted line segment information is traversed. For each line segment, if its starting point is not a node already existing in the graph, it is added as a new node. Similarly, the ending point of the line segment is checked; if it does not exist, it is added as a new node. For each line segment, after determining that both its starting and ending points are nodes in the graph, an edge is added between these two nodes to represent a direct physical connection between them.

[0061] When constructing a network topology diagram, special handling is required for cross-layer connections. In multi-layer PCB design, vias are used to connect different layers. Therefore, vias need to be handled specially when constructing the diagram. For each via, its corresponding position on different layers is identified as an endpoint, and edges are added between these endpoints to reflect the actual physical connection of the cross-layer connection.

[0062] Thus, the initial network topology is constructed by following the above steps.

[0063] Furthermore, to improve the efficiency of subsequent analysis, some optimizations can be performed on the initial network topology after it has been constructed.

[0064] For example, duplicate nodes can be merged. If multiple nodes have the same location coordinates (especially after considering layer information), they can be merged into one node, reducing computational cost.

[0065] For example, the graph structure can be simplified. Obviously unnecessary nodes or edges can be removed to reduce graph complexity, but it's crucial to ensure this doesn't affect the accurate detection of redundant lines. For instance, some non-high-speed signal lines don't significantly impact the overall functionality of the PCB; to reduce data analysis workload, the edges and nodes of these lines can be deleted, and they can be omitted from detection.

[0066] According to an embodiment of the present invention, after constructing a network topology diagram for a target board, redundant lines in the target board can be determined by searching and calculating the diagram.

[0067] By operating S202, valid nodes can be determined from multiple nodes in the network topology diagram based on the design reference data of the target board. Then, by operating S203, edges in the network topology diagram whose connections to valid nodes meet predetermined conditions are identified as invalid edges. Furthermore, the lines corresponding to these invalid edges are identified as redundant lines, and this is output as the result.

[0068] Because the design reference data includes design data related to components, power supplies, signal line types, and testing, this data determines that relevant lines must be designed as open circuits to enable normal functionality. For example, power line networks need to be designed as open circuits for power supply, and lines between components need to be designed as open circuits for signal transmission. Therefore, valid nodes can be determined from the network topology diagram based on the target board's design reference data. For instance, if the lines corresponding to the edges between nodes are designed as open circuits, then that node is a valid node. Multiple nodes in the network topology diagram can be traversed, and their validity can be determined according to the above rules.

[0069] According to an embodiment of the present invention, edges whose connections to valid nodes meet predetermined conditions are identified as invalid edges, and invalid edges correspond to redundant lines. A valid node represents the endpoint of the corresponding line that is in an available state and is defined as a valid endpoint. Multiple nodes and edges in the network topology graph can be traversed to determine whether the connection between each edge and a valid node meets predetermined conditions. If it does, it is an invalid edge, and the line corresponding to the invalid edge is a redundant line. Conversely, if it does not meet the conditions, it is a valid edge, and the line corresponding to the valid edge is not a redundant line. Determining whether the connection between each edge and a valid node meets predetermined conditions can be done by determining whether the edge and the valid node are not fully connected (e.g., only one end is connected to a valid node) or not connected at all (e.g., neither end is connected to a valid node). If the edge is not connected at all or not fully connected to a valid node, it can be determined that the line corresponding to that edge is not a line designed as a pathway, and the line corresponding to that edge is a redundant line.

[0070] According to embodiments of the present invention, the above method establishes a network topology diagram based on the wiring data of the PCB board, which can associate the actual wiring of the board under test. Valid nodes in the network topology diagram are determined based on the design reference data of the PCB board. Based on this design data, it is determined that the relevant lines need to be designed as passable states for normal use of their respective functions. Therefore, valid nodes can be identified, and invalid edges can be quickly identified based on these valid nodes, thus quickly identifying redundant line segments. It is evident that the above method, by constructing a network topology diagram and based on defined valid nodes, can achieve automated and rapid detection of redundant lines through automated processing of the network topology diagram, thereby improving the work efficiency of PCB design engineering and the standardization and manufacturability of PCB design. Compared to the method of manually visually inspecting each line segment one by one, the method of the present invention, through automated algorithms, can not only quickly detect and complete the scanning and analysis of the entire PCB design in a short time, significantly shortening the detection cycle, but also has high detection accuracy, accurately identifying redundant line segments that are not connected to valid network nodes, avoiding the problem of easy omissions in traditional manual inspection. Furthermore, this method relies solely on the actual circuit distribution data and design data of the board under test during detection, eliminating the need for pre-defined detection rules. This reduces the adverse effects of incomplete rule set coverage of actual situations, resulting in high detection accuracy and flexibility. It can adapt to the detection of various boards, especially non-standard boards. The method described in this invention can promptly identify and correct redundant line segments to prevent potential design errors, such as signal interference or electrical short circuits, thereby improving the reliability of the final product.

[0071] According to an embodiment of the present invention, after the redundant lines are calculated, the detection results can be visualized to enhance the user experience.

[0072] For example, it can generate detailed test reports, which include information such as the number of redundant lines, the location coordinates of each redundant line, the layer it belongs to, and the network it belongs to, which facilitates archiving and further analysis. It also supports exporting to multiple data formats and allows one-click deletion of redundant line segments.

[0073] For example, redundant lines identified in the PCB layout can be highlighted in the PCB design software interface, such as by using bright highlights, bolding, or special color markings, making the problem areas immediately apparent and facilitating quick location and handling by designers.

[0074] Figure 3 A schematic diagram illustrating the detection results of redundant lines according to an embodiment of the present invention is shown.

[0075] like Figure 3 As shown in the diagram, redundant lines are highlighted in the display interface (the example in the diagram is shown in bold), making it easier for designers to quickly locate and handle them.

[0076] Furthermore, interactive operations can be designed to allow users to click on a redundant line segment and jump to its specific location on the PCB interface, facilitating subsequent modifications.

[0077] According to an embodiment of the present invention, the operation S202 of determining a valid node from multiple nodes in a network topology graph can be performed by traversing the nodes using a predetermined graph search algorithm; similarly, the operation S203 of determining an invalid edge from multiple edges in a network topology graph can also be performed by traversing the nodes using a predetermined graph search algorithm.

[0078] Furthermore, the network topology can be divided into multiple subnetworks. For example, nodes associated with different signal line types can be assigned to different subnetworks; or nodes in different location intervals can be assigned to different subnetworks based on their position. Parallel processing can then be implemented to accelerate the overall detection speed.

[0079] Furthermore, if design modifications to the target board result in changes to the design reference data, only the modified local area can be analyzed, avoiding the need to recalculate the entire drawing.

[0080] According to an embodiment of the present invention, the design reference data of the target board includes at least one of the following: signal line type information of each of the multiple lines, pin positions of each of the multiple components designed to be installed in the target board, test point positions of the test unit designed to be installed in the target board, and reference positions of the custom functional units designed to be installed in the target board.

[0081] According to an embodiment of the present invention, the signal line type information of the line indicates the signal line type to which the line belongs, such as a power signal line, a ground network signal line, or a high-speed signal line, etc.

[0082] Based on this, determining valid nodes from multiple nodes in the network topology using the target board's design reference data involves: identifying the endpoints of lines belonging to a predetermined signal line type from among the multiple endpoints of multiple lines as the first endpoint, and identifying the nodes corresponding to the first endpoints as first-class valid nodes. The predetermined signal line type includes power signal lines or ground network signal lines. That is, if a node belongs to a power or ground network, that node is considered a valid node. Since the connection points of power signal lines or ground network signal lines are all valid nodes, they can be marked individually first, avoiding omissions of valid nodes and improving the accuracy of subsequent redundant line identification, preventing the erroneous identification of power or ground network lines as redundant lines.

[0083] According to embodiments of the present invention, the pin positions of multiple components designed and installed on a target board can be the coordinate information of the multiple pins of the components on the board. The components on the board can be any type of component according to design requirements, such as resistors, capacitors, inductors, diodes, transistors, filters, etc.

[0084] Based on this, the determination of valid nodes from multiple nodes in the network topology diagram using the design reference data of the target board includes: identifying the endpoint whose routing position corresponds to the pin position among the multiple endpoints of multiple lines as the second endpoint, and identifying the node corresponding to the second endpoint as a second type of valid node. That is, if the endpoint coordinates of a line in the topology diagram match the pin coordinates of a component, that endpoint is marked as the second endpoint, and the node corresponding to the second endpoint is determined as a valid node. In this way, the line segments used to connect components in the board are identified, and these lines are necessarily non-redundant lines.

[0085] According to an embodiment of the present invention, the test point location of the test unit installed in the target board can be the coordinates of the test points reserved for the test unit in the board. The test unit installed in the target board can be used to perform various electrical function tests on the board, and the test points are used to connect test circuits, such as physical probe contacts, pads, or virtual test interfaces.

[0086] Based on this, valid nodes are determined from multiple nodes in the network topology diagram using the design reference data of the target board. This includes: identifying the endpoints whose deployment locations match the test point locations among the multiple endpoints of multiple lines as third endpoints, and defining the nodes corresponding to these third endpoints as third-type valid nodes. In other words, when the endpoint coordinates of a line in the network topology diagram match the coordinates of a reserved test point, the node corresponding to that endpoint is defined as a valid node. In this way, the reserved test lines in the board are identified as non-redundant lines first, avoiding misidentification as redundant lines.

[0087] According to embodiments of the present invention, the reference location for designing a custom functional unit installed in the target board can be the coordinates of the line endpoints reserved for the custom functional unit. This allows users to design custom functional units and subsequently expand the board's functionality. For example, some lines are reserved in the target board to facilitate secondary development and functional expansion by users. Examples include reserved power interfaces, analog input interfaces, communication interfaces, etc.

[0088] Based on this, valid nodes are determined from multiple nodes in the network topology diagram using the design reference data of the target board. This includes identifying the endpoint whose placement position corresponds to the reference position among multiple endpoints of multiple lines as the fourth endpoint, and defining the node corresponding to the fourth endpoint as a fourth type of valid node. In other words, it allows users to define certain specific line nodes as valid nodes, offering good versatility and portability. It can be applied to PCB designs of different types and scales, providing good flexibility and scalability. This avoids misidentifying these user-defined reserved lines as redundant lines.

[0089] It is evident that the design requirements of various scenarios were considered in advance during the line testing process, avoiding the misidentification of certain specially designed lines as redundant lines and improving the accuracy of the testing.

[0090] According to an embodiment of the present invention, in the aforementioned operation S203, among the multiple edges included in the network topology graph, edges whose connections to valid nodes meet predetermined conditions are determined to be invalid edges. Further, the connection between an invalid edge and a valid node meeting the predetermined conditions includes: neither end of the invalid edge is connected to a valid node, or only one end of the invalid edge is connected to a valid node. The following is combined with... Figure 4 , Figure 5 An example is provided to illustrate the case of invalid edges.

[0091] Figure 4 An example of a network topology diagram according to an embodiment of the present invention is shown.

[0092] like Figure 4As shown in the diagram, the network topology includes multiple nodes. Nodes A1, B1, C1, and D1 correspond to component pins and are considered valid nodes. Nodes H1 and P1 correspond to measurement points and are also considered valid nodes. Nodes E1, F1, and G1 are not considered valid nodes and are defined as invalid nodes.

[0093] Edges A1-B1, A1-C1, B1-D1, and H1-P1 are valid edges because both ends of the edges are connected to valid nodes, and the corresponding lines are lines that must be retained.

[0094] Edge D1-E1 is invalid because only one end of its path is connected to a valid node. Similarly, edges E1-F1 and F1-G1 are invalid because neither end is connected to a valid node. This situation might arise because nodes E1, F1, and G1 correspond to three pins of a component, but that component was later removed, leaving redundant wiring.

[0095] Figure 5 An example of a network topology diagram according to another embodiment of the present invention is shown.

[0096] like Figure 5 As shown in the diagram, the network topology includes multiple nodes. Nodes A2, B2, and C2 correspond to power network nodes and are valid nodes. Nodes E2 and F2 correspond to component pins and are valid nodes. Node D2 corresponds to a user-defined reserved node and is a valid node. Nodes G2, H2, and L2 are not valid nodes and are defined as invalid nodes.

[0097] Edges A2-B2, B2-F2, F2-E2, and E2-D2 are valid edges because both ends of the edges are connected to valid nodes, and the corresponding lines are lines that must be retained.

[0098] Edge E2-G2 is invalid because only one end of its path is connected to a valid node. Similarly, edge H2-L2 is invalid because neither end of its path is connected to a valid node. This situation could arise during line dismantling, where line G2-L2 is dismantled, but its connected paths E2-G2 and H2-L2 remain, resulting in redundant lines.

[0099] According to an embodiment of the present invention, the operation of determining invalid edges from a network topology graph may involve calling a predetermined graph search engine based on a predetermined graph search algorithm to traverse each node and each edge in the network topology graph, and sequentially performing the operation of determining edges whose connections to valid nodes meet predetermined conditions as invalid edges.

[0100] The predetermined graph search algorithm can be a variety of graph search algorithms, including but not limited to depth-first search (DFS) and breadth-first search (BFS).

[0101] After constructing the network topology graph and defining valid nodes, a predefined graph search algorithm is used to traverse the graph. Initialization can be performed first, for example, by creating a "visited" set to record processed nodes and edges. Then, all nodes and edges in the graph are traversed. For each unvisited node, a traversal is initiated, searching for nodes directly connected to that node. Based on whether the directly connected nodes are valid nodes, it is determined whether the edges connecting them are invalid edges.

[0102] According to an embodiment of the present invention, an invalid edge is defined as having no valid nodes connected to either end, or having only one valid node connected to either end. Based on this method, redundant lines can be identified in various scenarios, such as suspended wires, physically redundant lines, and partially disconnected signal lines. Regardless of whether the circuit is tree-like, mesh-like, or hierarchical, redundant lines can be dynamically identified through node validity. It is not dependent on specific circuit or signal rules (such as impedance matching or logic levels) and can be adapted to various scenarios such as digital / analog circuits, PCB routing, and integrated circuit design. By filtering invalid edges, the computational load of subsequent analysis is reduced, significantly improving the efficiency and reliability of circuit design and analysis.

[0103] According to an embodiment of the present invention, in order to improve the computational efficiency of the graph search engine, during the process of calling a predetermined graph search engine to traverse the network topology graph based on a predetermined graph search algorithm, the embodiment of the present invention provides a method to accelerate the computation.

[0104] Specifically, the method for determining an edge whose connection to a valid node meets predetermined conditions as an invalid edge may include the following operations.

[0105] First, the network topology graph is divided into subgraphs to obtain at least one connected subgraph. In this subgraph, multiple nodes are directly or indirectly connected, and nodes in any two connected subgraphs are not connected to each other.

[0106] Then, from at least one connected subgraph, a first type of connected subgraph that does not include valid nodes is determined, wherein the edges in the first type of connected subgraph have no valid nodes connected to either end; the edges in the first type of connected subgraph are determined to be invalid edges.

[0107] Alternatively, identify a second type of connected subgraph containing valid nodes from at least one connected subgraph; use a predetermined graph search engine to traverse multiple nodes and multiple edges in the second type of connected subgraph, and identify edges in the second type of connected subgraph that have no valid nodes at both ends, and / or edges that have only one valid node at one end as invalid edges.

[0108] As described above, the method first divides the network topology graph into subgraphs to obtain at least one connected subgraph, and then performs corresponding operations based on the characteristics of the connected subgraphs. Since the first type of connected subgraph does not contain valid nodes, all edges in the graph have no valid nodes at either end, making them all invalid edges. Therefore, for nodes and edges in this type of connected subgraph, there is no need to traverse and determine their connections to valid nodes; all edges in this type of connected subgraph can be directly identified as invalid edges. If the connected subgraph contains valid nodes, then the method described above is used to traverse all nodes and edges in the graph, and edges whose connections to valid nodes meet predetermined conditions are identified as invalid edges. Thus, for the first type of connected subgraph (without valid nodes), all edges are directly marked as invalid edges, eliminating the need for edge-by-edge checks and saving computational resources. It is evident that this embodiment of the invention optimizes the graph traversal process through subgraph partitioning and classification, reducing time complexity and improving the computational efficiency of the graph search engine.

[0109] According to an embodiment of the present invention, based on the above graph search method, a further optimized method may include the following operations.

[0110] First, in the process of subgraphing the network topology to obtain at least one connected subgraph, the specific execution method can be as follows: First, perform an initial traversal of the network topology, searching only for nodes connected to each node, without initially determining whether edges in the graph are invalid. For each unvisited node, initiate a traversal, marking all nodes connected to that node to divide the connected subgraph. During the traversal, simultaneously record the information of valid nodes contained in the connected subgraph, and mark nodes other than valid nodes as invalid nodes.

[0111] Then, from at least one connected subgraph, a first-class connected subgraph that does not contain valid nodes is determined, and without traversing the first-class connected subgraph again, the edges in the first-class connected subgraph are directly determined as invalid edges.

[0112] Alternatively, a second type of connected subgraph containing valid nodes can be identified from at least one connected subgraph, and this second type of connected subgraph can be traversed a second time. This traversal can be based on the information of invalid nodes contained in the connected subgraph output after the first traversal, traversing only the invalid nodes and identifying edges directly connected to invalid nodes as invalid edges, without needing to traverse all edges and nodes in the second type of connected subgraph one by one. Edges directly connected to invalid nodes include edges connected to invalid nodes at both ends and edges connected to invalid nodes at only one end.

[0113] Using the above method, for the first type of connected subgraph (without valid nodes), all edges are directly marked as invalid, eliminating the need for edge-by-edge checking and saving computational resources. For the second type of connected subgraph (containing valid nodes), only invalid nodes need to be traversed, avoiding redundant calculations on irrelevant subgraphs. Since, in most designs, the vast majority of lines on a PCB board are valid lines, with only a few being redundant, the number of invalid nodes is far less than the number of valid nodes. By calculating invalid nodes, the computational load is significantly reduced. Therefore, this embodiment of the invention optimizes the graph traversal process through subgraph partitioning and classification, reducing time complexity and improving the computational efficiency of the graph search engine.

[0114] Furthermore, after subgraph partitioning, different connected subgraphs can be processed in parallel (e.g., multithreading / distributed computing), further accelerating the analysis of large-scale topology graphs.

[0115] Figure 6 An example is shown of subgraph partitioning a network topology graph to obtain multiple connected subgraphs according to an embodiment of the present invention. The following is combined with... Figure 6 The above method is illustrated by example.

[0116] like Figure 6 As shown, firstly, the network topology graph is divided into subgraphs to obtain three connected subgraphs: the first connected subgraph, the second connected subgraph, and the third connected subgraph. During the traversal, the information of the valid nodes contained in the connected subgraph is recorded synchronously. At the same time, nodes other than valid nodes are marked as invalid nodes, including nodes A3, G3, P3, Q3, M3, N3, R3, and S3.

[0117] Then, the first type of connected subgraph that does not include valid nodes is identified as the second connected subgraph. Without traversing the second connected subgraph again, the edges in the second connected subgraph are directly identified as invalid edges.

[0118] Finally, a second type of connected subgraph, including valid nodes, is identified: the first connected subgraph and the second connected subgraph. A second traversal is then performed on both. Based on the information of invalid nodes in the connected subgraphs output after the first traversal, only invalid nodes are traversed. Edges directly connecting invalid nodes are identified as invalid edges, such as edges A3-B3 and F3-G3 in the first connected subgraph, and edges O3-P3 and P3-Q3 in the second connected subgraph. This allows for a rapid search for invalid edges.

[0119] According to an embodiment of the present invention, when the target board includes multiple layers, the target board includes vias, and the vias correspond to the endpoints of the lines connecting the multiple target boards; determining the edges among the multiple edges included in the network topology graph that have connections with valid nodes that meet predetermined conditions as invalid edges includes the following operations.

[0120] First, from the network topology diagram, determine multiple topology subgraphs associated with the multi-layer target boards; each layer of target boards can be associated with one topology subgraph, and the topology subgraph associated with the board only includes the nodes corresponding to the endpoints of the lines in that board.

[0121] Then, from the network topology graph, determine the cross-layer associated subgraphs related to the vias; for example, associate the endpoints of line segments directly connected by vias in different layers, merge their nodes into a graph, and form a cross-layer connected graph.

[0122] Then, among the multiple edges included in each of the multiple topological subgraphs and cross-layer associated subgraphs, edges whose connections to valid nodes meet predetermined conditions are identified as invalid edges.

[0123] Furthermore, the operation of identifying invalid edges among the multiple edges included in each of the multiple topological subgraphs and cross-layer associated subgraphs, whose connections to valid nodes meet predetermined conditions, is performed in parallel by calling multiple graph search computing units in the graph search engine.

[0124] For example, suppose there are 3 layers of boards, with connections between every two adjacent layers. The network topology of these 3 layers can be divided into 3 topological subgraphs and 2 cross-layer connection subgraphs. The invalid edges in each of these subgraphs can be determined through computation. The computations for these 5 subgraphs can then be performed in parallel using 5 graph search computation units within a graph search engine.

[0125] According to an embodiment of the present invention, in a multilayer PCB design, line segments may be connected to different layers through vias. To accurately determine whether a cross-layer line segment belongs to a valid network, the endpoints of line segments connected by vias in different layers are merged to form a cross-layer association subgraph. The cross-layer line segments and the same-layer line segments are also calculated to ensure that redundant cross-layer line segments can also be correctly identified, taking into account the situation of multilayer boards and broadening the application scenarios of the board detection method of the present invention.

[0126] Furthermore, due to the interconnectedness of circuits between multi-layer boards, the connected graph of a multi-layer board contains a large number of nodes, especially when the circuitry is complex, resulting in a very large number of nodes. This leads to a high computational cost for graph search. The method described above divides the multi-layer network topology graph, calculating each layer separately. Simultaneously, local cross-layer nodes at vias are calculated as separate subgraphs. This not only ensures that redundant cross-layer segments are correctly identified but also allows for parallel computation, improving computational efficiency.

[0127] According to an embodiment of the present invention, the deployment location includes the location information of the endpoint in the target board and the layer identification information of the target board where the endpoint is located; the multiple nodes of the network topology diagram include a first node representing a via and a second node other than the first node.

[0128] From the network topology diagram, the determination of multiple topology subgraphs associated with multi-layer target boards includes: based on layer identification information, dividing the second node of the target board located in the same layer into the same topology subgraph to obtain multiple topology subgraphs corresponding to the multi-layer target board.

[0129] Determining the cross-layer association subgraph associated with vias from the network topology graph includes: determining multiple first target nodes that are interconnected from the multiple first nodes included in the network topology graph, and determining multiple second target nodes that are directly connected to the multiple first target nodes from the multiple second nodes included in the network topology graph, and generating a cross-layer association subgraph based on the multiple first target nodes and the multiple second target nodes.

[0130] Figure 7 This illustration shows an example of multiple topological subgraphs and cross-layer related subgraphs obtained based on a network topology graph in a multi-layer board scenario according to an embodiment of the present invention. The following is combined with... Figure 7 This section explains the methods for generating topological subgraphs and cross-layer related subgraphs.

[0131] like Figure 7 As shown, the board to be tested is a two-layer board, consisting of a first board and a second board. The first board includes one via, corresponding to via node T4, and the second board includes one via, corresponding to via node X4. These two vias are connected by a trace, corresponding to edge T4-X4.

[0132] Based on the layer identifier information of the nodes, the second nodes (non-via nodes) of the target board located in the same layer are divided into the same topology subgraph, resulting in two topology subgraphs corresponding to the two-layer board: the first topology subgraph and the second topology subgraph. For example, the layer identifier information corresponding to each node in the first topology subgraph is "1"; the layer identifier information corresponding to each node in the second topology subgraph is "2"; via nodes T4 and X4 are not included in the topology subgraph and will be considered separately later.

[0133] From the multiple first nodes included in the network topology graph, identify two first target nodes that are connected to each other, such as via node T4 and via node X4 in the figure; and from the multiple second nodes included in the network topology graph, identify multiple second target nodes that are directly connected to the multiple first target nodes, such as node F4 and node Q4 in the figure; and generate a cross-layer association subgraph based on via node T4, via node X4, node F4, and node Q4.

[0134] Identify invalid edges in the first topological subgraph, the second topological subgraph, and the cross-layer association subgraph, including: edge A4-B4, edge F4-G4, edge J4-M4, edge Q4-R4, and edge Q4-S4.

[0135] For each topological subgraph, the operation of determining invalid edges from the topological subgraph refers to the method in the aforementioned embodiment. For example, edges that have no valid nodes at both ends, or edges that have only one valid node at one end, are determined to be invalid edges.

[0136] Due to the unique nature of the wiring connections at vias on multilayer boards, the operation of identifying invalid edges from the cross-layer association subgraph needs to be handled separately.

[0137] The validity of a via node can be initially left undefined. The validity of edges in a cross-layer associated subgraph can be determined based on the status of the second node directly connected to it (whether it is a valid node).

[0138] Specifically, when multiple second nodes directly connected to the via node are all valid nodes, all edges in the cross-layer association subgraph are valid edges, and invalid edges are not included in the cross-layer association subgraph.

[0139] For example, Figure 7 In the cross-layer associated subgraph, nodes T4, X4, F4, and Q4 that are directly connected to via nodes are all valid nodes. Paths passing through via nodes are designed as passable paths, and invalid edges are not included in the graph.

[0140] In cases where multiple second nodes directly connected to a via node are not all valid nodes (including invalid nodes), the specific determination needs to be made based on the actual connection relationship.

[0141] The first scenario is: if the longest node path in the cross-layer associated subgraph consists of only one path, then as long as the multiple second nodes directly connected to the via node are not all valid nodes (including invalid nodes), then all edges in the cross-layer associated subgraph are invalid edges.

[0142] Alternatively, if the longest node path in the cross-layer associated subgraph includes multiple paths, then in each longest node path, as long as the multiple second nodes directly connected to the via node are not all valid nodes (including invalid nodes), then all edges in the cross-layer associated subgraph are invalid edges.

[0143] Figure 8 Another example of a cross-layer association subgraph according to an embodiment of the present invention is shown. For example... Figure 8 In the cross-layer connection subgraph, the longest node path includes 4 nodes. If the longest node path consists of only one path: via node T4, via node X4, node F4, and node S4, then all edges in the cross-layer connection subgraph are invalid edges. Because node S4 is an invalid node, even though via nodes T4 and X4 are directly connected and node F4 is a valid node, the longest node path is not a passable path. Therefore, all edges in the path are invalid edges. This situation is exemplified by the following scenario: at a certain historical stage, two components on two boards are connected, such as a capacitor on one board and a resistor on another board connected through via nodes T4 and X4. Node F4 connects to a pin of a capacitor, and node S4 connects to a pin of a resistor. However, the resistor connected to node S4 is later removed, so the connection between the capacitor and resistor becomes redundant. However, the capacitor is still validly connected to other components, therefore node F4 remains a valid node.

[0144] Figure 9 Another example of a cross-layer associated subgraph according to an embodiment of the present invention is shown. Figure 9 In the cross-layer associated subgraph, the longest node path includes 4 nodes. Therefore, there are two longest node paths: one consisting of via node T4, via node X4, node F4, and node S4; and the other consisting of via node T4, via node X4, node S4, and node Z4. In the longest node paths, nodes S4 and Z4 are invalid nodes. Although via nodes T4 and X4 are directly connected, and node F4 is a valid node, neither of the two longest node paths is passable. Therefore, all edges in these paths are invalid.

[0145] According to an embodiment of the present invention, the second case is: when the longest node path in the cross-layer associated subgraph includes multiple paths, in which at least one of the longest node paths has multiple second nodes directly connected to the via node that are all valid nodes, the via node can be defined as a valid node, and the edge that has no valid nodes connected at both ends, or only one end of the two ends is connected to a valid node, is determined as an invalid edge.

[0146] For example, suppose that Figure 9 The cross-layer associated subgraph shown is modified. Assuming node S4 is modified to a valid node, in the longest node path consisting of via node T4, via node X4, node F4, and node S4, all the second nodes directly connected to the via nodes are valid nodes. This path is designed as a passable path, and the via nodes in the path can be defined as valid nodes. Edge T4-Z4 has only one end connected to a valid node and is therefore an invalid edge.

[0147] According to an embodiment of the present invention, due to the special nature of the wiring connections at vias on multilayer boards, the operation of determining invalid edges from the cross-layer association subgraph is processed separately using the aforementioned rules. The validity of edges in the cross-layer association subgraph is determined based on the case of a second node directly connected to the via node. This method can correctly identify redundant wiring in cross-layer connections under various circumstances, ensuring that redundant cross-layer segments can also be accurately identified.

[0148] Based on the above method for determining redundant circuits on a circuit board, this invention also provides a device for determining redundant circuits on a circuit board. The following will be combined with... Figure 10 The device is described in detail.

[0149] Figure 10 A structural block diagram of an apparatus for determining redundant circuits on a circuit board according to an embodiment of the present invention is shown.

[0150] like Figure 10 As shown, the device 1000 for determining redundant circuits on a circuit board in this embodiment includes a construction module 1001, a first determination module 1002, a second determination module 1003, and a third determination module 1004.

[0151] Module 1001 is used to construct a network topology diagram for the target board based on the deployment positions of the endpoints of the multiple lines deployed in the target board. In the network topology diagram, the nodes represent the endpoints of the lines, and the edges used to connect the nodes represent the lines.

[0152] The first determining module 1002 is used to determine the effective nodes from multiple nodes in the network topology based on the design reference data of the target board, wherein the lines between the effective nodes are designed as a path.

[0153] The second determining module 1003 is used to determine the edges in the network topology graph whose connections to valid nodes meet predetermined conditions as invalid edges.

[0154] The third determination module 1004 is used to determine the line corresponding to the invalid edge as a redundant line.

[0155] According to embodiments of the present invention, any plurality of modules among the construction module 1001, the first determining module 1002, the second determining module 1003, and the third determining module 1004 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of the present invention, at least one of the construction module 1001, the first determining module 1002, the second determining module 1003, and the third determining module 1004 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging circuitry, or implemented in hardware or firmware, or in any one of the three implementation methods of software, hardware, and firmware, or in a suitable combination of any of these. Alternatively, at least one of the construction module 1001, the first determining module 1002, the second determining module 1003, and the third determining module 1004 can be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.

[0156] Figure 11 A block diagram of an electronic device suitable for implementing a method for determining redundant circuitry on a circuit board, according to an embodiment of the present invention, is shown.

[0157] like Figure 11 As shown, an electronic device 1100 according to an embodiment of the present invention includes a processor 1101, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1102 or a program loaded from a storage portion 1108 into a random access memory (RAM) 1103. The processor 1101 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1101 may also include onboard memory for caching purposes. The processor 1101 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0158] RAM 1103 stores various programs and data required for the operation of electronic device 1100. Processor 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. Processor 1101 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 1102 and / or RAM 1103. It should be noted that the programs may also be stored in one or more memories other than ROM 1102 and RAM 1103. Processor 1101 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0159] According to an embodiment of the present invention, the electronic device 1100 may further include an input / output (I / O) interface 1105, which is also connected to the bus 1104. The electronic device 1100 may also include one or more of the following components connected to the input / output (I / O) interface 1105: an input section 1106 including a keyboard, mouse, etc.; an output section 1107 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN card, modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the input / output (I / O) interface 1105 as needed. A removable medium 1111, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 1110 as needed so that computer programs read from it can be installed into the storage section 1108 as needed.

[0160] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0161] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 1102 and / or RAM 1103 and / or one or more memories other than ROM 1102 and RAM 1103 described above.

[0162] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the methods provided in the embodiments of the present invention.

[0163] When the computer program is executed by the processor 1101, it performs the functions defined in the system / apparatus of this embodiment of the invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0164] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 1109, and / or installed from the removable medium 1111. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0165] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 1109, and / or installed from removable medium 1111. When the computer program is executed by processor 1101, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0166] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0167] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0168] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0169] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for determining redundant circuits on a circuit board, characterized in that, The method includes: Based on the placement locations of the endpoints of multiple lines deployed in the target board, a network topology diagram for the target board is constructed. In this diagram, nodes represent endpoints of lines, and edges connecting the nodes represent the lines. When the target board comprises multiple layers, it includes vias, each corresponding to an endpoint of a line connecting multiple layers of the target board. The placement location includes the position information of the endpoint within the target board and the layer identifier information of the target board where the endpoint is located. The network topology diagram includes a first node representing the via and a second node other than the first node. Based on the design reference data of the target board, valid nodes are determined from multiple nodes in the network topology, wherein the lines between the valid nodes are designed to be in a path state. Among the multiple edges included in the network topology graph, the edges whose connections to the valid nodes meet predetermined conditions are determined as invalid edges. The connection between the invalid edge and the valid node meets the predetermined conditions, including: neither end of the invalid edge is connected to the valid node, or only one end of the invalid edge is connected to the valid node. The lines corresponding to the invalid edges are identified as redundant lines. The step of determining invalid edges among the multiple edges included in the network topology graph, where the connection between the valid node and the valid node meets a predetermined condition, includes: based on the layer identification information, dividing the second nodes of the target board located in the same layer into the same topology subgraph to obtain multiple topology subgraphs corresponding to the target boards in multiple layers; determining multiple first target nodes that are connected to each other from the multiple first nodes included in the network topology graph, and determining multiple second target nodes that are directly connected to the multiple first target nodes from the multiple second nodes included in the network topology graph, and generating a cross-layer association subgraph based on the multiple first target nodes and the multiple second target nodes; and determining invalid edges among the multiple edges included in each of the multiple topology subgraphs and the cross-layer association subgraph, where the connection between the valid node and the valid node meets a predetermined condition.

2. The method according to claim 1, characterized in that, The design reference data includes at least one of the following: The signal line type information of each of the multiple lines, the pin positions of each of the multiple components designed to be installed in the target board, the test point positions of the test unit designed to be installed in the target board, and the reference positions of the custom function units designed to be installed in the target board.

3. The method according to claim 2, characterized in that, Based on the design reference data of the target board, valid nodes are determined from multiple nodes in the network topology diagram, including at least one of the following: Among the multiple endpoints of the multiple lines, the endpoint of the line belonging to a predetermined signal line type is determined as the first endpoint, and the node corresponding to the first endpoint is determined as a first type of valid node, wherein the predetermined signal line type includes power signal line or ground network signal line. Among the multiple endpoints included in the multiple lines, the endpoint whose layout position corresponds to the pin position is determined as the second endpoint, and the node corresponding to the second endpoint is determined as the second type of valid node; Among the multiple endpoints included in the multiple lines, the endpoint whose deployment location corresponds to the measurement point location is determined as the third endpoint, and the node corresponding to the third endpoint is determined as the third type of valid node; Among the multiple endpoints included in the multiple lines, the endpoint whose deployment position corresponds to the reference position is determined as the fourth endpoint, and the node corresponding to the fourth endpoint is determined as the fourth type of valid node.

4. The method according to claim 1, characterized in that, Among the multiple edges included in the network topology graph, edges whose connections to the valid nodes meet predetermined conditions are identified as invalid edges, including: The network topology is divided into subgraphs to obtain at least one connected subgraph, wherein multiple nodes in the same connected subgraph are directly or indirectly connected, and nodes in any two connected subgraphs are not connected to each other. From the at least one connected subgraph, determine a first type of connected subgraph that does not include the valid node, wherein neither end of an edge in the first type of connected subgraph is connected to the valid node; The edges in the first type of connected subgraph are determined to be invalid edges.

5. The method according to claim 4, characterized in that, The method further includes: Determine a second type of connected subgraph that includes the valid nodes from the at least one connected subgraph; Using a predefined graph search engine, traverse multiple nodes and multiple edges in the second type of connected subgraph, and determine the edges in the second type of connected subgraph that have no connection to the valid node at both ends, and / or edges that have only one end connected to the valid node, as invalid edges.

6. The method according to claim 1, characterized in that, The operation of determining invalid edges among the multiple edges included in each of the multiple topological subgraphs and the cross-layer associated subgraphs, whose connections to the valid nodes meet predetermined conditions, is performed in parallel by calling multiple graph search computing units.

7. A device for determining redundant circuits on a circuit board, characterized in that, The device includes: A construction module is used to construct a network topology diagram for the target board based on the deployment positions of the endpoints of multiple lines deployed in the target board. In the network topology diagram, nodes represent endpoints of lines, and edges connecting the nodes represent the lines. When the target board has multiple layers, it includes vias, each corresponding to an endpoint of a line connecting multiple layers of the target board. The deployment position includes the location information of the endpoint within the target board and the layer identifier information of the target board where the endpoint is located. The multiple nodes in the network topology diagram include a first node representing the via and a second node other than the first node. The first determining module is used to determine valid nodes from multiple nodes in the network topology based on the design reference data of the target board, wherein the lines between the valid nodes are designed to be in a path state; The second determining module is used to determine invalid edges among the multiple edges included in the network topology graph whose connections to the valid nodes meet predetermined conditions. The conditions for invalid edges to meet the predetermined conditions include: neither end of the invalid edge is connected to the valid node, or only one end of the invalid edge is connected to the valid node. Determining invalid edges among the multiple edges included in the network topology graph includes: based on the layer identification information, dividing the second nodes of the target boards located in the same layer into the same topology subgraph to obtain multiple topology subgraphs corresponding to the target boards in multiple layers; determining multiple first target nodes that are connected to each other from the multiple first nodes included in the network topology graph, and determining multiple second target nodes that are directly connected to the multiple first target nodes from the multiple second nodes included in the network topology graph, and generating a cross-layer association subgraph based on the multiple first target nodes and the multiple second target nodes; and determining invalid edges among the multiple edges included in each of the multiple topology subgraphs and the cross-layer association subgraph whose connections to the valid nodes meet predetermined conditions. The third determination module is used to determine the lines corresponding to invalid edges as redundant lines.

8. An electronic device, comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 6.

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