Large-scale array circuit layout processing method and device

Abstract

The invention relates to a large-scale array circuit layout processing method and device. The problems that time consumed for calculating electrical parameters of nodes one by one is too long, and the data size of generated result files is huge are solved. The method comprises the following steps: traversing to obtain a plurality of sub-graphs in an integrated circuit layout; obtaining the classification of the sub-graphs according to the electrical characteristics of the sub-graphs; and endowing all the sub-graphs under the same classification with electrical parameters corresponding to the classification. The technical scheme provided by the invention is suitable for design and detection of a large-scale integrated circuit, and circuit analysis with high efficiency and low resource consumption is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit design, and in particular to a method and device for processing a large-scale array circuit layout. Background Art

[0002] In the design of integrated circuits and display panel circuits, to ensure chip reliability, circuit characteristics and performance indicators must be verified through layout simulation before tape-out, identifying design defects in advance to optimize solutions and reduce development costs. Among them, voltage drop effect (IR Drop) analysis, as a key step in layout simulation analysis, directly affects the integrity assessment of the chip power supply network. In the IR Drop analysis process, if you want to render the IR Drop analysis result graph, you need to establish a set of voltage-current equations for all nodes and perform numerical solutions to calculate the voltage and current information of the nodes. The calculation scale is positively correlated with the density of the graphics in the layout, resulting in a significant expansion of the data volume of the analysis results as the number of nodes increases.

[0003] As process nodes shrink and design complexity increases, the density of layout patterns increases exponentially. This leads to traditional analysis methods facing the dual challenges of increased computational time and expanded result file sizes. The resulting large-scale data can not only cause computational processes to crash, but also severely impact the efficiency of subsequent data processing. Summary of the Invention

[0004] To overcome the problems existing in the related art, the present disclosure provides a large-scale array circuit layout processing method and device.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for processing a large-scale array circuit layout is provided, comprising:

[0006] Traversing and obtaining multiple sub-graphs in the integrated circuit layout;

[0007] obtaining a classification of the sub-graphic according to electrical characteristics of the sub-graphic;

[0008] All sub-graphs under the same category are assigned electrical parameters corresponding to the category.

[0009] Furthermore, the electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-pattern, and the voltage value of each internal port. The step of obtaining the classification of the sub-pattern based on the electrical characteristics of the sub-pattern includes:

[0010] generating index data of the sub-pattern according to the electrical characteristics of the sub-pattern;

[0011] Comparing the index data with an existing classification model;

[0012] When a classification model matching the index data is obtained, the sub-graph is classified into a category corresponding to the classification model.

[0013] Furthermore, the electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-pattern, and the voltage value of each internal port. The step of obtaining the classification of the sub-pattern based on the electrical characteristics of the sub-pattern includes:

[0014] Generate index data of each sub-graph according to electrical characteristics;

[0015] All sub-graphs are divided into at least one category according to the index data.

[0016] Furthermore, the index data of the sub-graph is generated in the following manner:

[0017] Obtaining the voltage value of all internal ports and each internal port in the sub-graph;

[0018] The index data of the sub-graph is calculated according to the following expression:

[0019]

[0020] Among them, V k-1 is the voltage difference between the Kth internal port and the first internal port; ε is the preset matching error coefficient, which also represents the decimal error.

[0021] Furthermore, after the step of comparing the index data with the existing classification model, the method further includes:

[0022] In the case that a classification model matching the index data cannot be obtained, a new classification is created, and the index data is used as the classification model of the new classification.

[0023] Furthermore, the step of assigning electrical parameters corresponding to the category to all sub-graphics under the same category includes:

[0024] The electrical parameters calculated according to the classification model are assigned to the sub-graphs classified into the classification.

[0025] Furthermore, the step of assigning electrical parameters corresponding to the category to all sub-graphics under the same category includes:

[0026] Each category is processed as follows:

[0027] A sub-graph in a category is selected, electrical parameters of the sub-graph are calculated, and the electrical parameters are assigned to all other sub-graphs in the same category.

[0028] According to a second aspect of an embodiment of the present disclosure, there is provided a large-scale array circuit layout processing apparatus, comprising:

[0029] A layout parsing module, used to traverse and obtain multiple sub-graphs in the integrated circuit layout;

[0030] a classification module, configured to obtain a classification of the sub-pattern according to electrical characteristics of the sub-pattern;

[0031] The merging calculation module is used to assign electrical parameters corresponding to the category to all sub-graphs under the same category.

[0032] Furthermore, the electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-graph, the voltage value of each internal port, and the classification module includes:

[0033] A first index generating submodule, configured to generate index data of the sub-pattern according to electrical characteristics of the sub-pattern;

[0034] A first comparison submodule, configured to compare the index data with an existing classification model;

[0035] A first classification submodule is configured to classify the sub-graphic into a category corresponding to a classification model when a classification model matching the index data is obtained;

[0036] A second index generation submodule is used to generate index data of each sub-graph according to electrical characteristics;

[0037] The second classification submodule is configured to classify all sub-graphs into at least one category according to the index data.

[0038] Furthermore, the merging calculation module includes:

[0039] a model assignment submodule, configured to assign electrical parameters calculated according to the classification model to sub-graphs classified into the classification;

[0040] The classification assignment submodule is used to perform the following processing on each classification:

[0041] A sub-graph in a category is selected, electrical parameters of the sub-graph are calculated, and the electrical parameters are assigned to all other sub-graphs in the same category.

[0042] The technical solutions provided by the embodiments of the present disclosure may have the following beneficial effects:

[0043] The system traverses and obtains multiple sub-graphs within the integrated circuit layout. Based on their electrical characteristics, the sub-graphs are then classified and assigned electrical parameters corresponding to the classification. After classifying the sub-graphs based on their electrical characteristics, electrical parameter calculations are performed on these sub-graphs in batches, improving computational efficiency and avoiding the time-consuming and voluminous result file generation associated with calculating electrical parameters node by node. This enables highly efficient and resource-efficient circuit analysis.

[0044] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0046] Figure 1 The figure is a flow chart of a method for processing a large-scale array circuit layout according to an exemplary embodiment.

[0047] Figure 2 FIG. 1 is a schematic diagram of an example partitioning according to an exemplary embodiment.

[0048] Figure 3 The figure is a schematic diagram showing a sub-graph division method according to an exemplary embodiment.

[0049] Figure 4 The flowchart of another large-scale array circuit layout processing method is shown according to an exemplary embodiment.

[0050] Figure 5 The flowchart of another large-scale array circuit layout processing method is shown according to an exemplary embodiment.

[0051] Figure 6 The flowchart of another large-scale array circuit layout processing method is shown according to an exemplary embodiment.

[0052] Figure 7 It is a block diagram of another large-scale array circuit layout processing device according to an exemplary embodiment.

[0053] Figure 8 is a schematic structural diagram of the classification module 702 according to an exemplary embodiment.

[0054] Figure 9 FIG. 7 is a structural diagram of the merging calculation module 703 according to an exemplary embodiment.

[0055] Figure 10is a block diagram of a computer device according to an exemplary embodiment.

[0056] In the picture:

[0057] 100 - computer device; 1001 - computing unit; 1002 - ROM; 1003 - RAM; 1004 - bus; 1005 - input / output interface; 1006 - input unit; 1007 - output unit; 1008 - storage unit; 1009 - communication unit. DETAILED DESCRIPTION

[0058] As process nodes shrink and design complexity increases, the density of layout patterns increases exponentially. This leads to traditional analysis methods facing the dual challenges of increased computational time and expanded result file sizes. The resulting large-scale data can not only cause computational processes to crash, but also severely impact the efficiency of subsequent data processing.

[0059] To address the above-mentioned issues, embodiments of the present disclosure provide a method and apparatus for processing a large-scale array circuit layout. Exemplary embodiments will be described in detail herein, with examples shown in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0060] An exemplary embodiment of the present disclosure provides a large-scale array circuit layout processing method, which is used to process the large-scale array circuit layout to complete the IR Drop analysis process. Figure 1 Shown, including:

[0061] Step 101: traverse and obtain multiple sub-graphs in the integrated circuit layout.

[0062] The input of this step is the display panel layout graphics after being broken up and separated, which mainly includes geometric graphics.

[0063] like Figure 2 As shown in , the integrated circuit layout includes multiple cells, and each cell corresponds to an instance. Figure 3 As shown, each instance may contain one or more sub-graphs, each of which stores multiple process layers, and each layer needs to obtain information such as current and voltage.

[0064] Input the broken-down display panel layout graphic, then traverse the instances connected to VDD and / or VSS in sequence to obtain all sub-graphs. Furthermore, during each traversal, the solver calculates the internal port voltages of the sub-graphs within each instance based on the external port voltages of the instance.

[0065] According to an exemplary embodiment, the sub-graph includes at least one input port and at least one output port.

[0066] The sub-pattern division method can be customized based on actual application requirements. For example, an integrated circuit layout, typically a large rectangle, can be composed of six smaller square areas arranged in three rows and two columns. Each small square area is defined as a cell or instance, which contains one or more sub-patterns. Identical sub-patterns have the same or similar resistance and, therefore, the same electrical parameters such as current and voltage.

[0067] Step 102: Obtain the classification of the sub-pattern according to the electrical characteristics of the sub-pattern.

[0068] According to an exemplary embodiment, the electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-pattern, and the voltage value of each internal port.

[0069] In this step, the electrical characteristics of each sub-pattern are obtained, and the sub-patterns are classified based on the electrical characteristics.

[0070] Multiple sub-graphs with the same electrical characteristics are grouped into one category. For example, two or more sub-graphs with five internal ports and the same voltage value or voltage value within a preset range are grouped into one category.

[0071] Step 103: assign electrical parameters corresponding to the category to all sub-graphs in the same category.

[0072] According to an exemplary embodiment, the electrical parameters include at least one or more of the following information:

[0073] Voltage information of nodes within the subgraph, current information of nodes within the subgraph, and output power.

[0074] The voltage information may include the value of the output voltage, and the current information may include the value and direction of the output current.

[0075] In this step, electrical parameters are calculated only once for each category. The corresponding electrical parameters are then assigned to all sub-graphics within that category. Batch processing of sub-graphics with the same electrical characteristics avoids the time-consuming problem of calculating each one individually.

[0076] According to an exemplary embodiment, after obtaining electrical parameters for each sub-graph, the electrical parameters can be stored as a result file for subsequent data analysis and processing, such as IR Drop analysis. When storing the electrical parameters, the instance identifier (ID) corresponding to the sub-graph can also be stored.

[0077] An exemplary embodiment of the present disclosure also provides a large-scale array circuit layout processing method, which uses the method to generate sub-graphic index data based on electrical characteristics, as a classification basis process as shown below: Figure 4 Shown, including:

[0078] Step 401: Obtain the voltage value of all internal ports and each internal port in the sub-graph.

[0079] In this step, since the sub-graph may have multiple internal ports, it is necessary to obtain the voltage value of all internal ports and each internal port.

[0080] According to an exemplary embodiment, the sub-graph has N internal ports: a first internal port, a second internal port, ..., an Nth internal port. The N internal ports and their corresponding voltage values ​​are stored. For ease of management and subsequent calculations, the N ports may be numbered. The stored internal port voltages are the first internal port voltage value V1, the second internal port voltage value V2, ..., the Nth internal port voltage value V N .

[0081] Step 402: Calculate the index data of the sub-graph.

[0082] In this step, the index data of the sub-graph is calculated according to the following expression:

[0083]

[0084] Among them, V k-1 is the voltage difference between the Kth internal port and the first internal port, and ε is a preset matching error coefficient.

[0085] According to an exemplary embodiment, a classification model is established for each classification. For example, the index data is used as a key index array, and the corresponding pattern is matched based on the key to complete the classification.

[0086] The steps of converting the internal port voltage of the sub-graph into the keys index array include: recording the voltage value of the first internal port, and subtracting the voltage value of the first port from the voltage of the other internal ports in sequence to obtain a set of double type voltage difference values ​​[V 1-1 , V 2-1 , V 3-1 ,……,VN-1 In order to increase the flexibility of result reduction, the voltage difference values ​​obtained above are multiplied by the inverse of the matching error 1 / ε, and all the voltage differences are converted into long int type to obtain

[0087] The smaller the matching error coefficient ε, the larger the value of keys will be, the less data will be lost, the more refined the matching will be, and the corresponding final result file data volume will be larger; the larger the matching error coefficient ε, the smaller the value of keys will be, the more data will be lost, the coarser the matching will be, and the resulting result file data volume will be reduced.

[0088] By indexing data, a data basis is provided for subsequent classification and batch electrical parameter calculation, effectively improving the efficiency of IR Drop analysis.

[0089] An exemplary embodiment of the present disclosure also provides a large-scale array circuit layout processing method, which generates index data based on electrical characteristics and completes the process of sub-graphic classification. Figure 5 Shown, including:

[0090] Step 501: Generate index data of the sub-pattern according to the electrical characteristics of the sub-pattern.

[0091] In this step, index data is generated based on the electrical characteristics. The classification can be performed after index data is generated for all sub-patterns in sequence, or the classification of the next sub-pattern can be processed after index data is generated and classified for a certain sub-pattern.

[0092] Step 502: Compare the index data with the existing classification model.

[0093] In this step, when one or more classifications already exist, the index data of the sub-graph to be classified is compared with the classification models of the existing classifications.

[0094] According to an exemplary embodiment, the keys index array is used as index data, the first sub-graph in each category is used as the classification model (pattern) of the corresponding category, and the keys is used as one of the pattern indexes to match other possible identical sub-graphs.

[0095] Step 503: When a classification model matching the index data is obtained, classify the sub-graph into a category corresponding to the classification model.

[0096] In this step, if there is a matching result, it means that the sub-graph to be classified can be classified into the matching classification.

[0097] According to one exemplary embodiment, the keys index array is used as index data, the first sub-graph in each category is used as the pattern for that category, and the keys are used as one of the pattern indices to match other potentially identical sub-graphs. For each category's pattern, electrical parameters, such as internal node current and voltage information, are calculated after the pattern is set as the pattern.

[0098] Compare the keys of the subgraph to be classified with the existing pattern. If a match is successful, skip the next step of backcalculation and directly store the instance ID, subgraph ID, and voltage value of the first internal port corresponding to the pattern. The current, voltage, and other information of the internal nodes are basically consistent with the pattern.

[0099] When subsequently reading the result file for analysis such as IR Drop, the current and voltage information of the corresponding pattern internal nodes can be directly used. According to one exemplary embodiment, internal nodes refer to nodes obtained through triangulation, that is, nodes within the subgraph. The voltages of each internal port in the result file are recovered based on the data in the keys. Since the keys are generated by subtracting the first internal port voltage from the voltage of each internal port, the voltages of each internal port can be recovered based on the keys when the first port voltage is determined.

[0100] Step 504: If a classification model matching the index data cannot be obtained, a new classification is created, and the index data is used as a classification model for the new classification.

[0101] According to an exemplary embodiment, the keys index array is used as index data, the first sub-graph in each category is used as the pattern of the corresponding category, and the keys is used as one of the pattern indexes to match other possible identical sub-graphs.

[0102] For sub-graphs that fail to match, it is considered that there is currently no classification for this sub-graph, so the sub-graph is calculated and stored, and a new classification and corresponding pattern are established. The index data of the sub-graph is calculated, and the keys of the pattern are constructed based on the index data to retrieve whether the subsequent unclassified sub-graphs match the pattern. The matching error coefficient can be flexibly set according to application requirements, application environment software and hardware resource limitations, etc., and the accuracy of the matching can be adjusted by changing the matching error coefficient. Then, the solver is used to calculate the current size, direction, voltage size, power and other information on the grid in the triangulation and store them as electrical parameters of the pattern. Record the keys and the Instance ID, sub-graph ID and voltage value of the first internal port corresponding to the current keys to construct a new pattern.

[0103] After completing the classification in step 503, the electrical parameters calculated according to the classification model can be assigned to the sub-graphs classified into that category. Although the index data of each sub-graph within the same category may be identical, in some cases, the internal port voltages of one sub-graph are not exactly the same as those of another sub-graph within the same category, and may have an offset. Because each internal port voltage is restored by adding the corresponding element in the keys to the first internal port voltage value, this offset is caused by the different voltage values ​​of the first internal port of each sub-graph. However, since the keys are the same, the electrical parameters of each sub-graph, such as current magnitude, current direction, and power information, are consistent with the matched pattern.

[0104] According to an exemplary embodiment, the result file data is stored in a triangulated grid for subsequent use in IR Drop and other analyses.

[0105] According to an exemplary embodiment, successfully matched sub-graphs are stored, and their electrical parameters are consistent with the matched pattern. If a pattern is matched using a combination of keys, Instance ID, and sub-graph ID, the voltage value of the sub-graph's internal port can be obtained by combining the voltage of the first internal port with the index keys. Furthermore, rather than using a solver to calculate electrical parameters such as current and voltage on the triangulated mesh, the electrical parameters corresponding to the pattern are directly used. Because the sub-graphs are essentially identical, the resistance values ​​calculated by triangulation are also identical. If the input voltages are also the same, the resulting current and voltage information for the triangulated mesh is naturally identical. Therefore, only the current, voltage, and other electrical parameters need to be calculated for one sub-graph (i.e., one pattern). Finally, the Instance ID, sub-graph ID, and voltage value of the first port corresponding to the pattern are stored. After traversing all sub-graphs, the matching relationships can be used to obtain information on the electrical parameters of all sub-graphs, such as output voltage, output current, and output power. All matching relationships are obtained, the electrical parameters are stored in the mesh, and the results are output for IR drop analysis. If the pattern does not match, the electrical parameters of the sub-graph to be classified are updated to the graph triangulation grid. If the pattern matches, the current and voltage information of the pattern are updated to the graph triangulation grid. Finally, this information is stored in the actual routing.

[0106] By repeating the above steps, all matching information is obtained, and the electrical parameters such as output voltage, output current, and output power corresponding to each sub-graph are obtained to perform IR Drop analysis of the circuit.

[0107] An exemplary embodiment of the present disclosure also provides a large-scale array circuit layout processing method, which classifies the sub-graphs after calculating and obtaining the index data, and determines the electrical parameters of each classification through only one operation, thus saving computing resources. Figure 6 Shown, including:

[0108] Step 601: Generate index data of each sub-graph according to electrical characteristics.

[0109] The electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-graph, and the voltage value of each internal port.

[0110] In this step, after all sub-patterns of the integrated circuit layout are traversed and obtained, index data of each sub-pattern is generated according to its electrical characteristics.

[0111] Step 602: Divide all sub-graphs into at least one category according to the index data.

[0112] In this step, the sub-graphs are classified according to the index data. Multiple sub-graphs with the same electrical characteristics are grouped into the same category to prepare the data foundation for subsequent batch processing.

[0113] Step 603: Calculate the electrical parameters of each category.

[0114] In this step, each category is processed as follows:

[0115] A sub-graph in a category is selected, electrical parameters of the sub-graph are calculated, and the electrical parameters are assigned to all other sub-graphs in the same category.

[0116] According to an exemplary embodiment, the electrical parameters include at least one or more of the following information:

[0117] Voltage information of nodes within the subgraph, current information of nodes within the subgraph, and output power.

[0118] The voltage information may include the value of the output voltage, and the current information may include the value and direction of the output current.

[0119] After calculating and obtaining the electrical parameters of each category, the electrical parameters are assigned to all other sub-graphs in the same category. According to an exemplary embodiment, the result file data is stored in the triangulation grid for subsequent analysis such as IR Drop.

[0120] An exemplary embodiment of the present disclosure also provides a method for processing a large-scale array circuit layout. A sub-graph A included in the integrated circuit layout has three internal ports with voltages of 1V, 1.258468214V, and 1.5766842135V, respectively. The matching error coefficient ε is 0.001. The keys for this sub-graph are [0, 258, 576], which is an array. The specific contents of the keys vary depending on the matching error coefficient ε.

[0121] The keys are used to determine if a matching pattern exists. If no matching pattern exists, the keys array, along with the instance ID, subgraph type ID, and first internal port voltage, are stored as a new pattern. The instance ID is 5, the subgraph ID is 2, and the first internal port voltage is 1V. A solver is then used to determine the current, voltage, and other electrical parameters for this pattern. The remaining subgraphs in the integrated circuit layout are then traversed. If a subgraph B with keys matching the existing pattern is found, and the instance ID and subgraph type ID corresponding to the key of subgraph B are the same as the pattern, then subgraph B has matched the pattern. The instance ID, subgraph type ID, and first port voltage of subgraph B are stored as the matching relationship. The internal port voltage value can be calculated and recovered using the keys and the voltage of the first internal port of subgraph B (for example, reading the elements in the keys and adding the voltage of the first internal port yields the corresponding internal port voltage), thereby obtaining electrical parameters such as current and voltage information. If the matching error coefficient is large, the resulting electrical parameters will have significant errors. After all sub-patterns are traversed, information such as current and voltage corresponding to each pattern can be stored in VDD or VSS.

[0122] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

[0123] An exemplary embodiment of the present disclosure further provides a large-scale array circuit layout processing device, the structure of which is as follows: Figure 7 As shown, the device includes:

[0124] A layout parsing module 701 is used to traverse and obtain multiple sub-graphs in the integrated circuit layout;

[0125] A classification module 702, configured to obtain a classification of the sub-pattern according to the electrical characteristics of the sub-pattern;

[0126] The merging calculation module 703 is used to assign electrical parameters corresponding to the category to all sub-graphs in the same category.

[0127] Furthermore, the electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-graph, the voltage value of each internal port, and the structure of the classification module 702 is as follows: Figure 8 Shown, including:

[0128] A first index generating submodule 801 is configured to generate index data of the sub-pattern according to electrical characteristics of the sub-pattern;

[0129] A first comparison submodule 802 is used to compare the index data with an existing classification model;

[0130] A first classification submodule 803 is configured to classify the sub-graph into a category corresponding to a classification model when a classification model matching the index data is obtained;

[0131] The second index generating submodule 804 is used to generate index data of each sub-pattern according to the electrical characteristics;

[0132] The second classification submodule 805 is configured to classify all sub-graphs into at least one category according to the index data.

[0133] Furthermore, the first classification submodule 805 is further configured to create a new classification when a classification model matching the index data cannot be obtained, and use the index data as a classification model for the newly created classification.

[0134] Furthermore, the structure of the merging calculation module 703 is as follows: Figure 9 Shown, including:

[0135] The model assignment submodule 901 is used to assign the electrical parameters calculated according to the classification model to the sub-graphs classified into the classification;

[0136] The classification assignment submodule 902 is used to perform the following processing on each classification:

[0137] A sub-graph in a category is selected, electrical parameters of the sub-graph are calculated, and the electrical parameters are assigned to all other sub-graphs in the same category.

[0138] Furthermore, the first index generation submodule 801 is specifically configured to obtain the voltage values ​​of all internal ports and each internal port in the sub-graph, and calculate the index data of the sub-graph according to the following expression:

[0139]

[0140] Among them, V k-1 is the voltage difference between the Kth internal port and the first internal port, and ε is a preset matching error coefficient.

[0141] The second index generation submodule 804 is specifically configured to obtain the voltage values ​​of all internal ports and each internal port in the sub-graph, and calculate the index data of the sub-graph according to the following expression:

[0142]

[0143] Among them, V k-1 is the voltage difference between the Kth internal port and the first internal port, and ε is a preset matching error coefficient.

[0144] Each module in the above-mentioned apparatus may be implemented in whole or in part by software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor in a computer device in the form of hardware, or may be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0145] In an exemplary embodiment, a computer device is provided, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, any of the above-mentioned large-scale array circuit layout processing methods is implemented.

[0146] In one exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When executed by a processor, the computer program implements any of the aforementioned large-scale array circuit layout processing methods. The computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, or optical data storage device.

[0147] In an exemplary embodiment, a computer program product is provided, including a computer program, which implements any of the above-mentioned large-scale array circuit layout processing methods when executed by a processor.

[0148] refer to Figure 10 The following describes a block diagram of a computer device that can serve as the large-scale array circuit layout processing apparatus of the present disclosure. The computer device includes a computing unit 1001, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a random access memory (RAM) 103. Various programs and data required for the operation of the computer device 100 may also be stored in the RAM 1003. The computing unit 1001, the ROM 1002, and the RAM 103 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0149] Multiple components in the computer device 100 are connected to the I / O interface 1005, including: an input unit 1006, an output unit 1007, a storage unit 1008, and a communication unit 1009. The input unit 1006 can be any type of device that can input information to the computer device 100. The input unit 1006 can receive input digital or character information and generate key signal input related to user settings and / or function control of the computer device 100, and can include but is not limited to a mouse, a keyboard, a touch screen, a trackpad, a trackball, a joystick, a microphone, and / or a remote control. The output unit 1007 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 1008 can include but is not limited to a magnetic disk and an optical disk. The communication unit 1009 allows the computer device 100 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and may include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver and / or a chipset, such as a Bluetooth™ device, a WiFi device, a WiMax device, a cellular communication device and / or the like.

[0150] The computing unit 1001 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1001 performs the various methods and processes described above, such as a large-scale array circuit layout processing method. For example, in some embodiments, the large-scale array circuit layout processing method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 1008. In some embodiments, part or all of the computer program can be loaded and / or installed on the computer device 100 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into the RAM 1003 and executed by the computing unit 1001, one or more steps of the large-scale array circuit layout processing method described above can be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to execute the large-scale array circuit layout processing method in any other appropriate manner (for example, by means of firmware).

[0151] The computer device 100 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to execute the above-mentioned large-scale array circuit layout processing method.

[0152] The disclosed embodiments provide a large-scale array circuit layout processing method and apparatus. This method traverses and obtains multiple sub-graphs within an integrated circuit layout, then categorizes the sub-graphs based on their electrical characteristics, assigning electrical parameters corresponding to the classification to all sub-graphs within the same category. After categorizing the sub-graphs based on their electrical characteristics, electrical parameters are calculated for these sub-graphs in batches, improving computational efficiency and avoiding the time-consuming and voluminous result file generation associated with calculating electrical parameters for each sub-graph. This method enables highly efficient and resource-efficient circuit analysis.

[0153] By traversing all graphs within the same net, the internal port voltage of each sub-graph is calculated, and the voltage nodes are used as index keys to match the voltage, current, and other electrical parameters of other graphs. This means that only the voltage and current results of one sub-graph within the same graph in the layout array are calculated. For other sub-graphs, provided that the index data remains the same, the electrical parameters of the existing nodes are used, thus reducing the result file size and the calculation time.

[0154] Before matching graphics in an IC layout, analysis operations like IR Drop require node-by-node solver calculations. Large IC layouts with a large number of graphics significantly increase the number of nodes, leading to longer graphics calculation times. Simultaneously storing voltage and current information for all graphics creates result files that consume significant memory.

[0155] By segmenting and identifying sub-patterns within the integrated circuit layout, multiple identical sub-patterns are identified and the electrical parameters of only one of these sub-patterns are calculated and stored. For the remaining identical sub-patterns, the calculated electrical parameters are directly assigned, provided that the accuracy error and input voltage remain the same. This avoids repeated calculations of the same result data, thus reducing the result file size and computation time.

[0156] Those skilled in the art will appreciate that all or part of the steps in the above method can be performed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps in the above embodiment can be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or software functional modules. The present invention is not limited to any specific combination of hardware and software.

[0157] Other embodiments of the present invention will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

[0158] It should be understood that the present invention is not limited to the exact construction described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A large-scale array circuit layout processing method, characterized in that: include: Traversing and obtaining multiple sub-graphs in the integrated circuit layout; obtaining a classification of the sub-graphic according to electrical characteristics of the sub-graphic; All sub-graphs under the same category are assigned electrical parameters corresponding to the category.

2. The large-scale array circuit layout processing method according to claim 1, characterized in that: The electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-pattern, and the voltage value of each internal port. The step of obtaining the classification of the sub-pattern based on the electrical characteristics of the sub-pattern includes: generating index data of the sub-pattern according to the electrical characteristics of the sub-pattern; Comparing the index data with an existing classification model; When a classification model matching the index data is obtained, the sub-graph is classified into a category corresponding to the classification model.

3. The large-scale array circuit layout processing method according to claim 1, characterized in that: The electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-pattern, and the voltage value of each internal port. The step of obtaining the classification of the sub-pattern based on the electrical characteristics of the sub-pattern includes: Generate index data of each sub-graph according to electrical characteristics; All sub-graphs are divided into at least one category according to the index data.

4. The large-scale array circuit layout processing method according to claim 2 or 3, characterized in that: The index data of the sub-graph is generated by: Obtaining the voltage value of all internal ports and each internal port in the sub-graph; The index data of the sub-graph is calculated according to the following expression: Among them, V k-1 is the voltage difference between the Kth internal port and the first internal port, and ε is a preset matching error coefficient.

5. The large-scale array circuit layout processing method according to claim 2, characterized in that: After the step of comparing the index data with the existing classification model, the method further includes: In the case that a classification model matching the index data cannot be obtained, a new classification is created, and the index data is used as the classification model of the new classification.

6. The large-scale array circuit layout processing method according to claim 2, characterized in that: The step of assigning electrical parameters corresponding to the category to all sub-graphs under the same category includes: The electrical parameters calculated according to the classification model are assigned to the sub-graphs classified into the classification.

7. The large-scale array circuit layout processing method according to claim 2, characterized in that: The step of assigning electrical parameters corresponding to the category to all sub-graphs under the same category includes: Each category is processed as follows: A sub-graph in a category is selected, electrical parameters of the sub-graph are calculated, and the electrical parameters are assigned to all other sub-graphs in the same category.

8. A large-scale array circuit layout processing device, characterized in that: The device comprises: A layout parsing module, used to traverse and obtain multiple sub-graphs in the integrated circuit layout; a classification module, configured to obtain a classification of the sub-pattern according to electrical characteristics of the sub-pattern; The merging calculation module is used to assign electrical parameters corresponding to the category to all sub-graphs under the same category.

9. The large-scale array circuit layout processing device according to claim 8, characterized in that: The electrical characteristics include at least one or more of the following parameters: the number of internal ports in the sub-graph, and the voltage value of each internal port. The classification module includes: A first index generating submodule, configured to generate index data of the sub-pattern according to electrical characteristics of the sub-pattern; A first comparison submodule, configured to compare the index data with an existing classification model; A first classification submodule is configured to classify the sub-graphic into a category corresponding to a classification model when a classification model matching the index data is obtained; A second index generation submodule is used to generate index data of each sub-graph according to electrical characteristics; The second classification submodule is configured to classify all sub-graphs into at least one category according to the index data.

10. The large-scale array circuit layout processing device according to claim 9, characterized in that: The combined calculation module includes: a model assignment submodule, configured to assign electrical parameters calculated according to the classification model to sub-graphs classified into the classification; The classification assignment submodule is used to perform the following processing on each classification: A sub-graph in a category is selected, electrical parameters of the sub-graph are calculated, and the electrical parameters are assigned to all other sub-graphs in the same category.

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