ZVS control circuit and control method of resonant flyback power converter

Abstract

The invention relates to a ZVS control circuit and a control method of a resonant flyback power converter. A control circuit for a resonant flyback power converter includes upper and lower bridge signals controlling upper and lower bridge transistors. The circuit utilizes a negative current signal from the auxiliary winding related to its cross voltage. The circuit generates a threshold value and a sensing signal according to turn-on and turn-off of the upper bridge transistor and the lower bridge transistor, and generates a trigger signal by comparing the sensing signal with the threshold value. The upper bridge transistor and the lower bridge transistor switch the primary side winding through the resonant capacitor and generate an output voltage through the secondary side winding. The pulse width of the lower bridge signal is adjusted according to the trigger signal so as to realize zero-voltage switching of the upper bridge transistor.

Description

Technical Field

[0001] The present invention relates to a zero voltage switching (ZVS) control circuit, and more particularly to a ZVS control circuit for controlling a resonant flyback power converter. The present invention also relates to a control method for controlling the resonant flyback power converter. Background Art

[0002] A resonant flyback power converter is a highly efficient power converter. Its wide output voltage capability makes it an advantage in USB Type-C power supplies and power adapters, and is particularly suitable for USB PD EPR (Extended Power Range) converters. Recent energy conservation regulations require power converters to operate at high efficiency under heavy load conditions while maintaining high efficiency even under light load conditions.

[0003] The high efficiency performance of resonant flyback power converters is attributed to their resonant and zero-voltage switching operation. However, conventional resonant flyback power converters typically incur high power losses in achieving ZVS, making it difficult to save power during light-load operation.

[0004] In view of the above problems, in order to overcome the shortcomings of the prior art, the present invention provides a control method and a control circuit, aiming to solve this problem and achieve high-efficiency ZVS operation under heavy load and light load conditions. Summary of the Invention

[0005] From one perspective, the present invention provides a control circuit for controlling a resonant flyback power converter, comprising: an upper bridge signal for controlling an upper bridge transistor; a lower bridge signal for controlling a lower bridge transistor; a negative current signal generated by an auxiliary winding of a transformer, wherein the negative current signal is related to the voltage across the auxiliary winding; a first signal generated by the negative current signal when the upper bridge transistor is turned on; a second signal generated by the negative current signal when the lower bridge transistor is turned off, at which time the upper bridge transistor is in an off state; and a third signal generated by comparing the second signal with a voltage threshold, wherein the voltage threshold is related to the level of the first signal; the upper bridge transistor and the lower bridge transistor are used to switch a primary winding of the transformer through a resonant capacitor, thereby generating an output voltage through a secondary winding of the transformer; a pulse width of the lower bridge signal is adjusted according to the third signal to achieve zero voltage switching of the upper bridge transistor.

[0006] In a preferred embodiment, after the level of the second signal exceeds the voltage threshold, the upper bridge signal passes through a level shift buffer to turn on the upper bridge transistor.

[0007] In a preferred embodiment, the control circuit further includes a sampling and holding circuit for generating the first signal by sampling a current-to-voltage signal; wherein the current-to-voltage signal is generated by the negative current signal; wherein the level of the first signal is related to the input voltage level of the transformer.

[0008] In a preferred embodiment, the control circuit further includes an up-down counter for adjusting the pulse width of the lower bridge signal according to the first signal and the second signal.

[0009] In a preferred embodiment, the control circuit is further configured to adjust a shutdown period to be equal to a predetermined target period by adjusting the pulse width of the lower bridge signal; wherein the shutdown period is a duration from the disabling of the lower bridge signal to the subsequent enabling of the upper bridge signal.

[0010] In a preferred embodiment, the control circuit further includes a period reference signal generated based on the predetermined target period, and an off-period signal generated based on the off-period; wherein the level of the off-period signal is adjusted by adjusting the pulse width of the lower bridge signal to align with the level of the period reference signal, thereby aligning the off-period with the predetermined target period.

[0011] In a preferred embodiment, when the off period is determined to be longer than the predetermined target period, the pulse width of the lower bridge signal is increased; and when the off period is determined to be shorter than the predetermined target period, the pulse width of the lower bridge signal is reduced.

[0012] In a preferred embodiment, the voltage threshold includes an upper threshold and a lower threshold; wherein the off period is adjusted only when the second signal is between the upper threshold and the lower threshold.

[0013] In a preferred embodiment, the predetermined target period is associated with an optimal circulating current generated by the low-bridge transistor so that the voltage across the high-bridge transistor remains low enough to achieve zero voltage switching while the circulating current remains at a low enough level to achieve a target conversion efficiency.

[0014] In a preferred embodiment, the control circuit further includes a maximum off-period signal to limit the off-period to not exceed a corresponding maximum off-period.

[0015] In a preferred embodiment, an enabling period of the low-bridge signal is equal to or longer than the demagnetization time of the transformer.

[0016] In a preferred embodiment, the control circuit further includes a volt-second circuit for generating the low-bridge signal according to an enable period of the high-bridge signal, a level of the input voltage of the transformer, and a level of the output voltage of a power converter.

[0017] In a preferred embodiment, the conduction of the lower bridge transistor causes the transformer to be demagnetized to generate a circulating current, which is used to achieve zero voltage switching of the upper bridge transistor and is composed of the negative excitation current of the transformer.

[0018] In a preferred embodiment, when the level of the second signal is lower than the voltage threshold, the pulse width of the lower bridge signal is increased; wherein when the level of the second signal is higher than the voltage threshold, the pulse width of the lower bridge signal is reduced.

[0019] In a preferred embodiment, the voltage threshold includes an upper threshold and a lower threshold, and the upper threshold is higher than the lower threshold; when the level of the second signal is lower than the lower threshold, the pulse width of the lower bridge signal is increased; when the level of the second signal is higher than the upper threshold, the pulse width of the lower bridge signal is reduced.

[0020] In a preferred embodiment, the control circuit further includes a delay circuit, which is used to provide a delay time after the level of the second signal exceeds the voltage threshold before turning on the upper bridge transistor through a level shift buffer.

[0021] From another point of view, the present invention provides a control circuit for controlling a resonant flyback power converter, comprising: an upper bridge signal for controlling an upper bridge transistor; and a lower bridge signal for controlling a lower bridge transistor; the upper bridge transistor and the lower bridge transistor switch the primary winding of the transformer through a resonant capacitor, thereby generating an output voltage through the secondary winding of the transformer; wherein by adjusting the pulse width of the lower bridge signal, a turn-off period is adjusted to be equal to a predetermined target period to achieve zero voltage switching of the upper bridge transistor; wherein the turn-off period is the duration from the disabling of the lower bridge signal to the subsequent enabling of the upper bridge signal.

[0022] In a preferred embodiment, the control circuit further includes a period reference signal generated based on the predetermined target period; a turn-off period signal generated based on the turn-off period; and wherein the level of the turn-off period signal is adjusted by adjusting the pulse width of the lower bridge signal to align with the level of the period reference signal, thereby aligning the turn-off period with the predetermined target period.

[0023] From one viewpoint, the present invention provides a control method for controlling a resonant flyback power converter, comprising: generating an upper bridge signal for controlling an upper bridge transistor; generating a lower bridge signal for controlling a lower bridge transistor; generating a negative current signal related to the voltage on an auxiliary winding of a transformer; generating a threshold generated by the negative current signal, the negative current signal being responsive to the conduction of the upper bridge transistor; enabling the upper bridge signal when the negative current signal exceeds the threshold after the lower bridge transistor is turned off; switching the primary winding of the transformer through a resonant capacitor with the upper bridge transistor and the lower bridge transistor, thereby generating an output voltage through the secondary winding of the transformer; and adjusting the pulse width of the lower bridge signal based on a comparison between the negative current signal and the threshold, so as to achieve zero voltage switching by subsequently turning on the upper bridge transistor.

[0024] In a preferred embodiment, a turn-off period is adjusted to be equal to a predetermined target period by adjusting the pulse width of the lower bridge signal; wherein the turn-off period is a duration from the disablement of the lower bridge signal to the subsequent enablement of the upper bridge signal.

[0025] In a preferred embodiment, the voltage threshold includes an upper threshold and a lower threshold; wherein the step of adjusting the off period further includes: adjusting the off period only when the second signal is between the upper threshold and the lower threshold.

[0026] In a preferred embodiment, the step of adjusting the off period also includes: configuring the predetermined target period to be associated with an optimal circulating current generated by the lower bridge transistor so that the voltage across the upper bridge transistor remains low enough to achieve zero voltage switching, while the circulating current remains at a low enough level to achieve a target conversion efficiency.

[0027] In a preferred embodiment, the method further includes limiting the off-period to not exceed a maximum off-period.

[0028] In a preferred embodiment, an enabling period of the low-bridge signal is equal to or longer than a demagnetization time of the transformer.

[0029] From another point of view, the present invention provides a control method for a resonant flyback power converter, comprising: generating an upper bridge signal for controlling an upper bridge transistor; generating a lower bridge signal for controlling a lower bridge transistor; switching the primary winding of the transformer with the upper bridge transistor and the lower bridge transistor through a resonant capacitor, thereby generating an output voltage through the secondary winding of the transformer; and adjusting a turn-off period to be equal to a predetermined target period by adjusting the pulse width of the lower bridge signal to achieve zero voltage switching of the upper bridge transistor; wherein the turn-off period is a duration from the disabling of the lower bridge signal to the subsequent enabling of the upper bridge signal.

[0030] In a preferred embodiment, it also includes: generating a period reference signal according to the predetermined target period; generating a turn-off period signal according to the turn-off period; and adjusting the pulse width of the lower bridge signal so that the level of the turn-off period signal is aligned with the level of the period reference signal, thereby aligning the turn-off period with the predetermined target period.

[0031] The following will be described in detail through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The circuit diagram of a resonant flyback power converter is shown, namely, an asymmetric half-bridge (AHB) resonant flyback power converter in a preferred embodiment of the present invention.

[0033] Figure 2 Shows the Figure 1 The operating waveforms corresponding to the embodiment shown are shown.

[0034] Figure 3 A preferred embodiment of the control circuit of the present invention is shown.

[0035] Figure 4 The preferred circuit for generating the upper bridge signal is shown.

[0036] Figure 5 A preferred embodiment of the volt-second circuit of the present invention is shown.

[0037] Figure 6 The preferred circuit for generating the lower bridge signal in the present invention is shown.

[0038] Figure 7 Shows Figure 5 and Figure 6 Waveforms for the circuit shown.

[0039] Figure 8 The preferred circuit for generating adjustable current in the present invention is shown.

[0040] Figure 9 Another preferred embodiment of the lower bridge signal and the half-bridge circuit according to the present invention is shown.

[0041] Figure 10 The waveforms of an embodiment of the present invention operating in discontinuous conduction mode (DCM) are shown.

[0042] Figure 11 Waveforms are shown according to one embodiment of the present invention operating in asynchronous DCM.

[0043] Explanation of symbols in the figure

[0044] 10: Transformer

[0045] 12: First sample and hold circuit

[0046] 13: Second sample and hold circuit

[0047] 15: Volt-second circuit

[0048] 16: ZVS timer circuit

[0049] 20: Resonant capacitor

[0050] 21, 23: Voltage to Current Circuit

[0051] 30: Upper bridge transistor

[0052] 35: Body diode of upper bridge transistor

[0053] 40: Lower bridge transistor

[0054] 45: Body diode of the lower bridge transistor

[0055] 51, 52, 60, 120, 151, 152, 153, 181, 182, 183, 211: resistors

[0056] 53: Time to Voltage Circuit

[0057] 55: Level Shift Buffer

[0058] 70: Synchronous rectification switch

[0059] 75: Body diode of synchronous rectifier

[0060] 90: Optocoupler

[0061] 100: Main control circuit

[0062] 110, 201: Amplifier

[0063] 115, 116, 117, 180, 212, 213, 214, 533: transistors

[0064] 121, 122, 131, 132, 241, 242, 316, 537: switch

[0065] 123, 124, 133, 134, 250, 315, 539: capacitors

[0066] 125, 127, 135, 137, 187, 330, 375: Pulse generator

[0067] 150: Voltage buffer

[0068] 185, 320: Comparator

[0069] 191: Delay Circuit

[0070] 325, 335: Flip-flop

[0071] 350, 351, 360: Logic gates

[0072] 535: Current Source

[0073] 570: Up and down counter

[0074] 580: Digital-to-Analog Converter

[0075] 700: Secondary control circuit

[0076] 800: Adjust circuit

[0077] AHB: Asymmetric Half Bridge

[0078] BCM: Boundary Conduction Mode

[0079] Cr: Resonant capacitor

[0080] DCM: Discontinuous Conduction Mode

[0081] I214: Charging current

[0082] IADJ: adjustable current

[0083] IM: Excitation current

[0084] INEG: negative current signal

[0085] IP: primary side switching current

[0086] IS: Secondary side switching current

[0087] Lr: leakage inductance

[0088] MODE signal: mode signal

[0089] NA: Auxiliary winding

[0090] NP: Primary winding

[0091] NS: Secondary winding

[0092] PRES: Resonant Pulse

[0093] PZVS: Pulse Zero Voltage Switching

[0094] S2: Second signal

[0095] S3: Third Signal

[0096] SG: driving signal

[0097] SH: upper bridge signal

[0098] SIV: Current to Voltage Signal

[0099] SL: Lower bridge signal

[0100] SZVS: Zero Voltage Switching Pulse Signal

[0101] TDS: During demagnetization

[0102] Tmax: Maximum off-time signal

[0103] TRH, TRL: Dead time

[0104] V1: First signal

[0105] V1H, V1L: voltage threshold

[0106] V2: Second signal

[0107] VAUX: auxiliary winding related signal

[0108] VCS: Current sensing signal

[0109] VFB, VFB': feedback signal

[0110] VHB: Switching Node

[0111] VIN: input voltage

[0112] VNA: Auxiliary winding signal

[0113] VO: output voltage

[0114] VPD: Shutdown period signal

[0115] VPR: Period Reference Signal

[0116] VTM:Threshold

[0117] V_VS: voltage signal

[0118] V_ZVS: voltage signal

[0119] ZPLS: trigger signal

[0120] ZVS: Zero Voltage Switching DETAILED DESCRIPTION

[0121] The figures in this application are schematic, primarily intended to illustrate the coupling relationships between circuits and the relationships between signal waveforms. Circuits, signal waveforms, and frequencies are not drawn to scale. For clarity, many practical details are included in the following description, but this is not intended to limit the scope of the present invention.

[0122] Figure 1 The circuit diagram of a resonant flyback power converter is shown, namely, an asymmetric half-bridge (AHB) resonant flyback power converter in a preferred embodiment of the present invention. The resonant flyback power converter includes a half-bridge circuit, a transformer 10, a resonant capacitor 20, and a main control circuit 100.

[0123] The half-bridge circuit consists of a high-bridge transistor 30 and a low-bridge transistor 40 connected in series between an input voltage VIN and ground potential. Both high-bridge transistor 30 and low-bridge transistor 40 are connected to a switching node VHB. Resonant capacitor 20 and transformer 10 are connected in series to switching node VHB. Transformer 10 includes a primary winding NP, a secondary winding NS, and an auxiliary winding NA.

[0124] The main control circuit 100 is used to generate a high-bridge signal SH and a low-bridge signal SL. These signals are used to control the half-bridge circuit, thereby controlling the transformer 10 to generate an output voltage VO on the secondary winding NS. The high-bridge signal SH generated by the main control circuit 100 is used to drive the high-bridge transistor 30 to conduct via a level-shift buffer 55, thereby exciting the primary winding NP of the transformer 10. After turning off the high-bridge transistor 30, the main control circuit 100 enables the low-bridge signal SL to control the low-bridge transistor 40 to conduct.

[0125] Excitation energy is transferred to the secondary winding NS of the transformer 10 by magnetic induction, thereby generating the output voltage VO. This is achieved by resonance between the resonant capacitor 20 and the primary winding NP. The enable period of the low-bridge signal SL corresponds to the demagnetization period of the transformer 10, and the pulse width of the low-bridge signal SL during the enable period is set to be equal to or longer than the demagnetization period of the transformer 10.

[0126] Resistor 60 is used to detect the primary-side switch current IP and generate a current sense signal VCS. In one embodiment, the main control circuit 100 generates the upper bridge signal SH based on the feedback signal VFB generated by the output voltage VO of the resonant flyback power converter. In this embodiment, the secondary control circuit 700, connected to the output voltage VO, generates the feedback signal VFB based on the output voltage VO. In one embodiment, the feedback signal VFB is transmitted to the main control circuit 100 via the optocoupler 90. The secondary control circuit 700 is also designed to generate a drive signal SG during the demagnetization period of the transformer 10 for controlling the synchronous rectification switch 70. The auxiliary winding NA generates an auxiliary winding signal VNA. Resistors 51 and 52 are configured as a voltage divider to divide the auxiliary winding signal VNA to generate the auxiliary winding-related signal VAUX.

[0127] Figure 2Shows the Figure 1 The operating waveforms corresponding to the embodiment shown. When the upper bridge signal SH is enabled, the transformer 10 is excited and generates an excitation current IM. When the upper bridge signal SH is disabled, the transformer 10 is demagnetized. During this demagnetization period TDS, the transformer 10 generates a secondary side switching current IS. The enabling period of the lower bridge signal SL corresponds to the demagnetization period TDS of the transformer 10. In one embodiment, the enabling period TSL (i.e., the pulse width) of the lower bridge signal SL is set to be equal to or longer than the demagnetization period TDS of the transformer 10. During the demagnetization period TDS of the transformer 10, the resonant capacitor 20 is coupled to generate a voltage Vcr, Vcr=n VO, where n represents the turns ratio from the primary winding NP to the secondary winding NS.

[0128] The lower bridge signal SL can be enabled after the upper bridge signal SH is disabled, and vice versa. There is a dead time between the upper bridge signal SH and the lower bridge signal SL, such as TRH and TRL.

[0129] Figure 2 The operation during the different sub-periods is as follows: The period from t1 to t2 represents the transformer excitation sub-period. During this sub-period, high-bridge transistor 30 is on and low-bridge transistor 40 is off. Current IP in transformer 10 and the voltage across resonant capacitor 20 increase. Transformer 10 is excited, and resonant capacitor 20 charges. Secondary-side synchronous rectifier 70 is off, and its body diode 75 is reverse biased, preventing energy transfer to the secondary side.

[0130] The period from t2 to t3 represents the first circulating current sub-interval, during which both high-bridge transistor 30 and low-bridge transistor 40 are off. The circulating current in transformer 10 causes the switch node voltage VHB of the half-bridge circuit to drop until the body diode 45 of low-bridge transistor 40 conducts. The time interval from t2 to t3 corresponds to the quasi-resonant period, enabling zero-voltage switching (ZVS) of low-bridge transistor 40. At t3, the primary side of transformer 10 reaches the same voltage as resonant capacitor 20.

[0131] The period from t3 to t4 represents the resonator period (positive current). The high-bridge transistor 30 is off, and the low-bridge transistor 40 is on under ZVS conditions. The output voltage VO is equal to the voltage Vcr across the resonant capacitor 20 divided by the turns ratio n. Current begins to flow through the secondary-side synchronous rectifier 70, transferring the energy stored in the transformer 10 to generate the output voltage VO. Because the leakage inductance Lr of the transformer 10 and the resonant capacitor 20 (Cr) form an inductor-capacitor resonant circuit, the secondary-side current follows a sinusoidal pattern with a period determined by the resonant frequency of Lr and Cr. The primary-side current of the transformer 10 consists of the magnetizing current IM plus the reflected secondary-side current IS. The resonant circuit current (Lr, Cr) remains positive, driven primarily by the magnetizing inductance of the transformer 10 and flowing into the resonant capacitor 20.

[0132] The period from t4 to t5 represents the resonator period (negative current). High-bridge transistor 30 remains off, while low-bridge transistor 40 remains on. Energy continues to transfer to the secondary side, but the resonant circuit current is now reverse-driven by the voltage across resonant capacitor 20. The energy in resonant capacitor 20 is not only transferred to the secondary side but also used to reduce the magnetizing current of transformer 10 to a negative level, while low-bridge transistor 40 remains on (e.g., from t4 to t5).

[0133] The period from t5 to t6 represents the transformer reverse excitation sub-period (negative current). This sub-period begins when the demagnetization period TDS of the transformer 10 ends and lasts until the low-bridge transistor 40 turns off. The resonant capacitor 20 reverse excites the transformer 10, generating a negative current.

[0134] The period from t6 to t7 represents the second circulating current sub-period. Both high-bridge transistor 30 and low-bridge transistor 40 are off. The negative current induced in transformer 10 from t5 to t6 causes the voltage VHB at the switch node of the half-bridge circuit to rise, ultimately turning on body diode 35 of high-bridge transistor 30.

[0135] After time t7, another sub-period similar to that from t1 to t2 begins, with the high-bridge transistor 30 conducting under ZVS conditions and the low-bridge transistor 40 remaining off. If the circulating current in the transformer resonant circuit is still negative, any excess energy in the resonant circuit will be returned to the input voltage VIN.

[0136] Figure 3 The negative current signal INEG is generated in the auxiliary winding NA of the transformer 10, and the time period is from t1 to t2 and from t6 to t7 (as shown in FIG. Figure 2(as shown). First signal V1 is generated by negative current signal INEG in response to the conduction of high-bridge transistor 30. First sample-and-hold circuit 12 is configured to generate first signal V1 by sampling a current-to-voltage signal SIV when high-bridge signal SH is enabled. Current-to-voltage signal SIV is generated by the negative current signal INEG through the current-to-voltage circuit. The level of first signal V1 is related to the input voltage level of transformer 10 (i.e., VIN - Vcr, the voltage across the primary winding). Operational amplifier 110, transistors 115, 116, 117, and resistor 120 form the current-to-voltage circuit. Switches 121, 122, capacitors 123, 124, and pulse generators 125, 127 form first sample-and-hold circuit 12.

[0137] When high-bridge transistor 30 is off, second signal V2 is generated by converting negative current signal INEG in response to disabling low-bridge transistor 40. Third signal S3 is generated by comparing second signal V2 with voltage threshold V1L. Enabling third signal S3 (e.g., when second signal V2 exceeds voltage threshold V1L) indicates that the voltage across high-bridge transistor 30 has been reduced by the negative circulating current to a level sufficient to achieve zero-voltage switching (ZVS) when high-bridge signal SH is enabled. Voltage thresholds V1H and V1L are generated based on first signal V1 via voltage buffer 150 and a voltage divider comprised of resistors 151, 152, and 153. Voltage thresholds V1H and V1L are proportional to the level of first signal V1. The pulse width of low-bridge signal SL is adjusted based on third signal S3 to achieve zero-voltage switching (ZVS) for high-bridge transistor 30.

[0138] The second sample-and-hold circuit 13 is coupled to the auxiliary winding NA of the transformer 10 and generates a reflected output voltage nVO in response to the conduction of the low-bridge transistor 40 (during periods t4–t5). When the low-bridge transistor 40 is on, the level of the reflected output voltage nVO is related to the output voltage VO of the power converter. Switches 131 and 132, capacitors 133 and 134, and pulse generators 135 and 137 form the second sample-and-hold circuit 13.

[0139] Figure 4 FIG1 shows a preferred circuit for generating the high-side signal SH. In one aspect, the high-side signal SH is generated based on the feedback signal VFB and the current sense signal VCS. More specifically, comparator 185 compares the feedback signal VFB' with the current sense signal VCS to control the duty cycle of the high-side signal SH. In this embodiment, the feedback signal VFB' is proportional to the feedback signal VFB. This is achieved using a buffer and voltage divider circuit consisting of transistor 180, resistors 181, 182, and 183.

[0140] On the other hand, the generation of the high bridge signal SH also depends on the third signal S3. Under sufficient negative circulating current, S3 will be enabled, indicating that the voltage of the high bridge transistor 30 is low enough to achieve ZVS, thereby triggering the conduction of the high bridge signal SH.

[0141] When the negative circulating current is insufficient to achieve ZVS (S3 cannot be enabled), a timeout mechanism is required. The pulse generator 187 generates a maximum off-period signal Tmax to limit the maximum allowed duration between the shutdown of the low-bridge signal SL and the subsequent enablement of the high-bridge signal SH.

[0142] Figure 5 The figure shows a volt-second circuit according to a preferred embodiment of the present invention. The volt-second circuit 15 generates a low-bridge signal SL based on the enable period of the high-bridge signal SH, the input voltage level (VIN-Vcr) of the transformer 10, and the output voltage VO of the power converter. The voltage level of the first signal V1 is related to the voltage level of (VIN-Vcr). The voltage-to-current circuit 21 is used to generate a charging current I214 based on the first signal V1. The voltage-to-current circuit 21 includes a buffer circuit consisting of an amplifier 201, a transistor 212, and a feedback resistor 211, and a current mirror circuit consisting of transistors 213 and 214. The charging current I214 is used to charge a capacitor 250 through a switch 241. The switch 241 is turned on during the enable period of the high-bridge signal SH to charge the capacitor 250.

[0143] On the other hand, the reflected output voltage nVO is used to generate a discharge current, which, in a similar manner, passes through the voltage-to-current circuit 23 and discharges the capacitor 250 via switch 242. When the high-side signal SH is disabled, the switch 242 is turned on to discharge the capacitor 250. This generates a voltage signal V_VS across the capacitor 250, which simulates the magnetizing current and demagnetizing current of the transformer 10. The configuration and operational details of the voltage-to-current circuit 23 are similar to those of the voltage-to-current circuit 21 and are not further described here.

[0144] When the high bridge signal SH is disabled, the front low bridge signal pSL is enabled and disabled once V_VS is lower than the threshold VL2. The front low bridge signal pSL is used to generate the low bridge signal SL, whose pulse width is related to the demagnetization time of the transformer 10.

[0145] During the period when the high-side signal SH is disabled, when the level of V_VS falls below the threshold VL1, a trigger signal ZPLS is generated. This trigger signal ZPLS is used to trigger the zero-voltage switching pulse signal SZVS. In the present invention, the pulse width of the zero-voltage switching pulse signal SZVS can be adaptively adjusted to an optimal duration to achieve ZVS when the high-side transistor 30 is subsequently turned on, without causing excessive circulating current during the ZVS process. This will be described in detail later.

[0146] refer to Figure 5 and Figure 7 , Figure 7 Depicts the Figure 5 Corresponding operating waveforms: When the resonant flyback power converter operates in boundary conduction mode (BCM), the threshold of VL1 is set higher than the threshold of VL2, resulting in the overlap of the demagnetization period and the zero voltage switching pulse period, forming a single pulse of the low-bridge signal SL.

[0147] Figure 6 A preferred ZVS timer circuit 16 is shown. It uses a cooperative logic circuit to generate a low-bridge signal SL based on a trigger signal ZPLS and a front low-bridge signal pSL. When the high-bridge signal SH is disabled, a pulse generator 330 sets (triggers) a flip-flop 335. The front low-bridge signal pSL is used to reset the flip-flop 335. The output of the flip-flop 335 is used to generate the low-bridge signal SL via OR gates 350 and 360 and an AND gate 351. The pulse width of the output signal of the pulse generator 330 determines the period t2–t3 (e.g., Figure 2 ), which is crucial to achieve ZVS of the low-bridge transistor 40.

[0148] In addition to the demagnetization time of the transformer 10, the low-bridge signal SL also includes a zero-voltage switching pulse signal SZVS. This zero-voltage switching pulse signal SZVS is generated by a ZVS timer circuit consisting of a flip-flop 325, a comparator 320, a capacitor 315, a current source 310, an adjustable current IADJ, and a switch 316. The flip-flop 325 is set by a trigger signal ZPLS and reset by the comparator 320 when the voltage signal V_ZVS exceeds a threshold value VTM. The current source 310, together with the adjustable current IADJ, charges the capacitor 315 to generate a voltage signal V_ZVS based on the zero-voltage switching pulse signal SZVS. The adjustable current IADJ is used to adjust the pulse width of the zero-voltage switching pulse signal SZVS, thereby adjusting the pulse width of the low-bridge signal SL, thereby optimizing the ZVS performance of the high-bridge transistor 30 (during the period t6-t7). A shorter low-bridge signal SL (zero-voltage switching pulse signal SZVS) may result in a circulating current that is too low, potentially insufficient to achieve proper ZVS. Conversely, a longer duration can achieve ZVS but may result in greater power loss due to excessive circulating current. Optimal circulating current generated by the control circuit can ensure both ZVS and enhanced power efficiency, especially under light load conditions.

[0149] It should be noted that in the above Figure 6 In the illustrated embodiment, the pulse width of the low bridge signal SL is adjusted by adjusting the integrated current through IADJ. However, in other embodiments, the pulse width of the low bridge signal SL can alternatively be adjusted by adjusting the capacitance of the capacitor 315 or adjusting the level of the threshold VTM.

[0150] During light load and burst mode operation, when the MODE signal is set to 0, the low bridge signal SL is triggered by the burst signal BRST and is generated only by the zero voltage switching pulse signal of the pulse generator 375 .

[0151] Figure 7 Depicts the Figure 5 and Figure 6The waveforms corresponding to the BCM operation of the circuit shown in FIG. The period T1–T2 represents the enable period of the high-bridge signal SH, which is associated with the magnetization period of the transformer 10. The period T2–T5 represents the enable period of the front low-bridge signal pSL, which is associated with the demagnetization period TDS of the transformer 10. The period T2–T3 provides a dead time during which both the high-bridge transistor 30 and the low-bridge transistor 40 are turned off, thereby achieving zero voltage switching (ZVS) when the low-bridge transistor 40 is subsequently turned on. Similarly, the period T6–T7 provides a dead time during which both the high-bridge transistor 30 and the low-bridge transistor 40 are turned off, thereby achieving zero voltage switching (ZVS) when the high-bridge transistor 30 is subsequently turned on. Excluding the dead time T2–T3, a single pulse of the low-bridge signal xSL includes the periods of the front low-bridge signal pSL and the zero voltage switching pulse signal SZVS. The period T4 - T6 (zero voltage switching pulse width), ie, the period of the zero voltage switching pulse signal SZVS, is an adjustable period for generating an optimal circulating current to achieve ZVS of the upper bridge transistor 30 .

[0152] Figure 8 FIG. 8 shows a preferred adjustment circuit 800 for generating an adjustable current IADJ according to the present invention. The time-to-voltage circuit 53 is composed of a transistor 533, a current source 535, a switch 537, and a capacitor 539. These components together form a time-to-voltage circuit. The time-to-voltage circuit 53 generates an off-period signal VPD based on the interval from the disabling of the lower bridge signal SL to the enabling of the upper bridge signal SH (i.e., the off-period). A longer off-period results in a higher level of the off-period signal VPD. The digital-to-analog converter 580 generates the adjustable current IADJ based on the output of the up-down counter 570. It should be noted that in one embodiment, the off-period corresponds to Figure 7 During the period T6-T7 shown in FIG, both the upper bridge signal SH and the lower bridge signal SL are turned off during the turn-off period.

[0153] When the level of the second signal V2 drops below the voltage threshold V1L, a down count is triggered, which causes the count in the down counter 570 to decrease, thereby reducing IADJ and increasing the pulse width of the lower bridge signal SL, thereby increasing the circulating current. Conversely, if the level of the second signal V2 exceeds the voltage threshold V1H, an up count is triggered in the up counter 570, increasing IADJ, thereby reducing the pulse width of the lower bridge signal SL and reducing the circulating current.

[0154] If the level of the second signal V2 is between the voltage thresholds V1L and V1H, the adjusted current IADJ varies with the level of the off-period signal VPD. The level of the off-period signal VPD is proportional to the period T6–T7, affecting the operation of the counter. When the level of the off-period signal VPD exceeds the period reference signal VPR, a down-count is triggered, decreasing IADJ and increasing the pulse width of the low-bridge signal SL. Conversely, if the level of VPD falls below the period reference signal VPR, an up-count is triggered, increasing IADJ and decreasing the pulse width of the low-bridge signal SL, thereby reducing the circulating current.

[0155] In summary, in one embodiment, the off-period can be adjusted to be equal to a predetermined target period by adjusting the pulse width of the low-bridge signal SL. In one embodiment, the level of the off-period signal VPD generated during the off-period is adjusted to align with the level of the period reference signal VPR, thereby aligning the off-period with the predetermined target period.

[0156] By optimizing the circulating current generated by the low-bridge transistor 40 , zero-voltage switching of the high-bridge transistor 30 can be achieved without generating additional power loss due to undue (eg, excessive) negative circulating current.

[0157] Figure 9 Another preferred circuit for generating the lower bridge signal and the half-bridge circuit according to the present invention is shown. Figure 9 The embodiment shown is similar to Figure 4 The difference is that Figure 9 The embodiment shown is further configured with a delay circuit 191 to provide a delay time when the level of the second signal S2 exceeds the voltage threshold (V1L). Figure 9 In the illustrated embodiment, the delay circuit 191 delays the third signal S3 before enabling the upper bridge transistor 30 .

[0158] Figure 10 The waveforms of the DCM operation according to one embodiment of the present invention are depicted. The above-mentioned technique of automatically adjusting the pulse width of the lower bridge signal SL to achieve ZVS can also be applied to the discontinuous conduction mode (DCM). Figure 10 As shown in FIG. , in DCM, the low-bridge signal SL includes two pulses: a resonant pulse PRES and a zero-voltage switching pulse PZVS. Various embodiments exist in the art for triggering the zero-voltage switching pulse PZVS. In this embodiment, after the zero-voltage switching pulse PZVS is triggered, the PZVS pulse width can be adjusted according to the aforementioned embodiments to achieve ZVS while keeping the circulating current sufficiently low.

[0159] Figure 11The waveforms of an embodiment of the present invention operating in asynchronous DCM are depicted. The above-mentioned technique of automatically adjusting the pulse width of the lower bridge signal SL to achieve ZVS can also be applied to asynchronous DCM. Figure 11 As shown, in an asynchronous DCM, the low-bridge signal SL contains only the zero-voltage switching pulse PZVS and remains off during the demagnetization period TDS. During the demagnetization period TDS, the demagnetization current flows through the body diode of the low-bridge transistor 40. The triggering and width of the zero-voltage switching pulse PZVS can be found in the previous description of DCM operation.

[0160] The present invention has been described above with respect to preferred embodiments. However, the above description is intended only to facilitate understanding of the present invention by those skilled in the art and is not intended to limit the scope of the present invention. The various embodiments described are not limited to individual applications and can also be applied in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace corresponding components in another embodiment. In addition, within the same spirit of the present invention, those skilled in the art can conceive of various equivalent variations and combinations. For example, the present invention's term "processing or calculating or generating an output result based on a certain signal" is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or ratio conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. It can be seen that within the same spirit of the present invention, those skilled in the art can conceive of various equivalent variations and combinations, and there are many combinations, which are not listed here one by one. Therefore, the scope of the present invention should cover the above and all other equivalent variations.

Claims

1. A control circuit for controlling a resonant flyback power converter, comprising: An upper bridge signal for controlling an upper bridge transistor; A lower bridge signal used to control the lower bridge transistor; A negative current signal generated by an auxiliary winding of a transformer, wherein the negative current signal is related to a voltage across the auxiliary winding; a first signal generated by the negative current signal when the upper bridge transistor is turned on; a second signal generated by the negative current signal when the lower bridge transistor is turned off, and the upper bridge transistor is in an off state; as well as a third signal generated by comparing the second signal with a voltage threshold, wherein the voltage threshold is related to the level of the first signal; The upper bridge transistor and the lower bridge transistor are used to switch a primary winding of the transformer through a resonant capacitor, thereby generating an output voltage through a secondary winding of the transformer. A pulse width of the lower bridge signal is adjusted according to the third signal to achieve zero voltage switching of the upper bridge transistor.

2. The control circuit of claim 1, wherein: The upper bridge signal turns on the upper bridge transistor through a level shift buffer after the level of the second signal exceeds the voltage threshold.

3. The control circuit of claim 1 , wherein: Also includes: a sample-and-hold circuit for generating the first signal by sampling a current-to-voltage signal; The current-to-voltage signal is generated by the negative current signal; The level of the first signal is related to the input voltage level of the transformer.

4. The control circuit of claim 1, wherein: Also includes: An up-down counter is used to adjust the pulse width of the lower bridge signal according to the first signal and the second signal.

5. The control circuit of claim 1, wherein: The control circuit is further configured to adjust a turn-off period to be equal to a predetermined target period by adjusting the pulse width of the lower bridge signal; The off period is a duration from when the lower bridge signal is disabled to when the upper bridge signal is enabled.

6. The control circuit of claim 5, wherein: Also includes: a period reference signal generated according to the predetermined target period; and An off-period signal generated during the off-period; The level of the off-period signal is adjusted by adjusting the pulse width of the lower bridge signal to align with the level of the period reference signal, thereby aligning the off period with the predetermined target period.

7. The control circuit of claim 5, wherein: When the turn-off period is determined to be longer than the predetermined target period, the pulse width of the lower bridge signal is increased, and when the turn-off period is determined to be shorter than the predetermined target period, the pulse width of the lower bridge signal is reduced.

8. The control circuit of claim 5, wherein: The voltage threshold includes an upper threshold and a lower threshold; The off period is adjusted only when the second signal is between the upper threshold and the lower threshold.

9. The control circuit of claim 5, wherein: The predetermined target period is related to an optimal circulating current generated by the low-bridge transistor so that the voltage across the high-bridge transistor remains low enough to achieve zero voltage switching, while the circulating current remains low enough to achieve a target conversion efficiency.

10. The control circuit of claim 5, wherein: Also includes: A maximum off-period signal is used to limit the off-period to not exceed a corresponding maximum off-period.

11. The control circuit of claim 1 , wherein: An enabling period of the low-bridge signal is equal to or longer than the demagnetization time of the transformer.

12. The control circuit of claim 1, wherein: Also includes: A volt-second circuit is used to generate the low-bridge signal according to an enable period of the high-bridge signal, the level of the input voltage of the transformer, and the level of the output voltage of a power converter.

13. The control circuit of claim 1, wherein: The conduction of the lower bridge transistor causes the transformer to generate a circulating current after demagnetization. The circulating current is used to achieve zero voltage switching of the upper bridge transistor and is composed of the negative excitation current of the transformer.

14. The control circuit of claim 1, wherein: When the level of the second signal is lower than the voltage threshold, the pulse width of the lower bridge signal is increased; and when the level of the second signal is higher than the voltage threshold, the pulse width of the lower bridge signal is reduced.

15. The control circuit of claim 14, wherein: The voltage threshold includes an upper threshold and a lower threshold, and the upper threshold is higher than the lower threshold; When the level of the second signal is lower than the lower threshold, the pulse width of the lower bridge signal is increased; When the level of the second signal is higher than the upper threshold, the pulse width of the lower bridge signal is reduced.

16. The control circuit of claim 2, wherein: The invention also comprises a delay circuit, which is used for providing a delay time after the level of the second signal exceeds the voltage threshold before turning on the upper bridge transistor through a level shift buffer.

17. A control circuit for controlling a resonant flyback power converter, comprising: A high-bridge signal for controlling a high-bridge transistor; and A lower bridge signal used to control the lower bridge transistor; Switching the primary winding of the transformer via a resonant capacitor using the upper bridge transistor and the lower bridge transistor, thereby generating an output voltage via the secondary winding of the transformer; wherein by adjusting the pulse width of the lower bridge signal, an off period is adjusted to be equal to a predetermined target period, so as to achieve zero voltage switching of the upper bridge transistor; The off period is the duration from when the lower bridge signal is disabled to when the upper bridge signal is subsequently enabled.

18. The control circuit of claim 17, wherein: Also includes: a period reference signal generated according to the predetermined target period; an off-period signal generated according to the off-period; and The level of the off-period signal is adjusted by adjusting the pulse width of the lower bridge signal to align with the level of the period reference signal, thereby aligning the off period with the predetermined target period.

19. A control method for controlling a resonant flyback power converter, comprising: generating a high-bridge signal for controlling a high-bridge transistor; Generate a lower bridge signal for controlling a lower bridge transistor; generating a negative current signal related to a voltage on an auxiliary winding of a transformer; generating a threshold value generated by the negative current signal in response to the turning on of the upper bridge transistor; After the lower bridge transistor is turned off, the upper bridge signal is enabled when the negative current signal exceeds the threshold; Switching the primary winding of the transformer via a resonant capacitor using the upper bridge transistor and the lower bridge transistor, thereby generating an output voltage via the secondary winding of the transformer; as well as According to the comparison between the negative current signal and the threshold, the pulse width of the lower bridge signal is adjusted to subsequently turn on the upper bridge transistor to achieve zero voltage switching.

20. The control method according to claim 19, wherein: Also includes: By adjusting the pulse width of the lower bridge signal, a turn-off period is adjusted to be equal to a predetermined target period; The off period is a duration from when the lower bridge signal is disabled to when the upper bridge signal is enabled.

21. The control method according to claim 20, wherein: The voltage threshold includes an upper threshold and a lower threshold; The step of adjusting the off period further includes: adjusting the off period only when the second signal is between the upper threshold and the lower threshold.

22. The control method according to claim 20, wherein: The step of adjusting the off period also includes: configuring the predetermined target period to be related to an optimal circulating current generated by the lower bridge transistor so that the voltage across the upper bridge transistor remains low enough to achieve zero voltage switching, while the circulating current remains at a low enough level to achieve a target conversion efficiency.

23. The control method according to claim 20, wherein: The method further includes limiting the shutdown period to not exceed a maximum shutdown period.

24. The control method according to claim 19, wherein: An enabling period of the low-bridge signal is equal to or longer than a demagnetization time of the transformer.

25. A control method for a resonant flyback power converter, comprising: generating a high-bridge signal for controlling a high-bridge transistor; Generate a lower bridge signal for controlling a lower bridge transistor; Switching the primary winding of the transformer via a resonant capacitor using the upper bridge transistor and the lower bridge transistor, thereby generating an output voltage via the secondary winding of the transformer; and By adjusting the pulse width of the lower bridge signal, an off period is adjusted to be equal to a predetermined target period, so as to achieve zero voltage switching of the upper bridge transistor; The off period is a duration from when the lower bridge signal is disabled to when the upper bridge signal is enabled.

26. The control method according to claim 25, wherein: Also includes: generating a period reference signal according to the predetermined target period; generating a turn-off period signal according to the turn-off period; as well as The pulse width of the lower bridge signal is adjusted to align the level of the off-period signal with the level of the period reference signal, thereby aligning the off period with the predetermined target period.

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