Clock delay circuit and multiphase clock generation device

Abstract

The invention discloses a clock delay circuit and a multiphase clock generation device, relates to the technical field of clock integrated circuits, and provides a method for synchronously tuning and outputting delay of a multiphase clock by adjusting the proportion of charging current and discharging current, so that two parts of multiphase clock generation and delay adjustability can be combined together. And the power consumption and the area of a traditional multi-phase clock circuit are greatly reduced. According to the invention, the power consumption and area of the D2D interconnection interface circuit can be reduced, and higher-density integration is realized, so that the overall interaction total bandwidth of a chip is increased, and the calculation power of an artificial intelligence chip is promoted to be improved.

Description

Technical Field

[0001] The present application relates to the technical field of clock integrated circuits, and in particular to a clock delay circuit and a multi-phase clock generating device. Background Art

[0002] The traditional multi-phase clock circuit structure uses a separate multi-phase clock generator and an adjustable delay circuit unit, which has many problems: First, the delay unit can usually only delay a group of differential clocks in the multi-phase clock, and multiple delay units are needed to meet the synchronization and adjustment requirements; second, the delay unit will introduce additional clock jitter, which is more obvious when the delay is large. In order to achieve low-jitter and wide-range delay adjustment, the jump edge slope and circuit level need to be increased, resulting in high power consumption and large area; third, there is a delay mismatch between multiple delay units, and an additional phase interval calibration circuit module is required, which further increases power consumption and area.

[0003] At the same time, traditional multi-phase clock generators are often implemented using delay-locked loops (DLLs) or injection-locked ring oscillators, which also have shortcomings. For example, DLLs require multiple high-speed delay units, consume high power under low-jitter conditions, and require additional phase interval calibration circuit modules to calibrate delay unit mismatches. Although injection-locked oscillators can achieve synchronous low jitter and power consumption, they can cause mismatches in the ring oscillator output phase, and also require additional phase interval calibration circuit modules for phase deviation correction. Summary of the Invention

[0004] The present application provides a clock delay circuit and a multi-phase clock generation device to at least solve the problem of how to reduce the power consumption and area of ​​a traditional multi-phase clock circuit in the related art.

[0005] The present application provides a clock delay circuit, comprising: a single-ended to differential circuit, a switching circuit, multiple charging current sources, multiple discharging current sources, and a loop filter circuit, wherein the input end of the single-ended to differential circuit receives a clock signal, and the first output end and the second output end of the single-ended to differential circuit are connected to the control end of the switching circuit; the input end of each charging current source is connected to a power supply voltage, the output end of each charging current source is connected to the first end of the switching circuit, and the control end of each charging current source is connected to a first control signal; the input end of each discharging current source is connected to the second end of the switching circuit, the output end of each discharging current source is grounded, and the control end of each charging current source is connected to a second control signal; the third end of the switching circuit is grounded through the loop filter circuit, and the third end of the switching circuit outputs a clock delay signal; within a control cycle, the first control signal and the second control signal are complementary.

[0006] The present application provides a multi-phase clock generation device, comprising: a phase detection circuit, an oscillation circuit and the above clock delay circuit and oscillation circuit, the clock delay circuit comprising: a single-ended to differential circuit, a switch circuit, multiple charging current sources, multiple discharging current sources and a loop filter circuit, wherein the first input end of the phase detection circuit is connected to the clock signal, the second input end of the phase detection circuit is connected to the output end of the oscillation circuit, the output end of the phase detection circuit is connected to the input end of the single-ended to differential circuit; the input end of the single-ended to differential circuit receives the clock signal, the first output end and the second output end of the single-ended to differential circuit are connected to the control end of the switch circuit The circuit comprises a first circuit configured to connect a first end of the switching circuit to a second end of the switching circuit; an input end of each charging current source is connected to a supply voltage, an output end of each charging current source is connected to a first end of the switching circuit, and a control end of each charging current source is connected to a first control signal; an input end of each discharging current source is connected to a second end of the switching circuit, an output end of each discharging current source is grounded, and a control end of each charging current source is connected to a second control signal; a third end of the switching circuit is grounded through a loop filter circuit, and a third end of the switching circuit is connected to an input end of an oscillation circuit; an output end of the oscillation circuit outputs a multi-phase clock signal; and within a control cycle, the first control signal and the second control signal are complementary.

[0007] This application proposes a method for synchronously tuning the delay of a multiphase clock output by adjusting the ratio of charging and discharging currents. This method combines multiphase clock generation and adjustable delay, significantly reducing the power consumption and area of ​​traditional multiphase clock circuits. This invention can help reduce the power consumption and area of ​​D2D interconnect interface circuits, achieving higher-density integration, thereby increasing the overall interactive bandwidth of the chip and promoting the computing power of artificial intelligence chips.

[0008] Through this application, a multi-phase clock generation device achieves precise conversion from a reference clock to a multi-phase clock through the closed-loop coordination of a phase detector circuit, an oscillator circuit, and a clock delay circuit. The clock delay circuit, as the core of delay regulation, provides a stable and adjustable delay reference for the entire device through the complementary control of first and second control signals. The phase detector circuit and oscillator circuit, respectively, perform error correction and multi-phase output. Together, the three constitute a highly accurate and stable multi-phase clock generation system that can be widely used in electronic devices requiring multi-phase timing coordination (such as communication chips and data converters). BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1A block diagram of a multi-phase clock circuit module in related technology; FIG2( a ) is a block diagram of a multi-phase clock circuit module using a DLL in the related art; FIG2( b ) is a block diagram of a multi-phase clock circuit module of an injection-locked ring oscillator in the related art; Figure 3 A block diagram of a clock delay circuit module provided in an embodiment of the present invention; Figure 4 A circuit structure diagram of a single-ended to differential converter circuit provided in an embodiment of the present invention; Figure 5 A circuit structure diagram of a switch circuit, a charging current source, and a discharging current source provided in an embodiment of the present invention; Figure 6 A block diagram of another clock delay circuit module provided by an embodiment of the present invention; Figure 7 A block diagram of a multi-phase clock generation device module provided by an embodiment of the present invention; Figure 8 A circuit structure diagram of a phase detection circuit provided in an embodiment of the present invention; Figure 9 This is a circuit structure diagram of an oscillation circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0012] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0013] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0014] Multiphase clock generators with four or more phases are widely used in scenarios such as high-density die-to-die (D2D) interconnects and multi-channel serializer-deserializer (SerDes) transceivers. Furthermore, the delay of the multiphase clocks must be adjustable to ensure alignment of data symbol centers with clock edges in D2D and SerDes applications, thereby enabling data exchange with low bit error rates.

[0015] In the traditional multi-phase clock circuit structure, a separate multi-phase clock generator and an adjustable delay circuit unit are used, such as Figure 1 There are the following problems: 1) The delay unit usually adopts an adjustable delay chain based on an inverter or a phase interpolator, which can only delay one set of differential clocks in a multi-phase clock. Therefore, multiple delay units are needed to achieve the requirement of synchronous and adjustable delay of the multi-phase clock (for example, a commonly used 4-phase clock requires two delay units, such as Figure 1 As shown in the figure); 2) The delay unit will introduce additional clock jitter. Especially when a large delay is required, the clock signal transition edge in the delay unit needs to become slower, that is, more transistor noise will be injected into the clock transition edge, resulting in greater clock jitter. Therefore, it is usually necessary to increase the transition edge slope and increase the number of delay unit circuits to achieve low-jitter and wide-range delay adjustment, resulting in high circuit power consumption and large area; 3) There is a delay mismatch between multiple delay units. Therefore, an additional phase interval calibration circuit module is required, which also increases power consumption and area.

[0016] At the same time, traditional multi-phase clock generators are usually implemented using DLLs or injection-locked ring oscillators, as shown in Figures 2(a) and 2(b). However, these generators have the following problems: 1) DLLs require multiple high-speed delay units. As mentioned above, while ensuring low jitter, the delay units consume large amounts of power, and additional phase interval calibration circuit modules are required to calibrate the mismatch of the delay units. 2) Although injection-locked oscillators can achieve synchronous low jitter and power consumption, injection locking can cause mismatches in the ring oscillator output phase, and additional phase interval calibration circuit modules are also required to calibrate the phase deviation.

[0017] Based on the above problems, the embodiment of the present application provides a clock delay circuit, such as Figure 3 As shown, it includes: a single-ended to differential circuit 1, a switch circuit 2, multiple charging current sources 3, multiple discharging current sources 4 and a loop filter circuit 5. Figure 3 In the figure, three discharging current sources 4 and three charging current sources 3 are taken as an example, but the specific number of current sources can be set as needed.

[0018] like Figure 3As shown, the input of the single-ended to differential converter circuit 1 receives a clock signal, and the first and second outputs of the single-ended to differential converter circuit 1 are connected to the control terminal of the switch circuit 2. The input of each charging current source 3 is connected to the supply voltage, the output of each charging current source 3 is connected to the first terminal of the switch circuit 2, and the control terminal of each charging current source 3 is connected to the first control signal. The input of each discharging current source 4 is connected to the second terminal of the switch circuit 2, the output of each discharging current source 4 is grounded, and the control terminal of each charging current source 3 is connected to the second control signal. The third terminal of the switch circuit 2 is grounded through the loop filter circuit 5, and the third terminal of the switch circuit 2 outputs a clock delay signal. Within a control cycle, the first control signal and the second control signal are complementary.

[0019] Specifically, the input terminal of single-ended-to-differential circuit 1 is specifically designed to receive an external single-ended clock signal. As the circuit's "signal conversion station," its primary function is to convert the single-ended clock signal into a differential signal. The converted differential signal is output from the first and second output terminals, respectively, and connected to the control terminal of switch circuit 2, thereby controlling the on / off state of switch circuit 2 and laying the foundation for subsequent delay adjustment.

[0020] Specifically, in a complete control cycle, the first control signal and the second control signal show a strict complementary relationship - this means that when one of the signals is in a valid state (such as a high level), the other signal must be in an invalid state (such as a low level), and the two will not be valid or invalid at the same time, just like the "on" and "off" of a switch, they are opposite to each other and work together.

[0021] For example, if the first control signal is high, the second control signal must be low. When the first control signal turns low, the second control signal simultaneously turns high. The two control signals have completely different effective intervals on the time axis, covering the entire control cycle, with no signal overlap or gaps.

[0022] Taking the scenario of three charging current sources 3 and three discharging current sources 4 as an example, if the first control signal is "1," some charging current sources 3 are activated (turned on), and the second control signal must be "0," turning all discharging current sources 4 off. Conversely, when the second control signal is "1," some or all discharging current sources 4 are activated, while the first control signal is "0," turning all charging current sources 3 off. This either-or state ensures that charging and discharging processes don't occur simultaneously within the same control cycle, avoiding circuit anomalies caused by current conflicts.

[0023] Specifically, the input of each charging current source 3 is connected to a supply voltage, providing the energy required for operation. The output of each charging current source 3 is uniformly connected to the first terminal of the switching circuit 2. A first control signal, connected to the control terminal, determines whether each charging current source 3 is operational. When a charging current source 3 is operational, it provides charging current to subsequent circuits, affecting the circuit's charging speed and, in turn, altering the delay time.

[0024] Specifically, corresponding to charging current source 3, each discharging current source 4 has its input connected to the second terminal of switching circuit 2 and its output connected to ground. Its control terminal receives a second control signal, controlling the operating state of discharging current source 4. When discharging current source 4 is operating, it accelerates the circuit's discharge speed, also affecting the delay time.

[0025] Specifically, switch circuit 2 acts as a "valve" in the circuit, switching its operating state under the control of the differential signal output by single-ended-to-differential converter circuit 1. When switch circuit 2 is turned on, charging current source 3 or discharging current source 4 forms a path with loop filter circuit 5, and current begins to charge and discharge the energy storage element (such as a capacitor) in loop filter circuit 5.

[0026] Specifically, the third terminal of the switch circuit 2 is grounded via the loop filter circuit 5, which also serves as the output terminal for the clock delay signal. The loop filter circuit 5, primarily composed of components such as capacitors and resistors, smoothes the current during the charge and discharge process. During the charge and discharge process, the voltage across the energy storage element gradually changes. When it reaches a specific threshold, a delayed clock signal is output. Faster charge and discharge speeds result in shorter delays; conversely, slower charge and discharge speeds result in longer delays.

[0027] The core of this embodiment's clock delay circuit lies in utilizing multiple charging and discharging current sources 4. By controlling the number of connected current sources, the charge and discharge currents are varied, thereby adjusting the charge and discharge speeds of the energy storage elements in the loop filter circuit 5, ultimately achieving precise control of the clock signal delay. The single-ended-to-differential circuit 1 and the switching circuit 2 play a key role in signal conversion and path control, jointly ensuring the flexibility and stability of the circuit's delay adjustment. This structural design enables the circuit to be widely used in various electronic systems requiring clock signal delay control, meeting the timing requirements of different scenarios.

[0028] In some optional embodiments, such as Figure 4As shown, the single-ended to differential circuit 1 includes: a first inverter N1, a second inverter N2, a third inverter N3 and a transmission gate U1, wherein the input end of the first inverter N1 is connected to the input end of the transmission gate U1, and the input end of the first inverter N1 is also connected to the clock signal, the output end of the first inverter N1 is connected to the input end of the second inverter N2; the output end of the second inverter N2 is connected to the control end of the switch circuit 2; the input end of the third inverter N3 is connected to the input end of the transmission gate U1, and the output end of the third inverter N3 is connected to the control end of the switch circuit 2.

[0029] Specifically, the input of the first inverter N1 plays a dual role: directly connected to the input of transmission gate U1, and specifically receiving the external single-ended clock signal. This means that the first inverter N1 receives the original clock signal from the outset and passes it to transmission gate U1, while also inverting the signal. Its output is connected to the input of the second inverter N2, passing the inverted signal to the next inverter.

[0030] Specifically, the second inverter N2, acting as a subsequent stage to the first inverter N1, receives the inverted signal from N1 at its input and inverts it again. After two inversions, the output signal remains logically consistent with the original clock signal, but has been delayed and shaped by two stages of inverters. This output is directly connected to the control terminal of switch circuit 2, providing one of its control signals.

[0031] Specifically, the input of the third inverter N3 is also connected to the input of the transmission gate U1, which in turn is connected to the input of the first inverter N1. This means that the signal input to the third inverter N3 is from the same source as the original clock signal input to the first inverter N1. N3 inverts the original signal and outputs the inverted signal directly to the control terminal of the switch circuit 2, becoming another signal for controlling the switch circuit 2.

[0032] Specifically, the input of transmission gate U1 is connected to the input of first inverter N1 and the input of third inverter N3, and together receives the original clock signal. Transmission gate U1's role here is more inclined towards signal transmission and isolation, ensuring that the original signal can be stably transmitted to the relevant inverters while reducing signal interference between different inverters and ensuring the consistency of the input signals of each inverter.

[0033] based on Figure 4The key to converting single-ended signals into differential signals lies in the coordination of these three inverters. After the original clock signal enters the first inverter N1, it is inverted and output to the second inverter N2. After further inversion, the output signal of N2 is in phase with the original signal. The third inverter N3 directly inverts the original signal, outputting an inverted version of the original signal. This creates a complementary differential signal pair, with the in-phase signal output by the second inverter N2 and the inverted signal output by the third inverter N3. These differential signals are then connected to the control terminals of switch circuit 2, precisely meeting the differential control signal requirements of switch circuit 2.

[0034] In some optional embodiments, such as Figure 5 As shown, the switch circuit 2 includes: a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and an operational amplifier U2. A first end of the first switch Q1 is connected to the output of each charging current source 3 and the first end of the third switch Q3. A second end of the first switch Q1 is connected to the first end of the second switch Q2, the output of the operational amplifier U2, and the inverting input of the operational amplifier U2. A control end of the first switch Q1 is connected to the output of the second inverter N2. A second end of the second switch Q2 is connected to the input of each discharging current source 4 and the second end of the fourth switch Q4. A control end of the second switch Q2 is connected to the output of the third inverter N3. A second end of the third switch Q3 is connected to the positive input of the operational amplifier U2 and the first end of the fourth switch Q4. A second end of the third switch Q3 is also grounded via a loop filter circuit 5. A second end of the third switch Q3 outputs a clock delay signal. A control end of the third switch Q3 is connected to the output of the third inverter N3. A control end of the fourth switch Q4 is connected to the output of the second inverter N2.

[0035] Optionally, the first switch Q1 and the fourth switch Q4 are both PMOS transistors, the first end of the first switch Q1 and the second end of the fourth switch Q4 are the source of the PMOS transistor, and the second end of the first switch Q1 and the first end of the fourth switch Q4 are the drain of the PMOS transistor; the second switch Q2 and the third switch Q3 are both NMOS transistors, the second end of the second switch Q2 and the first end of the third switch Q3 are the source of the NMOS transistor, and the first end of the second switch Q2 and the second end of the third switch Q3 are the drain of the NMOS transistor.

[0036] Specifically, the operational amplifier U2 serves as the "error correction center" of the circuit and stabilizes the circuit state through a feedback mechanism: the reverse input terminal is connected to the second terminal of the first switch Q1, the first terminal of the second switch Q2, and its own output terminal, forming a negative feedback loop; the positive input terminal is connected to the second terminal of the third switch Q3 and the first terminal of the fourth switch Q4, and receives the signal from the loop filter circuit 5; the output terminal adjusts the output voltage in real time through the connection with the reverse input terminal, ensuring the stability of the signals at the positive input terminal and the reverse input terminal, and providing an accurate reference benchmark for the switching action.

[0037] Specifically, the core of the switch circuit 2 is to control the on-off state of the four switches through a pair of complementary differential signals (the in-phase signal of the second inverter N2 and the inverted signal of the third inverter N3) output by the single-ended to differential circuit 1, thereby realizing the alternating charging and discharging process: (1) When the second inverter N2 outputs a high level (the in-phase signal is valid) and the third inverter N3 outputs a low level (the inverted signal is invalid), Q1 and Q4 are turned on, and Q2 and Q3 are turned off. At this time, the current output by the charging current source 3 flows into the discharge current source 4 side through the reverse input terminal of the operational amplifier U2 and Q4. However, because Q2 is turned off, the discharge current source 4 does not work. The current actually charges the loop filter circuit 5 through the turned-on Q1 and Q4, starting the charging process.

[0038] (2) When the second inverter N2 outputs a low level (the in-phase signal is invalid) and the third inverter N3 outputs a high level (the inverted signal is valid), Q1 and Q4 are turned off, and Q2 and Q3 are turned on. At this time, the discharge current source 4 is started, and the current flows into the loop filter circuit 5 through Q2, the reverse input terminal of the operational amplifier U2, and Q3, accelerating the discharge of the energy storage element and starting the discharge process.

[0039] In this embodiment, switching circuit 2 achieves alternating charging and discharging currents by sequentially switching four switches under the control of complementary differential signals, coupled with feedback regulation from operational amplifier U2. During charging, current flows through Q1 and Q4 to store energy in loop filter circuit 5; during discharge, current flows through Q2 and Q3 to accelerate the release of stored energy. This structure ensures strict separation between the charging and discharging processes (avoiding current conflicts) while also stabilizing the circuit state through feedback from operational amplifier U2, providing a reliable hardware foundation for the precise output of clock delay signals.

[0040] In some optional embodiments, such as Figure 5As shown, the charging current source 3 includes: a fifth switch MP1 and a sixth switch MP2, wherein a first end of the fifth switch MP1 is connected to the supply voltage, a second end of the fifth switch MP1 is connected to the first end of the sixth switch MP2, and a control end of the fifth switch MP1 is connected to the first control voltage; a second end of the sixth switch MP2 is connected to the first end of the switch circuit 2, and a control end of the sixth switch MP2 is connected to the first control signal.

[0041] Optionally, the fifth switch MP1 and the sixth switch MP2 are both PMOS transistors, the first end of the fifth switch MP1 and the first end of the sixth switch MP2 are sources of the PMOS transistors, and the second end of the fifth switch MP1 and the second end of the sixth switch MP2 are drains of the PMOS transistors.

[0042] Specifically, the fifth switch MP1 serves as the "upstream control valve" of the charging current source 3. Its connection is directly related to the basic current supply: the first terminal is connected to the supply voltage, which is the energy source of the entire charging current source 3 and provides a stable voltage foundation for subsequent current output. The second terminal is connected to the first terminal of the sixth switch MP2, forming a cascade path, so that current must pass through MP1 and MP2 in sequence before flowing to the switching circuit 2. The control terminal is connected to the first control voltage, which determines the conduction level of MP1. Unlike simple on-off control, the first control voltage can precisely control the current flow by adjusting the on-resistance of MP1 (such as in a MOS transistor, where the gate voltage affects the channel resistance). This is the core link for achieving fine regulation of the charging current.

[0043] Specifically, the sixth switch MP2 acts as a "downstream switching valve" for the charging current source 3, focusing on managing the on / off state of the circuit. Its first terminal is connected to the second terminal of the fifth switch MP1, receiving the current regulated by MP1. Its second terminal is directly connected to the first terminal of the switch circuit 2, delivering the final charging current to the switch circuit 2 for subsequent charging and discharging. Its control terminal receives a first control signal, a digital logic signal (e.g., a high / low level), that directly controls the on / off state of MP2. When the first control signal is valid, MP2 conducts, establishing a path between the charging current source 3 and the switch circuit 2. When the first control signal is invalid, MP2 is off, cutting off the charging current output and ensuring that charging is initiated only when needed.

[0044] In this embodiment, charging current source 3 achieves dual control of the charging current through the cascade connection of a fifth switch MP1 (current level controlled by a first control voltage) and a sixth switch MP2 (on / off controlled by a first control signal). MP1 allows for fine-tuning of current intensity to meet varying delay accuracy requirements; MP2 also precisely controls the timing of current output to ensure coordination with the operating state of switch circuit 2. This structure balances flexible regulation with reliable control, providing solid support for precise control of the charging process in clock delay circuits.

[0045] In some optional embodiments, such as Figure 5 As shown, the discharge current source 4 includes: a seventh switch MN2 and an eighth switch MN1, wherein a first end of the seventh switch MN2 is connected to the second end of the switch circuit 2, a second end of the seventh switch MN2 is connected to the first end of the eighth switch MN1, and a control end of the seventh switch MN2 is connected to the second control signal; a second end of the eighth switch MN1 is grounded, and a control end of the eighth switch MN1 is connected to the second control voltage.

[0046] Optionally, the seventh switch MN2 and the eighth switch MN1 are both NMOS transistors, the first end of the seventh switch MN2 and the first end of the eighth switch MN1 are drains of the NMOS transistors, and the second end of the seventh switch MN2 and the second end of the eighth switch MN1 are sources of the NMOS transistors.

[0047] Specifically, the seventh switch MN2 serves as the "front-end switch" of the discharge current source 4, controlling the on / off state of the discharge path. Its first terminal is directly connected to the second terminal of the switch circuit 2, serving as the inlet for the discharge current. This means that the charge to be discharged from the switch circuit 2 must first flow through MN2. Its second terminal is connected to the first terminal of the eighth switch MN1, forming a cascade structure. This ensures that the discharge current must sequentially pass through MN2 and MN1 to complete the ground release. Its control terminal receives a second control signal, a digital logic signal (e.g., active high or active low), which directly determines the conduction state of MN2. When the second control signal is valid, MN2 conducts, providing a path for the discharge current to flow. When the second control signal is invalid, MN2 is off, severing the discharge path and ensuring that the discharge process is initiated only when needed.

[0048] Specifically, the eighth switch MN1 serves as the "back-end regulator" of the discharge current source 4, responsible for finely controlling the discharge current. Its first terminal is connected to the second terminal of the seventh switch MN2, receiving the discharge current transmitted by MN2. Its second terminal is directly connected to ground, forming the final loop of the discharge current, allowing charge to be discharged through the ground terminal. Its control terminal is connected to a second control voltage. This voltage signal continuously adjusts the discharge current by varying the conduction level of MN1 (for example, in a MOS transistor, changes in gate voltage affect the channel resistance). Different voltage values ​​result in different on-resistances of MN1, which in turn cause differences in the discharge current flowing through it.

[0049] In this embodiment, discharge current source 4 achieves on-demand start-up and rate control during the discharge process through timing control of the seventh switch MN2 and current regulation of the eighth switch MN1. Its symmetrical design with the charge current source 3 further ensures balanced regulation of the clock delay circuit in both the charge and discharge directions, providing a reliable current release mechanism for achieving stable and accurate clock signal delay. Whether rapidly discharging to shorten delay or slowly discharging to extend delay, this structure, through the coordinated operation of the two-stage switches, precisely meets the timing requirements of different scenarios.

[0050] In some optional embodiments, such as Figure 6 As shown, the loop filter circuit 5 includes: a first resistor R1 and a first capacitor C1, wherein a first end of the first resistor R1 is connected to the third end of the switch circuit 2, and a second end of the first resistor R1 is grounded through the first capacitor C1.

[0051] Specifically, the delay effect of loop filter circuit 5 stems from the charge-discharge characteristics of the RC circuit. During the charge-discharge process, the voltage across C1 changes exponentially (gradually approaching the supply voltage from 0 during charging and from the supply voltage to 0 during discharging). The voltage at the output node of the clock delay signal (i.e., the connection point between R1 and C1) must reach a specific threshold to trigger a valid signal. The charge-discharge time constant τ (τ = R1 × C1) directly determines the time it takes for the voltage to reach the threshold. A larger τ value results in a slower charge-discharge rate and a longer delay. By adjusting the parameters of R1 or C1, the τ value can be flexibly varied, thereby achieving precise control of the delay range.

[0052] When switching between charge and discharge states, the output current of switching circuit 2 may be accompanied by high-frequency noise or transient pulses. The RC structure effectively filters out these interferences. R1's blocking effect on high-frequency signals, combined with C1's bypassing properties (high-frequency signals are more easily connected to ground through capacitors), significantly attenuates the high-frequency components of the current, smoothing the voltage across C1 and preventing jitter in the delayed signal caused by noise. This filtering ensures the stability of the output clock delay signal, providing a reliable timing reference for subsequent circuits.

[0053] Specifically, the loop filter circuit 5 is connected to the switch circuit 2 through R1, becoming the "must-pass channel" for the charging and discharging current. When the charging current source 3 is working, the current flows into R1 through the switch circuit 2, and then slowly charges C1. The energy stored in C1 gradually increases, and the voltage at both ends steadily rises; when the discharging current source 4 is working, the energy stored in C1 flows to the ground through R1 and the switch circuit 2, and the voltage steadily decreases. This energy accumulation and release process is directly converted into the time delay of the voltage signal, and the parameter combination of R1 and C1 determines the rate of voltage change, which ultimately affects the accuracy and adjustable range of the clock delay signal. It can be said that the loop filter circuit 5 is a "converter" that converts current changes into time delays, and is the core carrier for the entire clock delay circuit to achieve precise delay control.

[0054] In some optional implementations, the clock delay circuit further includes: an inverting circuit, wherein a first end of the inverting circuit is connected to the first control signal, and a second end of the inverting circuit is connected to the control end of each charging current source 3 .

[0055] Alternatively, as Figure 5 As shown, the inverting circuit includes: a fourth inverter N4 , wherein the input end of the fourth inverter N4 is connected to the first control signal, and the output end of the fourth inverter N4 is connected to the control end of each charging current source 3 .

[0056] For example, consider the sixth switch MP2 in the charging current source 3 (whose control terminal requires a control signal to determine whether it is on or off). If the sixth switch MP2 is in a high-level on-state mode, and the active level of the original first control signal (i.e., the level that triggers charging) is low, directly connecting the control signal will prevent the switch from properly turning on. In this case, the inverting circuit (e.g., the fourth inverter N4) inverts the low-level first control signal to a high level, which satisfies the on-state condition for the sixth switch MP2 and ensures that the charging current source 3 can reliably start when needed.

[0057] On the contrary, if the effective level of the first control signal is consistent with the switching requirement, the introduction of the inverting circuit can also achieve "in-phase delay" through an additional level of reverse rotation - utilizing the inherent transmission delay of the inverter to fine-tune the triggering time of the control signal, so that the start of the charging current and the establishment of the path of the switching circuit 2 form a small timing difference, reducing instantaneous current shocks and improving circuit stability.

[0058] In some optional embodiments, the delay accuracy and phase consistency of multi-phase clocks in clock delay circuits are often significantly affected by environmental factors such as temperature, power supply voltage fluctuations, and chip aging. This can lead to insufficient performance stability in high-precision timing control scenarios (such as high-speed communications and precision measurement). Therefore, a real-time environmental parameter monitoring and adaptive compensation module is introduced. Specifically, the environmental parameter monitoring unit integrates a micro-temperature sensor and a voltage sensor to collect real-time temperature and power supply voltage data from the circuit's operating environment, converting these data into digital signals and transmitting them to the adaptive compensation algorithm unit. The adaptive compensation algorithm calculates the delay deviation in the current environment based on preset temperature-delay and voltage-delay characteristic curves (obtained through pre-factory calibration at multiple temperature zones and voltage points) combined with real-time monitoring data, and then generates a corresponding compensation control signal. The compensation control signal is transmitted to the programmable delay unit in the delay chain circuit, which dynamically adjusts the load capacitance or current source of the delay unit to achieve real-time calibration of the clock delay.

[0059] In this embodiment, a multi-phase clock generating device is provided. Figure 7 As shown, it includes: a phase detection circuit 6, an oscillation circuit 7 and the clock delay circuit and oscillation circuit 7 of the above embodiments and any optional implementation methods thereof. The clock delay circuit includes: a single-ended to differential circuit 1, a switching circuit 2, multiple charging current sources 3, multiple discharging current sources 4 and a loop filter circuit 5.

[0060] like Figure 7 As shown, the first input end of the phase detector circuit 6 is connected to the clock signal, the second input end of the phase detector circuit 6 is connected to the output end of the oscillation circuit 7, and the output end of the phase detector circuit 6 is connected to the input end of the single-ended to differential circuit 1; the input end of the single-ended to differential circuit 1 receives the clock signal, and the first and second output ends of the single-ended to differential circuit 1 are connected to the control end of the switch circuit 2; the input end of each charging current source 3 is connected to the supply voltage, the output end of each charging current source 3 is connected to the first end of the switch circuit 2, and the control end of each charging current source 3 is connected to the first control signal; the input end of each discharging current source 4 is connected to the second end of the switch circuit 2, the output end of each discharging current source 4 is grounded, and the control end of each charging current source 3 is connected to the second control signal; the third end of the switch circuit 2 is grounded through the loop filter circuit 5, and the third end of the switch circuit 2 is connected to the input end of the oscillation circuit 7; the output end of the oscillation circuit 7 outputs a multi-phase clock signal; within a control cycle, the first control signal and the second control signal are complementary.

[0061] Specifically, phase detector circuit 6 serves as the device's "signal comparison center." Its first input is specifically connected to the external reference clock signal, and its second input is connected to the output of oscillator circuit 7, receiving the feedback signal from oscillator circuit 7. By comparing the phase difference between these two signals, phase detector circuit 6 generates a corresponding error control signal, which is then transmitted from its output to the input of single-ended-to-differential converter 1 in the clock delay circuit. This connection creates a closed loop of "reference input - feedback comparison - error output," ensuring that the device can adjust the operating state of the delay circuit in real time based on the phase deviation of the output signal.

[0062] Specifically, oscillator circuit 7 serves as the device's "multi-phase signal generator." Its input receives the delayed signal from the clock delay circuit. Using an internal oscillation mechanism (such as a ring oscillator or LC oscillator), it converts the single delayed signal into a multi-phase clock signal, which is then output from its output. Simultaneously, the output of oscillator circuit 7 is connected to the second input of phase detector circuit 6, providing signal feedback. This allows phase detector circuit 6 to continuously monitor the phase state of the output signal, providing a basis for adjusting the delay circuit.

[0063] Specifically, Figure 7 In the embodiment, the phase detection circuit 6 and the clock delay circuit form a PLL loop, and the frequency of the oscillation circuit 7 is locked to the input clock frequency by the PLL loop. Since the input and output frequencies are equal, a sufficiently wide loop bandwidth can be obtained at a high clock frequency, thereby significantly suppressing the phase noise of the ring oscillator, achieving low jitter, and maintaining low power consumption of the ring oscillator. At the same time, the problem of phase interval mismatch caused by injection locking can be avoided.

[0064] In some optional embodiments, such as Figure 8 As shown, the phase detection circuit includes: an XOR gate U3, wherein the first input end of the XOR gate U3 is connected to the clock signal, the second input end of the XOR gate U3 is connected to the output end of the oscillation circuit 7, and the output end of the XOR gate U3 is connected to the input end of the single-ended to differential circuit 1. It should be noted that Figure 8 The internal structure of the medium current adjustable charge pump is as follows Figure 7 As shown, the current adjustable charge pump is composed of a single-ended to differential circuit 1, a charging current source 3, a discharging current source 4 and a switching circuit 2.

[0065] refer to Figure 8 The entire multi-phase clock generation circuit is composed of a PLL based on the XOR gate U3, including the XOR gate U3, the charge pump circuit, the loop filter circuit 5, and the oscillation circuit 7. Through the PLL, the output multi-phase clock is locked to the frequency of the input single-phase clock, thus achieving multi-phase clock generation.

[0066] Specifically, when the phase of the feedback signal output by the oscillation circuit 7 lags behind the reference clock signal, the width of the high-level pulse output by the XOR gate U3 will increase as the lag angle increases. After this signal is transmitted to the clock delay circuit, it will trigger the charging current source 3 to increase the charging current (or the discharging current source 4 to reduce the discharging current), speeding up the charging and discharging speed of the loop filter circuit 5, thereby shortening the delay time and pushing the output phase of the oscillation circuit 7 forward until it is consistent with the phase of the reference clock signal.

[0067] In some optional embodiments, such as Figure 8 As shown, the charge pump in the PLL includes a charging current I UP and discharge current I DN When the output of the XOR gate U3 is high, the charge pump charges the loop filter circuit 5; when the output of the XOR gate U3 is low, the charge pump discharges the loop filter circuit 5. Assume that the high-level pulse width of the output signal of the XOR gate U3 is τ UP , the low level pulse width is τ DN , then, when the PLL is locked, the following conditions must be met: (1) (2) When the PLL is locked and I UP =I DN When τ UP =τ DN =T CK / 4, where TCK is the period of the output and input clocks (the input and output clocks are of the same frequency). According to the lock timing of the PLL of the XOR gate U3, the delay difference between the rising edge of the input clock and the next rising edge of the feedback clock when the PLL is locked is τ UP .

[0068] If I change UP and I DN According to formulas (1) and (2), we can know that τ UP and τ DN will change, that is, the delay of the output multi-phase clock can be changed synchronously with the input clock, thereby achieving synchronous and adjustable multi-phase clock delay, and there will be no mismatch in the delay of clocks of different phases. According to formulas (1) and (2), we can get τ UP and τ DN The expression is as follows.

[0069] (3) (3) It can be seen that by controlling I UP and I DNThe ratio between them can be adjusted UP and τ DN , thereby controlling the delay of the output multi-phase clock.

[0070] In some optional embodiments, such as Figure 9 As shown, the oscillation circuit 7 includes: a ninth switch Q9 and at least one differential unit 71, wherein a first end of the ninth switch Q9 is connected to the third end of the switch circuit 2, a second end of the ninth switch Q9 is connected to the input end of the differential unit 71, and a control end of the ninth switch Q9 inputs a tuning voltage; and an output end of the differential unit 71 outputs a multi-phase clock signal.

[0071] Specifically, the ninth switch Q9 serves as the "input control valve" for oscillator circuit 7. Its first terminal is directly connected to the third terminal of switch circuit 2, receiving the delayed signal from the clock delay circuit. This signal, smoothed by loop filter circuit 5, serves as the reference for oscillator circuit 7 to generate the multi-phase clock. Its second terminal is connected to the input of differential unit 71, forming a signal transmission link from "delayed signal → ninth switch Q9 → differential unit 71," ensuring stable input of the delayed signal to the oscillator core. A tuning voltage is applied to the control terminal, which adjusts the signal strength input to differential unit 71 by altering the conduction characteristics of Q9 (e.g., the channel resistance of the MOS transistor). For example, when the tuning voltage increases, Q9's on-resistance decreases, transferring more energy to differential unit 71 and increasing the oscillation frequency. When the tuning voltage decreases, the on-resistance increases, weakening energy transfer and reducing the oscillation frequency. This design enables oscillator circuit 7 to flexibly adjust the output clock frequency within a certain range, adapting to the timing requirements of different scenarios.

[0072] Specifically, the differential unit 71 is the "core oscillator" that generates the multi-phase clock in the oscillation circuit 7. Its number can be flexibly adjusted based on the desired number of phases (for example, two differential units 71 can be cascaded to generate a four-phase clock). Each differential unit 71 typically consists of a pair of complementary amplifiers and a load element (such as a resistor or current source), and performs differential signal amplification and phase shifting. Its input is connected to the second end of the ninth switch Q9 and receives a tuned delayed signal, which serves as the starting excitation for the differential unit 71 and triggers its internal oscillation mechanism. The output can directly output a differential clock signal. Multiple differential units 71 can be cascaded or arranged in a phase-staggered arrangement to generate a multi-phase clock with a fixed phase difference. For example, a single differential unit 71 outputs a two-phase quadrature signal (0° and 180°). Two differential units 71 can be cascaded to generate a four-phase signal (0°, 90°, 180°, and 270°) with strictly equal phase differences, ensuring the timing consistency of the multi-phase clock.

[0073] In some optional embodiments, such as Figure 9As shown, the differential unit 71 includes: a first main inverter INV1, a second main inverter INV2, a first cross-coupled inverter INV3, and a second cross-coupled inverter INV4. The input terminal of the first main inverter is connected to the second terminal of the ninth switch Q9, the output terminal of the first main inverter is connected to the input terminal of the first cross-coupled inverter and the output terminal of the second cross-coupled inverter, and the output terminal of the first main inverter outputs a one-phase clock signal; the input terminal of the second main inverter is connected to the second terminal of the ninth switch Q9, the output terminal of the second main inverter is connected to the output terminal of the first cross-coupled inverter and the input terminal of the second cross-coupled inverter, and the output terminal of the second main inverter outputs the other-phase clock signal.

[0074] In a practical application scenario, based on Figure 4 、 Figure 5 、 Figure 8 、 Figure 9 The process of obtaining the multi-phase clock signal in this embodiment is as follows: (1) Taking the 1 / 4 rate D2D interconnection interface as an application scenario, a multi-phase clock circuit with a four-phase clock and a delay adjustment range of TCK / 4 (i.e., the length of one data symbol) needs to be implemented. The overall architecture is as follows: Figure 8 As shown, it includes an XOR gate U3, a current-adjustable charge pump circuit, a loop filter circuit 5 and an oscillation circuit 7. The oscillation circuit 7 is a four-phase voltage-controlled ring oscillator (VCO), that is, the input single-phase or differential clock is converted into a four-phase clock with the same frequency through the PLL, and the delay relationship between the output clock and the input clock can be tuned.

[0075] (2) The cascade gain expression of the XOR gate U3 and the charge pump circuit is K XOR-CP =(I UP +I DN ) / π, from which we can know that the loop bandwidth expression of PLL is f BW =K XOR-CP R1K VCO .K VCO is the tuning gain of the VCO, which can be determined by simulation. In order to significantly suppress the phase noise of the ring oscillator, f BW It needs to be as large as possible, taking into account the stability of the system. BW It can be selected as 1 / 10 of the clock frequency. BW and K VCO After that, determine R1 and C1 to ensure that the loop zero is less than f BW 1 / 3 of the current, thus maintaining the loop stability. The larger R1 is, the smaller 1C is. UP +I DN ) will be smaller, but the jitter will increase, so a compromise is needed. After determining R1 and C1, you can determine (IUP +I DN ).

[0076] (3) The charge pump circuit in PLL is as follows Figure 5 As shown in the figure, the charge pump uses a current steering structure, ensuring that the current source in the charge pump is always in the on state, thereby enabling rapid switching between charging and discharging currents, meeting the requirements of high-speed D2D application scenarios. Since the charge pump with a current steering structure requires a differential phase detector output signal to switch between two complementary current paths, and the output of XOR gate U3 is a single-ended signal, a single-ended to differential conversion module is required to convert the single-ended pulses output by the phase detector into differential pulses to control the charge pump.

[0077] (4) The charging current and discharging current of the charge pump are both composed of multiple gated current source units. The discharging current source 4 unit is composed of a current source transistor MN1 and a switch tube MN2 working in the saturation region, and the charging current source 3 unit is composed of a current source transistor MP1 and a switch tube MP2 working in the saturation region. The switch control signal bit SWP of the charging current and the switch control signal bit SWN of the discharging current are set to a complementary relationship, that is, each time a charging current source 3 unit is turned on, a discharging current source 4 unit is turned off, and vice versa, so that (I UP +I DN ), thereby maintaining a constant loop bandwidth and ensuring that the PLL can operate stably under different delays.

[0078] (5) The four-phase ring oscillator in PLL is as follows Figure 9 As shown. The ring oscillator is constructed using two differential units 71, enabling it to output a four-phase clock. Each differential unit 71 consists of a main inverter (i.e., INV1) and a cross-coupled inverter (i.e., INV2). INV2 is used to ensure that the two-stage ring oscillator can start oscillating and that the input and output signals of each stage are differential. The ring oscillator uses a current source formed by a PMOS transistor MP to convert its tuning voltage VC into a current to tune the VCO frequency. The operating frequency is adjusted by adjusting the aspect ratio of the transistors INV1 and INV2, as well as the ratio of their aspect ratios.

[0079] The above is a detailed introduction to a clock delay circuit and a multi-phase clock generation device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A clock delay circuit, characterized in that: include: A single-ended to differential circuit, a switch circuit, multiple charging current sources, multiple discharging current sources and a loop filter circuit, wherein: An input end of the single-ended to differential conversion circuit receives a clock signal, and a first output end and a second output end of the single-ended to differential conversion circuit are connected to a control end of the switch circuit; An input terminal of each of the charging current sources is connected to a supply voltage, an output terminal of each of the charging current sources is connected to a first terminal of the switch circuit, and a control terminal of each of the charging current sources is connected to a first control signal; The input end of each of the discharging current sources is connected to the second end of the switching circuit, the output end of each of the discharging current sources is grounded, and the control end of each of the charging current sources is connected to a second control signal; The third end of the switch circuit is grounded through the loop filter circuit, and the third end of the switch circuit outputs a clock delay signal; In one control cycle, the first control signal and the second control signal are complementary.

2. The clock delay circuit according to claim 1, wherein: The single-ended to differential circuit includes: a first inverter, a second inverter, a third inverter and a transmission gate, wherein: The input end of the first inverter is connected to the input end of the transmission gate, the input end of the first inverter is also connected to the clock signal, and the output end of the first inverter is connected to the input end of the second inverter; The output terminal of the second inverter is connected to the control terminal of the switch circuit; The input end of the third inverter is connected to the input end of the transmission gate, and the output end of the third inverter is connected to the control end of the switch circuit.

3. The clock delay circuit according to claim 2, wherein: The switch circuit includes: a first switch, a second switch, a third switch, a fourth switch and an operational amplifier, wherein: A first end of the first switch is connected to the output end of each of the charging current sources and the first end of the third switch, a second end of the first switch is connected to the first end of the second switch, the output end of the operational amplifier, and the inverting input end of the operational amplifier, and a control end of the first switch is connected to the output end of the second inverter; The second end of the second switch is connected to the input end of each of the discharge current sources and the second end of the fourth switch, and the control end of the second switch is connected to the output end of the third inverter; The second end of the third switch is connected to the positive input end of the operational amplifier and the first end of the fourth switch, the second end of the third switch is also grounded through the loop filter circuit, the second end of the third switch outputs a clock delay signal, and the control end of the third switch is connected to the output end of the third inverter; The control end of the fourth switch is connected to the output end of the second inverter.

4. The clock delay circuit according to claim 3, wherein: The first switch and the fourth switch are both PMOS transistors, the first end of the first switch and the second end of the fourth switch are sources of the PMOS transistors, and the second end of the first switch and the first end of the fourth switch are drains of the PMOS transistors; The second switch and the third switch are both NMOS transistors, the second end of the second switch and the first end of the third switch are sources of the NMOS transistors, and the first end of the second switch and the second end of the third switch are drains of the NMOS transistors.

5. The clock delay circuit according to claim 1, wherein: The charging current source includes a fifth switch and a sixth switch, wherein: A first end of the fifth switch is connected to the power supply voltage, a second end of the fifth switch is connected to the first end of the sixth switch, and a control end of the fifth switch is connected to the first control voltage; The second end of the sixth switch is connected to the first end of the switch circuit, and the control end of the sixth switch is connected to the first control signal.

6. The clock delay circuit according to claim 5, characterized in that: The fifth switch and the sixth switch are both PMOS transistors, the first end of the fifth switch and the first end of the sixth switch are sources of the PMOS transistors, and the second end of the fifth switch and the second end of the sixth switch are drains of the PMOS transistors.

7. The clock delay circuit according to claim 1, wherein: The discharge current source includes a seventh switch and an eighth switch, wherein: The first end of the seventh switch is connected to the second end of the switch circuit, the second end of the seventh switch is connected to the first end of the eighth switch, and the control end of the seventh switch is connected to the second control signal; A second terminal of the eighth switch is grounded, and a control terminal of the eighth switch is connected to a second control voltage.

8. The clock delay circuit according to claim 7, wherein: The seventh switch and the eighth switch are both NMOS transistors, the first end of the seventh switch and the first end of the eighth switch are drains of the NMOS transistors, and the second end of the seventh switch and the second end of the eighth switch are sources of the NMOS transistors.

9. The clock delay circuit according to claim 1, wherein: The loop filter circuit includes: a first resistor and a first capacitor, wherein: A first end of the first resistor is connected to the third end of the switch circuit, and a second end of the first resistor is grounded through the first capacitor.

10. The clock delay circuit according to claim 1, wherein: Also includes: Inverting circuit, where A first terminal of the inverting circuit is connected to a first control signal, and a second terminal of the inverting circuit is connected to a control terminal of each of the charging current sources.

11. The clock delay circuit according to claim 10, wherein: The inverting circuit includes: a fourth inverter, wherein: An input terminal of the fourth inverter is connected to the first control signal, and an output terminal of the fourth inverter is connected to a control terminal of each of the charging current sources.

12. A multi-phase clock generating device, characterized in that: include: A phase detection circuit, an oscillation circuit, and a clock delay circuit and an oscillation circuit as described in any one of claims 1 to 11, wherein the clock delay circuit comprises: a single-ended to differential circuit, a switch circuit, multiple charging current sources, multiple discharging current sources, and a loop filter circuit, wherein: The first input end of the phase detector circuit is connected to the clock signal, the second input end of the phase detector circuit is connected to the output end of the oscillation circuit, and the output end of the phase detector circuit is connected to the input end of the single-ended to differential converter circuit; An input end of the single-ended to differential conversion circuit receives a clock signal, and a first output end and a second output end of the single-ended to differential conversion circuit are connected to a control end of the switch circuit; An input terminal of each of the charging current sources is connected to a supply voltage, an output terminal of each of the charging current sources is connected to a first terminal of the switch circuit, and a control terminal of each of the charging current sources is connected to a first control signal; The input end of each of the discharging current sources is connected to the second end of the switching circuit, the output end of each of the discharging current sources is grounded, and the control end of each of the charging current sources is connected to a second control signal; The third end of the switch circuit is grounded through the loop filter circuit, and the third end of the switch circuit is connected to the input end of the oscillation circuit; The output end of the oscillation circuit outputs a multi-phase clock signal; In one control cycle, the first control signal and the second control signal are complementary.

13. The multi-phase clock generating device according to claim 12, wherein: The phase detection circuit includes: an XOR gate, wherein: The first input end of the XOR gate is connected to the clock signal, the second input end of the XOR gate is connected to the output end of the oscillation circuit, and the output end of the XOR gate is connected to the input end of the single-ended to differential circuit.

14. The multi-phase clock generating device according to claim 12, wherein: The oscillation circuit includes: a ninth switch and at least one differential unit, wherein: The first end of the ninth switch is connected to the third end of the switch circuit, the second end of the ninth switch is connected to the input end of the differential unit, and the control end of the ninth switch inputs the tuning voltage; The output end of the differential unit outputs a multi-phase clock signal.

15. The multi-phase clock generating device according to claim 14, wherein: The differential unit includes: a first main inverter, a second main inverter, a first cross-coupled inverter and a second cross-coupled inverter, wherein: The input end of the first main inverter is connected to the second end of the ninth switch, the output end of the first main inverter is connected to the input end of the first cross-coupled inverter and the output end of the second cross-coupled inverter, and the output end of the first main inverter outputs a single-phase clock signal; The input end of the second main inverter is connected to the second end of the ninth switch, the output end of the second main inverter is connected to the output end of the first cross-coupled inverter and the input end of the second cross-coupled inverter, and the output end of the second main inverter outputs another phase clock signal.

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