A gate driver and power device

Abstract

The application relates to the technical field of power semiconductors, and discloses a gate driver and a power device, wherein the gate driver is connected to a power tube and comprises a comparator, a pull-down switch tube, a first path and a second path; the source of the pull-down switch tube is grounded, and the drain is connected to the gate of the power tube; the first path is provided with an inverter and a MOS tube, and is adapted to respond to a high-level signal; the first path provides a charging current to the gate of the pull-down switch tube through the inverter and the MOS tube; the second path is provided with a MOS tube and a diode, and the second path directly transfers part of the charge stored on the gate of the power tube to the gate of the pull-down switch tube. Thus, the gate driver controls the gate of the pull-down switch tube and realizes charge transfer based on the first path and the second path, so that the gate voltage is rapidly pulled down without increasing static power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor, in particular to a gate driver and a power device. BACKGROUND

[0002] In power electronic systems, the gate driver of power devices such as Si-based MOSFET (Silicon Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and wide-bandgap semiconductors GaN, SiC is the core module to ensure its efficient and reliable switching. The pull-down capability directly determines the turn-off speed, anti-interference and safety of the device.

[0003] However, in the process of pursuing energy efficiency optimization, the traditional low-power consumption driving architecture often reduces static loss by reducing driving current or simplifying negative voltage circuit, resulting in significant degradation of pull-down capability, which is specifically manifested as increased turn-off delay, intensified gate voltage oscillation, and even triggered false turn-on risk. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings of the prior art and provide a gate driver with low power consumption and good pull-down capability.

[0005] In a first aspect, the application discloses a gate driver connected to a power tube, comprising: a comparator, a pull-down switch tube, a first path and a second path; the comparator is used to respond to a turn-off signal and output a high-level signal; the source of the pull-down switch tube is grounded, and the drain is connected to the gate of the power tube; the first path is provided with an inverter and a MOS tube M2, and is adapted to respond to the high-level signal, the first path provides a charging current to the gate of the pull-down switch tube through the inverter and the MOS tube M2; the second path is provided with a MOS tube M1 and a diode, and the second path directly transfers part of the charge stored on the gate of the power tube to the gate of the pull-down switch tube.

[0006] The gate driver of the present application controls the gate of the pull-down switch tube and realizes charge transfer based on the first path and the second path, thereby realizing rapid pull-down of the gate voltage without the need for series connection of multiple inverters and without increasing static power consumption, while maintaining low power consumption and realizing high pull-down capability.

[0007] Furthermore, the inverter includes: a first inverter and a second inverter composed of MOSFETs M2 and M3, and is adapted to charge and discharge the gate of the pull-down transistor after receiving the output signal of the first inverter; one end of the first resistor is connected to the drain of the MOSFET M3, and the other end is connected to the gate of the pull-down switch transistor; when the high-level signal is received, the MOSFET M2 is turned on and the MOSFET M3 is turned off, forming a charging circuit for the gate-source capacitance of the pull-down switch transistor through the second inverter.

[0008] Furthermore, the gate of the MOSFET M1 directly receives the high-level signal, and its source is connected to the gate of the pull-down switch. The anode of the diode is connected to the gate of the power transistor, and its cathode is connected to the drain of the MOSFET M1. When the high-level signal is received, the MOSFET M1 is turned on, and a low-resistance channel is formed between the gate of the power transistor and the gate of the pull-down switch. The diode is in a forward bias state, so that part of the charge on the gate of the power transistor is directly injected into the gate of the pull-down switch through the MOSFET M1.

[0009] Furthermore, it also includes a second resistor connected between the gate of the pull-down switch and ground. The second resistor is used to maintain the gate of the pull-down switch close to ground potential in the inactive state.

[0010] Furthermore, the pull-down switch is an N-channel MOSFET.

[0011] Furthermore, when the gate voltage of the power transistor is higher than the sum of the gate-source voltage of the pull-down switch and the forward voltage drop of the diode, the diode remains forward biased, and the second path continues to transfer the charge of the power transistor gate to the gate of the pull-down switch.

[0012] Secondly, this application discloses a power device, comprising: the gate driver and the power transistor, wherein the gate driver is connected to the gate of the power transistor to control its on / off state. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a gate driver circuit according to some embodiments of this application;

[0014] Figure 2 This is a partial circuit diagram of a power device according to some embodiments of this application;

[0015] In the diagram: 100 - gate driver, 11 - first inverter, 12 - comparator. Detailed Implementation

[0016] The technical solutions of the present application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of the present application.

[0017] First, some professional terms are explained.

[0018] Pull-down capability: the ability to quickly and stably reduce the gate voltage of a power device from above the working threshold to below the off threshold through an internal discharge loop or an external auxiliary circuit.

[0019] Comparator: a circuit or device that can compare two or more data items to determine if they are equal, with the output control signal including a high-level signal and a low-level signal.

[0020] ‌ Figure 1 VDD2 represents the power supply voltage.

[0021] Next, refer to Figures 1-2 , understand the gate driver 100 and the power device disclosed in the embodiments of the present application.

[0022] In high-speed power conversion systems such as server power supplies, motor drives, or high-frequency DC-DC converters, the switching speed of power MOSFETs directly affects the efficiency and reliability of the system. Switching loss is proportional to switching time, especially during the off process. If the gate charge of the power tube cannot be quickly extracted, its slow off process not only produces significant overlap loss, but also may cause bridge arm shoot-through and other situations.

[0023] Traditional solutions rely on a series of inverter chains to increase the pull-down driving capability, but each inverter introduces additional delay and static power consumption; if you want to maintain low power consumption, it is difficult to achieve good pull-down capability.

[0024] Therefore, the embodiments of the present application disclose a gate driver 100 connected to a power tube (such as M5), as shown in Figures 1-2 , including a comparator 12, a pull-down switch tube and a first path, a second path. Figure 2 In it, VDD1 and VDD2 are both power supplies, GATE is a gate signal, and POWER is a direct representation that the power tube M5 can serve as an energy source.

[0025] The comparator 12 is used to output a high-level signal in response to an off signal, such as Figure 1The output high level signal V1 is input to the gate of the pull-down switch tube, and the source of the pull-down switch tube is grounded, and the drain is connected to the gate of the power tube (e.g. M5). Here, the off signal is a signal received to turn off the driver, which can be in any form.

[0026] The first path is adapted to provide a charging current to the gate of the pull-down switch tube (e.g. M4) through the second inverter composed of MOS tube M2 and MOS tube M3 in response to the high level signal output by the comparator 12; in some examples, the first path only provides two inverters, i.e. the first inverter 11 and the second inverter composed of MOS tube M2 and MOS tube M3; it can be understood that the MOS tube M2 and the MOS tube M3 are actually used to realize the function of the inverter, which is different from the prior art in which multiple inverters are connected in series. For details, please refer to Figure 1 and based on subsequent examples.

[0027] The second path is adapted to directly transfer part of the charge stored on the gate of the power tube (e.g. M5) to the gate of the pull-down switch tube (e.g. M4) through the MOS tube (e.g. M1) and the diode (e.g. D1) in response to the high level signal output by the comparator 12. Thus, the first path and the second path work together to accelerate the rise of the gate voltage of the pull-down switch tube (e.g. M4), thereby enhancing its pull-down capability on the gate of the power tube (e.g. M5).

[0028] It can be understood that the gate driver 100 of the embodiment of the present application controls the gate of the pull-down switch tube and realizes charge transfer based on the first path and the second path, thereby realizing rapid pull-down of the gate voltage without the need for connecting multiple inverters in series and without increasing static power consumption, while maintaining low power consumption and achieving high pull-down capability.

[0029] Next, with Figure 2 For example, when the comparator 12 detects a signal (outputting a high level signal) that requires the power tube M5 to be turned off, the drive circuit is activated, and its goal is to charge the gate capacitance of the power tube M5.

[0030] For example, M4 is an N-channel MOS tube, MOS tube M2 and MOS tube M3 form a second inverter, MOS tube M2 is a P-channel MOS tube, MOS tube M3 is an N-channel MOS tube, and MOS tube M1 is an N-channel MOS tube.

[0031] As Figure 1The one end of the resistor R1 is connected to the drain of the MOS transistor M3, and the other end is connected to the gate of the MOS transistor M4. The one end of the resistor R2 is connected to the gate of the MOS transistor M4, and the other end is connected to the ground. The drain of the MOS transistor M1 is connected to the gate of the MOS transistor M5 through the diode D1. The source of the MOS transistor M1 is connected to the gate of the MOS transistor M4. The MOS transistor M2 and the MOS transistor M3 form a second inverter and are connected to the gate of the MOS transistor M4. The input of the driver is connected to the gate of the MOS transistor M1, and is connected to the gates of the MOS transistor M2 and the MOS transistor M3 through the first inverter 11. Therefore, there are only two inverters in the example, and there is no problem of increasing power and delay caused by setting multiple inverters.

[0032] When the comparator 12 outputs a high level, it means that the gate of the power transistor M5 needs to be pulled down to the ground. When the comparator 12 outputs a low level, the driving circuit does not work. The resistor R2 is a pull-down resistor, which ensures that the gate of the MOS transistor M4 is at a low level, preventing the driving circuit from working due to interference.

[0033] Specifically, in operation, the pull-down transistor M4 is turned on, and the gate of the pull-down MOS transistor M4 is charged through two paths. The first path includes the first inverter 11, the MOS transistor M2 and the MOS transistor M3 (which form a second inverter). The second path is composed of the diode D1 and the MOS transistor M1. Thus, by directly extracting the charge stored in the gate of the power transistor M5, the gate of the pull-down MOS transistor M4 is charged through two paths at the same time, thereby increasing the pull-down capability of the pull-down MOS transistor M4.

[0034] In detail, when the comparator 12 outputs a high level, the comparator 12 outputs a high level signal to the first path. In the first path:

[0035] The high level signal acts on the gates of the MOS transistor M2 and the MOS transistor M3. The signal is converted to a low level signal by the first inverter 11 and applied to the gates of the MOS transistor M2 and the MOS transistor M3. Then, the MOS transistor M2 enters the on state because the gate receives a low level signal, and the on path is from the power voltage VDD2 to the gate of the MOS transistor M4. At the same time, the MOS transistor M3 remains in the off state because the gate receives the same low level signal. The circuit configuration realizes the charging path of the gate capacitor of the MOS transistor M4 through the conduction of the MOS transistor M2, thereby establishing the gate bias voltage of the MOS transistor M4.

[0036] Correspondingly, the high level outputted by the comparator 12 directly acts on the gate of the MOS transistor M1 to enter the second path to transfer the charge and make the MOS transistor M1 immediately conductive. In the second path, the source of the MOS transistor M1 is connected to the gate of the MOS transistor M4, and the drain is connected to the gate of the power transistor M5 through the diode D1. In this way, when the MOS transistor M1 is conductive, the gate of the power transistor M5 stores high charge (corresponding to its conductive state) with high voltage, and the initial voltage of the gate of the MOS transistor M4 is close to the ground (maintained through R2), the MOS transistor M1 is conductive to form a low resistance channel between its drain and source, and the diode D1 is in a forward bias state at the corresponding moment.

[0037] Therefore, the circuit directly uses the charge stored on the gate of the power transistor M5 to be released as an energy source to accelerate the opening of the switch M4 responsible for pulling down it, so that part of the charge of the gate of M5 is not slowly released to the ground, but is directly extracted and injected into the gate capacitor of M4; in this way, the directly injected charge raises the gate voltage of M4 at a speed far exceeding that of charging through the MOS transistor M2 only, so that M4 reaches a strong opening state faster, and part of the charge of the gate of M5 has been transferred and consumed before M4 is completely opened.

[0038] Further, the first path and the second path cooperate to form positive feedback, that is, as described in the above embodiment, in the initial stage, the first path and the second path inject charge into the gate capacitor of M4 at the same time, and the gate voltage of M4 starts to rise.

[0039] When M4 starts to pull down the gate voltage of M5, the gate voltage of M4 starts to drop; however, as long as the gate voltage of M5 is still significantly higher than the sum of the gate-source voltage of M4 and the forward conduction voltage drop of the diode D1, the diode D1 is kept in a forward bias state at this time, so that the drop of the gate voltage of M5 continues to deliver charge to the gate capacitor of M4 to continue to raise the gate voltage of M4. The higher gate voltage means that the conductive resistance of M4 is smaller, and the pull-down ability is stronger, so that the gate voltage of M5 can be pulled down at a faster speed.

[0040] According to an embodiment of the present application, a power device includes the gate driver 100 described in the above embodiment and the power transistor, and the gate driver 100 is connected to the gate of the power transistor to control the on-off of the power transistor. Figure 2 The power device shown can be any component or device provided with the gate driver 100.

[0041] The foregoing is considered as illustrative only of the principles of the application. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the application to the exact construction and operation described. Accordingly, all such variations are intended to be included within the scope of the present application as defined in the claims below and their equivalents.

Claims

1. A gate driver connected to a power transistor, characterized by, Comprising: a comparator for outputting a high level signal in response to an off signal; a pull-down switch tube, the source of which is connected to ground, and the drain of which is connected to the gate of the power tube; a first path provided with an inverter and a MOS tube, the inverter comprising a first inverter and a second inverter composed of MOS tube M2 and MOS tube M3, and at least one of the MOS tube M2 and the MOS tube M3 has an output terminal of the first inverter and is adapted to receive the output signal of the first inverter to charge and discharge the gate of the pull-down tube; the first path is adapted to respond to the high level signal, and the first path provides a charging current to the gate of the pull-down switch tube through the inverter and the MOS tube; and a second path provided with MOS tube M1 and a diode, the gate of the MOS tube M1 directly receives the high level signal, and the source is connected to the gate of the pull-down switch tube; the anode of the diode is connected to the gate of the power tube, and the cathode is connected to the drain of the MOS tube M1, and the second path directly transfers part of the charge stored on the gate of the power tube to the gate of the pull-down switch tube; wherein the first path and the second path cooperatively form positive feedback, the first path and the second path simultaneously inject charge into the gate capacitor of the pull-down switch tube, so that the gate voltage of the pull-down switch tube rises, and when the gate voltage of the power tube is higher than the sum of the gate-source voltage of the pull-down switch tube and the forward voltage drop of the diode, the diode is kept in forward bias, and the second path continues to transfer the charge of the power tube gate to the gate of the pull-down switch tube.

2. The gate driver of claim 1, wherein, The inverter further comprises: a first resistor, one end of which is connected to the drain of the MOS tube M3, and the other end is connected to the gate of the pull-down switch tube; when receiving the high level signal, the MOS tube M2 is turned on and the MOS tube M3 is turned off, forming a charging loop for the gate-source capacitor of the pull-down switch tube through the second inverter.

3. The gate driver of claim 1 or 2, wherein when the second path receives the high level signal, the MOS tube M1 is turned on and a low resistance channel is formed between the gate of the power tube and the gate of the pull-down switch tube, and the diode is in a forward bias state, so that part of the charge of the power tube gate is directly injected into the gate of the pull-down switch tube through the MOS tube M1.

4. The gate driver of claim 1, wherein, Further comprising a second resistor connected between the gate of the pull-down switch tube and ground, the second resistor being used to maintain the gate of the pull-down switch tube close to ground potential in a non-activated state.

5. The gate driver of claim 1, wherein, The pull-down switch tube is an N-channel MOS tube.

6. The gate driver of claim 1, wherein, When the gate voltage of the power tube is higher than the sum of the gate-source voltage of the pull-down switch tube and the forward voltage drop of the diode, the diode is kept in forward bias, and the second path continues to transfer the charge of the power tube gate to the gate of the pull-down switch tube.

7. A power device, characterized by Comprising: The gate driver of any one of claims 1-6, connected to the gate of the power tube to control its on-off.

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