Level conversion circuit and chip

Abstract

The invention discloses a level conversion circuit and a chip. In the level conversion circuit, a signal receiving module is used for transmitting a first signal to a level conversion module; the enabling control module is used for closing an enabling function when the control signal is in a first state, and switching on the second power supply voltage when the control signal is in a second state, so that the input end of the first phase inverter is in a high level, and the output end of the first phase inverter is in a low level; and the level conversion module is used for performing level conversion on the first signal when the enabling function of the enabling control module is closed so as to output a second signal adaptive to a second power domain. The function of the level conversion circuit can be perfected, and the application flexibility of the level conversion circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a level conversion circuit and chip. Background Art

[0002] In low-power chip design, signal communication delivery across power domains is often required. When communicating signals across power domains, a level conversion circuit is required to enable the electrical signal of one power domain to be processed through level conversion and output to adapt to the electrical signal of another power domain. When a low-power design requires a power domain to be powered off, this level conversion circuit also needs to be able to send a fixed clamping value to the normally-on power domain to ensure signal stability, correct functionality, and normal power consumption. Traditional solutions can achieve the above-mentioned level conversion function through the following two circuits: One circuit is a traditional level conversion circuit with an output clamping value placed in the normally-on power domain. This circuit is required to be placed only in the normally-on power domain due to power supply reasons. However, because it can only be placed in the normally-on power domain, it has considerable limitations on back-end design implementation and physical integration, such as Figure 1a As shown, module A is used as a power-off module, and module B is used as another power domain module that is normally open. The signal from module A to module B must be added with a level conversion circuit with a clamping value ( Figure 1a All ELSs can either be placed in module B or a separate physical area needs to be opened up in module A to set up the level conversion circuit; another circuit is a level conversion circuit with output clamping value that can be placed in the power off area (i.e. module A), for example, Figure 1b However, this circuit currently only clamps the output to "1" and does not have a "0" output. When a chip design encounters a more complex low-power design where two functional modules are independently powered on and off and communicate directly with each other, using this traditional level shifter circuit not only encounters limitations and difficulties in physical implementation, such as demarcating independent power domains, but also encounters the problem of not being able to clamp the output to 0 when the power is turned off, as required by the functional design. Therefore, traditional level shifters have limitations in their application. Summary of the Invention

[0003] In view of this, the present application provides a level conversion circuit and chip to solve the problem that traditional level conversion circuits have limitations in application.

[0004] The present application provides a level conversion circuit, which includes a signal receiving module, an enable control module, a level conversion module and a first inverter; The first end of the signal receiving module is used to receive the first signal corresponding to the first power domain, and the second end is connected to the first end of the level conversion module; the first end of the enable control module is used to receive the control signal, the second end is used to receive the second power supply voltage corresponding to the second power domain, and the third end is respectively connected to the second end of the level conversion module and the input end of the first inverter; the third end of the level conversion module is grounded; the control signal is characterized as a first state when the first signal is in a stable state, and is characterized as a second state when the first signal is in a power-off state; The signal receiving module is used to transmit the first signal to the level conversion module; The enable control module is configured to disable the enable function when the control signal is in a first state, and to connect the second power supply voltage when the control signal is in a second state, so that the input end of the first inverter is at a high level and the output end of the first inverter is at a low level; The level conversion module is configured to perform level conversion on the first signal when the enable function of the enable control module is turned off, so as to output a second signal adapted to the second power domain.

[0005] Optionally, the second state includes a low level; the enable control module includes a buffer and a first transistor; the input end of the buffer serves as the first end of the enable control module, the output end is connected to the gate of the first transistor, the source of the first transistor serves as the second end of the enable control module, and the drain serves as the third end of the enable control module; the buffer is used to transmit the control signal to the gate of the first transistor; the first transistor is used to turn on when the control signal is at a low level to turn on the second power supply voltage.

[0006] Optionally, the buffer comprises an even number of inverters connected in series.

[0007] Optionally, the signal receiving module includes a second inverter and a third inverter; the input end of the second inverter serves as the first end of the signal receiving module, and the output end is connected to the input end of the third inverter; the output end of the third inverter serves as the second end of the signal receiving module.

[0008] Optionally, the level conversion module includes a signal conversion unit and at least one signal transmission unit; each of the signal transmission units is respectively arranged between each signal transmission point in the level conversion module, and is used to buffer and process the signal change state corresponding to each signal transmission point; the signal conversion unit is used to transform the first signal so that the transformed signal is adapted to the second power domain.

[0009] Optionally, the signal conversion unit includes at least one second transistor connected in parallel; the drain of each second transistor serves as the first end of the signal conversion unit for receiving the first signal, the gate is used for receiving the control signal, and the source is grounded.

[0010] Optionally, the at least one signal transmission unit includes a first signal transmission unit and a second signal transmission unit; the first end of the first signal transmission unit serves as the first end of the level conversion module, the second end serves as the second end of the level conversion module, the third end is used to access the second power supply voltage, and the fourth end is respectively connected to the first end of the second signal transmission unit and the first end of the signal conversion unit; the second end of the second signal transmission unit is connected to the output end of the second inverter, and the third end is used to access the second power supply voltage.

[0011] Optionally, each of the signal transmission units includes multiple stages of transistors connected in sequence.

[0012] Optionally, the level conversion circuit is arranged inside the first power domain.

[0013] The present application also provides a chip, which includes any of the above-mentioned level conversion circuits.

[0014] The above-mentioned level conversion circuit and chip of the present application, by turning off the enable function when the control signal is in the first state, level-converts the first signal, and outputs a second signal adapted to the second power domain, so that the level conversion circuit stably performs the level conversion between the first power domain and the second power domain when the first power domain is in the power-on state, and connects the second power supply voltage when the control signal is in the second state to make the input end of the first inverter high level, at which time the output end of the first inverter is low level. The level conversion circuit can stably output a low level when the first power domain is in the power-off state, and can supplement the circuit unit library of traditional low-power design with a level conversion circuit that can be placed in the power-off area and has an output clamp value of low level, solving the limitation problem that when the power-off area needs to output a fixed low-level signal, the original level conversion circuit unit clamped to a low level can only be placed in the normally-on power area. It can improve the function of the level conversion circuit and enhance its application flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1a and Figure 1b This is a schematic diagram of the level conversion circuit setup during the research process of this application; Figure 2 This is a schematic diagram of the structure of a level conversion circuit according to an embodiment of the present application; Figure 3 1 is a schematic diagram of the configuration of a level conversion circuit in an embodiment of the present application; Figure 4 2 is a schematic diagram of the structure of a level conversion circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0017] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0018] In a first aspect, the present application provides a level conversion circuit, which can be provided in a chip having multiple power domains and requiring signal conversion between the power domains. Figure 2 As shown, the level conversion circuit includes a signal receiving module 100, an enable control module 200, a level conversion module 300 and a first inverter N1.

[0019] The first terminal of the signal receiving module 100 is used to receive the first signal I corresponding to the first power domain, and the second terminal of the signal receiving module 100 is connected to the first terminal of the level conversion module 300. The first terminal of the enable control module 200 is used to receive the control signal NSLEEP, and the second terminal of the enable control module 200 is used to receive the second power supply voltage VDDS corresponding to the second power domain. The third terminal of the enable control module 200 is respectively connected to the second terminal of the level conversion module 300 and the input terminal of the first inverter N1. The third terminal of the level conversion module 300 is grounded ( Figure 2 (not shown). The first inverter N1 may further include an output terminal and a power supply terminal. The output terminal may be used to output the second signal Z, and the power supply terminal may be used to receive the second power supply voltage VDDS. Optionally, the control signal NSLEEP may change in accordance with the first signal I. For example, the control signal NSLEEP may be characterized as a first state when the first signal I is in a stable state (e.g., a powered-on state of the first power domain), and as a second state when the first signal I is in a powered-down state (i.e., a powered-down state of the first power domain).

[0020] The signal receiving module 100 is used to transmit the first signal I to the level conversion module 300 to ensure that the first signal I can be stably received and processed by the level conversion module 300, thereby preventing unstable states such as sudden changes of the first signal I from affecting the stability of the level conversion operation.

[0021] The enable control module 200 is configured to disable the enable function when the control signal NSLEEP is in the first state, and to connect the second power supply voltage VDDS when the control signal NSLEEP is in the second state, i.e., the first power domain is in the power-off state, so that the input end of the first inverter N1 is at a high level. At this time, the output end of the first inverter N1 is at a low level. The level conversion circuit can stably output a low level (i.e., a 0 level) when the first power domain is in the power-off state.

[0022] The level conversion module 300 is used to perform level conversion on the first signal I when the enable function of the enable control module 200 is turned off, that is, when the first power domain is in the power-on state, to output a second signal Z adapted to the second power domain, so that the level conversion circuit can stably perform the level conversion between the first power domain and the second power domain when the first power domain is in the power-on state.

[0023] The level conversion circuit can be arranged inside the first power domain, for example, Figure 3 As shown, it is only necessary to connect the normally-on second power supply voltage VDDS to the enable control module 200, so that when the first power domain is in the power-on state, the level conversion between the first power domain and the second power domain can be performed. When the first power domain is in the power-off state, a low level is stably output, which can improve the level conversion function of the level conversion circuit and make the level conversion circuit have high stability in all states of the first power domain.

[0024] In some embodiments, the second state includes a low level (ie, 0), and correspondingly, the first state includes a high level (ie, 1). Figure 4 As shown, the enabling control module 200 includes a buffer B1 and a first transistor M22, wherein the first transistor M22 may be a PMOS transistor.

[0025] The input terminal of buffer B1 serves as the first terminal of the enable control module 200 and is used to receive the control signal. The output terminal of buffer B1 is connected to the gate of the first transistor M22. Buffer B1 may also include a power supply terminal, which can be used to receive the second power supply voltage VDDS corresponding to the second power domain. The source terminal of the first transistor M22 serves as the second terminal of the enable control module 200 and is used to receive the second power supply voltage VDDS. The drain terminal of the first transistor M22 serves as the third terminal of the enable control module 200 and is connected to the second terminal of the level shifter module 300 and the input terminal of the first inverter N1, respectively.

[0026] The buffer B1 is used to transmit the control signal NSLEEP to the gate of the first transistor M22 so as to buffer the control signal NSLEEP during the transmission process, thereby making the output control signal NSLEEP more stable and reliable.

[0027] The first transistor M22 is configured to be turned on when the control signal NSLEEP is at a low level to connect to the second power supply voltage VDDS. Specifically, when NSLEEP=0, the first transistor M22 is turned on. At this time, the second signal Z output by the first inverter N1 is 0, so that the level conversion circuit can clamp the output to 0 when the first power domain is powered off. When NSLEEP=1, the first transistor M22 is turned off. At this time, the second signal Z output by the first inverter N1 is k*I, so that the level conversion circuit can stably perform the level conversion between the first power domain and the second power domain when the first power domain is powered on. k represents a level conversion coefficient of the level conversion module 300. The level conversion coefficient k can be determined based on the level requirements between the first power domain and the second power domain. For example, the level conversion coefficient k can take a value such as 1.

[0028] Optionally, the buffer B1 includes an even number of inverters connected in series, wherein the specific number of inverters can be set according to the signal buffering requirements of the enable control module 200. Optionally, the inverters here can be implemented using MOS transistors.

[0029] In some embodiments, as Figure 4 As shown, the signal receiving module 100 includes a second inverter N2 and a third inverter N3. The input end of the second inverter N2 serves as the first end of the signal receiving module 100 and is used to receive the first signal I. The output end of the second inverter N2 is connected to the input end of the third inverter N3. The output end of the third inverter N3 serves as the second end of the signal receiving module 100 and is connected to the first end of the level conversion module 300. The second inverter N2 and the third inverter N3 can each include a power supply terminal, and their power supply terminals can be used to receive the first power supply voltage VDD corresponding to the first power domain.

[0030] In this embodiment, the signal receiving module 100 uses the second inverter N2 and the third inverter N3 to transmit the first signal I, which can make the first signal I transmitted to the first end of the signal receiving module 100 more stable. Optionally, the second inverter N2 and the third inverter N3 can be implemented using MOS transistors.

[0031] In some embodiments, as Figure 4 As shown, the level conversion module 300 includes a signal conversion unit 310 and at least one signal transmission unit ( Figure 4 (No reference numerals are shown).

[0032] Each signal transmission unit is respectively arranged between each signal transmission point in the level conversion module 300, and is used to buffer and process the signal change state corresponding to each signal transmission point, so that the signal conversion unit 310 can perform conversion processing on a more reliable signal, thereby improving the reliability of the conversion processing work.

[0033] Optionally, the signal transmission point includes a signal access point (such as the first end of the level conversion module 300), a voltage access point (such as the endpoint of the level conversion module 300 connected to the second power supply voltage VDDS) and / or a signal output point (such as the second end of the level conversion module 300), so as to perform buffering and other processing on the signal input and / or output of the level conversion module 300, so that the signal conversion unit 310 can perform more stable level conversion (or switching) on ​​the corresponding signal.

[0034] The signal conversion unit 310 is configured to perform conversion processing on the first signal I so that the converted signal adapts to the second power domain.

[0035] In some examples, at least one signal transmission unit includes a first signal transmission unit and a second signal transmission unit. The first end of the first signal transmission unit serves as the first end of the level conversion module 300 and is connected to the second end of the signal receiving module 100. The second end of the first signal transmission unit serves as the second end of the level conversion module 300 and is respectively connected to the third end of the enable control module 200 (i.e., the drain of the first transistor M22) and the input end of the first inverter N1. The third end of the first signal transmission unit is connected to the second power supply voltage VDDS. The fourth end of the first signal transmission unit is respectively connected to the first end of the second signal transmission unit and the first end of the signal conversion unit 310. The second end of the second signal transmission unit is connected to the output end of the second inverter N2, and the third end of the second signal transmission unit is connected to the second power supply voltage VDDS. Furthermore, the second end of the signal conversion unit 310 is connected to the output end of the buffer B1, and the third end of the signal conversion unit 310 serves as the third end of the level conversion module 300 and is connected to ground.

[0036] Specifically, each signal transmission unit may include a multi-stage transistor connected in sequence, which may be a pure digital CMOS transistor. A level conversion circuit may be designed and constructed using pure digital CMOS transistors, and the level conversion circuit may be made into a standard unit library to facilitate flexible calling of automated design tools.

[0037] Specifically, if Figure 4 As shown, the first signal transmission unit includes a third transistor M2, a fourth transistor M3, and a fifth transistor M4; wherein the third transistor M2 and the fourth transistor M3 can constitute a first-stage transistor, and the fifth transistor M4 can constitute a second-stage transistor; the third transistor M2 and the fifth transistor M4 can be PMOS transistors, and the fourth transistor M3 can be an NMOS transistor. The second signal transmission unit includes a sixth transistor M5, a seventh transistor M6, and an eighth transistor M1; wherein the sixth transistor M5 and the seventh transistor M6 can constitute a first-stage transistor, and the eighth transistor M1 can constitute a second-stage transistor; the sixth transistor M5 and the eighth transistor M1 can be PMOS transistors, and the seventh transistor M6 can be an NMOS transistor.

[0038] The gate of the third transistor M2 serves as the first terminal of the first signal transmission unit, connected to the second terminal of the signal receiving module 100 and the gate of the fourth transistor M3. The source of the third transistor M2 serves as the fifth terminal of the first signal transmission unit, connected to the drain of the eighth transistor M1 (which can be considered the fourth terminal of the second signal transmission unit). The drain of the third transistor M2 serves as the second terminal of the first signal transmission unit, connected to the drain of the first transistor M22, the input terminal of the first inverter N1, the drain of the fourth transistor M3, and the gate of the fifth transistor M4. The source of the fourth transistor M3 serves as the fourth terminal of the first signal transmission unit, connected to the source of the seventh transistor M6 and the first terminal of the signal conversion unit 310. The source of the fifth transistor M4 serves as the third terminal of the first signal transmission unit, connected to the second power supply voltage VDDS, and connected to the source of the eighth transistor M1 and the source of the first transistor M22. The drain of the fifth transistor M4 serves as the sixth terminal of the first signal transmission unit, connected to the source of the sixth transistor M5 (which can be considered the fifth terminal of the second signal transmission unit). The gate of the sixth transistor M5 serves as the second end of the second signal transmission unit and is connected to the output end of the second inverter N2 and the gate of the seventh transistor M6 respectively. The drain of the sixth transistor M5 is connected to the drain of the seventh transistor M6 and the gate of the eighth transistor M1 respectively.

[0039] In some examples, the signal conversion unit 310 includes at least one second transistor connected in parallel, for example, Figure 4 As shown, Figure 4The signal conversion unit shown includes a second transistor M11, which is an NMOS transistor. The drain of each second transistor can serve as the first terminal of the signal conversion unit 310, for receiving the first signal I (or the first signal I after being buffered by the signal transmission unit). The gate of each second transistor can serve as the second terminal of the signal conversion unit 310, for receiving the control signal NSLEEP (or the control signal NSLEEP after being buffered by buffer B1). The source of each second transistor can serve as the third terminal of the signal conversion unit 310, connected to the ground terminal. Parameters such as the number and size of the second transistors in the signal conversion unit 310 can be determined through simulation testing and other means to ensure that the signal conversion parameters of the signal conversion unit 310 match the signal conversion requirements between the first power domain and the second power domain.

[0040] Optionally, the signal conversion function performed by the level conversion module 300 can also be called a level conversion function, that is, the first signal I output by the first power domain is level-converted and the second signal Z adapted to the second power domain is output. Specifically, when the control signal NSLEEP=1, the first transistor M22 is turned off. At this time, the two-stage inverter of the signal receiving module 100 can assist the level conversion module 300 in a positive feedback manner to form a complete level conversion circuit to convert the first signal I into the second signal Z. The signal conversion unit 310 and other components in the above-mentioned level conversion module 300 use pure digital transistors to implement the level conversion function. Therefore, by connecting the signal transmission unit between its various signal transmission points, the signal therein can be more stably level-switched, and the transient signal jump caused by the uncertain state of the transistor signal at the moment of power off can be eliminated, thereby improving the reliability of the level conversion module 300 when performing the level conversion function.

[0041] The inventor Figure 4 The level conversion circuit shown in the figure is simulated and analyzed. The simulation analysis process shows that when NSLEEP=1, the second signal Z can follow the change of the first signal I, and at this time Z=k*I; when NSLEEP=0, the output of the level conversion circuit can be clamped to 0, that is, Z=0. The inventor further verified the electrical performance of the above-mentioned level conversion circuit. During the verification process, the level conversion circuit can perform accurate and stable level conversion in the range of 0.65V to 0.9V. It can be seen that the above-mentioned level conversion circuit can convert between different voltage values ​​and can also meet the requirements of cross-power domain design for level conversion circuits with clamped values. The above simulation analysis shows that Figure 4The illustrated level shifter circuit can be used for level conversion between two independent power domains. When one power supply (e.g., the first power supply VDD of the first power domain) is powered off, it can output a constant "0" as required by the function. Furthermore, the level shifter circuit can be placed directly within the power-off region (i.e., the first power domain), eliminating the need for a dedicated external power domain in current designs. When both power supplies are operating normally, the level shifter circuit functions as a level shifter (Z = k*I). When the power supply of the current power domain (e.g., the first power supply VDD of the first power domain) is powered off while the external target power domain is powered on and operating normally, the level shifter circuit, unaffected by the current power domain's power outage, directly uses the external power supply (e.g., the first power supply VDDS of the second power domain) to output a constant "0" to the normally operating modules, thus ensuring proper function of the entire system.

[0042] Furthermore, components in the aforementioned level shifter circuit, such as the signal receiving module 100, enable control module 200, level shifter module 300, and first inverter N1, can all be designed and constructed using purely digital CMOS transistors. This can be compiled into a corresponding standard cell library, facilitating access to automated design tools. Specifically, for the aforementioned level shifter circuit, a corresponding layout can be drawn, physical parasitic parameters extracted, and a standard .lib file generated using timing and power consumption characterization extraction tools for standardized digital chip design.

[0043] In the above level shifter circuit, when the control signal NSLEEP is in the first state, i.e., the first power domain is in the power-on state, the enable function is disabled, the first signal I is level shifted, and the second signal Z adapted to the second power domain is output. This allows the level shifter circuit to stably perform level shifting between the first and second power domains when the first power domain is in the power-on state. When the control signal NSLEEP is in the second state, i.e., the first power domain is in the power-off state, the second power supply voltage VDDS is connected, so that the input of the first inverter N1 is at a high level. At this time, the output of the first inverter N1 is at a low level. This level shifter circuit can stably output a low level when the first power domain is in the power-off state. This supplements the circuit unit library of traditional low-power designs with a level shifter circuit whose output is clamped to 0 (i.e., a low level) and can be placed in a power-off region. This solves the limitation that when the power-off region requires a fixed output signal of 0, the original level shifter circuit unit with a clamped output of 0 can only be placed in a normally-on power region. This improves the functionality of the level shifter circuit and enhances its application flexibility.

[0044] A second aspect of the present application provides a chip, which may include a low-power chip that needs to perform cross-power domain signal communication delivery. The chip includes the level conversion circuit described in any of the above embodiments.

[0045] The above chip includes the level conversion circuit described in any of the above embodiments, and has all the beneficial effects of the level conversion circuit described in any of the above embodiments, which will not be described in detail here.

[0046] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the components described above, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the designated function of the component (e.g., which is functionally equivalent), even if the structure is not identical to the disclosed structure that performs the function in the exemplary implementation of this specification shown herein.

[0047] That is, the above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the various embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0048] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals to identify them. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0049] In this application, the word "exemplary" is used to mean "serving as an example, illustration or description". Any embodiment described in this application as "exemplary" is not necessarily to be construed as being more preferred or more advantageous than other embodiments. The above description is provided to enable any person skilled in the art to implement and use the present application. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

Claims

1. A level conversion circuit, characterized in that: The level conversion circuit includes a signal receiving module, an enable control module, a level conversion module and a first inverter; The first end of the signal receiving module is used to receive the first signal corresponding to the first power domain, and the second end is connected to the first end of the level conversion module; the first end of the enable control module is used to receive the control signal, the second end is used to receive the second power supply voltage corresponding to the second power domain, and the third end is respectively connected to the second end of the level conversion module and the input end of the first inverter; the third end of the level conversion module is grounded; the control signal is characterized as a first state when the first signal is in a stable state, and is characterized as a second state when the first signal is in a power-off state; The signal receiving module is used to transmit the first signal to the level conversion module; The enable control module is configured to disable the enable function when the control signal is in a first state, and to connect the second power supply voltage when the control signal is in a second state, so that the input end of the first inverter is at a high level and the output end of the first inverter is at a low level; The level conversion module is configured to perform level conversion on the first signal when the enable function of the enable control module is turned off, so as to output a second signal adapted to the second power domain.

2. The level conversion circuit according to claim 1, wherein: The second state includes a low level; the enable control module includes a buffer and a first transistor; The input end of the buffer serves as the first end of the enable control module, the output end is connected to the gate of the first transistor, the source of the first transistor serves as the second end of the enable control module, and the drain serves as the third end of the enable control module; The buffer is used to transmit the control signal to the gate of the first transistor; The first transistor is configured to be turned on when the control signal is at a low level, so as to connect to the second power supply voltage.

3. The level conversion circuit according to claim 2, wherein: The buffer includes an even number of inverters connected in series.

4. The level conversion circuit according to claim 2, wherein: The signal receiving module includes a second inverter and a third inverter; The input end of the second inverter serves as the first end of the signal receiving module, and the output end of the second inverter is connected to the input end of the third inverter; the output end of the third inverter serves as the second end of the signal receiving module.

5. The level conversion circuit according to claim 4, wherein: The level conversion module includes a signal conversion unit and at least one signal transmission unit; Each of the signal transmission units is respectively arranged between each signal transmission point in the level conversion module, and is used for buffering and processing the signal change state corresponding to each signal transmission point; The signal conversion unit is used to perform conversion processing on the first signal so that the converted signal is adapted to the second power domain.

6. The level conversion circuit according to claim 5, wherein: The signal conversion unit includes at least one second transistor connected in parallel; The drain of each second transistor serves as the first end of the signal conversion unit for receiving the first signal, the gate is used for receiving the control signal, and the source is grounded.

7. The level conversion circuit according to claim 5, wherein: The at least one signal transmission unit includes a first signal transmission unit and a second signal transmission unit; the first end of the first signal transmission unit serves as the first end of the level conversion module, the second end serves as the second end of the level conversion module, the third end is used to access the second power supply voltage, and the fourth end is respectively connected to the first end of the second signal transmission unit and the first end of the signal conversion unit; the second end of the second signal transmission unit is connected to the output end of the second inverter, and the third end is used to access the second power supply voltage.

8. The level conversion circuit according to claim 7, wherein: Each of the signal transmission units includes multiple stages of transistors connected in sequence.

9. The level conversion circuit according to claim 1, wherein: The level conversion circuit is arranged inside the first power domain.

10. A chip, characterized in that: The chip includes the level conversion circuit according to any one of claims 1 to 9.

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