A method for burst signal detection of a shared resource

Abstract

The application discloses a burst signal detection method of shared resources, relates to the technical field of communication systems and integrated circuits, and aims to solve the problems of hardware resource waste and high cost caused by using independent ADC circuits to respectively process continuous signals and burst signals in the prior art. The method of the application uses one shared ADC to process all signals, and the core of the method is that when a high-priority burst trigger signal is detected, the normal continuous signal quantization task being performed by the shared ADC can be immediately interrupted, the data source is switched to preferentially process the burst signal, and after the processing is completed, the system can seamlessly recover the interrupted normal task. By combining the shared ADC architecture and the instant queuing recovery mechanism, the application does not need to additionally increase the ADC circuit, significantly optimizes the circuit resources, reduces the chip area and power consumption, ensures instant and reliable detection of the burst signal, and realizes the best balance between performance and cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication systems and integrated circuit technology, and in particular, to a burst signal detection method for sharing resources. BACKGROUND

[0002] In a communication system, due to the diversity of application scenarios, it is often necessary to process two kinds of signals at the same time: continuous analog signals and burst analog signals. Continuous signals have time continuity, while burst signals have the characteristics of random occurrence, short duration, and variable intensity.

[0003] In a traditional technical solution, in order to cope with the completely different characteristics of the two kinds of signals, a separate processing architecture is generally used. Specifically, the system configures independent and dedicated analog-to-digital converter (ADC) circuits for continuous analog signals and burst analog signals. As shown in FIG. Figure 1 The traditional method generally includes an ADC module (ADC module 1) for processing multiple continuous signals, and an ADC module (ADC module 2) specially arranged in parallel for processing burst signals. The two kinds of signals complete sampling, holding, quantization, and coding on independent physical paths, and then the data is finally aggregated.

[0004] Although this separate architecture can ensure the processing performance of each signal, its defects are also very prominent and serious, with the core defect being the huge waste of hardware resources. The use of multiple ADC modules directly leads to the following problems: the circuit complexity and chip area increase significantly, each additional ADC and its supporting circuit occupies valuable chip layout resources, increasing the complexity of design and wiring difficulty; the system total power consumption rises, multiple ADC modules work simultaneously or standby, which brings additional static and dynamic power consumption, which is contrary to the trend of low power consumption design of modern integrated circuits; the hardware cost increases, and ADC is a key component in analog circuits, increasing the number of which will directly increase the bill of materials (BOM) cost of the entire chip or system.

[0005] The reason why the prior art adheres to this resource-consuming solution is that simply connecting the burst signal to the ADC that processes the continuous signal cannot solve the high real-time requirement of the burst signal, which will lead to processing delay and signal missing. Therefore, how to break this inherent mode of "high performance must be high cost", and design a detection method that can both reuse hardware resources and ensure immediate response to burst signals, is a technical problem that needs to be solved in the field. SUMMARY

[0006] The technical problem to be solved by the present application is that in the prior art, independent ADC circuits are generally used when processing continuous signals and burst signals, resulting in waste of hardware resources and high chip cost; and simple hardware multiplexing cannot meet the high real-time requirement of burst signals. Therefore, the present application aims to provide a burst signal detection method sharing resources, which can not only reduce cost by sharing hardware resources, but also ensure immediate response to burst signals through intelligent scheduling mechanism, thereby breaking the inherent contradiction between performance and cost.

[0007] In order to achieve the above-mentioned purpose, the present application provides a burst signal detection method sharing resources, which comprises: when no burst trigger signal is detected, controlling a data selection module to periodically select a continuous analog signal from a plurality of continuous analog signals according to a time-sharing wheel control signal, and outputting the continuous analog signal to a shared analog-to-digital converter for quantization processing; when a burst trigger signal is detected, interrupting the quantization processing procedure being performed by the analog-to-digital converter for the continuous analog signal; controlling the data selection module to switch to selecting a burst analog signal, and outputting the burst analog signal to the analog-to-digital converter for preferential quantization processing to obtain a burst quantization signal; after the preferential quantization processing of the burst analog signal is completed, resuming the interrupted quantization processing procedure for the continuous analog signal, ensuring the continuity and integrity of data processing.

[0008] Further, the interrupting, switching and resuming are controlled by a dynamic priority control module; the dynamic priority control module is responsible for receiving the time-sharing wheel control signal and the burst trigger signal, and when the burst trigger signal is detected, generating and outputting a high-priority control signal for forcing the data selection module to switch the input and instructing the analog-to-digital converter to perform preferential quantization tasks, so as to realize immediate response and processing of the burst analog signal.

[0009] Further, in order to ensure seamless connection of task switching, before the data selection module switches to select the burst analog signal, the task state information of the continuous analog signal being processed is saved; the task state information at least includes register configuration information related to the current quantization task and unfinished data buffer; accordingly, after the quantization of the burst analog signal is completed, the register configuration is automatically restored and the data in the buffer is continued to be processed according to the saved task state information.

[0010] Further, the method further comprises: routing the quantized digital signal by using an analog-to-digital converter distribution module; and the control signal output by the dynamic priority control module is further used to temporarily freeze the distribution state of the analog-to-digital converter distribution module determined by the time-sharing wheel control signal, so that the distribution of the continuous quantized signal is stopped, and the burst quantized signal output by the analog-to-digital converter is directly transmitted and stored in a special register preset for the burst signal, so as to avoid data stream confusion.

[0011] Further, the control signal generated by the dynamic priority control module comprises a data selection signal and a priority control signal; when no burst trigger signal is detected, the dynamic priority control module generates a wheel control data selection signal and a wheel control priority control signal; when a burst trigger signal arrives, the dynamic priority control module immediately stops generating the wheel control data selection signal and the wheel control priority control signal, and instead generates a burst data selection signal and a burst priority control signal, so as to force the system resources to serve the burst signal processing task.

[0012] Further, the interruption comprises the following two cases:

[0013] If the analog-to-digital converter is performing a quantization task of a certain continuous analog signal when the burst trigger signal is detected, the task is immediately interrupted to preferentially process the burst signal;

[0014] If the analog-to-digital converter has completed the quantization task of a previous continuous analog signal but has not started the next one when the burst trigger signal is detected, the quantization task of the burst analog signal is preferentially performed, which covers the quantization task of the next continuous analog signal originally planned, and after the quantization task of the burst analog signal is completed, the quantization task of the continuous analog signal covered is no longer performed.

[0015] Further, in the circuit system architecture relied on by the method, all continuous analog signal input channels and burst analog signal input channels to be processed are uniformly connected to a plurality of input ends of the data selection module, and are selectively fed to the shared analog-to-digital converter according to the priority judgment by a single data selection module.

[0016] Further, the method supports nested interruption processing logic, which comprises: when the system is processing a first burst analog signal, if a second burst trigger signal with a higher priority is detected, the system can interrupt the current first burst analog signal processing task again, and instead preferentially process the second burst analog signal; after the processing of the task with a higher priority is completed, the system will sequentially restore and complete all interrupted tasks in reverse order of priority, so as to realize orderly response to multiple burst events with different priorities, and exhibit strong ability to process complex concurrent events.

[0017] Compared with the prior art, the application has the following advantages:

[0018] 1) The hardware resources are highly optimized, and the cost and power consumption are significantly reduced. By defining a shared analog-to-digital converter and a unified input method, the application completely abandons the separate design of configuring independent ADC modules for different signals in the prior art, and only one set of ADC circuit can complete the quantization of all signals, directly reducing the chip area, reducing the hardware cost and reducing the total power consumption of the system.

[0019] 2) Real-time response to burst signals is achieved, and the performance is improved instead of being reduced. By the interrupt-priority processing method and accurate control by the dynamic priority control module, the delay problem caused by simple multiplexing ADC is solved. When a burst signal arrives, the system can break the regular processing sequence and forcibly insert the queue to achieve zero-delay response, thereby ensuring reliable capture of the burst signal and meeting the demand of high real-time application.

[0020] 3) Task switching is seamlessly connected to ensure data integrity. The application ensures that the interrupted continuous signal task can be seamlessly continued from the breakpoint in the subsequent task by the task state saving and restoring mechanism, avoiding data loss or processing disorder. Combined with the freeze control of the ADC distribution module, it ensures that the data streams from different sources are correctly separated, and the stability of the system operation and the integrity of the data are jointly ensured.

[0021] 4) The system scheduling logic is advanced and has high flexibility and scalability. The application can intelligently judge and execute suspended tasks or task insertion, making the interrupt processing more efficient. The application supports nested interrupts and can handle multiple concurrent burst events with different priorities. This hierarchical and nestable priority scheduling capability far exceeds the traditional fixed architecture, making the application flexible and adaptable to more diversified application demands in the future.

[0022] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the following embodiments of the application are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0024] Figure 1 is the framework for detecting burst analog signals by the traditional method;

[0025] Figure 2 is a method schematic diagram in the embodiment of the present application;

[0026] Figure 3 is a detection waveform schematic diagram in the embodiment of the present application;

[0027] Figure 4 is a system architecture diagram in the embodiment of the present application;

[0028] Figure 5 is a system workflow diagram in the embodiment of the present application;

[0029] Figure 6 is a dynamic priority control module workflow diagram in the embodiment of the present application;

[0030] Figure 7 is a dynamic priority control module internal waveform diagram in the embodiment of the present application;

[0031] Figure 8 is a MUX module internal waveform diagram in the embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments.

[0033] The present application proposes a burst signal detection method for sharing resources, the core idea of which is to realize efficient and low-cost processing of continuous analog signals and burst analog signals through a shared hardware processing unit and a set of dynamic priority scheduling mechanism.

[0034] As shown in the accompanying Figure 4 The system architecture corresponding to the method of the present application realizes high integration at the hardware level. All signals to be processed, including multiple continuous analog signals (such as continuous analog signals 1, 2... n) and burst analog signals, are uniformly connected to multiple input ends of a data selection module (MUX), and a single output end of the data selection module is connected to an input end of a shared analog-to-digital converter (ADC). This "many-to-one" convergent input structure is the basis for resource sharing in the present application.

[0035] The control core of the system is a dynamic priority control module. As the "brain" of the system, the module is responsible for receiving external time-sharing wheel control signals and burst trigger signals. Based on these inputs, it generates a series of accurate control signals in real time to command the data flow and processing priority of the entire system.

[0036] The shared ADC is responsible for quantizing any signal from the data selection module. The output digital signal is sent to an ADC distribution module. The distribution module is also controlled by the dynamic priority control module, which routes the quantized digital signal (including continuous quantized signal and burst quantized signal) to the corresponding register for storage according to the instruction. The Figure 2 In a simplified block diagram, the core data flow path from multiple inputs, through shared ADC processing, and finally output to the register is clearly summarized.

[0037] The method of the present application realizes efficient task scheduling on shared hardware through a set of precise timing control logic. The workflow of the method is described in detail below Figure 3 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 .

[0038] 1. Normal working mode

[0039] As shown in the system workflow diagram of Figure 5 , after the system starts, if no burst trigger signal is detected, the system works in normal mode and performs the regular continuous signal quantization task.

[0040] Control logic: In this mode, as shown in the internal waveform diagram of Figure 7 , the dynamic priority control module generates a series of pulsed round control data selection signals 1, 2, and 3 according to the periodic input round control signals 1, 2, and 3.

[0041] Data flow: As shown in the MUX module working waveform diagram of Figure 8 , when the round control data selection signal 1 is high, the output of the data selection module (MUX) is the continuous analog signal 1. This signal is sent to the shared ADC for quantization. When the round control data selection signal 2 is high, the MUX output switches to continuous analog signal 2. This process is repeated to realize the time-sharing quantization of multiple continuous signals.

[0042] 2. Burst response mode

[0043] When a burst event occurs, i.e., a burst trigger signal is detected, the system immediately starts the burst response mode and performs a set of precise operations of "interrupt-save-switch-process-recover".

[0044] Step 1: Interrupt and queue

[0045] Please refer to Figure 3The waveform diagram illustrates the "instantaneous queue-jumping mechanism" of this invention. When a burst trigger signal (burst TRIGER signal) arrives, regardless of which consecutive signal quantization task the shared ADC is currently processing (as shown in the figure, during the quantization period of analog signal 1), the dynamic priority control module will immediately issue an interrupt command, forcibly interrupting the ongoing regular quantization process. If, when the burst trigger signal is detected, the shared ADC has completed the quantization task of the previous consecutive analog signal but has not yet started the quantization task of the next consecutive analog signal, the quantization task of the burst analog signal will overwrite the quantization task of the next consecutive analog signal. After the quantization task of the burst analog signal is completed, the quantization task of the overwritten consecutive analog signal will no longer be executed.

[0046] Step 2: State saving, switching, and priority quantification

[0047] Figure 6 The flowchart details the internal logic of the dynamic priority control module at this stage. Upon detecting a sudden trigger signal, the module immediately enters the priority processing branch and outputs a control signal to forcibly switch between the data selection module and the ADC distribution module.

[0048] To ensure seamless recovery of subsequent tasks, the system first saves the task status information of the currently interrupted task, which includes at least register configuration and unfinished data cache.

[0049] Figure 7 The waveform clearly shows that the arrival of the sudden trigger signal will immediately interrupt the generation of the regular wheel control data selection signal and instead generate a high-level sudden data selection signal pulse. Figure 8 The waveform diagram visually illustrates the data stream changes caused by the control signal. The burst data selection signal pulse immediately switches the output of the data selection module (MUX) from a continuous signal to a burst analog signal. This burst analog signal is then fed into the shared ADC for priority quantization processing. For example... Figure 3 As shown, after the quantization of the interrupted analog signal 1, the system immediately enters the "burst quantization" period.

[0050] Step 3: Data Routing and Recovery

[0051] During sudden quantitative events, such as Figure 7 As shown, the dynamic priority control module generates a continuous burst priority control signal. This signal is used to temporarily freeze the normal routing state of the ADC distribution module and instruct it to store the burst quantization signal output by the ADC into a dedicated register preset for the burst signal.

[0052] like Figure 5 and Figure 6When the burst signal transmission is completed, the dynamic priority control module will release the freeze state of the ADC distribution module and cancel the high priority instruction.

[0053] Finally, the system resumes the regular quantization process that was interrupted. It will call the previously saved task state information and continue the original task from the interruption point. As shown in Figure 3 After the first "burst quantization" period ends, the system immediately starts the analog signal 2 quantization period, demonstrating seamless connection capability.

[0054] The method of the present application also supports nested interruption processing logic to deal with more complex application scenarios. Although not separately drawn in the figure, the principle is the recursive application of the above-mentioned mechanism. When the system is processing a first burst signal, if a second burst trigger signal with higher priority arrives, the dynamic priority control module can identify the priority difference and execute the complete "interruption-save-switch-process-recovery" process again. It will interrupt the current first burst task and process the second burst task with higher priority. After completion, all interrupted tasks are recovered and completed in turn according to the "last in first out" principle. This gives the present application the powerful ability to handle multiple concurrent events of different priorities.

[0055] In summary, the system architecture and method disclosed in the above embodiments of the present application effectively solve the defects of the prior art and achieve the dual goals of hardware resource optimization and system performance improvement.

[0056] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for detecting burst signals in shared resources, characterized in that, include: When no sudden trigger signal is detected, a data selection module is controlled to periodically select one continuous analog signal from multiple continuous analog signals according to the time-sharing control signal, and output it to a shared analog-to-digital converter for quantization processing. When a burst trigger signal is detected, the quantization process of the continuous analog signal being executed by the analog-to-digital converter is interrupted; the data selection module is controlled to switch to selecting the burst analog signal, and the burst analog signal is output to the analog-to-digital converter for priority quantization processing to obtain the burst quantized signal; After the priority quantization processing of the burst analog signal is completed, the interrupted quantization processing flow for the continuous analog signal is resumed. Before the data selection module switches to selecting burst analog signals, save the task status information of the currently being processed continuous analog signals; The task status information includes at least register configuration information related to the current quantization task and unfinished data cache; accordingly, after completing the quantization of the burst analog signal, the register configuration is automatically restored and the data in the cache is processed again based on the saved task status information.

2. The method for detecting burst signals of shared resources according to claim 1, characterized in that, The interruption, switching, and recovery are controlled by a dynamic priority control module. This dynamic priority control module is responsible for receiving time-sharing control signals and sudden trigger signals. When a sudden trigger signal is detected, it generates and outputs a high-priority control signal to force the data selection module to switch inputs and instruct the analog-to-digital converter to perform priority quantization tasks, so as to realize the immediate response and processing of sudden analog signals.

3. The method for detecting burst signals of shared resources according to claim 2, characterized in that, It also includes: using an analog-to-digital converter distribution module to route the quantized digital signal; the control signal output by the dynamic priority control module is also used to temporarily freeze the distribution state in the analog-to-digital converter distribution module determined by the time-sharing control signal, so that it stops distributing the continuous quantized signal, and at the same time, the burst quantized signal output by the analog-to-digital converter is directly transmitted and stored in a dedicated register preset for the burst signal.

4. The method for detecting burst signals of shared resources according to claim 2, characterized in that, The control signals generated by the dynamic priority control module include data selection signals and priority control signals. When no sudden trigger signal is detected, the dynamic priority control module generates a round-robin data selection signal and a round-robin priority control signal. When a sudden trigger signal arrives, the dynamic priority control module immediately stops generating the round-robin data selection signal and the round-robin priority control signal, and instead generates a sudden data selection signal and a sudden priority control signal to force system resources to serve the sudden signal processing.

5. The method for detecting burst signals of shared resources according to claim 1, characterized in that, The interruption includes the following two scenarios: If the analog-to-digital converter is performing a quantization task of a continuous analog signal when a sudden trigger signal is detected, the task is immediately stopped to prioritize the processing of the sudden signal. If, when a sudden trigger signal is detected, the analog-to-digital converter has completed the quantization task of the previous continuous analog signal but has not yet started the next one, then the quantization task of the sudden analog signal is executed, and this quantization task directly overwrites the originally planned quantization task of the next continuous analog signal.

6. The method for detecting burst signals of shared resources according to claim 1, characterized in that, In the circuit system architecture upon which this method relies, all continuous analog signal input channels and burst analog signal input channels to be processed are uniformly connected to multiple input terminals of the data selection module, and selectively fed to the shared analog-to-digital converter by a single data selection module based on priority.

7. The method for detecting burst signals of shared resources according to claim 1, characterized in that, This method supports nested interrupt handling logic, including: when the system is processing a first burst analog signal, if a second burst trigger signal with a higher priority is detected, the system can interrupt the current first burst analog signal processing task again and prioritize the processing of the second burst analog signal; after the higher priority task is completed, the system will resume and complete all interrupted tasks in reverse order of priority, so as to achieve orderly response to multiple burst events of different priorities.

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