Analog-to-digital converter structure with mixed chips

Abstract

The invention discloses a chip hybrid analog-to-digital converter structure, which comprises a coarse quantization part and a fine quantization part, and is characterized in that the coarse quantization part is realized through an SAR ADC, and the fine quantization part is realized through a Sigma-Delta ADC; the residual error part which is not quantized by the SAR ADC is precisely quantized by the Sigma-Delta ADC, and finally, the quantization results of the coarse quantization stage and the precise quantization stage are combined and output by a digital adder; the analog input signal is sampled only in the acquisition phase of coarse quantization, but not in the fine quantization phase. An input signal is sampled only in the coarse quantization stage, only one-bit quantizer is multiplexed in the coarse quantization stage and the fine quantization stage, finally, a digital adder is adopted for output, analog signal gain is achieved through a feedback DAC of a first-stage integrator, and a larger signal-to-noise ratio and better quantization precision can be obtained.

Description

Technical Field

[0001] The present invention relates to a chip hybrid analog-to-digital converter structure, in particular to an analog-to-digital converter adopting a hybrid structure. Background Art

[0002] Successive approximation register analog-to-digital converters (SAR ADCs) require only a single comparator to achieve multi-bit quantization, resulting in extremely low power consumption. The advent of fully asynchronous clock technology has eliminated the need for a high-speed clock, further reducing the overall power consumption of SAR ADCs. Consequently, this type of SAR ADC has become one of the most popular ADC architectures in recent years.

[0003] Sigma-Delta ADCs employ oversampling and noise shaping techniques to shift the primary power of quantization noise to high frequencies. Combined with subsequent digital filtering, these techniques enable extremely high signal-to-noise ratios (SNRs) within the signal bandwidth. This structure enables high-resolution analog-to-digital conversion using a low-resolution quantizer, significantly reducing the requirements for circuit component matching. If a single-bit quantizer (requiring only a single comparator) is used within a Sigma-Delta ADC, a naturally linear quantization result is achieved.

[0004] As mentioned above, both SAR ADC and Sigma-Delta ADC have outstanding advantages, but their circuit structures are not perfect. Traditional successive approximation analog-to-digital converters and Sigma-Delta analog-to-digital converters have certain disadvantages.

[0005] SAR ADC essentially trades time for power consumption and area, and obtains quantization results from high to low bits through binary division. Before completing the quantization result of a bit, its internal digital-to-analog converter will generate an analog output (VDAC) based on the quantization results of all previous bits, and continue to compare it with the analog input (Vin) of the analog-to-digital converter. The difference between VADC and Vin will become smaller and smaller as the quantization proceeds. Unlike pipelined analog-to-digital converters, successive approximation analog-to-digital converters do not amplify the difference between VADC and Vin. Therefore, the low-bit quantization results of the SAR ADC are easily interfered with by circuit noise and cause errors. Figure 1 As shown, taking a traditional 5-bit successive approximation analog-to-digital converter circuit as an example, the circuit shown in the figure adopts a differential structure and a charge redistribution digital-to-analog converter (CDAC). Figure 2 Shown Figure 1The waveform shown in the figure shows how the CDAC output voltage of a successive approximation ADC (SAADC) changes as the ADC performs successive quantization under a certain input voltage. If the SAADC is operating properly, after completing 5 bits of quantization, the difference in the differential CDAC output voltage will be less than its LSB. This means that DACP - DACN is less than the LSB = 2 * (VREFP - VREFN) / 2^5 = VDD / 16. In the figure, VREFP = VDD, and VREFN = GND. This differential CDAC output voltage is also called the residual error of the SAADC.

[0006] In short, it is difficult to achieve high-precision analog-to-digital conversion with traditional SAR ADC.

[0007] The traditional Sigma-Delta ADC essentially trades time for accuracy. It primarily consists of an analog Sigma-Delta modulator and a digital low-pass filter. The performance of the entire analog-to-digital converter is primarily determined by the Sigma-Delta modulator. The signal-to-noise ratio (SNR) achievable by the Sigma-Delta modulator can be expressed as follows:

[0008]

[0009] As can be seen from the above formula, the signal-to-noise ratio (SNR) of a sigma-delta ADC is proportional to the order (L) of the sigma-delta modulator, the oversampling ratio (OSR), and the number of bits in the internal quantizer (B). A higher order improves the SNR of the sigma-delta modulator, but also reduces its stability. A higher oversampling ratio increases the bandwidth and power consumption required by the op amp within the modulator. A higher number of bits in the internal quantizer increases the nonlinearity of the entire analog-to-digital converter.

[0010] In short, the higher the conversion accuracy achieved by the traditional Sigma-Delta ADC, the greater the challenges encountered in circuit design, which inevitably leads to deterioration in stability, power consumption and linearity.

[0011] Based on the aforementioned advantages and disadvantages of traditional SAR ADCs and Sigma-Delta ADCs, Professor Kofi of Delft University in the Netherlands first proposed a two-step zoom ADC in 2013. This architecture uses a SAR ADC for coarse quantization and a Sigma-Delta ADC for fine quantization, combining the advantages of both. CN118100940A discloses a zoom ADC that reuses an LSB-first SAR quantizer. Building on the original zoom ADC structure, the SAR ADC used for coarse quantization is reused as the quantizer in the Sigma-Delta ADC, thereby reducing the overall zoom ADC chip area. However, both optimized ZOOM ADCs require the SAR ADC to participate in quantization during each Sigma-Delta ADC operating clock cycle. As we all know, the Sigma-Delta ADC is an oversampling ADC, and its operating frequency (Fs) is much higher than the signal bandwidth. The SAR ADC has only one comparator inside, so the comparator needs to operate at a frequency of N*Fs (N is the number of quantization bits of the SAR ADC, and Fs is the conversion frequency of the SAR ADC, which is also equal to the oversampling frequency of the Sigma-Delta ADC) to complete the quantization operation required by the Sigma-Delta ADC within one Sigma-Delta ADC operating cycle.

[0012] In summary, the above-mentioned traditional ZOOM ADC and the CN118100940A ZOOM ADC introduce the coarse quantization results in the digital domain and feed them into the fine quantization Sigma-Delta ADC through a multi-bit DAC. Therefore, the Sigma-Delta structure is a multi-bit structure, which is inevitably affected by the mismatch of the multi-bit DAC device.

[0013] In summary, based on the above analysis, we can see that current ZOOM systems all use digital signals to add the coarse and fine quantization signals. This forces the fine quantization Sigma-Delta ADC to adopt a multi-bit feedback structure, making it impossible to avoid the nonlinearity caused by device mismatch. While reusing the coarse quantization SAR ADC as the quantizer in the fine quantization Sigma-Delta ADC can reduce chip area, it forces the multi-bit SAR ADC to maintain high-speed oversampling quantization, which in turn increases power consumption. Summary of the Invention

[0014] The technical problem to be solved by the present invention is to overcome the respective shortcomings of the above-mentioned traditional SAR ADC and Sigma-Delta ADC, and to provide a hybrid analog-to-digital converter with a simple structure and the ability to obtain a higher signal-to-noise ratio and better quantization accuracy.

[0015] The technical solution of the present invention is:

[0016] A hybrid analog-to-digital converter (ADC) architecture consists of two stages: coarse quantization and fine quantization. Coarse quantization is performed using a SAR ADC, while the residual signal that the SAR ADC fails to quantize is further refined using a Sigma-Delta ADC. Finally, a digital adder combines and outputs the quantization results from both stages. The analog input signal is sampled only during the coarse quantization acquisition phase and does not require further sampling during the fine quantization phase.

[0017] The coarse quantization phase of the SAR ADC, consisting of a CDAC, a single-bit comparator, and SAR logic, quantizes the analog input signal. When the control signal of switch T1s is high, the analog input signal is captured by the SAR ADC's CDAC. When switch T1s is disconnected, the SAR ADC enters the quantization phase. After all bits of the SAR ADC are quantized, the coarse quantization result is stored in a register within the SAR ADC's logic circuitry. The residual error after coarse quantization is directly stored in the SAR ADC's CDAC, eliminating the need for additional generation.

[0018] The fine quantization stage, consisting of a Sigma-Delta ADC consisting of an integrator, a DAC, a single-bit comparator, and a digital filter, quantizes the quantization residual generated during the coarse quantization stage. This Sigma-Delta ADC is equivalent to fine quantizing a DC input voltage, while the analog input signal is not resampled during the fine quantization stage until the next coarse quantization step.

[0019] In order to use the same reference voltage in the subsequent Sigma-Delta ADC and also to maximize the input voltage, the Sigma-Delta ADC uses a capacitor array at its input to achieve analog gain.

[0020] Furthermore, the time for the coarse quantization part and the fine quantization part can be designed to be unequal according to system requirements. Preferably, in order to achieve high-precision fine quantization, the Sigma-Delta ADC needs to have a higher oversampling rate, so the time for the fine quantization part is longer than the coarse quantization part.

[0021] Furthermore, in order to increase the quantization speed, the SAR ADC adopts asynchronous logic for control.

[0022] Furthermore, in order to ensure the quantization accuracy of all bits of the SAR ADC, the SAR ADC performing the coarse quantization selects a quantization accuracy lower than 5 bits.

[0023] Furthermore, the residual signal stored in the CDAC of the SAR ADC is isolated through a buffer.

[0024] Furthermore, the sampling capacitors of the first-stage integrator in the capacitor array have a total of 16 groups of capacitor units when sampling the output of the previous-stage CDAC (ie, the residual voltage of the SAR ADC).

[0025] Furthermore, the feedback signal of the Sigma-Delta modulator DAC is only connected to one of the 16 groups of capacitor units (taking a 5-bit successive approximation analog-to-digital converter as an example).

[0026] Compared with the prior art, the input signal of the present invention is sampled only in the coarse quantization stage, and only one quantizer is reused in the coarse quantization stage and the fine quantization stage. The final output adopts a digital adder, and the analog signal gain is achieved through the feedback DAC of the first-stage integrator. It has the following advantages and effects:

[0027] 1) SAR ADCs have a low quantization bit count and do not need to process small analog signals, thus avoiding quantization errors.

[0028] 2) The quantizer requirement of the Sigma-Delta ADC is shared by the Successive Approximation ADC, thus reducing the design difficulty of the Sigma-Delta modulator;

[0029] 3) The successive approximation analog-to-digital converter and the Sigma-Delta converter share a comparator, which reduces circuit cost and power consumption.

[0030] 4) The analog signal entering the Sigma-Delta analog-to-digital converter can be amplified by a capacitor array, and the circuit is simple;

[0031] 5) The digital signal superposition of the two analog-to-digital converters can be achieved through a shift operation, and the circuit is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is the electrical schematic diagram of a 5-bit traditional successive approximation analog-to-digital converter (SAR ADC).

[0033] Figure 2 Schematic diagram of the output voltage change of the traditional analog-to-digital converter CDAC.

[0034] Figure 3 Electrical schematic diagram of the hybrid structure analog-to-digital converter of the present invention.

[0035] Figure 4 Timing diagram of the hybrid structure analog-to-digital converter of the present invention.

[0036] Figure 5This is the electrical schematic diagram of the Sigma-Delta analog-to-digital converter with a gain of 16.

[0037] Figure 6 for Figure 5 Schematic diagram of the selection strategy for the first-stage capacitor array of the integrator shown.

[0038] Figure 7 This is another specific implementation of the present invention.

[0039] Figure 8 This is the electrical schematic diagram of a Sigma-Delta analog-to-digital converter with a gain of 1. DETAILED DESCRIPTION

[0040] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0041] like Figure 3 and Figure 4 As shown in FIG. 1 , a chip hybrid analog-to-digital converter structure of the present invention is specifically an analog-to-digital converter using a hybrid structure, which includes two parts: coarse quantization and fine quantization. The coarse quantization is implemented by a SAR ADC, and the residual part that the SAR ADC fails to quantize is further fine quantized by a Sigma-Delta ADC. Finally, a digital adder is used to combine and output the quantization results of the coarse quantization (coarse adjustment) and fine quantization (fine adjustment) stages. Figure 3 As shown in the figure, the analog input signal is sampled only in the coarse quantization acquisition phase and does not need to be sampled again in the fine quantization phase. The time for the coarse quantization phase and the fine quantization phase can be designed to be unequal according to system requirements. In order to achieve high-precision fine quantization, the Sigma-Delta ADC is often required to have a high oversampling rate. Therefore, the time for the fine quantization phase is generally longer than that for the coarse quantization phase.

[0042] The coarse quantization part is composed of a SAR ADC consisting of a CDAC, a single-bit comparator, and SAR logic to quantize the analog input signal. When the control signal of switch T1s is high, the analog input signal is collected on the CDAC of the SAR ADC. After switch T1s is disconnected, the SAR ADC enters the quantization stage. To increase the quantization speed, the SAR ADC is generally controlled by asynchronous logic. To ensure the quantization accuracy of all bits of the SAR ADC, the SAR ADC performing coarse quantization generally selects a quantization accuracy of less than 5 bits. After completing the quantization of all bits of the SAR ADC, the digital result of the coarse quantization will be stored in the register of the SAR ADC logic circuit; the residual after the coarse quantization is directly stored in the CDAC of the SAR ADC, without the need for additional generation.

[0043] The fine quantization stage, consisting of a Sigma-Delta ADC consisting of an integrator, a DAC, a single-bit comparator, and a digital filter, quantizes the quantization residual generated during the coarse quantization phase. The residual signal stored in the CDAC of the SAR ADC must be isolated via a buffer; otherwise, charge sharing between the CDAC and the integrator in the Sigma-Delta ADC will alter the residual voltage. This Sigma-Delta ADC is equivalent to fine quantizing a DC input voltage, and the analog input signal does not need to be resampled during the fine quantization phase before the next coarse quantization step.

[0044] In order to use the same reference voltage in the subsequent Sigma-Delta ADC and also to maximize the input voltage, such as Figure 5 As shown in FIG, the Sigma-Delta ADC used in the present invention uses a capacitor array at its input end to achieve this analog gain. Figure 5 In the example, the sampling capacitor of the first-stage integrator has 16 groups of capacitor units when sampling the output of the previous-stage CDAC (i.e., the residual voltage of the successive approximation analog-to-digital converter); Figure 5 The feedback signal of the Sigma-Delta modulator DAC shown is connected to only one of the 16 groups of capacitor units (taking a 5-bit successive approximation analog-to-digital converter as an example).

[0045] From the above description, it can be seen that, as an embodiment, Figure 3 The coarse quantization part and the fine quantization part shown share the same comparator, which can save the area of ​​the entire analog-to-digital converter chip.

[0046] During the operation of the Sigma-Delta ADC, the hybrid structure analog-to-digital converter of the present invention does not need to sample the input signal again, and only requires an input buffer to isolate the output of the CDAC.

[0047] In addition, Figure 5 In the Sigma-Delta modulator shown in FIG, due to the presence of capacitor mismatch, if a fixed capacitor is used to receive the feedback signal of the DAC, there may be a gain error, which will increase the quantization error of the final output. Figure 6 The pointer rotation circuit similar to DWA (Data-Weighted Average) shown in the figure uniformly selects the capacitor units in the first-stage sampling capacitor array as DAC feedback capacitors. The input signal is fixedly sampled to 16 input capacitors each time, and the feedback DAC signal is based on Figure 6In the method shown, only one of the capacitors is selected as the feedback node at a time, and the capacitor selected as the feedback node is rotated among the 16 capacitors in turn, thereby achieving mismatch averaging throughout the entire fine quantization stage. The above averaging process can eliminate the random mismatch of the first-stage capacitor array, thereby reducing the mismatch between the analog gain and the subsequent digital gain, thereby reducing the final quantization error. Unlike multi-bit DAC feedback, the capacitor mismatch here only causes a mismatch between the analog gain and the digital gain, which has a much smaller impact on quantization accuracy than the nonlinearity caused by the multi-bit feedback structure, and the gain mismatch here can also be eliminated through background gain correction.

[0048] Figure 7 Another specific implementation of the present invention, and Figure 3 Compared with the circuit implementation in , this circuit uses a PGA with gain amplifier to amplify the quantization residual of the successive approximation analog-to-digital converter, thereby avoiding the use of a multi-capacitor array in the subsequent Sigma-Delta analog-to-digital converter, thereby reducing the chip area. Figure 8 for Figure 7 The unity-gain (gain of 1) Sigma-Delta analog-to-digital converter used in the circuit shown.

[0049] exist Figure 3 and Figure 7 It can be seen that the n-bit output of the successive approximation analog-to-digital converter and the m-bit output of the Sigma-Delta analog-to-digital converter are added in the digital domain. From the working principle described above, it can be seen that the digital output of the successive approximation analog-to-digital converter is located in the MSB bit of the overall hybrid structure analog-to-digital converter output, and this digital gain can be achieved only through digital operations.

[0050] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A chip hybrid analog-to-digital converter structure, comprising a coarse quantization part and a fine quantization part, wherein the coarse quantization part is implemented by a SAR ADC and the fine quantization part is implemented by a Sigma-Delta ADC; characterized in that: The residual part that the SAR ADC fails to quantize is finely quantized by the Sigma-Delta ADC, and finally the quantization results of the coarse quantization and fine quantization stages are combined and output by a digital adder; The analog input signal is sampled only in the coarse quantization acquisition phase, but not in the fine quantization phase; The coarse quantization part is composed of a SAR ADC consisting of a CDAC, a one-bit comparator and a SAR logic to quantize the analog input signal; the fine quantization part is composed of a Sigma-Delta ADC consisting of an integrator, a DAC, a one-bit comparator and a digital filter to quantize the quantization residual generated in the coarse quantization stage.

2. The chip hybrid analog-to-digital converter structure according to claim 1, characterized in that: When the control signal of the signal input switch T1s of the coarse quantization part is turned on, the analog input signal is collected on the CDAC of the SAR ADC. After the signal input switch T1s is turned off, the SAR ADC enters the quantization stage. After completing the quantization of all bits of the SAR ADC, the coarse quantization digital result is stored in the register in the logic circuit of the SAR ADC; the residual after the coarse quantization is directly stored in the CDAC of the SAR ADC.

3. The chip hybrid analog-to-digital converter structure according to claim 1, characterized in that: The Sigma-Delta ADC uses a capacitor array at its input to achieve analog gain.

4. The chip hybrid analog-to-digital converter structure according to claim 1, characterized in that: The duration of the coarse quantization part and the duration of the fine quantization part are not equal.

5. The chip hybrid analog-to-digital converter structure according to claim 4, characterized in that: The time of the fine quantization part is longer than that of the coarse quantization part.

6. The chip hybrid analog-to-digital converter structure according to claim 1, characterized in that: The SAR ADC is controlled by asynchronous logic.

7. The chip hybrid analog-to-digital converter structure according to any one of claims 1 to 6, characterized in that: The SAR ADC selects a quantization accuracy of less than 5 bits.

8. The chip hybrid analog-to-digital converter structure according to any one of claims 1 to 6, characterized in that: The residual signal stored in the CDAC of the SAR ADC is isolated through a buffer.

9. The chip hybrid analog-to-digital converter structure according to claim 3, characterized in that: The capacitor array is an array composed of 16 capacitors with a dynamic element selection function, which is used to uniformly select capacitor units in the first-stage sampling capacitor array as DAC feedback capacitors.

10. The chip hybrid analog-to-digital converter structure according to claim 9, characterized in that: The input signal is fixedly sampled onto the 16 capacitors each time, and the feedback DAC signal selects only one of the capacitors as a feedback node each time. The capacitor selected as the feedback node rotates in the array of the 16 capacitors in turn, thereby achieving mismatch averaging throughout the entire quantization stage.

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