Data transmission method based on digital receiver, digital receiver and data transmission system

Abstract

The invention provides a data transmission method based on a digital receiver, the digital receiver and a data transmission system. The method comprises the following steps: a digital receiver obtains an initial signal which is a signal sent by a radio frequency chip; the digital receiver carries out digital preprocessing on the initial signal to obtain an intermediate signal; the digital receiver performs down-conversion and / or filtering on the intermediate signal to obtain a target signal; the digital receiver transmits the target signal to a baseband. According to the scheme, the problem of relatively high power consumption of the DFE in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of radio frequency front-end data communication technology, and in particular to a data transmission method based on a digital receiver, a digital receiver, and a data transmission system. Background Art

[0002] With the rapid development of wireless communication technologies such as 5G, the Internet of Things, and satellite communications, modern communication systems are placing increasing demands on the performance of RF receive links. Achieving low-power design while ensuring high reception performance is a key challenge, particularly in power-sensitive applications such as mobile terminals and satellite-borne equipment. As a key module connecting the RF front-end and baseband processing, optimizing the power consumption of digital receivers has a crucial impact on the energy efficiency of the entire system. Therefore, a method to reduce the power consumption of digital receivers is urgently needed. Summary of the Invention

[0003] The main purpose of the present application is to provide a data transmission method based on a digital receiver, a digital receiver, and a data transmission system, so as to at least solve the problem of high power consumption of DFE in the prior art.

[0004] To achieve the above-mentioned objectives, according to one aspect of the present application, a data transmission method based on a digital receiver is provided, including: the digital receiver obtains an initial signal, wherein the initial signal is a signal sent by a radio frequency chip; the digital receiver performs digital preprocessing on the initial signal to obtain an intermediate signal, wherein the digital preprocessing method includes one or more of serial-to-parallel conversion, IQ deinterleaving, offset code, IQ compensation, IQ scaling, IQ exchange, and IQ limiting; the digital receiver down-converts and / or filters the intermediate signal to obtain a target signal; and the digital receiver transmits the target signal to the baseband.

[0005] Optionally, the digital receiver down-converts and / or filters the intermediate signal to obtain a target signal, including one of the following: the digital receiver down-converts or filters the intermediate signal to obtain the target signal, and the filtering method includes one or more of Farrow interpolation filtering, decimation filtering, and matched filtering, wherein the decimation filtering is a cascade form of several filters; the digital receiver down-converts the intermediate signal and filters the down-converted intermediate signal to obtain the target signal; the digital receiver filters the intermediate signal and down-converts the filtered intermediate signal to obtain the target signal.

[0006] Optionally, the digital receiver performs the down-conversion on the intermediate signal to obtain the target signal, including: the digital receiver extracts the carrier frequency of the intermediate signal; the digital receiver uses a CORDIC algorithm to convert the intermediate signal from the carrier frequency to an intermediate frequency carrier frequency to obtain the target signal, wherein the intermediate frequency carrier frequency is lower than the carrier frequency.

[0007] Optionally, the digital receiver performs the filtering on the intermediate signal to obtain the target signal, including one of the following: the digital receiver performs the Farrow interpolation filtering on the intermediate signal, or performs the extraction filtering on the intermediate signal, or performs the matched filtering on the intermediate signal to obtain the target signal; the digital receiver uses a first filtering method to filter the intermediate signal to obtain a first filtered signal, and uses a second filtering method to filter the first filtered signal to obtain the target signal, wherein the first filtering method and the second filtering method are both one of the Farrow interpolation filtering, the matched filtering and the extraction filtering, and the first filtering method is different from the second filtering method; the digital receiver uses a third filtering method to filter the intermediate signal to obtain a second filtered signal, uses a fourth filtering method to filter the second filtered signal to obtain a third filtered signal, and uses a fifth filtering method to filter the third filtered signal to obtain the target signal, wherein the third filtering method, the fourth filtering method and the fifth filtering method are all one of the Farrow interpolation filtering, the matched filtering and the extraction filtering, and the third filtering method, the fourth filtering method and the fifth filtering method are all different.

[0008] Optionally, the digital receiver performs the Farrow interpolation filtering on the intermediate signal to obtain the target signal, including: the digital receiver uses a first formula to perform the Farrow interpolation filtering on the intermediate signal to obtain the target signal, wherein the first formula is:

[0009]

[0010] y(l) represents the target signal obtained by the Farrow interpolation filter, N represents the order of the filter, x() represents the intermediate signal, h() represents the time impulse response, k l represents the current sampling time point, k represents the sampling time point, T represents the sampling period, μ l Indicates the preset delay parameters, M represents the number of filters, Represents the preset coefficient matrix.

[0011] Optionally, the digital receiver performs the decimation filtering on the intermediate signal to obtain the target signal, including: the digital receiver uses a second formula to perform the decimation filtering on the intermediate signal to obtain the target signal, wherein the second formula is:

[0012]

[0013] y(n) represents the target signal obtained by the decimation filtering, L represents the length of the filter, x() represents the intermediate signal,

[0014]

[0015] Optionally, the digital receiver transmits the target signal to the baseband, including: the digital receiver extracts an initial data throughput rate; the digital receiver transmits the target signal to the baseband at a target data throughput rate, wherein the target data throughput rate is higher than the initial data throughput rate.

[0016] Optionally, after the digital receiver transmits the target signal to the baseband, the method further includes: the digital receiver stores the target signal in a cache; the digital receiver extracts the free capacity of the cache; and when the free capacity is less than or equal to a preset capacity threshold, the digital receiver slows down the speed of receiving the initial signal until the free capacity is greater than the preset capacity threshold.

[0017] According to another aspect of the present application, a digital receiver is provided, including: an acquisition unit, configured to acquire an initial signal, wherein the initial signal is a signal sent by a radio frequency chip; a first processing unit, configured to perform digital preprocessing on the initial signal to obtain an intermediate signal, wherein the digital preprocessing method includes one or more of serial-to-parallel conversion, IQ deinterleaving, offset code, IQ compensation, IQ scaling, IQ exchange, and IQ limiting; a second processing unit, configured to down-convert and / or filter the intermediate signal to obtain a target signal; and a transmission unit, configured to transmit the target signal to a baseband.

[0018] According to another aspect of the present application, a data transmission system is provided, comprising: a radio frequency chip; a baseband; and a digital receiver, wherein the digital receiver is communicatively connected to the radio frequency chip and the baseband, respectively, and the digital receiver is used to execute any one of the digital receiver-based data transmission methods.

[0019] By applying the technical solution of the present application, after a digital receiver receives an initial signal, the initial signal is digitally preprocessed to obtain an intermediate signal, which is then down-converted and / or filtered. Down-conversion reduces the frequency of the received signal, thereby reducing the energy and resources required to process the signal. Filtering can filter out high-frequency noise and interference signals in the signal, reducing unnecessary energy consumption. Improving data throughput can reduce the retention time of data in the digital receiver, thereby reducing storage power consumption. This solution improves on the traditional DFE and can reduce power consumption through the above-mentioned processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0021] Figure 1 A schematic flow chart of a data transmission method based on a digital receiver according to an embodiment of the present application is shown;

[0022] Figure 2 A schematic diagram showing data transmission of a digital receiver;

[0023] Figure 3 shows a schematic diagram of a RAIC module;

[0024] Figure 4 shows a schematic diagram of the DSHA module;

[0025] Figure 5 shows a schematic diagram of the code Doppler effect;

[0026] Figure 6 Shows a schematic diagram of the Farrow filter calculation process;

[0027] Figure 7 shows a schematic diagram of the hardware implementation of the Farrow filter;

[0028] Figure 8 shows the schematic diagram of the classic decimation filter design;

[0029] Figure 9 The schematic diagram of the low-power polyphase double-decimation filter;

[0030] Figure 10 The schematic diagram of the low-power polyphase triple decimation filter;

[0031] Figure 11 The schematic diagram of the low-power polyphase four-fold decimation filter;

[0032] Figure 12is a schematic diagram of the SSAC module;

[0033] Figure 13 Shows the structural block diagram of a digital receiver. DETAILED DESCRIPTION

[0034] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] Traditional DFE architectures typically employ discrete designs, with independent functional modules implemented, leading to redundant hardware resources and wasted power. The additional power consumption caused by dynamic reconfiguration is particularly significant when processing multi-standard, multi-bandwidth signals.

[0038] The main technical difficulties currently faced by low-power DFE design include: (1) how to reduce the power consumption of data processing hardware resources while ensuring signal quality; (2) how to achieve efficient reuse of filter hardware resources; and (3) how to optimize the data interaction mechanism between modules to reduce redundant operations. These issues are particularly prominent when supporting wide-band, multi-standard scenarios such as 5G and satellite communications.

[0039] To address these challenges, a new low-power RF receive processing architecture is urgently needed. Through hardware acceleration and system-level optimization, it can significantly reduce power consumption while maintaining high reception performance. The ideal solution should integrate innovative algorithm implementation, efficient hardware architecture, and intelligent power management strategies to provide better energy efficiency for next-generation wireless communication devices.

[0040] As introduced in the background technology, the power consumption of DFE in the prior art is relatively high. To solve the above problem, the embodiments of the present application provide a data transmission method based on a digital receiver, a digital receiver, and a data transmission system.

[0041] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0042] In this embodiment, a data transmission method based on a digital receiver is provided that runs on a mobile terminal, a computer terminal or a similar computing device. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] Figure 1 FIG is a flow chart of a data transmission method based on a digital receiver according to an embodiment of the present application. Figure 1 As shown, the method includes the following steps:

[0044] Step S101: A digital receiver obtains an initial signal, wherein the initial signal is a signal sent by a radio frequency chip;

[0045] Specifically, the digital receiver first receives original digital radio frequency signals from the radio frequency chip. These signals usually carry a lot of noise and interference, and the frequency may not be suitable for direct processing.

[0046] Step S102: The digital receiver performs digital preprocessing on the initial signal to obtain an intermediate signal, wherein the digital preprocessing includes one or more of serial-to-parallel conversion, IQ deinterleaving, offset coding, IQ compensation, IQ scaling, IQ swapping, and IQ limiting.

[0047] Specifically, after receiving the initial signal from the RF chip, it first undergoes digital preprocessing, including IQ deinterleaving, serial-to-parallel conversion, offset coding, IQ scaling, IQ limiting, etc. These all belong to digital preprocessing.

[0048] Step S103: the digital receiver down-converts and / or filters the intermediate signal to obtain a target signal;

[0049] Specifically, the content of this solution lies in the digital receiver. During down-conversion, static configuration is combined with cordic rotation mode to reduce computational overhead and resource consumption. In the filter module, a reconfigurable multi-stage decimation filter bank is adopted, which can not only adapt to the requirements of different communication standards but also minimize the hardware area, thereby achieving the purpose of optimizing power consumption.

[0050] In step S104 , the digital receiver transmits the target signal to a baseband.

[0051] Specifically, the initial signal is processed multiple times to obtain the target signal, and the digital receiver quickly transmits the target signal to the baseband.

[0052] Through this embodiment, after the digital receiver receives an initial signal, it performs digital preprocessing on the initial signal to obtain an intermediate signal, which is then down-converted and / or filtered. Down-conversion reduces the frequency of the received signal, thereby reducing the energy and resources required to process the signal. Filtering can filter out high-frequency noise and interference signals in the signal, reducing unnecessary energy consumption. Improving data throughput can reduce the retention time of data in the digital receiver, thereby reducing storage power consumption. This solution improves on the traditional DFE and can reduce power consumption through the above-mentioned processing.

[0053] Specifically, the RF receiving and processing architecture involved in this solution has high energy efficiency, high integration and multi-standard adaptability, and is suitable for receiving-end signal preprocessing in various wireless communication systems such as 5G, 4G, satellite communications and the Internet of Things.

[0054] Specifically, the digital receiver is suitable for front-end processing of the radio frequency signal receiving link in wireless communication SoC. Figure 2 As shown in the figure, it mainly includes the Radio Frequency Adaptation Interface Controller (RAIC), the Digital Signal Hardware Accelerator (DSHA), and the Single-channel Storage Access Controller (SSAC). These modules are connected via a standardized bus interface and use a backpressure feedback mechanism to ensure the orderly and reliable data processing.

[0055] During the specific implementation process, the above-mentioned digital receiver down-converts and / or filters the above-mentioned intermediate signal to obtain the target signal, which can be achieved by one of the following steps: the above-mentioned digital receiver down-converts or filters the above-mentioned intermediate signal to obtain the above-mentioned target signal, and the above-mentioned filtering method includes one or more of Farrow interpolation filtering, decimation filtering, and matched filtering, wherein the decimation filtering is a cascade form of several filters; the above-mentioned digital receiver down-converts the above-mentioned intermediate signal, and filters the above-mentioned intermediate signal after the down-conversion to obtain the above-mentioned target signal; the above-mentioned digital receiver filters the above-mentioned intermediate signal, and down-converts the above-mentioned intermediate signal after the filtering to obtain the above-mentioned target signal.

[0056] In this solution, Farrow interpolation filtering, decimation filtering, and matched filtering technologies are used to improve signal purity and further reduce power consumption. Down-conversion can reduce the frequency of the received intermediate signals, thereby reducing the energy and resources required to process these signals, further reducing power consumption.

[0057] During filtering processing, usually only one farrow filter and one matched filter are required in a digital receiver. The farrow filter is placed after down-conversion and the matched filter is placed before the baseband. The decimation filter in the middle is selected in several cascades according to the requirements of the communication standard.

[0058] In a specific application, the above-mentioned digital receiver processing method is particularly applicable in satellite communication systems. Since satellite communication signals have long transmission distances and are susceptible to the Doppler effect, the use of Farrow interpolation filters can effectively correct the carrier frequency offset of the signal. In high-data-rate applications, the dynamic configuration of the multi-stage decimation filter group can adapt to different bandwidth requirements, reduce hardware resource consumption, and optimize power consumption. For example, the bandwidth required by a satellite communication system may range from 2MHz to 20MHz. By adjusting the decimation factor, efficient signal processing can be achieved under different bandwidths. At the same time, the matched filter module can optimize the signal quality according to standards such as root raised cosine and GMSK, thereby improving the robustness of communication under complex channel conditions.

[0059] In some embodiments, the digital receiver performs the down-conversion on the intermediate signal to obtain the target signal, which can be specifically achieved through the following steps: the digital receiver extracts the carrier frequency of the intermediate signal; the digital receiver uses the CORDIC algorithm to convert the intermediate signal from the carrier frequency to an intermediate frequency carrier frequency to obtain the target signal, wherein the intermediate frequency carrier frequency is lower than the carrier frequency.

[0060] In this solution, the carrier frequency determines the specific parameter settings of the frequency conversion operation. Due to the static configuration characteristics of the CORDIC algorithm, dynamic calculation of the rotation angle is avoided, reducing unnecessary computing resource consumption, thereby further reducing power consumption.

[0061] Specifically, a digital receiver extracts the carrier frequency information of the RF signal before downconversion. This carrier frequency extraction ensures that the CORDIC downconversion unit can accurately convert the RF signal from its high frequency to the target intermediate frequency (IF). The digital receiver uses the CORDIC algorithm to achieve signal frequency conversion, converting the received RF signal from its original carrier frequency to a lower IF carrier frequency. This process is performed by the CORDIC downconversion unit. The CORDIC algorithm is based on the principle of vector rotation and uses iterative calculations to rotate the signal to the desired IF carrier frequency.

[0062] Specifically, the dynamic calculation mode of the traditional CORDIC algorithm will generate unnecessary power consumption; although the reconfigurable filter bank can adapt to different communication standards, the conventional implementation method often requires complex control logic and additional cache overhead.

[0063] Specifically, the RF adapter interface controller (RAIC) includes a RF interface module and a CORDIC down-conversion module. The RF interface module is used to receive the digital signal output by the RF chip. Due to various deviations and undesirable conditions caused by analog RF links, channel transmission and hardware implementation in actual communication systems, data pre-processing is required in ASIC (custom integrated circuit) design to deal with such situations; the CORDIC down-conversion module is used to complete the down-conversion processing. The above-mentioned CORDIC module uses a rotation mode to pre-statically configure the registers according to known RF requirements to avoid dynamic calculation of power consumption.

[0064] Specifically, if Figure 3 As shown in the figure, the RAIC module is located at the front end of the receiving chain, and its function is to perform frequency conversion and preprocessing on the received signal from the RFIC chip. It mainly includes:

[0065] RF input interface module: receives serial or parallel I / Q signals output by RFIC and performs preliminary data buffering and clock alignment;

[0066] CORDIC down-conversion unit: It adopts a CORDIC structure based on a vector rotation algorithm to down-convert the received signal. Its internal CORDIC adopts a static register configuration method, eliminating the dynamic rotation angle calculation, reducing hardware complexity and dynamic power consumption.

[0067] Serial-to-parallel conversion (S / P) converts serial data received from the RF chip into a parallel data format. In the receive chain, data is typically output in serial format, but subsequent digital signal processing modules often require parallel data input for efficient processing. The function of the serial-to-parallel converter is to convert the high-speed serial data stream into a slower parallel data stream for subsequent processing.

[0068] IQ deinterleaving separates the I (In-Phase) and Q (Quadrature) signals from the serial stream. In wireless communications, RF signals are modulated onto two orthogonal carriers, forming I and Q components. The RFIC output signal typically interleaves these two components. The IQ deinterleaving module separates them for subsequent processing.

[0069] Offset code refers to compensating for any DC offset or bias voltage that may be present in the RFIC output signal. DC offset may be introduced during digital signal conversion and needs to be corrected during preprocessing to avoid affecting subsequent signal processing.

[0070] IQ compensation corrects the amplitude and phase imbalance between the I and Q signals due to the non-ideal characteristics of the RFIC and RF front-end. This reduces signal distortion and improves receiver performance.

[0071] IQ scaling refers to adjusting the amplitude of the I and Q signals. This is usually done to solve the matching problem between the signal dynamic range and the RFIC output dynamic range, ensuring that the signal does not overflow or become too weak during subsequent processing.

[0072] IQ swapping involves swapping the positions of the I and Q components in certain situations, depending on the characteristics of the received signal, to correctly demodulate the signal. Different modulation schemes may use different I and Q components, and IQ swapping ensures correct signal decoding.

[0073] IQ limiting limits the amplitude of the I and Q signals to prevent them from becoming too large and causing saturation or overload. In digital signal processing, limiting is a common method for protecting subsequent circuits from damage caused by strong signals.

[0074] The two antennas mentioned here refer to a multi-antenna configuration for the receiving system. Multi-antenna reception provides diversity gain, enhancing signal reception stability and interference immunity. The signal received by each antenna undergoes the aforementioned preprocessing steps and may then undergo further signal combining or processing to improve received signal quality.

[0075] The CORDIC module implements frequency rotation based on the following iterative formula:

[0076]

[0077] x i Indicates the x-axis coordinate position, corresponding to the in-phase component (I) of the signal, y i Indicates the y-axis coordinate position, corresponding to the orthogonal component (Q) of the signal, z i represents the rotation angle or phase angle, corresponding to the frequency difference between the RF signal and the local oscillator signal, and i represents the index of the iteration number.

[0078] where d i Depends on z i The symbol indicates the direction of rotation;

[0079]

[0080] After N iterations, the sine and cosine values ​​required for frequency conversion can be obtained.

[0081] Specifically, RAIC pre-processes the RF signal to improve the receiving demodulation accuracy, reduce the burden of post-processing, and reduce power consumption; RAIC uses a static CORDIC algorithm to avoid real-time calculation of rotation angles and reduce dynamic power consumption.

[0082] In a specific application, the down-conversion method of this embodiment demonstrates its unique advantages in processing high-frequency RF signals in mobile communication base station receiving equipment. Assuming that the center frequency of the RF signal received by the base station is 2.6 GHz, it needs to be converted to a lower intermediate frequency carrier frequency for more efficient subsequent signal processing. Using the CORDIC algorithm of this solution, the signal can be smoothly down-converted to an intermediate frequency carrier frequency of 43.75 MHz. This conversion process not only maintains the integrity and quality of the signal, but also greatly reduces system power consumption because the static configuration of the CORDIC algorithm does not require the real-time calculation of expensive rotation angles.

[0083] At the same time, since the signal bandwidth and format received by base station equipment at different time periods may vary, for example, from 5MHz to 100MHz, the flexible configuration of the CORDIC downconversion unit can adapt to these changes and ensure that the signal is always in the optimal processing state.

[0084] In a specific implementation process, the digital receiver performs the filtering on the intermediate signal to obtain the target signal, which can be achieved by one of the following steps: the digital receiver performs the Farrow interpolation filtering on the intermediate signal, or performs the extraction filtering on the intermediate signal, or performs the matched filtering on the intermediate signal to obtain the target signal; the digital receiver uses a first filtering method to filter the intermediate signal to obtain a first filtered signal, and uses a second filtering method to filter the first filtered signal to obtain the target signal, wherein the first filtering method and the second filtering method are both the Farrow interpolation filtering, the above filtering method and the above filtering method. The digital receiver adopts a third filtering method to filter the intermediate signal to obtain a second filtered signal, adopts a fourth filtering method to filter the second filtered signal to obtain a third filtered signal, and adopts a fifth filtering method to filter the third filtered signal to obtain the target signal, wherein the third filtering method, the fourth filtering method and the fifth filtering method are all one of the Farrow interpolation filter, the matched filter and the decimation filter, and the third filtering method, the fourth filtering method and the fifth filtering method are all different.

[0085] In this solution, the digital receiver performs one or more of Farrow interpolation filtering, decimation filtering, or matched filtering on the intermediate signal, so that the most appropriate filtering method can be selected and the appropriate filtering order can be used for filtering, thereby reducing interference in the signal and further reducing power consumption.

[0086] Specifically, the Farrow interpolation filter uses a polynomial piecewise fitting interpolation function to achieve interpolation of arbitrary fractional delays with low hardware complexity. It is particularly suitable for eliminating the Doppler effect of carrier frequency and code chip rate, reducing the power consumption of signal processing. The polyphase structure of the decimation filter optimizes the calculation process, reducing the number of multiplication operations by approximately (n-1) / n (n is the decimation filter multiple), significantly reducing the power consumption of the filtering process. The matched filter targets specific impulse responses, such as root raised cosine and GMSK, to enhance the signal reception performance and improve the robustness of the system.

[0087] Specifically, the digital signal hardware accelerator (DSHA) includes a FIFO buffer module, a Farrow interpolation filter, a reconfigurable multi-stage decimation filter bank and a matched filter. The FIFO buffer module buffers data transmission. RAIC and DSHA may operate in different clock domains or at different processing rates. FIFOs provide timing isolation and rate buffering, effectively preventing data loss and overflow. Farrow interpolates arbitrary fractional delays with low computational complexity by fitting a polynomial interpolation function piecewise. This eliminates the Doppler effect of carrier frequency and chip rate. Compared to classic interpolation schemes (sinc interpolation), this approach offers a simpler hardware structure and lower power consumption. A reconfigurable multistage decimation filter bank achieves low-power design based on classic filters. Using a polyphase structure, filtering is performed only at the decimation points, avoiding multiplication and addition calculations on all input data. This reduces approximately n-1 / n multiplication operations (n ​​is the decimation filter factor), facilitating pipeline implementation in FPGAs or ASICs. Calculations are performed only within the effective decimation period. Changing the decimation factor to other values ​​(such as 3, 4, or 5) simply requires expanding the number of polyphase paths. This results in a clear and easily scalable architecture. It can significantly reduce hardware resources and power consumption, adopt a multi-phase filtering strategy, support filtering processing of different communication standards, and reduce redundant power consumption.

[0088] Specifically, if Figure 4 As shown in the figure, the DSHA module, as the core signal processing unit, filters, modulates, and matches the intermediate frequency signal output by the RAIC. It integrates the following functional modules: FIFO buffer module, Farrow interpolation module, decimation filter module, and matched filter module.

[0089] FIFO buffer module: solves the problem of clock domain crossing and data rate mismatch, ensuring data transmission stability.

[0090] In a specific application, in the data reception scenario of the remote sensor of the Internet of Things, the multi-stage filtering processing strategy of this embodiment is particularly important because the signal transmission path is complex and may involve the conversion of different communication standards. Assuming that the signal bandwidth sent by the sensor is 200kHz, it needs to be adapted to the intermediate frequency carrier frequency of 43.75MHz through multi-stage filtering for data processing. First, the possible frequency offset is corrected by the Farrow interpolation filter, and then the signal is bandwidth-limited and down-sampled by the decimation filter (for example, a 3x decimation filter). Finally, the signal-to-noise ratio of the signal is further improved by the matching filter, ensuring the stable transmission and reception of the signal in a complex environment. At the same time, the power consumption in the processing process is significantly reduced, the operating time of the sensor is extended, and the maintenance cost is reduced.

[0091] In some embodiments, the digital receiver performs the Farrow interpolation filtering on the intermediate signal to obtain the target signal, which can be specifically achieved by the following steps: the digital receiver uses a first formula to perform the Farrow interpolation filtering on the intermediate signal to obtain the target signal, wherein the first formula is:

[0092]

[0093] y(l) represents the target signal obtained by the Farrow interpolation filter, N represents the order of the filter, x() represents the intermediate signal, h() represents the time impulse response, k l represents the current sampling time point, k represents the sampling time point, T represents the sampling period, μ l Indicates the preset delay parameters, M represents the number of filters, Represents the preset coefficient matrix.

[0094] In this solution, the Doppler shift in 5G communications is effectively corrected through the precise parameter setting and flexible fractional delay interpolation capability of the Farrow interpolation filter. It can achieve signal interpolation with arbitrary fractional delay with low computational complexity, effectively correcting the Doppler effect of carrier frequency offset and code chip rate. Since the core of the Farrow interpolation filter is polynomial fitting, its calculation process can be effectively simplified, reducing the occupation of hardware resources, thereby further reducing power consumption.

[0095] Specifically, the code Doppler effect is as follows Figure 5 shown. Figure 5 This paper demonstrates the impact of the Doppler effect on signals and how it can be compensated for using a Farrow filter. The Doppler effect occurs when there is relative motion between the source and receiver, causing the received signal's frequency to shift. This can pose challenges to the signal integrity and synchronization of communication systems. A Farrow filter is a fractional delay filter that effectively cancels or compensates for the frequency shift caused by the Doppler effect.

[0096] The solid black dots generally represent the sampling points of the original signal. They reflect the signal samples collected at a fixed sampling frequency without any additional delay points. The dashed black dots are the new signal sampling points generated by interpolation after Farrow filter processing. The Farrow filter uses fractional delay interpolation to insert new points between the original sampling points to compensate for time shifts caused by the Doppler effect.

[0097] Figure 5Comparing the unprocessed (top) and Farrow-filtered (bottom) signals demonstrates the effectiveness of the Farrow filter in compensating for the Doppler effect. The unprocessed signal (top) may show a mismatch between the signal and the expected sampling points, resulting in a decrease in received signal quality. However, the Farrow-filtered signal (bottom) improves signal quality by inserting new sampling points at appropriate locations, bringing the signal's time domain position more in line with the expected position.

[0098] Specifically, the Farrow filter calculation process is as follows: Figure 6 As shown in Figure 2, the input signal din is fed into the filter, where it is represented as a digital value at each sample point. The din signal then enters the register delay block (din_reg), which typically contains multiple delay cells (Z-1) to store the most recent input signal samples. The number of delay cells depends on the filter order and design requirements. For a filter order of 4, there will be four register delay stages, storing the four most recent input signal samples.

[0099] The rx_pha module calculates the signal's phase information, which is dynamically adjusted based on the signal's characteristics or system requirements. This phase information is used to determine the delay of the Farrow filter, thereby achieving fractional delay. The phase calculation results determine the parameters of the polynomial interpolation calculation in the filter, namely the delay d.

[0100] Based on the delay parameter d calculated by rx_pha, the corresponding signal sample is selected from din_reg. Polynomial interpolation is performed. Farrow filters are typically based on polynomial interpolation functions and can calculate signal values ​​for arbitrary fractional delays. This step involves adjusting the polynomial coefficients based on the delay parameter d and applying them to the selected signal samples to calculate the interpolated signal value. The interpolated signal value is further processed using a multiply-accumulate (MAC) operation. MAC is one of the core operations in digital signal processing, used to multiply the signal value by the filter coefficients and accumulate the results to obtain the final filtered output.

[0101] In a Farrow filter, the MAC operation is based on the delay parameter d and predefined polynomial coefficients, which are typically optimized during filter design based on the filter's requirements and performance goals. The final output signal, fir_far_row_dout, may be clipped. This is to prevent the signal amplitude from exceeding the dynamic range of subsequent circuits or systems, thereby avoiding signal distortion or hardware damage. Clipping typically involves checking whether the output signal's amplitude exceeds a predetermined threshold and, if so, clipping it to that threshold to maintain signal stability and reliability.

[0102] The Farrow interpolation module implements an efficient digital filter structure for fractional delay filtering and variable interpolation. It is used for signal resampling and interpolation in digital signal processing. Its core is a polynomial filter structure, where the input signal is processed through multiple parallel branches, each corresponding to a polynomial coefficient of a different order. The output is the weighted sum of these branches, expressed as the first formula.

[0103] Specifically, in the first formula, y(l) represents the sampled signal of the l-th output, k represents the filter index, x(n) represents the input discrete signal, μ represents the fractional delay parameter corresponding to the l-th output, h(n) represents the filter time impulse response, and T represents the sampling period; (the overall meaning is: the input signal x(n) is delayed by a non-integer value kT+μ l The filter h(n) of T is convolved and summed to get the output), and its expression is transformed as follows:

[0104]

[0105] In summary, the transformation of the sampling sequence expression of the lth output can be:

[0106]

[0107] c m,k is the polynomial coefficient matrix (the mth-order term corresponds to the coefficient of the kth sampling point), M is the number of parallel FIR sub-filters (4 in this example) (polynomial order), N is the filter order (4th order), where v m (k l ) is the mth sub-filter at the current sampling point k l The output on can be expressed as:

[0108]

[0109] The filter coefficients in this example are set as follows:

[0110]

[0111] The Farrow filter hardware obtained using the above settings is as follows Figure 7 As shown in the figure, the process includes multiple key steps, including signal delay, weighted processing using a polynomial interpolation function, and signal adjustment based on the delay parameters. Through these calculation mechanisms, the Farrow filter can achieve flexible signal delay in time without changing the signal's spectral characteristics. This is crucial for processing dynamic communication signals with Doppler shift. This type of filter plays an important role in various wireless communication systems, especially when processing signals in high-speed mobile scenarios.

[0112] In a specific implementation process, the digital receiver performs the decimation filtering on the intermediate signal to obtain the target signal, which can be achieved by the following steps: the digital receiver uses the second formula to perform the decimation filtering on the intermediate signal to obtain the target signal, wherein the second formula is:

[0113]

[0114] y(n) represents the target signal obtained by the above extraction and filtering, L represents the length of the filter, x() represents the above intermediate signal,

[0115]

[0116] In this solution, by adopting a multi-phase filtering strategy, the decimation filter can perform calculations only within the effective decimation period, avoiding multiplication and addition operations on all input data, significantly reducing the number of multiplication operations, and further reducing power consumption.

[0117] Specifically, compared with traditional decimation filters, the use of a polyphase structure can reduce approximately (n-1) / n multiplication operations (n ​​is the decimation filter multiple). This feature makes the decimation filter more advantageous when processing multi-standard, multi-bandwidth signals.

[0118] The filter in this digital receiver implements the function of a decimation filter. The structure of the classic filter is improved and named a low-power multi-phase N-fold decimation filter (N can be 2, 3, 4, 5, 6, etc.). The optimal multiple is selected for cascade implementation design based on the specific supported communication standard. In comparison, the improved filter can reduce power consumption while improving hardware implementation efficiency.

[0119] Specifically, the reconfigurable multi-stage decimation filter bank uses a polyphase filter to reduce the computational complexity of the decimation process and improve the efficiency of hardware implementation. The design principle is explained using a three-stage decimation filter as an example. Assume that the input signal is x(n), the decimation filter coefficient is h(n), the filter length is L, and the decimation factor is M=3. Figure 8 As shown, the output of the classic FIR decimation filter is the second formula. Using polyphase decomposition, the decimation filter can be decomposed into M sub-filters. When M is equal to 2, the structure is as follows Figure 9 As shown, when M is equal to 3, the structure is as follows Figure 10 As shown, when M is equal to 4, the structure is as follows Figure 11 As shown, when M is equal to 3,

[0120]

[0121] The extracted output signal can be expressed as:

[0122]

[0123] Here, h0, h1, and h2 are the three sub-filters of the polyphase filter, processing the portion of the input signal with index modulo 3 equal to 0, 1, and 2, respectively. The input data din is periodically distributed in three paths as din[3n], din[3n+1], and din[3n+2]. Each path has its own corresponding sub-filter path with corresponding filter coefficients H0, H3, H6, ..., H1, H4, H7, ..., H2, H5, H8, ...; finally, the three outputs are added together to obtain the decimated output result dout.

[0124] Matched filter module: matches the transmitter-end shaped pulse to improve the signal-to-noise ratio (SNR) of the received signal, supporting different pulse shaping standards such as root-raised cosine and GMSK.

[0125] The DSHA module is highly configurable and suitable for a variety of communication formats. Each filter module supports online parameter updates to meet system robustness requirements in dynamic channel environments.

[0126] Specifically, DSHA achieves power consumption optimization under different communication standards through a reconfigurable polyphase filter group strategy; a back-pressure control mechanism is adopted between modules to achieve flow control collaboration of the data processing link to ensure continuity and efficiency.

[0127] In some embodiments, the digital receiver transmits the target signal to the baseband, which can be specifically achieved through the following steps: the digital receiver extracts the initial data throughput rate; the digital receiver transmits the target signal to the baseband at the target data throughput rate, wherein the target data throughput rate is higher than the initial data throughput rate.

[0128] In this solution, the increase in data throughput ensures the continuity and efficiency of signal processing and transmission. Even when processing signals with high data rates, it can ensure timely processing and transmission of signals to the baseband, meeting the needs of high-speed data communication.

[0129] Specifically, a digital receiver needs to determine the current initial data throughput rate before transmitting the signal to the baseband. This rate is determined by monitoring the read and write rates of the buffer. This initial data throughput rate reflects the original rate before signal processing and serves as an important reference for subsequent adjustments to the data transmission rate.

[0130] The digital receiver adjusts its data transmission strategy to deliver the pre-processed target signal to the baseband processing module at a higher target data throughput. This operation is primarily accomplished through the collaborative work of the AXI_master module and the cross-clock domain conversion module within the SSAC module. This increased target data throughput enhances signal processing and transmission capabilities, enabling it to handle larger data volumes and improving overall system performance and responsiveness.

[0131] Specifically, if Figure 12 As shown in the figure, the SSAC module serves as the output interface of the system and is responsible for writing the data processed by DSHA into the data storage space within the SoC system for use by subsequent baseband processing modules or high-level protocol processing modules. Its functions include:

[0132] Data buffer FIFO module: Buffers continuous sampling results into FIFO and optionally packages them to optimize bandwidth utilization;

[0133] AXI master module: initiates AXI write operations and uses the standard AXI4 protocol to connect to the system bus;

[0134] Cross-clock domain conversion module: uses the AXI_x2x mechanism to achieve high-speed writing and stable transmission.

[0135] Specifically, in high-speed data interfaces, the rate mismatch between the RF front-end and baseband processor is typically addressed through large caches, which not only increases chip area but also introduces additional static power consumption. Furthermore, the lack of systematic optimization of data flow control between multi-level processing modules reduces effective energy efficiency. Traditional architectures struggle to achieve a dynamic balance between power consumption and performance, especially when handling bursty communications.

[0136] In a specific application, when the initial data throughput before signal processing is detected to be 1Mbps, the SSAC module's AXI_master module proactively increases the data rate based on the baseband processing system's needs. This increase dynamically adjusts the data transmission strategy by analyzing the cache status and the actual load of the baseband processor, ensuring that the increased transmission rate does not cause data backlogs or excessive processor load.

[0137] To achieve the data throughput increase from 1Mbps to 10Mbps, the SSAC module's cross-clock domain conversion mechanism played a key role. By leveraging the AXI_x2x bridging mechanism, a balance between high-speed writes and stable transmission was achieved. In practice, the SSAC module's FIFO cache unit, acting as an intermediate buffer, not only absorbs the rate difference between the signal processing module and the baseband processor but also pre-loads data to ensure a quick response and avoid data delays when increasing data throughput.

[0138] Through this mechanism, when the target signal needs to be transmitted to the baseband at a target data throughput rate of 10 Mbps, the SSAC module can quickly adjust its data transmission strategy to ensure stable and continuous data transmission. This process, through the backpressure control mechanism, coordinates the data flow between the RAIC, DSHA, and SSAC, ensuring the orderly and reliable data processing. Ultimately, it achieves high data throughput transmission, meeting the high-speed data processing requirements of satellite communication systems.

[0139] During the specific implementation process, after the above-mentioned digital receiver transmits the above-mentioned target signal to the baseband, the above-mentioned method also includes the following steps: the above-mentioned digital receiver stores the above-mentioned target signal in a cache; the above-mentioned digital receiver extracts the free capacity of the above-mentioned cache; and when the above-mentioned free capacity is less than or equal to the preset capacity threshold, the above-mentioned digital receiver slows down the speed of receiving the above-mentioned initial signal until the above-mentioned free capacity is greater than the above-mentioned preset capacity threshold.

[0140] In this solution, by dynamically adjusting the data receiving rate, cache overflow can be effectively avoided, the continuity of data processing and storage can be maintained, and data loss and overload can be prevented.

[0141] Specifically, the SSAC module temporarily stores processed data in its internal FIFO buffer module and continuously monitors the free capacity of the FIFO buffer to determine the system's storage space availability. The preset capacity threshold is a key control parameter used to balance the data reception rate and storage space utilization. When the free capacity of the FIFO buffer drops to or below the preset threshold, the SSAC module sends a backpressure signal feedback mechanism to the RAIC module to slow down the data reception rate to prevent data overflow and storage space exhaustion.

[0142] Reasonable setting of the preset capacity threshold can achieve refined control of data flow. For example, the preset capacity threshold is set to 20% of the total cache capacity.

[0143] In one embodiment, in a video streaming transmission scenario over a 4G mobile network, due to the high throughput and real-time requirements of video data, effective measures must be taken to ensure the continuity of data processing and storage. Assume that at a certain point in time, the free capacity of the system cache drops to 15% of the total capacity, i.e., below a preset capacity threshold. At this point, the FIFO cache mechanism in the SSAC module is triggered, and through the backpressure control mechanism, a command is sent to the RAIC module to slow down the speed of receiving digital signals from the RF chip until the free capacity of the cache is restored to at least above the preset threshold of 20%.

[0144] Specifically, the entire system uses a back-pressure control signal feedback mechanism to enable each module to adjust its working status in a timely manner under full / empty conditions, thus avoiding cache overflow and power waste.

[0145] Specifically, the single-channel storage access controller (SSAC) is used to achieve high-speed handling and reliable storage of DSHA output data. It includes a FIFO cache module, an AXI_master module, and an AXI bridge module. The SSAC as a whole acts as an efficient WDMA (Write DMA) data handling unit, responsible for writing processed data to the baseband processing module or system storage at a high throughput rate. Through the multi-level cache within the module and the cross-domain interface conversion mechanism, the stability and timing correctness of data transmission are guaranteed.

[0146] Specifically, the SSAC module integrates a WDMA transport mechanism to improve single-channel data processing capabilities and reduce access latency. It is highly configurable and adaptable to multiple standards such as 5G, 4G, satellite communications, and NB-IoT. It is particularly suitable for scenarios with strict power consumption constraints, such as mobile devices, satellite systems, and remote terminals.

[0147] Specifically, in the above solution, the back pressure control mechanism is used to coordinate the data flow between RAIC, DSHA and SSAC to prevent data loss and congestion, and improve processing continuity and power consumption performance.

[0148] The method specifically comprises the following steps:

[0149] Step 1: Receive the digital RF signal from the RF chip through the RAIC module, perform data preprocessing and static CORDIC down-conversion;

[0150] Step 2: Use the DSHA module to perform FIFO buffering, FARROW interpolation, multi-stage decimation filtering, and matched filtering in sequence;

[0151] Step 3: High-speed data transmission is completed through the SSAC module to the baseband processing module or storage system;

[0152] Step 4: Coordinate the module operation status through the back pressure control mechanism within the system to ensure data processing stability.

[0153] Specifically, the above-mentioned digital receiver of the present application adopts a three-level modular architecture, including a radio frequency adaptation interface controller (RAIC), a digital signal hardware accelerator (DSHA), and a single-channel storage access controller (SSAC). The RAIC module integrates the radio frequency interface and CORDIC down-conversion functions, the DSHA module integrates the FIFO buffer, Farrow interpolation filter, reconfigurable multi-stage extraction filter group and matched filter, and the SSAC module contains an efficient WDMA data handling unit. To improve power consumption efficiency, the RAIC module adopts a statically configured CORDIC algorithm to avoid dynamic computing overhead; the DSHA module implements reconfigurable filtering operations and optimizes power consumption performance through hardware multiplexing and multi-phase filtering strategies. The system coordinates various modules through a back pressure control mechanism to ensure data transmission stability and processing continuity. This method uses RAIC to complete signal preprocessing and down-conversion, uses DSHA to perform filtering and signal enhancement, and realizes high-speed data handling through SSAC. While ensuring reception performance, it effectively reduces system power consumption and optimizes chip hardware resource area, making it suitable for various wireless communication scenarios such as 5G, 4G and satellite communications.

[0154] In summary, the above solution achieves low-power, high-performance RF reception processing by optimizing the module structure and collaborative control mechanism, and is widely applicable to various wireless communication application scenarios.

[0155] The present application also provides a digital receiver. It should be noted that the digital receiver of the present application can be used to implement the digital receiver-based data transmission method provided in the present application. This digital receiver is used to implement the above-described embodiments and preferred implementations, and details already described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the digital receiver described in the following embodiments is preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0156] The digital receiver provided in the embodiments of the present application is introduced below.

[0157] Figure 13 FIG is a structural block diagram of a digital receiver according to an embodiment of the present application. Figure 13 As shown, the digital receiver includes:

[0158] An acquisition unit 10 is configured to acquire an initial signal, wherein the initial signal is a signal sent by a radio frequency chip;

[0159] A first processing unit 20 is configured to perform digital preprocessing on the initial signal to obtain an intermediate signal, wherein the digital preprocessing includes one or more of serial-to-parallel conversion, IQ deinterleaving, offset coding, IQ compensation, IQ scaling, IQ swapping, and IQ limiting;

[0160] A second processing unit 30 is configured to down-convert and / or filter the intermediate signal to obtain a target signal;

[0161] The transmission unit 40 is configured to transmit the target signal to a baseband.

[0162] Through this embodiment, after the digital receiver receives an initial signal, it performs digital preprocessing on the initial signal to obtain an intermediate signal, which is then down-converted and / or filtered. Down-conversion reduces the frequency of the received signal, thereby reducing the energy and resources required to process the signal. Filtering can filter out high-frequency noise and interference signals in the signal, reducing unnecessary energy consumption. Improving data throughput can reduce the retention time of data in the digital receiver, thereby reducing storage power consumption. This solution improves on the traditional DFE and can reduce power consumption through the above-mentioned processing.

[0163] During the specific implementation process, the second processing unit includes a first processing module, a second processing module and a third processing module. The first processing module is used to perform the above-mentioned down-conversion or the above-mentioned filtering on the above-mentioned intermediate signal to obtain the above-mentioned target signal. The above-mentioned filtering method includes one or more of Farrow interpolation filtering, extraction filtering, and matched filtering, wherein the extraction filtering is a cascade form of several filters; the second processing module is used to perform the above-mentioned down-conversion on the above-mentioned intermediate signal, and perform the above-mentioned filtering on the above-mentioned intermediate signal after the above-mentioned down-conversion to obtain the above-mentioned target signal; the third processing module is used to perform the above-mentioned filtering on the above-mentioned intermediate signal, and perform the above-mentioned down-conversion on the above-mentioned intermediate signal after the above-mentioned filtering to obtain the above-mentioned target signal.

[0164] In this solution, Farrow interpolation filtering, decimation filtering, and matched filtering technologies are used to improve signal purity and further reduce power consumption. Down-conversion can reduce the frequency of the received intermediate signals, thereby reducing the energy and resources required to process these signals, further reducing power consumption.

[0165] In some embodiments, the second processing unit includes an extraction submodule and a down-conversion submodule, the extraction submodule is used to extract the carrier frequency of the above-mentioned intermediate signal; the down-conversion submodule is used to use the CORDIC algorithm to convert the above-mentioned intermediate signal from the above-mentioned carrier frequency to the intermediate frequency carrier frequency to obtain the above-mentioned target signal, wherein the above-mentioned intermediate frequency carrier frequency is lower than the above-mentioned carrier frequency.

[0166] In this solution, the carrier frequency determines the specific parameter settings of the frequency conversion operation. Due to the static configuration characteristics of the CORDIC algorithm, dynamic calculation of the rotation angle is avoided, reducing unnecessary computing resource consumption, thereby further reducing power consumption.

[0167] In the specific implementation process, the second processing unit includes a first filtering submodule, a second filtering submodule and a third filtering submodule. The first filtering submodule is used to perform the above-mentioned Farrow interpolation filtering on the above-mentioned intermediate signal, or perform the above-mentioned extraction filtering on the above-mentioned intermediate signal, or perform the above-mentioned matched filtering on the above-mentioned intermediate signal to obtain the above-mentioned target signal; the second filtering submodule is used to filter the above-mentioned intermediate signal using the first filtering method to obtain the first filtered signal, and filter the above-mentioned first filtered signal using the second filtering method to obtain the above-mentioned target signal, wherein the above-mentioned first filtering method and the above-mentioned second filtering method are both the above-mentioned Farrow interpolation filtering, the above-mentioned matched filtering, and the above-mentioned target signal. The first filtering method is different from the second filtering method; the third filtering submodule is used to filter the intermediate signal by a third filtering method to obtain a second filtered signal, filter the second filtered signal by a fourth filtering method to obtain a third filtered signal, and filter the third filtered signal by a fifth filtering method to obtain the target signal, wherein the third filtering method, the fourth filtering method and the fifth filtering method are all one of the Farrow interpolation filter, the matched filter and the decimation filter, and the third filtering method, the fourth filtering method and the fifth filtering method are all different.

[0168] In this solution, the digital receiver performs one or more of Farrow interpolation filtering, decimation filtering, or matched filtering on the intermediate signal, so that the most appropriate filtering method can be selected and the appropriate filtering order can be used for filtering, thereby reducing interference in the signal and further reducing power consumption.

[0169] In some embodiments, the second processing unit is configured to perform the Farrow interpolation filtering on the intermediate signal using a first formula to obtain the target signal, wherein the first formula is:

[0170]

[0171] y(l) represents the target signal obtained by the Farrow interpolation filter, N represents the order of the filter, x() represents the intermediate signal, h() represents the time impulse response, k l represents the current sampling time point, k represents the sampling time point, T represents the sampling period, μ l Indicates the preset delay parameters, M represents the number of filters, Represents the preset coefficient matrix.

[0172] In this solution, the Doppler shift in 5G communications is effectively corrected through the precise parameter setting and flexible fractional delay interpolation capability of the Farrow interpolation filter. It can achieve signal interpolation with arbitrary fractional delay with low computational complexity, effectively correcting the Doppler effect of carrier frequency offset and code chip rate. Since the core of the Farrow interpolation filter is polynomial fitting, its calculation process can be effectively simplified, reducing the occupation of hardware resources, thereby further reducing power consumption.

[0173] In a specific implementation process, the second processing unit is used to perform the decimation filtering on the intermediate signal using a second formula to obtain the target signal, wherein the second formula is:

[0174]

[0175] y(n) represents the target signal obtained by the above extraction and filtering, L represents the length of the filter, x() represents the above intermediate signal,

[0176]

[0177] In some embodiments, the transmission unit includes an extraction module and a transmission module, the extraction module is used to extract the initial data throughput rate; the transmission module is used to transmit the above-mentioned target signal to the baseband at the target data throughput rate, wherein the above-mentioned target data throughput rate is higher than the above-mentioned initial data throughput rate.

[0178] In this solution, the increase in data throughput ensures the continuity and efficiency of signal processing and transmission. Even when processing signals with high data rates, it can ensure timely processing and transmission of signals to the baseband, meeting the needs of high-speed data communication.

[0179] During the specific implementation process, the above-mentioned device also includes a storage unit, an extraction unit and a speed adjustment unit. The storage unit is used to store the above-mentioned target signal in the cache after transmitting the above-mentioned target signal to the baseband; the extraction unit is used to extract the free capacity of the above-mentioned cache; the speed adjustment unit is used to slow down the speed of receiving the above-mentioned initial signal when the above-mentioned free capacity is less than or equal to the preset capacity threshold, until the above-mentioned free capacity is greater than the above-mentioned preset capacity threshold.

[0180] In this solution, by dynamically adjusting the data receiving rate, cache overflow can be effectively avoided, the continuity of data processing and storage can be maintained, and data loss and overload can be prevented.

[0181] The digital receiver includes a processor and memory. The acquisition unit, first processing unit, second processing unit, and transmission unit are all stored as program units in the memory. The processor executes the program units stored in the memory to implement the corresponding functions. The modules are all located in the same processor; alternatively, the modules can be located in different processors in any combination.

[0182] The processor includes a core, which retrieves the corresponding program unit from the memory. One or more cores can be set, and the problem of high power consumption of DFE in the existing technology can be solved by adjusting the core parameters.

[0183] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0184] An embodiment of the present invention provides a computer-readable storage medium, which includes a stored program. When the program is executed, the device containing the computer-readable storage medium is controlled to execute the digital receiver-based data transmission method.

[0185] An embodiment of the present invention provides a processor, which is used to run a program, wherein the program executes the data transmission method based on the digital receiver when running.

[0186] An embodiment of the present invention provides a device comprising a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements at least the steps of a data transmission method based on a digital receiver. The device herein may be a server, a PC, a PAD, a mobile phone, or the like.

[0187] A computer program product includes a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the digital receiver-based data transmission method in each embodiment of the present application are implemented.

[0188] The present application also provides a data transmission system, including a radio frequency chip, a baseband and a digital receiver, wherein the digital receiver is respectively communicatively connected to the radio frequency chip and the baseband, and the digital receiver is used to execute any one of the above-mentioned data transmission methods based on the digital receiver.

[0189] Obviously, those skilled in the art will appreciate that the various modules or steps of the present invention described above can be implemented using a general-purpose computing device, can be centralized on a single computing device, or can be distributed across a network of multiple computing devices. They can be implemented using program code executable by the computing device, and thus, can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described herein can be performed in a different order than that shown, or can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0190] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0191] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0192] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0193] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0194] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0195] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0196] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0197] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0198] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0199] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A data transmission method based on a digital receiver, characterized in that: include: The digital receiver obtains an initial signal, wherein the initial signal is a signal sent by the radio frequency chip; The digital receiver performs digital preprocessing on the initial signal to obtain an intermediate signal, wherein the digital preprocessing includes one or more of serial-to-parallel conversion, IQ deinterleaving, offset coding, IQ compensation, IQ scaling, IQ swapping, and IQ limiting; The digital receiver down-converts and / or filters the intermediate signal to obtain a target signal; The digital receiver transmits the target signal to baseband.

2. The method according to claim 1, characterized in that The digital receiver down-converts and / or filters the intermediate signal to obtain a target signal, including one of the following: The digital receiver performs the down-conversion or filtering on the intermediate signal to obtain the target signal, wherein the filtering method includes one or more of Farrow interpolation filtering, decimation filtering, and matched filtering, wherein the decimation filtering is a cascade form of multiple filters; The digital receiver performs the down-conversion on the intermediate signal, and performs the filtering on the down-converted intermediate signal to obtain the target signal; The digital receiver performs the filtering on the intermediate signal and performs the down-conversion on the filtered intermediate signal to obtain the target signal.

3. The method according to claim 2, characterized in that The digital receiver performs the down-conversion on the intermediate signal to obtain the target signal, comprising: The digital receiver extracts the carrier frequency of the intermediate signal; The digital receiver uses a CORDIC algorithm to convert the intermediate signal from the carrier frequency to an intermediate frequency carrier frequency to obtain the target signal, wherein the intermediate frequency carrier frequency is lower than the carrier frequency.

4. The method according to claim 2, characterized in that The digital receiver performs the filtering on the intermediate signal to obtain the target signal, including one of the following: The digital receiver performs the Farrow interpolation filtering on the intermediate signal, or performs the decimation filtering on the intermediate signal, or performs the matched filtering on the intermediate signal to obtain the target signal; The digital receiver filters the intermediate signal using a first filtering method to obtain a first filtered signal, and filters the first filtered signal using a second filtering method to obtain the target signal, wherein the first filtering method and the second filtering method are both one of the Farrow interpolation filter, the matched filter, and the decimation filter, and the first filtering method is different from the second filtering method; The digital receiver uses a third filtering method to filter the intermediate signal to obtain a second filtered signal, uses a fourth filtering method to filter the second filtered signal to obtain a third filtered signal, and uses a fifth filtering method to filter the third filtered signal to obtain the target signal, wherein the third filtering method, the fourth filtering method and the fifth filtering method are all one of the Farrow interpolation filtering, the matched filtering and the extraction filtering, and the third filtering method, the fourth filtering method and the fifth filtering method are all different.

5. The method according to claim 4, characterized in that The digital receiver performs the Farrow interpolation filtering on the intermediate signal to obtain the target signal, including: The digital receiver performs the Farrow interpolation filtering on the intermediate signal using a first formula to obtain the target signal, wherein the first formula is: y(l) represents the target signal obtained by the Farrow interpolation filter, N represents the order of the filter, x() represents the intermediate signal, h() represents the time impulse response, k l represents the current sampling time point, k represents the sampling time point, T represents the sampling period, μ l Indicates the preset delay parameters, M represents the number of filters, Represents the preset coefficient matrix.

6. The method according to claim 4, characterized in that The digital receiver performs the decimation filtering on the intermediate signal to obtain the target signal, comprising: The digital receiver performs the decimation filtering on the intermediate signal using a second formula to obtain the target signal, wherein the second formula is: y(n) represents the target signal obtained by the decimation filtering, L represents the length of the filter, x() represents the intermediate signal, 7. The method according to claim 1, characterized in that The digital receiver transmits the target signal to a baseband, comprising: The digital receiver extracts an initial data throughput rate; The digital receiver transmits the target signal to a baseband at a target data throughput rate, wherein the target data throughput rate is higher than the initial data throughput rate.

8. The method according to any one of claims 1 to 7, characterized in that After the digital receiver transmits the target signal to a baseband, the method further includes: The digital receiver stores the target signal in a buffer; The digital receiver extracts the free capacity of the buffer; When the idle capacity is less than or equal to a preset capacity threshold, the digital receiver slows down the speed of receiving the initial signal until the idle capacity is greater than the preset capacity threshold.

9. A digital receiver, characterized in that: include: an acquiring unit, configured to acquire an initial signal, wherein the initial signal is a signal sent by a radio frequency chip; a first processing unit, configured to perform digital preprocessing on the initial signal to obtain an intermediate signal, wherein the digital preprocessing comprises one or more of serial-to-parallel conversion, IQ deinterleaving, offset coding, IQ compensation, IQ scaling, IQ swapping, and IQ limiting; a second processing unit, configured to down-convert and / or filter the intermediate signal to obtain a target signal; A transmission unit is used to transmit the target signal to a baseband.

10. A data transmission system, characterized in that: include: RF chips; baseband; A digital receiver, wherein the digital receiver is respectively connected to the radio frequency chip and the baseband communication, and the digital receiver is used to execute the data transmission method based on the digital receiver according to any one of claims 1 to 8.

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