Dynamic timing loop gain to compensate for phase interpolator nonlinearity

Abstract

The invention relates to a dynamic timing loop gain for compensating for phase interpolator nonlinearity. An integrated circuit transceiver with a digital timing recovery loop with phase interpolation may compensate for nonlinearity of phase interpolation in conjunction with dynamic loop gain. An illustrative integrated receiver circuit includes a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. A phase interpolator provides a sampled signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element generates a digital reception signal by sampling an analog reception signal according to a sampling signal; the timing error estimator generates a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scaling factor dependent on the phase control signal.

Description

Background Art

[0001] Digital communication occurs between a transmitting device and a receiving device over an intermediate communication medium (e.g., fiber optic cable or insulated copper wire) having one or more designated communication channels (e.g., carrier wavelengths or frequency bands). Each transmitting device typically transmits symbols at a fixed symbol rate, while each receiving device detects potentially corrupted symbol sequences and attempts to reconstruct the transmitted data.

[0002] A "symbol" is a state or significant condition of a channel that persists for a fixed period of time, called a "symbol interval." For example, a symbol can be a voltage or current level, an optical power level, a phase value, or a specific frequency or wavelength. The change from one channel state to another is called a symbol transition. Each symbol can represent (i.e., encode) one or more binary bits of data. Alternatively, data can be represented by symbol transitions or by a sequence of two or more symbols. The simplest digital communication links use only one bit per symbol; a binary "0" is represented by one symbol (e.g., a voltage or current signal within a first range), and a binary "1" is represented by another symbol (e.g., a voltage or current signal within a second range).

[0003] Channel imperfections create dispersion, which can cause each symbol to interfere with its neighbors, resulting in inter-symbol interference (ISI). As the symbol rate increases, ISI can make it difficult for a receiving device to determine which symbols were sent in each interval (especially when such ISI is combined with additive noise).

[0004] The public literature discloses numerous equalization and demodulation techniques for recovering digital data from degraded received signals even in the presence of ISI. Key to such techniques is determining the correct sampling timing, as sampling timing directly impacts the signal-to-noise ratio of discrete samples. Numerous strategies exist for detecting and tracking the optimal sampling time, with varying degrees of tradeoff between simplicity and performance. Notable examples can be found, for example, in U.S. Patent 7,058,150, “High-Speed ​​Serial Data Transceiver and Related Methods,” and U.S. Patent 10,892,763, “Second-order Clock Recovery Using Three Feedback Paths,” both of which are incorporated herein by reference. These examples are particularly noteworthy due to their use of sampling clock phase interpolators.

[0005] Nonlinearity is a potential problem when using phase interpolators, and it becomes more challenging at higher clock frequencies. The authors have found that such nonlinearities can cause oscillations and instabilities in the clock recovery circuit, leading to a corresponding degradation in receiver performance. Summary of the Invention

[0006] Thus, disclosed herein are integrated circuit transceivers, receivers, and methods having digital timing recovery loops with phase interpolation and dynamic loop gain to compensate for nonlinearities in the phase interpolation. An illustrative integrated receiver circuit includes a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator is configured to provide a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element is configured to generate a digital receive signal by sampling an analog receive signal according to the sampling signal. The timing error estimator is configured to generate a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit is configured to derive a phase control signal from the timing error signal, the feedback circuit including a scaling element configured to scale the estimated timing error by a scaling factor that depends on the phase control signal.

[0007] An illustrative clock recovery method includes: providing a phase control signal to a phase interpolator to derive a sampling signal from a clock signal; sampling an analog received signal according to the sampling signal to obtain a digital received signal; generating a timing error signal, which indicates an estimated timing error of the sampling signal relative to the analog received signal; and deriving a phase control signal from the estimated timing error, the deriving including scaling the estimated timing error by a scaling factor that depends on the phase control signal.

[0008] The aforementioned circuit can be embodied as a semiconductor IP core residing on a non-transitory information storage medium. The core can use, for example, a hardware description language to represent a circuit schematic, or use, for example, GDSII or OASIS language to represent a semiconductor manufacturing process mask pattern.

[0009] Each of the above features may be implemented individually or in combination, and may be implemented in any suitable combination with any one or more of the following features: 1. A demodulator that extracts the transmitted symbol stream from the digital received signal. 2. A histogram circuit configured to determine the relative probability of each phase control signal value. 3. An inverting element configured to determine a scaling factor using the inverse of the relative probabilities. 4. The scaling factor is stored in a lookup table configured to receive the phase control signal. 5. The scaling factor is derived from the contents of the lookup table configured to receive the phase control signal. 6. The scaling element is part of a first feedback path in the feedback circuit, the first feedback path being configured to minimize the phase component of the estimated timing error. 7. The feedback circuit includes a second feedback path configured to minimize the frequency component of the estimated timing error. 8. A fractional-frequency phase-locked loop configured to generate a clock signal. 9. The scaling element is part of a first feedback path in the feedback circuit, the first feedback path being configured to minimize the phase component of the estimated timing error. 10. The feedback circuit includes an additional feedback path configured to derive a division ratio error from the estimated timing error. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An illustrative network is shown.

[0011] Figure 2 is a block diagram of an illustrative switch.

[0012] Figure 3-6 Illustrative digital communications receivers with different clock recovery circuit configurations are shown.

[0013] Figure 7 is a block diagram of an illustrative nonlinear compensation circuit.

[0014] Figure 8 is a block diagram of an illustrative decision feedback equalizer ("DFE").

[0015] Figure 9 is a block diagram of an illustrative parallelized DFE. DETAILED DESCRIPTION

[0016] While specific embodiments are presented in the drawings and the following description, it should be noted that they do not limit the present disclosure. Rather, they provide a basis for one of ordinary skill in the art to identify alternatives, equivalents, and modifications that are included within the scope of the appended claims.

[0017] For context, Figure 1An illustrative network, such as might be found in a data processing center, is shown in which a plurality of server racks 102-106 each contain a plurality of servers 110 and at least one "top of rack" (TOR) switch 112. The TOR switches 112 are connected to an aggregator switch 114 for interconnecting and connecting to a regional network and the Internet. (As used herein, the term "switch" includes not only traditional network switches, but also routers, bridges, hubs, and other devices that forward network communication packets between ports.) Each of the servers 110 is connected to the TOR switch 112 by a network cable 120 that can transmit signals at a high symbol rate.

[0018] Figure 2 An illustrative switch 112 is shown having an application-specific integrated circuit (ASIC) 202 that implements packet switching functionality coupled to a port connector 204 of a line card or "pluggable module" 206. The pluggable module 206 is coupled between the port connector 204 and a cable connector 208 to improve communication performance through equalization and optional format conversion (e.g., conversion between electrical and optical signals). The pluggable module 206 can conform to any of a variety of pluggable module standards, including SFP, SFP-DD, QSFP, QSFP-DD, and OSFP. Alternatively, the cable itself can have a connector that conforms to the pluggable module standard and contains pluggable module circuitry.

[0019] The pluggable modules 206 may each include a retimer chip 210 and a microcontroller chip 212 that controls the operation of the retimer chip 210 according to firmware and parameters that may be stored in non-volatile memory 214. The operating mode and parameters of the pluggable retimer modules 206 may be set via a two-wire bus (such as I2C or MDIO) that connects the microcontroller chip 212 to a host device (e.g., switch 112). The microcontroller chip 212 responds to queries and commands received via the two-wire bus and, in response, retrieves information from and saves information to the control registers 218 of the retimer chip 210.

[0020] The retimer chip 210 includes a host-side transceiver 220 coupled to a line-side transceiver 222 via a first-in, first-out (FIFO) buffer 224. Although only a single channel is shown, the transceiver can support multiple channels transmitted via multiple corresponding optical fibers or electrical conductors. A controller 226 coordinates the operation of the transceiver based on the contents of the control registers and can provide multiple communication phases in accordance with a communication standard (such as the Fibre Channel standard promulgated by the National Institute for Standards and Technology (INCITS)). This provides phases for link speed negotiation (LSN), equalizer training, and normal operation.

[0021] The receiver portion of each transceiver can employ any of the many equalization and demodulation techniques disclosed in the public literature to recover the digital data from a degraded received signal even in the presence of ISI. As previously mentioned, the key to such techniques is the determination of correct sampling timing, as sampling timing directly affects the signal-to-noise ratio of discrete samples.

[0022] Figure 3-Figure 6 Various clock recovery methods that can be implemented by illustrative integrated receiver circuits are shown. The illustrated receivers each employ a phase interpolator as part of the clock recovery circuit and further employ dynamic gain in the digital timing loop to compensate for potential nonlinearities of the phase interpolator.

[0023] Figure 3 The receiver includes an analog-to-digital converter 304 or other sampling element that samples the analog received signal 302 at sampling instants corresponding to transitions in the sampled signal 305, thereby providing a digital received signal to a demodulator 306. The demodulator 306 can apply equalization and symbol detection using, for example, a matched filter, a decision feedback equalizer, a maximum likelihood sequence estimator, or other suitable techniques to extract the digital symbol stream conveyed by the analog received signal. The resulting detected symbol stream 308 can be provided as a parallelized symbol stream for processing by the "on-chip" circuit system (e.g., FIFO buffering, error correction, and retransmission).

[0024] Demodulator 306 includes some form of timing error estimator for generating an estimated timing error signal 310. Any suitable design may be used for the timing error estimator, including, for example, a bang-bang phase detector or a proportional phase detector. Suitable timing error estimators are described in commonly-owned U.S. Patent 10,447,509, “Precompensator-based quantization for clock recovery,” which is incorporated herein by reference in its entirety. Other suitable timing error estimators can be found in the public literature, including, for example, Mueller, “Timing Recovery in Digital Synchronous Data Receivers,” IEEE Journal of Communications, Vol. 24, No. 5, May 1976, and Musa, “High-speed Baud-Rate Clock Recovery,” University of Toronto Dissertation, 2008.

[0025] exist Figure 3 In the embodiment, the feedback circuit derives a phase control signal from the timing error signal 310 to control the phase interpolator 320 in a manner that statistically minimizes the timing error signal 310. The frequency error accumulator 312 generates a phase control signal after the timing error signal has been processed by the frequency coefficient (K F ) is scaled and then the timing error signal is integrated to obtain the frequency offset signal. The multiplier or other scaling element 314 uses the dynamic phase coefficient (K P ) scales the phase error. Adder 316 adds the scaled phase error to the frequency offset signal. Filter 318 operates on the output of adder 316 to obtain a control signal for phase interpolator 320. Figure 3 , filter 318 is shown as an accumulator, but other filter implementations would also be suitable.

[0026] Phase interpolator 320 also receives a clock signal from a phase-locked loop (PLL) 322. The phase control signal causes phase interpolator 320 to generate a sampled signal by adjusting the phase of the clock signal in a manner that minimizes the expected value of the timing error signal. In other words, the control signal compensates for both the frequency offset component and the phase component of the estimated timing error of the clock signal relative to analog received signal 302, thereby phase-aligning sampled signal 305 with the data symbols in analog received signal 302. Various suitable phase interpolator implementations can be found in the public literature. See, for example, U.S. Patent 7,058,150 to Buchwald et al., "High-Speed ​​Serial Data Transceiver and Related Methods."

[0027] The clock signal generated by PLL 322 is a multiplied version of the reference clock signal from reference oscillator 324. Voltage-controlled oscillator (VCO) 326 supplies the clock signal to both phase interpolator 320 and counter 328, which divides the frequency of the clock signal by a constant modulus, N. The counter supplies the divided clock signal to phase frequency detector (PFD) 330. PFD 330 may use a charge pump (CP) as part of determining which input (i.e., the divided clock signal or the reference clock signal) has earlier or more frequent transitions than the other. Low-pass filter 332 filters the output of PFD 330 to provide a control voltage for VCO 326. The filter coefficients are selected so that the divided clock becomes phase-aligned with the reference oscillator.

[0028] It should be noted that for at least some intended uses, the reference clock used by the receiver will typically drift relative to the reference clock used by the transmitter, and may differ by hundreds of ppm. Figure 3 In an embodiment, the resulting frequency offset between the clock signal output of the PLL and the analog data signal may need to be corrected by continuous phase rotation by the phase interpolator 320. This mode of operation places stringent requirements on the linearity of the phase interpolator 320 throughout its tuning range, as the interpolator will repeatedly cycle through each of the phase interpolations during the continuous rotation.

[0029] The presence of phase interpolation nonlinearity can be visualized as a dependence of the feedback loop gain on the current phase interpolation setting of the phase interpolator, causing the clock recovery circuit to be more or less sensitive to timing errors depending on the control signal value. In the presence of continuous phase rotation, this sensitivity can be observed as a change in the probability for each phase interpolation setting. (Continuous phase rotation can be introduced by, for example, adding a small offset bias to the phase error signal 310, adjusting the frequency offset stored by the frequency accumulator 312, causing the adder 316 to introduce an additional offset, or adjusting the PLL to introduce the actual frequency offset). Those phase interpolation settings that have reduced sensitivity to phase errors will exhibit a higher probability relative to those phase interpolation settings that have enhanced sensitivity and therefore an accelerated response to small phase errors. Once the relative probability of each phase control signal value is determined, the feedback loop gain can be dynamically adjusted to compensate for the phase interpolator nonlinearity. In Figure 3 In the example, dynamic adjustment is provided by a lookup table 340 which provides the phase coefficient K depending on the control signal value of the phase interpolator. P .

[0030] Figure 3 The receiver further includes a histogram circuit 342 for determining the relative probabilities of phase interpolation settings when successive phase rotations are introduced. The histogram circuit 342 can intermittently sample the values ​​of the control signal over a sufficiently long time window to ensure that the histogram statistics represent the relative probabilities. A histogram count is obtained for each possible value of the control signal. An inversion element 344 converts each histogram count into a corresponding phase coefficient K. P or optionally converted to a phase coefficient K P The normalized scaling factor of the control signal is calculated and the result is stored in the location associated with the value of the control signal in the lookup table 340. A microcontroller programmed with firmware can perform the function of the inverting element 344.

[0031] Figure 4 A receiving module embodying an alternative clock recovery circuit configuration is provided. The receiving module retains an analog-to-digital converter 304 for sampling an analog received signal 302 and providing a digital received signal to a demodulator 306. As previously described, the demodulator includes a timing error estimator that generates a timing error signal 310, and a feedback circuit having a feedback path with a dynamic phase coefficient (K P ) accumulator 314 and the feedback path of the filter. However, Figure 3 The frequency offset accumulator 312 in this embodiment is replaced by another feedback path that couples the timing error signal 310 to the fractional frequency phase locked loop 422 to correct the frequency offset separately from the phase interpolator 320. This feedback path includes a frequency division ratio scaling factor (K D) and the frequency division ratio error accumulator 412, which supplies the frequency division ratio control signal to the fractional frequency division phase locked loop 422.

[0032] A fractional frequency phase-locked loop 422 is used in place of the original phase-locked loop 322 to provide finer-grained frequency control of the clock signal supplied to the phase interpolator 322. The division ratio control signal adjusts the frequency offset of the clock signal relative to the data in the analog receive signal 302, substantially reducing the phase rotation rate required from the phase interpolator 320.

[0033] Figure 3 and Figure 4 The comparison of FIGURE 4 shows that both the phase-locked loop 322 and the fractional-N phase-locked loop 422 employ a PFD / CP 330 (to compare the divided clock signal with the reference clock), a low-pass filter 332 (to filter the error to reduce noise), and a voltage-controlled oscillator 326 (to supply the output clock signal). Rather than using a fixed-modulus divider 328, the fractional-N phase-locked loop 422 uses a multi-modulus divider 428 to divide the output clock signal. The multi-modulus divider 428 divides by N or N+1, depending on whether the modulus select signal is asserted at the end of the count cycle (or, in alternative embodiments, at the beginning of the count cycle or at any point during the count cycle). A delta-sigma modulator (DSM) 429 converts the divide ratio control signal into pulses for the modulus select signal. The pulse density controls which fractional value between N and N+1 the divider implements, enabling very fine control of the clock frequency supplied to the interpolator 320.

[0034] We now turn to Figure 5 , which shows that including Figure 3 The feedback path in the embodiment and Figure 4 To ensure that the division ratio error accumulator 412 and the frequency offset accumulator 512 operate in concert, the frequency offset error accumulator 312 may be modified to include a leakage coefficient K L In the modified accumulator 512, the frequency offset signal is multiplied by (1-K L ). Leakage coefficient (K L) represents a gradual loss of memory, which, while enabling the feedback path to provide a fast response, causes the frequency offset signal to approach zero over a longer time scale. The division ratio error accumulator 412, in conjunction with the low-pass filter 332 of the phase-locked loop 422, operates over a longer time scale to overcome the memory loss of the modified accumulator 512. Under steady-state or slowly changing conditions, frequency offset correction is provided by the division ratio error accumulator 412, thereby reducing the rate of continuous phase rotation that the phase interpolator 320 might otherwise need to provide. Under conditions where the frequency offset is changing more rapidly, the modified frequency offset accumulator 512 provides more transient correction.

[0035] Figure 6 Yet another feedback circuit configuration is shown, in which the modified frequency offset accumulator 512 is further modified into a second-order filter 612, and an adder 616 combines the output of the second-order filter 612 with the output of the phase error filter 318 to form the phase interpolator control signal. Figure 5 This implementation enables different filters and accumulators to be driven at different clock frequencies, which is potentially advantageous for some applications.

[0036] Figure 7 More specifically, an illustrative implementation of a nonlinear compensation circuit (elements 340-344) is shown. Figure 7 , histogram circuit 342 includes a memory 702 that can be reset to a clear state by a CLR signal from a controller 710. When an address is supplied to memory 702, the memory 702 responsively provides read data (RD) representing the contents of the selected address location to adder 704, which increments the contents by one. A saturation element 706 prevents the contents from rolling over beyond the maximum value that memory 702 can store, for example, by detecting whether the incremented value is all zeros, in which case the saturation element can set the memory location contents to all ones. Memory 702 can be configured to accept the value from saturation element 706 as write data (WD) for storage at the address location.

[0037] Multiplexer 708 supplies the address to memory 702. When the histogram circuit 342 is collecting statistical data, multiplexer 708 is configured to provide the phase interpolator phase setting control signal value as an address to memory 702, enabling memory 702 to increment the contents of the location corresponding to the current value of the control signal. Once the collection window is closed, multiplexer 708 is configured to forward any address supplied by controller 710, enabling the controller to access the histogram counts for processing or storage elsewhere.

[0038] The controller 710 can supply a clock signal to the memory 702 during the collection window. The memory clock signal can be derived from the sampling clock signal, where the counter 712 is within the length of the collection window (e.g., 2 N The enable signal EN is asserted when N is large enough to provide reliable statistical data collection without being so large as to saturate any histogram counts. Some implementations may adjust N, such as decreasing N if saturation is detected or increasing N if any histogram count is below a predetermined threshold at the end of the collection window. When the collection window closes, that is, when the counter 712 reaches 2 N When , gate 714 blocks the memory clock signal. To reduce the correlation, divider 716 can divide the memory clock signal by a factor of 2. L Reduce the sampling clock frequency so that the phase interpolator controls the signal value sampling interval, for example, every 2 L The sample is sampled once every code element.

[0039] Once the collection window is closed, the controller 710 can systematically retrieve the histogram counts and store the corresponding reciprocal (multiplicative inverse) values ​​provided by the inversion element 344 in the lookup table 340. The illustrated lookup table 340 includes a memory 720 that receives an address from a multiplexer 728. The multiplexer 728 is initially set to provide an address location selected by the controller 710, which can further provide a read / write signal 724 to store the inverse histogram count or other multiplicative K value. P Once the lookup table 720 has been filled, the multiplexer 728 is configured to provide the current value of the phase interpolator control signal PHS as an address, causing the lookup table to provide the corresponding K P The multiplier 726 can determine the selected K P Factor and nominal K P The product of the coefficient values ​​is used as the dynamic phase coefficient K P_dyn .

[0040] In a contemplated variation, the memory 702 may be employed both for the collection of histogram counts and as a lookup table during normal operation of the receiver. Once the histogram count collection process is complete, the incrementing circuitry is disabled. The controller 710 may store the K values ​​derived from the histogram counts. P factor, or alternatively, K can be derived from the histogram counts by inverting the elements as needed. P factor.

[0041] Figure 8 and Figure 9 An illustrative receiver embodiment is shown to provide additional details of the implementation of demodulator 306 and insight into adapting clock recovery circuitry for parallelism.

[0042] Figure 7 An illustrative digital receiver is shown that includes a continuous time linear equalizer ("CTLE") 801 to attenuate out-of-band noise and optionally provide some spectral shaping to improve the response to high-frequency components of the received signal. An ADC 304 is provided to digitize the received signal, and a digital filter (also known as a feed-forward equalizer or "FFE") 802 performs further equalization to further shape the overall channel response of the system and minimize the impact of leading ISI on the current symbol. As part of shaping the overall channel response, the FFE 802 can also be designed to shorten the channel response of the filtered signal while minimizing any accompanying noise enhancement.

[0043] Adder 803 subtracts an optional feedback signal from the output of FFE 802 to minimize the effect of post-ISI on the current symbol, thereby generating an equalized signal that is coupled to a decision element ("slicer") 804. Decision element 804 includes one or more comparators that compare the equalized signal with corresponding decision thresholds to determine, for each symbol interval, which constellation symbol the signal's value most closely corresponds to. The equalized signal may also be referred to herein as the "combined signal."

[0044] The decision element 804 generates a symbol decision sequence (denoted as A k , where k is the time index.) In some contemplated embodiments, the signal constellation is a bipolar (non-return-to-zero) constellation representing -1 and +1, requiring the use of only one comparator with a decision threshold of zero. In some other contemplated embodiments, the signal constellation is PAM4 (-3, -1, +1, +3), requiring the use of three comparators with decision thresholds of -2, 0, and +2, respectively. (For generality, the units used to express symbols and thresholds are omitted, but can be assumed to be volts for purposes of explanation. In practice, a scaling factor will be employed.)

[0045] Feedback filter ("FBF") 805 uses the stored recent output symbol decisions (A k-1 、A k-2 ,…,A k-N , where N is the filter coefficient f i The feedback signal is derived by a series of delay elements (e.g., latches, flip-flops, or registers) with a number of bits. Each stored symbol is associated with a corresponding filter coefficient f i are multiplied, and these products are combined to obtain the feedback signal.

[0046] Additionally, we note that the receiver also includes a filter coefficient adaptation unit, but such considerations are addressed in the literature and are well known to those skilled in the art. However, we note that at least some contemplated embodiments include one or more additional comparators in decision element 804 for comparing the combined signal with one or more of the symbol values, thereby providing an error signal that can be used for timing recovery and / or coefficient adaptation.

[0047] As symbol rates increase into the gigahertz range, it becomes increasingly difficult for the ADC 304 and demodulator 306 components to fully perform their required operations within each symbol interval, making it advantageous to parallelize their operations. Parallelization generally involves the use of multiple components that share the workload by taking turns, thereby providing each of the components with more time to complete its operations. Such parallel components are driven by a set of staggered clock signals. For example, quadruple parallelization employs a set of four clock signals, each with a frequency of one-quarter the symbol rate, such that each symbol interval in the set of staggered clock signals contains only one upward transition. While quadruple parallelization is used for discussion purposes herein, the actual degree of parallelization can be higher, for example, 8x, 16x, 32x, or 64x. Furthermore, the degree of parallelization is not limited to powers of 2.

[0048] Figure 9 An illustrative receiver with a parallelized equalizer implementation (including an optional feedback filter for DFE) is shown. Figure 8 Similar to the implementation of CTLE 801, CTLE 801 filters the channel signals to provide received signals, which are provided in parallel to an array of analog-to-digital converters (ADC0-ADC3). Each of the ADC elements is provided with one of the corresponding interleaved clock signals. The clock signals have different phases, causing the ADC elements to take turns sampling and digitizing the received signals, so that at any given time, only one of the ADC element outputs is transitioning.

[0049] An array of FFEs (FFE0 to FFE3), each forming a weighted sum of the ADC element outputs. The weighted sum employs filter coefficients that are cyclically shifted relative to each other. FFE0 operates on the held signals from ADC3 (elements operating before CLK0), ADC0 (elements responsive to CLK0), and ADC1 (elements operating after CLK0) such that during the assertion of CLK2, the weighted sum produced by FFE0 is summed with FFE 802 ( Figure 8) corresponds to the output of FFE 802. FFE1 operates on the held signals from ADC0 (the element operating before CLK1), ADC1 (the element responsive to CLK1), and ADC2 (the element operating after CLK1) so that during the assertion of CLK3, the weighted sum corresponds to the output of FFE 802. The operation of the remaining FFEs in the array follows the same pattern with associated phase shifts. In practice, the number of filter taps can be smaller, or the number of elements in the array can be larger, to provide a longer valid output window.

[0050] and Figure 8 Like a receiver, an adder can combine the output of each FFE with a feedback signal to provide an equalized signal to the corresponding decision element. Figure 9 An array of decision elements (Limiter 0 to Limiter 3) is shown, each operating on an equalized signal derived from a corresponding FFE output. Figure 8 Like the decision elements of FIG, the illustrated decision element uses a comparator to determine which symbol the equalized signal most likely represents. The decision is made when the corresponding FFE output is valid (e.g., limiter 0 operates when CLK2 is asserted, limiter 1 operates when CLK3 is asserted, etc.). Preferably, the decision is provided in parallel on the output bus to enable a lower clock rate to be used for subsequent operations.

[0051] An array of feedback filters (FBF0-FBF3) operates on the previous symbol decisions to provide feedback signals for the adder. As with the FFE, the input to the FBF is cyclically shifted and is only used when the input corresponds to the FBF 805 ( Figure 8 ) content, consistent with the time window of the corresponding FFE. In practice, the number of feedback filter taps can be less than that shown, or the number of array elements can be larger to provide a longer valid output window.

[0052] and Figure 8 Like the decision-making element, Figure 9 The decision elements in may each employ additional comparators to provide timing recovery information, coefficient training information, and / or pre-calculation to expand one or more taps of the feedback filter. Figure 9 In an embodiment of the present invention, the digital timing circuit is also parallelized, wherein the timing error estimator 910 receives the codeword decision and the equalized signal in parallel to determine the timing error signal 310 ( Figure 3). A set of timing loop filters 912 implements the feedback circuitry discussed previously to provide control signals to a phase interpolator 920 and a division ratio control signal to the PLL. Phase interpolator 920 operates similarly to phase interpolator 320 to convert the PLL clock signal into a set of interleaved clock signals having evenly spaced phase and symbol-aligned transitions. A set of delay lines (DL0-DL3) is provided for fine-tuning the individual clock phases relative to each other as needed, for example, to compensate for different propagation delays of the various ADC elements.

[0053] The delay lines can be individually adjusted by clock skew adjustment circuit 944 based on parameters from controller 942. Controller 942 can optimize the clock skew adjustment settings based on reliability indicators from the monitoring circuits. Figure 9 In FIG, the monitoring circuit is a margin calculator 940 that calculates the minimum difference between the equalized signal and the decision threshold (or equivalently, the maximum error between the equalized signal and the nominal symbol value). Clock offset adjustment is described in more detail in commonly-owned U.S. application Ser. No. 16 / 836,553, “Eye Monitor for Parallelized Digital Equalizers,” filed Mar. 31, 2020, which is incorporated herein by reference in its entirety.

[0054] Most integrated circuit devices that incorporate receiver and clock recovery circuitry have become so complex that designing them from scratch is impractical for electronic device designers. Instead, electronic device designers rely on predefined modular units designed using integrated circuit layouts, arranging and joining them as needed to implement the various functions of the desired device. Each modular unit has a defined interface and behavior that has been verified by its creator. Although creating each modular unit can require significant time and investment, the availability of modular units for reuse and further development significantly reduces product cycle time and enables better products. Predefined units can be organized hierarchically, where a given unit contains one or more lower-level units, which in turn are contained within higher-level units. Many organizations maintain libraries of such predefined modular units for sale or licensing, including, for example, embedded processors, memories, interfaces for different bus standards, power converters, frequency multipliers, sensor transducer interfaces, and so on. Predefined modular units are also referred to as cells, blocks, cores, and macros; these terms have different meanings and variations ("intellectual property (IP) cores," "soft macros"), but are often used interchangeably.

[0055] Modular cells can be expressed in different ways, for example, as hardware description language (HDL) files or as fully routed designs that can be directly printed to create a range of manufacturing process masks. Fully routed design files are often process-specific, meaning additional design effort is often required to migrate the modular cells to different processes or manufacturers. Modular cells in HDL form require subsequent synthesis, placement, and routing steps to implement, but they are process-independent, meaning that different manufacturers can apply their preferred automated synthesis, placement, and routing processes to implement the cells across a wide range of manufacturing processes. Due to their higher-level representation, HDL cells are more amenable to modification and the use of variable design parameters, while fully routed cells can provide greater predictability in terms of area requirements, reliability, and performance. While there are no fixed rules, digital block designs are more commonly specified in HDL form, while analog and mixed-signal cells are more commonly specified as lower-level physical descriptions. In any case, such semiconductor IP cores can be maintained in a design database that resides on a non-transitory information storage medium. Once the device has been fully designed, commercially available software can convert the semiconductor intellectual property core and other integrated circuit components into semiconductor mask patterns, which are also stored on non-transitory information storage media. These patterns can then be transferred to various processing units on the appropriate assembly lines in an integrated circuit fabrication facility.

[0056] Numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, the above description focuses on the use of an integral-based accumulator, but other recursive filter or moving average filter implementations that provide a low-pass filter response may also be employed. It is intended that the claims be interpreted as encompassing all such alternatives, equivalents, and modifications as fall within the scope of the appended claims.

Claims

1. An integrated receiver circuit, comprising: a phase interpolator configured to provide a sampled signal by applying a phase shift to the clock signal in response to a phase control signal; a sampling element configured to generate a digital reception signal by sampling an analog reception signal according to the sampling signal; a timing error estimator configured to generate a timing error signal indicating an estimated timing error of the sampled signal relative to the analog received signal; as well as A feedback circuit is configured to derive the phase control signal from the timing error signal, the feedback circuit comprising a scaling element configured to scale the estimated timing error by a scaling factor that depends on the phase control signal.

2. The integrated receiver circuit of claim 1 , further comprising a demodulator that derives a stream of digital symbols from the digital received signal.

3. The integrated receiver circuit of claim 1 , further comprising a histogram circuit configured to determine a relative probability of each phase control signal value. 4 . The integrated receiver circuit of claim 3 , further comprising an inverting element configured to determine the scaling factor using an inverse of the relative probability. 5 . The integrated receiver circuit of claim 1 , wherein the scaling factor is stored in a lookup table configured to receive the phase control signal.

6. The integrated receiver circuit of claim 1, wherein the scaling factor is derived from contents of a lookup table configured to receive the phase control signal.

7. The integrated receiver circuit of claim 1 , wherein the scaling element is part of a first feedback path in the feedback circuit, the first feedback path being configured to minimize a phase component of the estimated timing error, the feedback circuit further comprising a second feedback path being configured to minimize a frequency component of the estimated timing error.

8. The integrated receiver circuit of claim 1 , further comprising a fractional-frequency phase-locked loop configured to generate the clock signal, wherein the scaling element is part of a first feedback path in the feedback circuit, the first feedback path configured to minimize a phase component of the estimated timing error, the feedback circuit further comprising an additional feedback path configured to derive a division ratio error from the estimated timing error.

9. A clock recovery method, comprising: providing a phase control signal to a phase interpolator to derive a sampled signal from the clock signal; Sampling the analog received signal according to the sampling signal to obtain a digital received signal; generating a timing error signal indicating an estimated timing error of the sampled signal relative to the analog received signal; as well as The phase control signal is derived from the estimated timing error, the deriving comprising scaling the estimated timing error by a scaling factor that depends on the phase control signal.

10. The clock recovery method of claim 9, further comprising demodulating the digital received signal to extract a digital symbol stream.

11. The clock recovery method of claim 9, further comprising determining a relative probability of each phase control signal value.

12. The clock recovery method of claim 11, further comprising determining the scaling factor using an inverse of the relative probability.

13. The clock recovery method of claim 9, wherein the phase control signal is used to retrieve the scaling factor from a lookup table.

14. The clock recovery method of claim 9, wherein the phase control signal is used to retrieve relative probabilities from a lookup table, and wherein the method further comprises deriving the scaling factor from the relative probabilities.

15. The clock recovery method of claim 9, wherein the scaling is performed in a first feedback path to minimize a phase component of the estimated timing error, and wherein the deriving the phase control signal employs a second feedback path to minimize a frequency component of the estimated timing error.

16. A clock recovery method as claimed in claim 9, wherein the scaling is performed in a first feedback path to minimize the phase component of the estimated timing error, and wherein the method further includes providing a division ratio error to a fractional frequency phase-locked loop that provides the clock signal, the division ratio error being derived from the estimated timing error.

17. A non-transitory information storage medium having a semiconductor intellectual property core for generating a circuit system, the circuit system comprising: a phase interpolator configured to provide a sampled signal by applying a phase shift to the clock signal in response to a phase control signal; a sampling element configured to generate a digital reception signal by sampling an analog reception signal according to the sampling signal; a timing error estimator configured to generate a timing error signal indicating an estimated timing error of the sampled signal relative to the analog received signal; as well as A feedback circuit is configured to derive the phase control signal from the timing error signal, the feedback circuit comprising a scaling element configured to scale the estimated timing error by a scaling factor that depends on the phase control signal.

18. The non-transitory information storage medium of claim 17, wherein the circuitry further comprises a histogram circuit configured to determine a relative probability of each phase control signal value. 19 . The non-transitory information storage medium of claim 18 , wherein the circuit system further comprises an inversion element configured to determine the scaling factor using an inverse of the relative probability.

20. The non-transitory information storage medium of claim 17, wherein the circuitry further comprises a lookup table configured to retrieve the scaling factor in response to the phase control signal.

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