Low-latency hardware acceleration method and system for SM4 symmetric cryptographic algorithm

Abstract

The application discloses a kind of SM4 symmetric cipher algorithm low latency hardware acceleration method and system, belong to hardware acceleration technical field, including S1, the key input by user and the plaintext to be encrypted are obtained;S2, 32 round keys are generated according to the key input by user;S3, the plaintext to be encrypted is encrypted, and the encryption operation is composed of cascaded 32 round operation sub-steps, and the round operation sub-step uses variable flow water level connection mode;S4, the processing result output by the 31st round operation sub-step is the ciphertext after plaintext encryption in step S1 is completed;The SM4 symmetric cipher algorithm low latency hardware acceleration method and system provided by the application can significantly improve the execution speed of SM4 algorithm under the premise of ensuring security, reduce processing latency, and simultaneously flexibly adjust hardware resource configuration according to different application scenarios, to realize efficient use of resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware acceleration, in particular to a low-latency hardware acceleration method and system for SM4 symmetric cryptographic algorithm. BACKGROUND

[0002] With the rapid development of information technology, data security has become crucial in various fields. As a self-designed commercial cryptographic algorithm in China, SM4 symmetric cryptographic algorithm has good security and stability, and is widely used in data encryption storage, information encryption communication and other scenarios. However, in some applications with extremely high real-time requirements, such as high-speed network communication and real-time data processing, the traditional implementation of SM4 algorithm is difficult to meet the demand in processing speed. The main reason is that the software implementation needs to perform a large number of complex operations, resulting in a long processing delay, which cannot meet the strict requirements of low-latency application scenarios.

[0003] In order to improve the execution efficiency of SM4 algorithm, various methods have been adopted in existing technologies. Some studies optimize the software code and use the instruction set characteristics of CPU to improve the algorithm performance. However, due to the limitation of CPU clock frequency and instruction execution period in software execution, the performance improvement is limited. Some other solutions use hardware acceleration, such as designing a dedicated hardware circuit or using FPGA to implement SM4 algorithm. In FPGA implementation, although the traditional loop architecture has relatively low resource consumption, the throughput and efficiency are low, and a large number of clock cycles are needed to complete one encryption. Although the pipeline architecture improves the throughput and speed of encryption, it consumes too much hardware resource, and in some cases, due to the fixed nature of the pipeline stage, it cannot flexibly adapt to different application scenarios with different requirements for latency and resource. In addition, the implementation of S-box permutation operation in existing technologies, such as lookup table, occupies a large chip area and has low efficiency, and algebraic expression, although occupying a compact chip area, has large calculation amount and complex combinatorial logic, resulting in high circuit delay, which greatly affects the overall frequency and performance of the scheme when implementing SM4 cryptographic algorithm based on FPGA. Therefore, it is of great practical significance and application value to develop a hardware acceleration method and system that can effectively reduce the processing delay of SM4 symmetric cryptographic algorithm while reasonably balancing resource consumption and performance. SUMMARY

[0004] The purpose of the present application is to provide a low-latency hardware acceleration method and system for SM4 symmetric cryptographic algorithm to solve the problems in the background art.

[0005] To achieve the above purpose, the present application provides a low-latency hardware acceleration method for SM4 symmetric cryptographic algorithm, comprising the following steps:

[0006] S1, obtaining the key input by the user and the plaintext to be encrypted;

[0007] S2, generating 32 round keys according to the input key of the user , ;

[0008] S3, encrypting the plaintext to be encrypted, the encryption operation consisting of 32 round operation sub-steps in cascade, the round operation sub-steps adopting a variable flow level connection mode;

[0009] S4, the processing result output by the 31st round operation sub-step being the ciphertext after the encryption of the plaintext in step S1 is completed.

[0010] Preferably, the input initial key in step S2 is represented by , the round key is represented by , and the generation process of the round key comprises:

[0011] S21, performing XOR operation between the initial key and the system parameter to obtain the initial round key register :

[0012] ;

[0013] S22, generating the round key through 32 rounds of iteration;

[0014] S23, obtaining 32 round keys after 32 rounds of iteration, which are used for the 32 iterations of the encryption process in step S3.

[0015] Preferably, in step S22, for , the calculation formula of the th round key is:

[0016] ;

[0017] wherein is a fixed parameter.

[0018] Preferably, in step S22, one round key is generated every round, and the register is updated, and the specific process is:

[0019] S221, performing XOR operation between the register value , , of the current round and the fixed parameter to obtain an intermediate value :

[0020] ;

[0021] S222, take the intermediate value Applying the synthetic permutation function ,get ;

[0022] S223, Set the register value of the current round. With the synthesized permutation function The result Perform an XOR operation to generate the next register value. , for the first Wheel key It also serves as the register value for the next iteration.

[0023] Preferably, the synthetic permutation function in step S222 It consists of a nonlinear transformation and a linear transformation, specifically including:

[0024] Will Split into 4 octets Each byte is independently processed through the S-box of the SM4 algorithm to obtain the four bytes after permutation. Then concatenate it back to a 32-bit value. ;

[0025] right Perform a linear transformation:

[0026] ;

[0027] in, Indicates a circular left shift;

[0028] If the synthetic permutation function is used linear transformations in Replace with , and then I got function:

[0029] .

[0030] Preferably, in step S3, the plaintext to be encrypted is set as follows: The 32-round operation of SM4 encryption is used to process plaintext blocks. Perform 32 iterative transformations. The input to each round operation is the intermediate result of the previous round, and the output is passed to the next round. The calculation formula for the sub-step of a single round operation is as follows:

[0031] ;

[0032] From the initial plaintext block Initially, the above operations are executed round by round, forming a pipeline-like iteration; after 32 rounds of operations, four new 32-bit words are obtained. .

[0033] Preferably, the above operations are performed round by round starting from the initial plaintext packet to form a pipelined iteration, specifically:

[0034] 0th stage: input , calculate ; ;

[0035] 1st stage: input , calculate ; ;

[0036] …

[0037] 31st stage: input , calculate .

[0038] Preferably, step S4 specifically comprises:

[0039] S41, reverse the order of the 32 round operation output to obtain ;

[0040] S42, splice the four 32-bit words after reversing the order into 128 bits to obtain the final ciphertext :

[0041] .

[0042] The application also provides a low-latency hardware acceleration system for SM4 symmetric cipher algorithm, comprising:

[0043] a round key expansion module for generating 32 round keys according to a user input key, the round key expansion module adopts a parallel computing structure to reduce data dependency and operation delay in the key expansion process;

[0044] an encryption module composed of 32 round operation sub-modules connected in cascade, each round operation sub-module corresponding to a round operation of the SM4 algorithm, the round operation sub-modules being connected in a variable pipelining level connection mode and dynamically adjusting the pipelining level according to a control signal;

[0045] a control module for sending control signals to the round operation sub-modules to adjust the pipelining level, optimizing the calculation order of the round key expansion module, and adjusting the resource allocation of the modules in the hardware system according to different application scenario requirements.

[0046] Preferably, the round operation sub-module comprises:

[0047] ​Data splitting unit, for splitting input data into blocks , block , block and block ;

[0048] XOR operation unit, for performing XOR operation on block , block and block , obtaining first XOR result, then performing XOR operation on first XOR result and corresponding round key , obtaining first data;

[0049] S-box permutation unit, for performing permutation operation on block , block , block and block , obtaining permutation data;

[0050] Cyclic shift unit, for performing left cyclic shift operation on each permutation data after bit splicing, obtaining first shift data, second shift data, third shift data and fourth shift data;

[0051] Result generating unit, for performing XOR operation on first shift data and second shift data, obtaining second data, then performing XOR operation on third shift data and fourth shift data, obtaining third data, finally performing XOR operation on second data and third data, and storing the processing result of the first round operation sub-module into corresponding register.

[0052] Therefore, the SM4 symmetric cipher algorithm low-latency hardware acceleration method and system has the following beneficial effects:

[0053] (1) By using reconfigurable hardware architecture, especially variable pipeline design, and optimized round key expansion module and S-box permutation mode, the processing latency of SM4 algorithm can be significantly reduced, meeting the requirements of high-speed network communication, real-time data processing and other application scenarios with extremely high latency requirements;

[0054] (2) The configuration of hardware resources can be dynamically adjusted according to the requirements of different application scenarios.

[0055] The technical solutions of the present application will be further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 is the flowchart of the SM4 symmetric cipher algorithm low-latency hardware acceleration method of the present application;

[0057] Figure 2The encryption process schematic diagram of the embodiment of the present application;

[0058] Figure 3 The structure schematic diagram of the system of the embodiment of the present application. DETAILED DESCRIPTION

[0059] The following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0060] Please refer to Figure 1 , a low-latency hardware acceleration method of SM4 symmetric cipher algorithm, comprising the following steps:

[0061] S1, obtaining the key input by the user and the plaintext to be encrypted;

[0062] S2, generating 32 round keys according to the key input by the user , ; the initial key input by the user is denoted as K0, the round key is denoted as Ki, and the generation process of the round key includes:

[0063] S21, performing XOR operation on the initial key K0 and the system parameter to obtain the initial round key register :

[0064] ;

[0065] S22, generating round keys through 32 iterations; for the i-th round key , the calculation formula is:

[0066] ;

[0067] wherein, a is a fixed parameter, and its value is shown in Table 1:

[0068] ;

[0069] Each round generates a round key Ki, and the register Ri is updated, and the specific process is:

[0070] S221, performing XOR operation on the current round register value , , ​​​​​​​​With fixed parameters Perform an XOR operation to obtain the intermediate value. :

[0071] ;

[0072] S222, take the intermediate value Applying the synthetic permutation function ,get ; Synthesis of permutation functions It consists of a nonlinear transformation and a linear transformation, specifically including:

[0073] Will Split into 4 octets Each byte is independently processed through the S-box of the SM4 algorithm to obtain the four bytes after permutation. Then concatenate it back to a 32-bit value. ;

[0074] right Perform a linear transformation:

[0075] ;

[0076] in, Indicates a circular left shift;

[0077] If the synthetic permutation function is used linear transformations in Replace with , and then I got function:

[0078] .

[0079] S223, Set the register value of the current round. With the synthesized permutation function The result Perform an XOR operation to generate the next register value. , for the first Wheel key This value also serves as the register value for the next iteration.

[0080] S23. After 32 rounds of iteration, 32 round keys are obtained. , used for step S3 encryption process 32 iterations.

[0081] S3. Encrypt the plaintext to be encrypted. The encryption operation consists of 32 cascaded round operation sub-steps, which are connected in a variable pipelined manner, such as... Figure 2 As shown; suppose the plaintext to be encrypted is... , the 32-round level operation of SM4 encryption is a 32-bit XOR operation on the plaintext block The 32 iterations of transformation are performed, and the input of the single-round operation is the intermediate result of the previous round, and the output is passed to the next round, wherein the calculation formula of the single-round operation sub-step is as follows:

[0082] ;

[0083] From the initial plaintext block , the above operation is performed round by round to form a pipeline iteration, specifically as follows:

[0084] 0th round: input , calculate ; ;

[0085] 1st round: input , calculate ; ;

[0086] …

[0087] 31st round: input , calculate ; After the 32-round operation, four new 32-bit words are obtained.

[0088] S4, the processing result output by the 31st round operation sub-step is the ciphertext after the plaintext encryption in step S1, including:

[0089] S41, reverse the four 32-bit words output by the 32nd round operation to obtain ;

[0090] S42, splice the four 32-bit words after the reverse into 128 bits to obtain the final ciphertext :

[0091] .

[0092] As shown in Figure 3 , a low-latency hardware acceleration system of an SM4 symmetric encryption algorithm includes:

[0093] A round key expansion module is configured to generate 32 round keys according to a user input key, and the round key expansion module adopts a parallel computing structure to reduce data dependency and operation delay in the key expansion process; the algorithm flow is as follows:

[0094] Input: / / key

[0095] Output: / / round key

[0096] 1. function KEYEXPAND( / / Generate the initial round key / /

[0097] 2.

[0098] / / Nonlinear Iteration / /

[0099] 3.

[0100] 4.

[0101] 5.endfor

[0102] 6.

[0103] 7.endfunction

[0104] The encryption module consists of 32 cascaded round operation submodules. Each round operation submodule corresponds to one round of the SM4 algorithm. The round operation submodules are connected in a variable pipeline stage manner, and the number of pipeline stages is dynamically adjusted according to control signals. The algorithm flow is shown below:

[0105] enter: / / Round key, original text block

[0106] Output: / / Encryption result

[0107] 1. function ENCRYPT / / Nonlinear Iteration / /

[0108] 2.

[0109] 3.

[0110] 4. end for

[0111] 5. return / / Reverse the iteration result to obtain the encrypted ciphertext.

[0112] 6. end function

[0113] The wheel operation submodule includes:

[0114] Data splitting unit, used to divide input data into blocks bit by bit. ,piece ,piece and blocks ;

[0115] XOR operation unit, configured to perform XOR operation on the blocks , the block , the block , the block and the block to obtain a first XOR result, and perform XOR operation on the first XOR result and the corresponding round key

[0116] to obtain first data; S-box permutation unit, configured to perform permutation operation on the blocks , the block , the block and the block

[0117] to obtain permutation data;

[0118] Cyclic shift unit, configured to perform left cyclic shift operation on each permutation data after being spliced by bit to obtain first shift data, second shift data, third shift data and fourth shift data; Result generation unit, configured to perform XOR operation on the first shift data and the second shift data to obtain second data, perform XOR operation on the third shift data and the fourth shift data to obtain third data, and perform XOR operation on the second data and the third data, and store the processing result of the first round operation sub-module in the corresponding register.

[0119] Control module, configured to send control signals to the round operation sub-module to adjust the number of pipeline stages, optimize the calculation order of the round key expansion module, and adjust the resource allocation of each module in the hardware system according to different application scenarios.

[0120] Therefore, the low-latency hardware acceleration method and system of the SM4 symmetric cipher algorithm are adopted to solve the problems that the SM4 algorithm in the prior art cannot meet the real-time requirements in terms of processing latency, and the resource consumption and performance cannot be effectively balanced. Through the above method and system, the execution speed of the SM4 algorithm can be significantly improved under the premise of ensuring security, the processing latency is reduced, and the efficient use of resources is realized by flexibly adjusting the hardware resource configuration according to different application scenarios.

[0121] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application and not to limit them, although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can still be modified or replaced by equivalents, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present application.

Claims

1. A low-latency hardware acceleration method for the SM4 symmetric cryptography algorithm, characterized in that, Includes the following steps: S1. Obtain the key input by the user and the plaintext to be encrypted; S2. Generate 32 round keys based on the key input by the user. , ; S3. Encrypt the plaintext to be encrypted. The encryption operation consists of 32 cascaded round operation sub-steps, which are connected in a variable pipelined manner. S4. The processing result output by the 31st round of operation sub-step is the ciphertext after the plaintext is encrypted in step S1; In step S2, the input initial key is used... Indicates that the round key is used The process of generating the round key includes: S21. Transfer the initial key With system parameters Perform an XOR operation to obtain the initial round key register. : ； S22. Generate the round key after 32 rounds of iteration; S23. After 32 rounds of iteration, 32 round keys are obtained. , used for the 32nd iteration of the encryption process in step S3; In step S22, for , No. Each round key The calculation formula is: ； in, For fixed parameters, To synthesize the permutation function linear transformations in Replace with The resulting permutation function; In step S3, set the plaintext to be encrypted. The 32-round operation of SM4 encryption is used to process plaintext blocks. Perform 32 iterative transformations. The input of each round operation is the intermediate result of the previous round, and the output is passed to the next round. The calculation formula for the sub-step of a single round operation is as follows: ； From the initial plaintext block Initially, the above operations are executed round by round, forming a pipeline-like iteration; after 32 rounds of operations, four new 32-bit words are obtained. ; From the initial plaintext block Initially, the above operations are executed round by round, forming a pipeline-like iteration, specifically as follows: Level 0: Input ,use calculate ; Level 1: Input ,use calculate ; …… Level 31: Input ,use calculate ; In addition, the following modules are used to implement low-latency hardware acceleration methods, including: The round key expansion module is used to generate 32 round keys based on the key input by the user. The round key expansion module adopts a parallel computing structure to reduce data dependency and computational latency in the key expansion process. The encryption module consists of 32 cascaded wheel operation sub-modules. Each wheel operation sub-module corresponds to one round of the SM4 algorithm. The wheel operation sub-modules are connected in a variable pipeline stage manner, and the number of pipeline stages is dynamically adjusted according to the control signal. The control module is used to send control signals to the wheel operation submodule to adjust the number of pipeline stages, optimize the calculation order of the wheel key expansion module, and adjust the resource allocation of each module in the hardware system according to different application scenario requirements. The wheel operation submodule includes: The data splitting unit is used to divide the input data into blocks by bit. ,piece ,piece and blocks ; The XOR operation unit is used for blocks. ,piece and blocks Perform an XOR operation to obtain the first XOR result, and then combine the first XOR result with the corresponding round key. Perform an XOR operation to obtain the first data; The S-box permutation unit divides the first data into blocks bit by bit. ,piece ,piece and blocks Perform a permutation operation to obtain the permutation data; The cyclic shift unit is used to concatenate each permutation data bit by bit, and then perform a leftward cyclic shift operation to obtain the first shifted data, the second shifted data, the third shifted data, and the fourth shifted data. The result generation unit is used to perform an XOR operation on the first shifted data and the second shifted data to obtain the second data, then perform an XOR operation on the third shifted data and the fourth shifted data to obtain the third data, and finally perform an XOR operation on the second data and the third data, and then generate the result. The processing results of each round operation submodule are stored in the corresponding register.

2. The low-latency hardware acceleration method for the SM4 symmetric cryptography algorithm according to claim 1, characterized in that, In step S22, a round key is generated for each round. Simultaneously update the registers The specific process is as follows: S221. Set the register value of the current round. , , With fixed parameters Perform an XOR operation to obtain the intermediate value. : ； S222, take the intermediate value Applying the synthetic permutation function ,get ; S223, Set the register value of the current round. With the synthesized permutation function The result Perform an XOR operation to generate the next register value. , for the first Wheel key This value also serves as the register value for the next iteration.

3. The low-latency hardware acceleration method for the SM4 symmetric cryptography algorithm according to claim 2, characterized in that, The synthetic permutation function in step S222 It consists of a nonlinear transformation and a linear transformation, specifically including: Will Split into 4 octets Each byte is independently processed through the S-box of the SM4 algorithm to obtain the four bytes after permutation. Then concatenate it back to a 32-bit value. ; right Perform a linear transformation: ； in, Indicates a circular left shift; If the synthetic permutation function is used linear transformations in Replace with , and then I got function: 。 4. The low-latency hardware acceleration method for the SM4 symmetric cryptography algorithm according to claim 1, characterized in that, Step S4 specifically includes: S41, Output the 32-level wheel operation. Reverse order, to obtain ; S42. Concatenate the four reversed 32-bit words into a 128-bit string to obtain the final ciphertext. : 。

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