Center-node-free distributed clock coherent synchronization method

Abstract

The invention discloses a distributed clock coherent synchronization method without a central node, and belongs to the technical field of clock synchronization. The method comprises the following steps: step 1, clock coherent synchronization; step 2, timing system synchronization; and step 3, multi-node synchronization. Through multi-station cooperative clock coherence and relative timing synchronization, high-precision clock frequency synchronization between stations is realized, and a stable and accurate clock source is provided for equipment, so that errors caused by different clock oscillators of a receiving party and a transmitting party are reduced, a guarantee is provided for receiving and transmitting of information between unmanned aerial vehicles, and the reliability of the unmanned aerial vehicles is improved. The problem that in the prior art, clock synchronization is difficult to maintain when satellite guide signals are interfered is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization, and in particular to a distributed clock coherent synchronization method without a central node. Background Art

[0002] In recent years, the development of warfare has clearly shown a trend of shifting from "manned" to "unmanned". As an important part of "unmanned" warfare, drone warfare is particularly important.

[0003] The development of swarm intelligence technology inspired by organisms such as bee colonies and ant colonies has promoted the research on new organizational structures of unmanned aerial vehicles. It has proposed a distributed control formation mechanism consisting of multiple small drones without a central node, based on information sharing, computing decisions, planning individual tasks, and achieving coordination between individual and cluster goals. This cluster-based, distributed control and decision-making mechanism has good redundancy and linkage. Regardless of whether it is a traditional formation mode or a cluster distributed mode, its clock synchronization accuracy is an important prerequisite for achieving real-time and precise cluster control.

[0004] A time synchronization system, also known as a time-frequency system or time unified system, is a system that provides standardized time and frequency signals, enabling the coordination and unification of time and frequency across the entire system. With the widespread application of distributed systems in radar detection, the Internet of Things, industrial automation, and other fields, high-precision clock synchronization between multiple nodes has become a key technology for data consistency, signal-level coherence fusion, and improved system performance. Currently, devices generally achieve time synchronization through satellite navigation. GPS synchronization accuracy is generally 100-150ns, which is not high and is easily affected by the ionosphere at high altitudes, further reducing accuracy.

[0005] Currently, devices generally use satellite navigation to synchronize time between devices. This presents the following issues: 1) High dependency: Clock synchronization relies on the satellite navigation system, making it difficult to maintain synchronization if the satellite navigation signal is interfered with; 2) Low accuracy: Satellite navigation clock synchronization accuracy is generally between 100 and 150 nanoseconds, which is low and easily affected by complex environments; 3) High environmental impact: Time synchronization must be performed in open, outdoor locations. Summary of the Invention

[0006] The embodiment of the present application solves the problem in the prior art that it is difficult to maintain clock synchronization when the satellite signal is interfered with by providing a distributed clock coherent synchronization method without a central node, and reduces the error caused by the different clock oscillators of the sender and receiver.

[0007] An embodiment of the present application provides a distributed clock coherent synchronization method without a central node, comprising the following steps: Step 1, clock coherent synchronization: the receiving end generates a synchronization carrier based on the received original carrier and uses it as the local clock reference of the receiving end, so that the receiving end is synchronized with the transmitting end clock; Step 2, time system synchronization: the transmitting end obtains a linear frequency modulated second pulse signal based on the synchronization carrier modulation and broadcasts it. When the receiving end receives the second linear frequency modulated second pulse signal, it down-converts it according to the synchronization carrier to obtain a baseband time domain signal, performs matched filtering on the baseband time domain signal to generate a time domain narrow pulse, extracts the second pulse moment from the time domain narrow pulse, and synchronizes the receiving end with the transmitting end time system; Step 3, multi-node synchronization: the time of the signal exchange and reception moment of each node is marked, the transmission delay and inherent delay are deducted, and the initial clock deviation between nodes is solved to synchronize the distributed node time system.

[0008] Furthermore, the transmitting end is a dynamic reference node; the dynamic reference node is obtained through the following steps: each node periodically broadcasts its own clock stability evaluation parameters, and the clock stability evaluation parameters are received by neighboring nodes; the stability score of each node is obtained, and the node with the highest stability score is recorded as the dynamic reference node.

[0009] Furthermore, the formula for obtaining the stability score is: ; Where S is the stability score, and is the weight, is the crystal temperature drift rate, is the crystal oscillator frequency deviation, is the crystal oscillator temperature change, is the phase noise power spectrum density. Further, the update period of the dynamic reference node is satisfy: ;in is the maximum frequency drift rate, is the maximum phase jitter frequency.

[0010] Furthermore, generating a synchronous carrier and using it as a local clock reference at the receiving end includes the following steps: when the receiving end receives a BPSK-modulated original carrier through a data link channel, doubling the frequency of the BPSK-modulated original carrier to obtain a single carrier signal converted from the BPSK modulated signal, and then inputting the single carrier signal into a Costas phase-locked loop to obtain an output signal; the receiving end divides the output signal into two, recovers the carrier, and obtains a synchronous carrier; detects the phase difference between the synchronous carrier and the original carrier at the transmitting end, and if the phase difference remains constant over a long period of time, determines that the two are co-frequency and coherent; and uses the recovered synchronous carrier as the local clock reference at the receiving end. Furthermore, inputting the single carrier signal into the Costas phase-locked loop to obtain an output signal includes the following steps: comparing the phase of the doubled frequency signal with the output signal of a voltage-controlled oscillator using a phase detector to generate a phase error signal; filtering out high-frequency noise in the phase error signal using a low-pass filter and outputting a smooth control voltage; regulating the voltage-controlled oscillator based on the smooth control voltage so that the real-time output frequency of the voltage-controlled oscillator gradually approaches the target value of the doubled frequency of the original carrier; and obtaining the output signal from the voltage-controlled oscillator.

[0011] Furthermore, the generation of time domain narrow pulses includes the following steps: transforming the baseband time domain signal into a baseband frequency domain signal by Fourier transform ; The baseband frequency domain signal is matched with the matched filter function Multiply to get the compressed signal spectrum ; ; For the compressed signal spectrum Perform an inverse Fourier transform to generate a time-domain narrow pulse.

[0012] Furthermore, the matched filter function is: ; Where rect is the rectangular window function, f is the signal frequency domain variable, k is the modulation frequency of the linear frequency modulated pulse-second signal, T is the transmit pulse width, j is the imaginary unit, and π is the pi constant. It is a windowing function used to suppress sudden changes at the edge of the spectrum.

[0013] Furthermore, the deduction of transmission delay and inherent delay and calculation of initial clock deviation between nodes specifically includes the following steps: node A sends a detection signal at a first local time, and node B receives the detection signal at a second local time; the second local time is marked according to the second pulse extracted by node B, and the clock deviation is calculated in combination with the signal propagation delay and inherent delay.

[0014] Furthermore, the formula for calculating the clock deviation is: ;in, is the clock deviation, is the first local time, is the second local time, is the signal propagation delay, Inherent delay.

[0015] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: 1. Through multi-station collaborative clock coherence technology, high-precision clock frequency synchronization is achieved between stations, providing a stable and accurate clock source for devices, thereby reducing the error caused by the different clock oscillators of the sender and receiver, and thus providing a guarantee for the transmission and reception of information between drones, effectively solving the problem in existing technologies that it is difficult to maintain clock synchronization when the satellite signal is interfered with.

[0016] 2. Through multi-station collaborative time synchronization technology, high-precision clock synchronization is achieved, and all nodes in the system are included in the same clock domain for management and distribution, thereby achieving high clock synchronization accuracy and strong anti-interference ability.

[0017] 3. By using decentralized distributed multi-nodes, there is no need to rely on a specific device, which improves the robustness of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a flow chart of a distributed clock coherent synchronization method without a central node; Figure 2 This is a schematic diagram of the node's active timing; Figure 3 Provides a block diagram of the clock coherence implementation principle; Figure 4 This is the block diagram for time synchronization implementation; Figure 5 This is the principle diagram of matched filtering; Figure 6 The time domain spectrum of the baseband modulated signal in Example 1; Figure 7 This is a spectrum diagram of the modulated signal after adding noise in Example 1; Figure 8 Extracting a carrier wave for the phase-locked loop of embodiment 1; Figure 9 is the signal spectrum after frequency division by two in Example 1; Figure 10 Comparison of the carrier wave at the transmitting end and the carrier wave extracted at the receiving end in Example 1; Figure 11 is the phase difference output of Example 1; Figure 12 is the standard deviation of the carrier error between the transmitting and receiving ends in Example 1; Figure 13 Generating a linear frequency modulation signal for the transmitting end of embodiment 2; Figure 14 is the down-converted baseband signal of Example 2; Figure 15It is the frequency domain filtering correlation peak of Example 2. DETAILED DESCRIPTION

[0019] The embodiment of the present application solves the problem in the prior art that it is difficult to maintain clock synchronization when the satellite signal is interfered with by providing a distributed clock coherence synchronization method without a central node. Through the two parts of multi-station collaborative clock coherence and relative time synchronization, the clock synchronization accuracy of each device in the system is effectively improved, while reducing the hardware complexity and improving the system's working efficiency.

[0020] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0021] like Figure 1 As shown, an embodiment of the present application provides a distributed clock coherent synchronization method without a central node, which includes the following steps: Step 1, clock coherent synchronization: the receiving end generates a synchronization carrier based on the received original carrier and uses it as the local clock reference of the receiving end, so that the receiving end is synchronized with the transmitting end clock; Step 2, time synchronization: the transmitting end obtains a linear frequency modulated second pulse signal based on the synchronization carrier modulation and broadcasts it. After the receiving end receives the second linear frequency modulated second pulse signal, it down-converts it according to the synchronization carrier to obtain a baseband time domain signal, performs matched filtering on the baseband time domain signal to generate a time domain narrow pulse, extracts the second pulse moment from the time domain narrow pulse, and synchronizes the receiving end with the transmitting end time; Step 3, multi-node synchronization: mark the time of the signal exchange and reception moment of each node, deduct the transmission delay and inherent delay, and solve the initial clock deviation between nodes to synchronize the distributed node time.

[0022] Furthermore, the transmitting end is a dynamic reference node; the dynamic reference node is obtained through the following steps: each node periodically broadcasts its own clock stability evaluation parameters, and the clock stability evaluation parameters are received by neighboring nodes; the stability score of each node is obtained, and the node with the highest stability score is recorded as the dynamic reference node.

[0023] Furthermore, the formula for obtaining the stability score is: ; Where S is the stability score, and is the weight, is the crystal temperature drift rate, is the crystal oscillator frequency deviation, is the crystal oscillator temperature change, is the phase noise power spectral density.

[0024] Furthermore, the update cycle of the dynamic reference node satisfy: ;in is the maximum frequency drift rate, is the maximum phase jitter frequency.

[0025] In this embodiment, the dynamic reference node is used as the central node, and the clock synchronization between nodes can be achieved by the central node actively providing time and the sub-nodes passively receiving time. Figure 2 , and the final calculated clock deviation is , supporting the number of nodes ≥ 32.

[0026] Further, such as Figure 3 As shown, the generation of a synchronous carrier and using it as a local clock reference at the receiving end includes the following steps: when the receiving end receives the original carrier modulated by BPSK through the channel of the data link, the original carrier modulated by BPSK is doubled in frequency to obtain a single carrier signal converted from the BPSK modulated signal, and the single carrier signal is input into a Costas phase-locked loop to obtain an output signal; the receiving end divides the output signal by two, recovers the carrier, and obtains a synchronous carrier; by detecting the phase difference between the synchronous carrier and the original carrier of the transmitting end, if the phase difference is constant for a long time, it is determined that the two are of the same frequency and coherent; and the receiving end uses the recovered synchronous carrier as the local clock reference.

[0027] Furthermore, the step of inputting a single carrier signal into a Costas phase-locked loop to obtain an output signal includes: comparing the phase of the doubled frequency signal with the output signal of a voltage-controlled oscillator through a phase detector to generate a phase error signal; filtering out high-frequency noise in the phase error signal through a low-pass filter to output a smooth control voltage; regulating the voltage-controlled oscillator according to the smooth control voltage so that the real-time output frequency of the voltage-controlled oscillator gradually approaches the doubled frequency target value of the original carrier; and obtaining the output signal from the voltage-controlled oscillator.

[0028] In this embodiment, the receiving end first multiplies the frequency and removes the DC component, and then uses the Costas phase-locked loop to extract the local oscillator of the received signal. The phase difference between the extracted carrier and the transmitting end carrier is determined to be constant to determine whether the phase coherence is achieved, that is, and Are they on the same frequency and have a constant phase difference?

[0029] Furthermore, the generation of time domain narrow pulses includes the following steps: transforming the baseband time domain signal into a baseband frequency domain signal by Fourier transform ; The baseband frequency domain signal is matched with the matched filter function Multiply the frequency components one by one to get the compressed signal spectrum At this time, the exponential term imposes differentiated phase delays on the frequency components of the signal, that is, the low-frequency component (small f) has a long time domain delay due to slow phase accumulation; the high-frequency component (large f) has a short time domain delay due to fast phase accumulation. ; For the compressed signal spectrum An inverse Fourier transform is performed. In the time domain, the previously dispersed frequency components are precisely aligned due to delay differences, compressing the wide pulse of width T at the transmitter into a narrow pulse of width u. The compression ratio D = T / u improves time accuracy by a factor of D, generating a narrow pulse in the time domain. In this embodiment, the transmitter performs linear frequency modulation (LFM) on the pulse-second signal based on a synchronized carrier, causing the carrier frequency to vary linearly within the pulse width. This generates a LFM pulse-second signal, leveraging a large bandwidth-time product to increase transmission distance and subsequent resolution accuracy, and is then broadcast via a data link.

[0030] After receiving the broadcast signal, the receiver downconverts the RF signal to a baseband time-domain signal using a synchronized carrier wave coherent with the transmitter. Matched filtering is then performed on the baseband time-domain signal. This process leverages the linear frequency modulation (LFM) signal's characteristic of long delays for low-frequency components and short delays for high-frequency components to align different frequency components in time. This compresses the original wide pulse width T into a narrow pulse width u, achieving a compression ratio of D = T / u and increasing time accuracy by D times the original width. Finally, the pulse-per-second time is extracted from the narrow pulse, achieving time synchronization between the transmitter and receiver.

[0031] like Figure 4 As shown in the figure, the implementation principle of time synchronization is as follows: On the transmitter side, a high-precision clock source outputs a stable reference clock. This is calibrated by a precise synchronization module to eliminate clock drift, driving the pulse generation unit to generate synchronization pulses, which serve as the time reference for the unified signal. The synchronization pulses are input to the linear frequency modulation module, causing the signal carrier frequency to vary linearly within the pulse width, forming a linear frequency modulation signal. This utilizes the "large bandwidth-time-width product" to both increase data link transmission distance and enhance temporal resolution. The frequency control unit fine-tunes signal parameters to optimize spectral characteristics. The linear frequency modulation signal is converted to an analog signal by a DA converter, amplified by a power amplifier, and then injected into the data link channel for transmission.

[0032] At the receiving end, the RF front-end captures the linear frequency modulation (LFM) signal transmitted from the data link and feeds it into a mixing component for downconversion to an intermediate frequency (IF) frequency (IF) to reduce the signal frequency. The IF processing component filters the IF signal to remove clutter and enhance weak signals. A / D conversion then generates a digital signal for synchronization processing. This digital signal is then subjected to frequency-domain correlation with a pre-set LFM matched filter template. The essence of matched filtering is to exploit the linear phase variation of LFM signals to compress the wide transmitter pulse into a narrow pulse, significantly improving temporal resolution and making it easier to detect the arrival time of the signal. The correlation peak, where the energy is most concentrated, is extracted during the correlation operation. The peak's location corresponds to the arrival time of the transmitted signal. Because the signal energy is highly concentrated after pulse compression, the peak is sharp, enabling high-precision detection. The capture module uses this correlation peak to lock onto the signal's frequency, phase, and timing characteristics. Because the transmitter has achieved clock coherence, the receiver can more accurately match signal parameters, reducing synchronization errors. The tracking module dynamically tracks signal changes, responds to channel fading and frequency drift, and continuously calibrates the local time system; it ultimately outputs high-precision pulse per second (PPS) to fully align the receiving end's time system with the transmitting end's clock frequency, phase, and time reference, completing time system synchronization.

[0033] Further, such as Figure 5 As shown, the matched filter function is: ; Where rect is the rectangular window function, f is the signal frequency domain variable, k is the modulation frequency of the linear frequency modulated pulse-second signal, T is the transmit pulse width, j is the imaginary unit, and π is the pi constant. It is a windowing function used to suppress sudden changes at the edge of the spectrum.

[0034] In this embodiment, the rectangular window Limits the effective bandwidth of the signal, exponential term A quadratic phase conjugate to the transmitter frequency modulation slope is introduced.

[0035] Windowing functions include Taylor, Chebyshev, Hanning, Hamming, and Kaiser windows. Window function parameters must meet the following requirements: a mainlobe width to sidelobe attenuation ratio ≥ 25 dB; and a spectral transition band slope ≥ 40 dB / dec. Windowing the matched filter mitigates discontinuities at the spectral edges and reduces mainlobe energy leakage in the compressed pulse, but at the expense of resolution.

[0036] Furthermore, the deduction of transmission delay and inherent delay and calculation of initial clock deviation between nodes specifically includes the following steps: node A sends a detection signal at a first local time, and node B receives the detection signal at a second local time; the second local time is marked according to the second pulse extracted by node B, and the clock deviation is calculated in combination with the signal propagation delay and inherent delay.

[0037] Furthermore, the formula for calculating the clock deviation is: ;in, is the clock deviation, is the first local time, is the second local time, is the signal propagation delay, Inherent delay. Example 1

[0038] Clock coherence: For the BPSK modulated signal sent by the transmitter, its local oscillator frequency can be extracted at the receiver and a signal with the same frequency as the transmitter's carrier can be obtained, thus achieving clock synchronization between the transmitter and the receiver.

[0039] Parameter settings: sampling frequency fs: 30MHz; symbol rate :30k; carrier frequency fc:0.5MHz; signal-to-noise ratio snr:12dB.

[0040] Generate a random sequence at the transmitter and perform BPSK modulation to obtain the waveform after BPSK modulation as shown below: Figure 6 The signal transmitted by the transmitter is processed by adding noise through the Gaussian channel. The signal spectrum after adding noise is shown as follows. Figure 7 The receiving end extracts the local oscillator frequency of the received signal through a phase-locked loop, processes the noise-added signal using a frequency doubling method, and then filters out the DC component to obtain a doubled frequency single carrier signal as shown in the figure. Figure 8 As shown. Divide the carrier extracted by the phase-locked loop into two frequencies and draw its spectrum diagram as shown Figure 9 As shown in the figure, it can be observed that the carrier frequency is the same as that of the transmitter. Figure 10 As shown, the phase difference is calculated by Hilbert transform, as Figure 11 As shown in Figure 1, its phase error fluctuates around a fixed value and is relatively stable. Therefore, through this process, a signal with the same frequency and constant phase difference as the carrier at the transmitting end can be recovered at the receiving end. The simulation output results with a signal-to-noise ratio of 12dB are verified, and the standard deviation of the phase error between the extracted carrier and the transmitting end carrier is obtained as follows: Figure 12 As shown in the figure, the final standard deviation is stable at around 3°, which meets the design index requirements. Example 2

[0041] Time synchronization: The transmitter transmits a wide-time-product linear frequency-modulated pulse-second signal, and the receiver receives the pulse-second signal through a correlation filter to obtain a high-gain correlation peak, thereby achieving time synchronization between the sender and receiver. It has the advantages of high precision and strong anti-interference ability.

[0042] Parameter setting: 300MHz.

[0043] The transmitter generates a linear frequency modulation signal such as Figure 13 As shown. The receiving end down-converts the received signal to obtain the baseband signal as shown Figure 14 As shown. The correlation peak of the baseband signal is extracted by matched filtering, and the high-precision correlation peak is obtained as shown in Figure 15 As shown in FIG, when the system clock is 300 MHz, the obtained correlation peak accuracy can reach 3.3 ns.

[0044] In summary, the embodiments of the present application achieve high-precision clock synchronization between stations through multi-station collaborative clock coherence technology, provide a stable and accurate clock source between devices, reduce the error caused by the different clock oscillators of the sender and receiver, and provide a guarantee for the transmission and reception of information between drones. The multi-station collaborative time synchronization technology lays the foundation for achieving high-precision relative ranging, with the advantages of high synchronization accuracy and strong anti-interference ability. At the same time, the use of appropriate ranging methods can greatly reduce ranging errors and improve ranging accuracy.

[0045] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0046] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0047] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0048] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0049] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0050] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A distributed clock coherent synchronization method without a central node, characterized in that: The following steps are involved: Step 1: Clock coherence synchronization: The receiving end generates a synchronization carrier based on the received original carrier and uses it as the receiving end's local clock reference to synchronize the receiving end with the transmitting end clock; Step 2: Time synchronization: The transmitter modulates the synchronous carrier to obtain a linear frequency modulated pulse-second signal and broadcasts it. When the receiver receives the linear frequency modulated pulse-second signal, it down-converts it according to the synchronous carrier to obtain a baseband time domain signal. The baseband time domain signal is matched filtered to generate a time domain narrow pulse. The pulse-second time is extracted from the time domain narrow pulse, thus synchronizing the time systems of the receiver and the transmitter. Step 3, multi-node synchronization: Mark the time when each node exchanges signals, deduct the transmission delay and inherent delay, and solve the initial clock deviation between nodes to synchronize the distributed node time.

2. The method for coherent synchronization of distributed clocks without a central node according to claim 1, wherein: The transmitting end is a dynamic reference node; The dynamic reference node is obtained by the following steps: Each node periodically broadcasts its own clock stability evaluation parameters, and neighboring nodes receive the clock stability evaluation parameters; Obtain the stability score of each node, and record the node with the highest stability score as the dynamic reference node.

3. The method for coherent synchronization of distributed clocks without a central node according to claim 2, wherein: The formula for obtaining the stability score is: ; Where S is the stability score, and is the weight, is the crystal temperature drift rate, is the crystal oscillator frequency deviation, is the crystal oscillator temperature change, is the phase noise power spectral density.

4. The method for coherent synchronization of distributed clocks without a central node according to claim 2, wherein: Update period of the dynamic reference node satisfy: ; in is the maximum frequency drift rate, is the maximum phase jitter frequency.

5. The method for coherent synchronization of distributed clocks without a central node according to claim 1, wherein: Generating a synchronous carrier and using it as a local clock reference at the receiving end comprises the following steps: When the receiving end receives the original carrier modulated by BPSK through the data link channel, it performs double frequency processing on the original carrier modulated by BPSK to obtain a single carrier signal converted from the BPSK modulated signal, and then inputs the single carrier signal into the Costas phase-locked loop to obtain the output signal; The receiving end divides the output signal into two frequencies, recovers the carrier, and obtains the synchronous carrier; By detecting the phase difference between the synchronization carrier and the original carrier at the transmitting end, if the phase difference remains constant for a long time, it is determined that the two are of the same frequency and coherent; The receiving end uses the recovered synchronous carrier as the local clock reference.

6. The method for coherent synchronization of distributed clocks without a central node according to claim 5, wherein: The step of inputting a single carrier signal into a Costas phase-locked loop to obtain an output signal comprises: The phase detector compares the phase of the doubled frequency signal with the output signal of the voltage controlled oscillator to generate a phase error signal; The high-frequency noise in the phase error signal is filtered out by a low-pass filter, and a smooth control voltage is output; The voltage controlled oscillator is regulated according to the smooth control voltage so that the real-time output frequency of the voltage controlled oscillator gradually approaches the double frequency target value of the original carrier; The output signal is obtained from the voltage controlled oscillator.

7. The method for coherent synchronization of distributed clocks without a central node according to claim 1, wherein: Generating a time domain narrow pulse comprises the following steps: Convert the baseband time domain signal into the baseband frequency domain signal through Fourier transform ; The baseband frequency domain signal is matched with the matched filter function Multiply to get the compressed signal spectrum ; ; Compressed signal spectrum Perform an inverse Fourier transform to generate a time-domain narrow pulse.

8. The method for coherent synchronization of distributed clocks without a central node as claimed in claim 7, wherein: The matched filter function is: ; Where, rect is the rectangular window function, f is the signal frequency domain variable, k is the modulation frequency of the linear frequency modulated pulse-second signal, T is the transmit pulse width, j is the imaginary unit, and π is the pi constant. It is a windowing function used to suppress sudden changes at the edge of the spectrum.

9. The method for coherent synchronization of distributed clocks without a central node according to claim 1, wherein: The deduction of transmission delay and inherent delay and calculation of initial clock deviation between nodes specifically includes the following steps: Node A sends a detection signal at a first local time, and node B receives the detection signal at a second local time; The second local time is marked by the second pulse extracted by Node B, and the clock deviation is calculated by combining the signal propagation delay and inherent delay.

10. The method for coherent synchronization of distributed clocks without a central node according to claim 9, wherein: The formula for calculating the clock deviation is: ; in, is the clock deviation, is the first local time, is the second local time, is the signal propagation delay, Inherent delay.

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