Methods for determining the development process of card holes in PCBs and electronic equipment

Abstract

This invention provides a method for determining the via development process of a printed circuit board (PCB) and an electronic device, which can be applied to the field of printed circuit board processing technology. The method for determining the via development process includes: determining the effective area of ​​the PCB based on its shape; determining the area occupied by the physical layout of the multiple devices and the area occupied by the wiring between the multiple devices under the via process based on the layout information of multiple devices related to the PCB, thereby obtaining the occupied area of ​​the PCB; and determining the via development process of the PCB based on the effective area and the occupied area.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board processing technology, specifically to a method for determining the hole development process of a circuit board and an electronic device. Background Technology

[0002] With the development of computer technology, storage system products, such as high-density storage server control motherboards and SSD (Solid State Drive) boards, are trending towards miniaturization and integration. The multi-pin characteristics of these products lead to insufficient space during the layout and routing process of the entire board.

[0003] In related technologies, PCB (Printed Circuit Board) processes can be improved to increase the space utilization of the board. However, such processes usually require additional steps, which makes the manufacturing cost of PCBs relatively high.

[0004] Engineers often rely on personal experience when choosing PCB through-hole development processes, which can lead to problems such as design rework and over-design during PCB development, failing to meet the development requirements of storage product boards for high efficiency, low cost, and high reliability. Summary of the Invention

[0005] In view of the above problems, the present invention provides a method for determining the hole development process of a board and an electronic device.

[0006] According to one aspect of the present invention, a method for determining the via development process of a board is provided, comprising: determining the effective area of ​​the board to be developed based on the shape of the board to be developed; determining, based on the layout information of a plurality of devices related to the board to be developed, the area occupied by the body layout of the plurality of devices and the area occupied by the wiring between the plurality of devices in the via process state, thereby obtaining the occupied area of ​​the board to be developed; and determining the via development process of the board to be developed based on the effective area and the occupied area.

[0007] According to another aspect of the present invention, an electronic device is provided, comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above. Attached Figure Description

[0008] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0009] Figure 1A flowchart of a method for determining the hole-punch development process in a plate according to an embodiment of the present invention is shown.

[0010] Figure 2 A schematic diagram of the structure of a development board according to an embodiment of the present invention is shown.

[0011] Figure 3A A schematic diagram of the structure of a development board according to another embodiment of the present invention is shown.

[0012] Figure 3B A schematic diagram of the equivalent wiring area according to an embodiment of the present invention is shown.

[0013] Figure 4A A schematic diagram of the power topology of a single-phase power module according to an embodiment of the present invention is shown.

[0014] Figure 4B A schematic diagram of the power topology of a multi-power supply module according to an embodiment of the present invention is shown.

[0015] Figure 5 A block diagram of an electronic device suitable for implementing a method for determining board hole development process according to an embodiment of the present invention is shown. Detailed Implementation

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0018] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0019] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0020] In the storage product system, board-type products such as high-density storage server control motherboards and SSD cards often have a large number of pins due to their complex functional requirements. At the same time, constrained by the trend towards miniaturization and integration, these boards are typically small in size. This "high pin count, small size" characteristic directly leads to a severe challenge of insufficient space during the overall board layout and routing process.

[0021] When layout and routing space is insufficient, conventional through-hole board technology often fails to meet design requirements, rendering the board design infeasible. To address this issue, the industry typically employs methods to improve PCB manufacturing processes, such as POFV (Plating Over Filled Via). POFV technology directly places vias within the component pads and then electroplats them to fill the vias, effectively improving board space utilization and providing more usable space for layout and routing. However, compared to conventional through-hole technology, POFV requires additional steps, directly resulting in significantly higher PCB manufacturing costs.

[0022] Currently, in PCB development, determining whether layout and routing space is sufficient and whether special processes such as POFV are necessary relies primarily on subjective judgments based on engineers' personal experience, lacking systematic scientific theoretical support and objective quantitative evidence. Due to differences in individual engineers' experience, technical habits, and risk preferences, this experience-based approach has led to a series of problems. For example, some engineers, fearing that discovering insufficient space in the later stages of layout and routing, necessitates switching to POFV and would result in extensive design rework, causing significant project delays and increased development costs, subjectively determine early in the project that conventional processes are not feasible, prematurely adopting POFV and allowing for substantial design margins. While this approach ensures the feasibility of the board design to some extent, it clearly suffers from over-design, needlessly increasing the product's manufacturing costs and technical implementation difficulty. For example, some engineers, based on their personal intuition, determine that conventional through-hole technology is sufficient to meet the requirements and believe that the risks are controllable. However, as the development process progresses, they find that there is insufficient space for layout and routing. At this point, they have to rework the design and add special processes such as POFV to solve the space problem. This also leads to a large amount of rework, seriously affecting the project's development progress, causing increased development costs and wasted resources.

[0023] In conclusion, the current method of determining the PCB board hole development process based solely on personal experience and subjective intuition has significant shortcomings and can no longer meet the development requirements of storage product boards for high efficiency, low cost, and high reliability. Therefore, how to accurately and objectively determine the required process in the early stages of PCB board development based on scientific theory and objective practical data, using intelligent means such as algorithms, has become an urgent technical problem to be solved in this field.

[0024] In view of this, embodiments of the present invention provide a method and electronic device for determining the via development process of PCB boards, aiming to solve the problems of over-design, increased costs, and large rework volume that arise from relying on personal experience to determine the via development process of PCB boards. The method for determining the via development process includes: determining the effective area of ​​the board to be developed based on its shape; determining the area occupied by the physical layout of the multiple components and the area occupied by the wiring between the multiple components in the via process state, based on the layout information of multiple components related to the board to be developed, to obtain the occupied area of ​​the board to be developed; and determining the via development process of the board to be developed based on the effective area and the occupied area. The method for determining the via development process of the present invention, while meeting the requirements of structural constraints, manufacturability, and signal integrity, can, from the perspective of development feasibility, achieve the scientific and accurate determination of the via development process of PCB boards through systematic data processing and calculation, providing strong support for the efficient, low-cost, and high-quality development of storage product boards.

[0025] Figure 1 A flowchart of a method for determining the hole-punch development process in a plate according to an embodiment of the present invention is shown.

[0026] like Figure 1 As shown, the method includes operations S110 to S130.

[0027] In operation S110, the effective area of ​​the board to be developed is determined based on its shape.

[0028] In operation S120, based on the layout information of multiple devices related to the board to be developed, the area occupied by the body layout of multiple devices and the area occupied by the wiring between multiple devices are determined under the through-hole process, and the area occupied by the board to be developed is obtained.

[0029] In operation S130, the through-hole development process of the board to be developed is determined based on the effective area and the occupied area.

[0030] The board to be developed can be any type of PCB board with features such as multiple pins and small size. For example, it can be a high-density storage server control motherboard, storage SSD board, or other board products in the storage product system. No limitation is made here.

[0031] The shape of the board to be developed can be set by the developers themselves when drawing the board diagram. For example, developers can use specific software to draw the board diagram. When drawing the board diagram, they can draw one or more closed curves in a specific layer of the board. These one or more closed curves can define the shape of the board to be developed.

[0032] The effective area of ​​the board to be developed can refer to the area on the board that can be used for the placement of components and the routing of traces between components. Optionally, one or more closed curves can be used to represent the shape outline of the board, the shape outline of the do-not-wire area on the board, etc. Based on the one or more closed curves, the total area of ​​the board to be developed and the area of ​​the area on the board where routing or component placement is prohibited can be determined respectively. The effective area can be expressed as the difference between the total area of ​​the board to be developed and the area of ​​the area on the board where routing or component placement is prohibited.

[0033] Alternatively, the shape of the board to be developed can be defined by the structural design parameters of the board imported through the system. Correspondingly, the effective area of ​​the board to be developed can also be calculated based on the imported structural design parameters. For example, the system can import information such as the physical dimensions of the board, the structural restriction areas reserved at the edges of the board, and the area of ​​mounting positions for fixed components on the board that cannot be used for layout and routing. Based on the imported information, the total area of ​​the board to be developed and the area of ​​the areas on the board where routing or component placement is prohibited can be calculated separately. The difference between the total area of ​​the board to be developed and the area of ​​the areas on the board where routing or component placement is prohibited can then be calculated to obtain the effective area of ​​the board to be developed.

[0034] The layout information of multiple components associated with the board to be developed can include the positions of at least some of the components within the board. These at least some components can include chips, connectors, and other devices on the board. After determining the board's border, the chips, connectors, and other devices can be placed in the board's layout diagram to determine their layout information.

[0035] In embodiments of the present invention, the area occupied by the board to be developed can be expressed as the area occupied by the device layout and wiring calculated based on a layout of chips, connectors, and other devices. After changing the placement of chips, connectors, and other devices, the area occupied by the board to be developed can change accordingly. For example, in one example, connector A1 can be placed at the first edge of the board, and connector A2 can be placed at the second edge of the board. The first edge and the second edge can be two adjacent edges, and the length of the trace between connector A1 and connector A2 can be B1. In another example, connector A1 can be placed at the first edge of the board, and connector A2 can be placed at the third edge of the board. The first edge and the third edge can be two opposite edges, and the length of the trace between connector A1 and connector A2 can be B2. Then the values ​​of B1 and B2 can be unequal, that is, the area occupied by the trace between connector A1 and connector A2 in the two examples is not equal, thus making the calculated area unequal in the two examples.

[0036] By comparing the effective area and the occupied area, it can be determined whether the board under development is suitable for through-hole technology or a special process such as POFV. For example, if the effective area is larger than the occupied area, it can be assumed that through-hole technology can accommodate the routing of all components and their signal traces, and the through-hole development process for the board under development can be determined to be through-hole technology. If the effective area is smaller than the occupied area, it can be assumed that through-hole technology cannot accommodate the routing of all components and their signal traces, and the through-hole development process for the board under development can be determined to be a special process such as POFV.

[0037] According to embodiments of the present invention, by accurately determining the effective area of ​​the board and meticulously calculating the layout and wiring area that affects process selection, and comparing the calculated actual effective area of ​​the board with the actual required conventional through-hole process area value, the required process can be determined based on the numerical relationship between the two. This scientifically and rationally determines the process category to be adopted for board development, effectively solving the problems of over-design, increased costs, and large rework volume that exist when relying on personal experience to determine the board through-hole development process. It achieves the scientific and accurate determination of the board through-hole development process, providing strong support for the efficient, low-cost, and high-quality development of storage product boards.

[0038] The following description, with reference to the accompanying drawings and specific embodiments, illustrates... Figure 1 The method for determining the process of creating a hole in the plate shown will be further explained.

[0039] The effective area of ​​the board to be developed can be calculated by subtracting the area of ​​the area on the board where devices and traces are prohibited from being placed from the total area of ​​the board to be developed.

[0040] Optionally, during the development and design of the board to be developed, one or more closed curves drawn by the developers on a specific layer of the board can constitute one or more shape elements, which are recorded in the corresponding board structure file. By parsing the structure file, the multiple shape elements included in the board to be developed can be determined, as well as the type of each shape element and the area of ​​the region defined by each shape element. By filtering the multiple shape elements and calculating the areas of the multiple shape elements, the total area of ​​the board to be developed and the area of ​​the region where devices and traces are prohibited can be obtained respectively. Based on the total area of ​​the board to be developed and the area of ​​the region where devices and traces are prohibited, the effective area of ​​the board to be developed can be calculated.

[0041] Specifically, the board structure file of the board to be developed can be parsed to obtain multiple shape elements; based on the type of the shape elements and the board layer level where the shape elements are located, a first target shape element and at least one second target shape element can be determined from the multiple shape elements; and based on the area of ​​the first target shape element and the area of ​​at least one second target shape element, the effective area of ​​the board to be developed can be determined.

[0042] The board structure file can be entered into the corresponding PCB design software, and multiple shape elements can be obtained by filtering elements based on shape attributes through the consultation command.

[0043] For the multiple shape elements obtained from the initial screening, the target attribute information can be extracted from the attribute information contained in the shape element by using the type and board layer level of each shape element as keywords. Each element can be numbered and recorded in a data table along with its target attribute information, area, and other key information, as shown in Table 1. Table 1 can include 9 shape elements. Among them, shape element Item1 is a circuit board geometry, located at the border layer, with an area of ​​a1; shape element Item2 is a circuit board geometry, located at the border layer, with an area of ​​a2; shape element Item3 is a circuit board geometry, located at the cut layer, with an area of ​​a3; shape element Item4 is a no-route area, located at the first surface layer, with an area of ​​a4; shape element Item5 is a no-route area, located at the second surface layer, with an area of ​​a5; and so on. Item 6 is a restricted layout area, located on the first surface layer of the board layer, with an area of ​​a6 and a component height threshold of b1. Item 7 is also a restricted layout area, located on the first surface layer of the board layer, with an area of ​​a7 and a component height threshold of b2. Item 8 is a restricted layout area, located on the second surface layer of the board layer, with an area of ​​a8 and a component height threshold of b3. Item 9 is also a restricted layout area, located on the second surface layer of the board layer, with an area of ​​a9 and a component height threshold of b4. The first surface layer could be, for example, the TOP layer (top layer) of the board to be developed, and the second surface layer could be, for example, the BOTTOM layer (bottom layer) of the board to be developed.

[0044] Table 1

[0045]

[0046] Figure 2 A schematic diagram of the structure of a development board according to an embodiment of the present invention is shown.

[0047] like Figure 2 As shown, the board to be developed can be composed of a single PCB board. The border of the PCB board can be represented as a first shape element 201, such as shape element Item1 or shape element Item2 in Table 1.

[0048] In the PCB board represented by the first shape element 201, a circular opening can be provided. This circular opening can serve as a mounting position for the PCB board, through which the PCB board can be mounted to the structural component. When manufacturing the PCB board, the board needs to be cut out in the area of ​​the circular opening. That is, the circular opening can be represented as the second shape element 202, as shown in shape element Item3 in Table 1.

[0049] A no-wiring area can be provided on the edge region of the PCB board represented by the first shape element 201, such as... Figure 2 The single-diagonal shaded area in the diagram prohibits the placement of components and traces to ensure proper electrical isolation of the PCB board. This single-diagonal shaded area can be represented as a third shape element 203, such as shape element Item4 or shape element Item5 in Table 1.

[0050] A restricted layout area can be set on the PCB board represented by shape element Item1 201, such as... Figure 2 The double-shaded area in the diagram represents a restricted layout area where the height of components placed therein varies due to structural constraints and the need for electrical isolation between adjacent boards. This double-shaded area can be represented as a fourth shape element 204, such as shape element Item6, shape element Item7, shape element Item8, or shape element Item9 in Table 1.

[0051] After extracting information from each shape element, the extracted information can be used for filtering to determine at least one first target shape element and at least one second target shape element from multiple shape elements.

[0052] Specifically, for each shape element, it can be determined as a first target shape element if the shape element type is a circuit board geometry and the board layer level where the shape element is located is a border layer; if the shape element type is a circuit board geometry and the board layer level where the shape element is located is a cut-off layer; if the shape element type is a prohibited routing area and the board layer level where the shape element is located is the first or second surface layer of the board to be developed; and if the shape element type is a restricted layout area, the board layer level where the shape element is located is the first surface layer, and the component height threshold value of the shape element is less than a preset value.

[0053] For example, if the preset value is set to be less than b1 and greater than b2, then for the nine shape elements shown in Table 1: For shape element Item1, whose type is circuit board geometry and whose layer level is the border layer, shape element Item1 is the first target shape element; for shape element Item2, whose type is circuit board geometry and whose layer level is the border layer, shape element Item2 is the first target shape element; for shape element Item3, whose type is circuit board geometry and whose layer level is the cut-off layer, shape element Item3 is the second target shape element; for shape element Item4, whose type is a no-wiring area and whose layer level is the first surface layer, shape element Item4 is the second target shape element; for shape element Item5, whose type is a no-wiring area and whose layer level is the second surface layer, shape element Item5 is the second target shape element. Shape element; For shape element Item6, its type is a restricted layout area, its layer level is the first surface, and its component height threshold value b1 is greater than the preset value, so shape element Item6 can be filtered out; For shape element Item7, its type is a restricted layout area, its layer level is the first surface, but its component height threshold value b2 is less than the preset value, so shape element Item7 is the second target shape element; For shape element Item8, its type is a restricted layout area, its layer level is the second surface, not the first surface, so shape element Item8 can be filtered out; For shape element Item9, its type is a restricted layout area, its layer level is the second surface, not the first surface, so shape element Item9 can be filtered out.

[0054] The filtered shape elements can be as shown in Table 2. Among the six shape elements included in Table 2, the first shape element can include Item1 and Item2, and the second shape element can include Item3, Item4, Item5 and Item7.

[0055] Table 2

[0056]

[0057] The area of ​​the first target shape element can be represented as the total area of ​​the board to be developed, and the area of ​​the second target shape element can be represented as the area of ​​the area on the board to be developed where the routing of devices and traces is prohibited.

[0058] Optionally, the effective area of ​​the board to be developed can be determined based on the area of ​​the first target shape element and the area of ​​at least one second target shape element. Specifically, the area of ​​the invalid region can be obtained based on the sum of the areas of at least one second target shape element; the effective area of ​​the board to be developed can be obtained by subtracting the area of ​​the invalid region from the sum of the areas of at least one first target shape element.

[0059] Taking Table 2 as an example, the areas of at least one second target shape element can be summed to obtain the invalid area Sn=a3+a4+a5+a7, and the areas of at least one first target shape element can be summed to obtain the total area of ​​the board Sd=a1+a2. Then the effective area of ​​the board to be developed can be expressed as S0=Sd-Sn=a1+a2-a3-a4-a5-a7.

[0060] Optionally, the multiple devices may include multiple first-type devices. Accordingly, the area occupied by the board to be developed may include the area occupied by the body layout of the multiple first-type devices and the area occupied by the routing of the multiple first-type devices.

[0061] Specifically, the board layout file of the board to be developed can be parsed to determine the connection topology and the respective layout positions of multiple Class I devices; based on the connection topology, the first layout area of ​​multiple Class I devices can be determined; based on the connection topology and the respective layout positions of multiple Class I devices, the wiring area between multiple Class I devices can be determined; and based on the first layout area and the wiring area, the occupied area can be obtained.

[0062] The board layout file can be obtained after the layout of multiple Class 1 devices is completed. This layout file can be parsed, and the Class 1 devices, such as chips and connectors, included on the board to be developed can be identified using keywords related to chip and connector packages. By querying the shape attributes in the layout file, information such as the layout position, body area, and connection topology of each Class 1 device can be obtained. Each Class 1 device is assigned a number based on its device type. This information, along with the numbers, is entered into a data table, resulting in the data table shown in Table 3. The connection topology can be represented as the connection relationships between the various Class 1 devices. The layout position of a Class 1 device can be represented as the coordinates of its geometric center point.

[0063] As shown in Table 3, parsing the board layout file of the board to be developed yields four Class I devices: chip U1, chip U2, connector J1, and connector J2. In a coordinate system with the lower left corner of the board to be developed as the origin, the layout position of chip U1 can be (x1, y1), its body area is c1, and the number of outgoing lines is d1; the layout position of chip U2 can be (x2, y2), its body area is c2, and the number of outgoing lines is d2; the layout position of connector J1 can be (x3, y3), its body area is c3, and the number of outgoing lines is d3; and the layout position of connector J4 can be (x4, y4), its body area is c4, and the number of outgoing lines is d4.

[0064] Table 3

[0065]

[0066] Figure 3A A schematic diagram of the structure of a development board according to another embodiment of the present invention is shown.

[0067] like Figure 3A As shown, the development board can be equipped with a first chip 301 and a second chip 302. The first pin 3011 of the first chip 301 can be connected to the second pin 3021 of the second chip 302 via a signal trace 303. The contact area between the signal trace 303 and the first pin 3011 can form a first output area 3012 of the first pin 3011, and the contact area between the signal trace 303 and the second pin 3021 can form a second output area 3022 of the second pin 3021.

[0068] The outgoing area can be represented as the transition area between the pins of the first type of device and the high-speed signal traces. The layout area of ​​the first type of device can be obtained based on the area occupied by the body of the first type of device and the area occupied by the outgoing area of ​​the first type of device. Specifically, the number of outgoing lines of the first type of device can be determined based on the connection topology; the outgoing area of ​​the first type of device can be determined based on the number of outgoing lines and the outgoing line type of the first type of device; and the first layout area can be obtained based on the outgoing area and the body area of ​​the first type of device.

[0069] The area of ​​the outgoing area of ​​a single pin of the first type of device can be determined based on the outgoing line type. The area of ​​the outgoing line area corresponding to each outgoing line type can be preset. For example, if the outgoing line type of the first type of device is X1, the area of ​​its outgoing line area can be set to m1; if the outgoing line type of the first type of device is X2, the area of ​​its outgoing line area can be set to m2, and so on.

[0070] The first type of device has an X2 output type, which means that a single pin can lead out two high-speed signal traces. When calculating the output area, the area of ​​the output area of ​​the corresponding X2 trace needs to be divided by 2 to obtain the output area of ​​a single high-speed signal trace.

[0071] Taking the four Class I devices shown in Table 3 as examples, if the outgoing wire type of chips U1 and U2 is X2, then the first layout area of ​​chip U1 is Su1 = c1 + d1 × m2 / 2, and the first layout area of ​​chip U2 is Su2 = c2 + d2 × m2 / 2. If the outgoing wire type of connectors J1 and J2 is X1, then the first layout area of ​​connector J1 is Sj1 = c3 + d3 × m1, and the first layout area of ​​connector J2 is Sj2 = c4 + d4 × m1.

[0072] Optionally, based on the connection topology between multiple Class I devices obtained from the analysis, the number of signal traces between each Class I device can also be determined. With each signal trace having a substantially uniform width, the area occupied by the traces between each Class I device can be further determined by considering their relative positions. Specifically, for a first device and a second device among multiple Class I devices, the number of signal traces between the first device and the second device can be determined based on their connection topology; the equivalent routing area can be determined based on the layout position of the first device, the layout position of the second device, the number of signal traces, and the preset signal line width; and the routing area between the first device and the second device can be obtained based on the area of ​​the equivalent routing area.

[0073] Taking the four Class I devices shown in Table 3 as examples, based on the connection topology between these four Class I devices, the number of signal traces between them can be obtained, as shown in Table 4. In Table 4, the number of signal traces between chip U1 and chip U2 can be e1, the number of signal traces between chip U1 and connector J1 can be e2, the number of signal traces between chip U1 and connector J2 can be e3, the number of signal traces between chip U2 and connector J1 can be e4, and the number of signal traces between chip U2 and connector J2 can be e5. The transmitting end can be represented as the first device as described above, and the receiving end can be represented as the second device as described above.

[0074] Table 4

[0075]

[0076] To ensure impedance and signal delay consistency, the width, spacing, and length of multiple signal traces between the transmitting and receiving ends can generally be kept consistent. Therefore, the length and width of multiple signal traces can be equivalently obtained based on the length and width of a single signal trace, thereby obtaining the area occupied by the wiring between the transmitting and receiving ends, and thus the wiring area between the corresponding first and second devices.

[0077] Optionally, when calculating the wiring area, the equivalent line width of multiple signal traces can be determined first. If the line width of a signal trace is w1 and the spacing between signal traces is w2, then the equivalent line width of multiple signal traces between the first device and the second device can be expressed as F=(w1+w2)×e+w2, where e can represent the number of signal traces between the first device and the second device.

[0078] Taking the four Class I devices shown in Table 4 as examples, the equivalent linewidth of the signal trace between chip U1 and chip U2 can be expressed as F1=(w1+w2)×e1+w2; the equivalent linewidth of the signal trace between chip U1 and connector J1 can be expressed as F2=(w1+w2)×e2+w2; the equivalent linewidth of the signal trace between chip U1 and connector J2 can be expressed as F3=(w1+w2)×e3+w2; the equivalent linewidth of the signal trace between chip U2 and connector J1 can be expressed as F4=(w1+w2)×e4+w2; and the equivalent linewidth of the signal trace between chip U2 and connector J2 can be expressed as F5=(w1+w2)×e5+w2.

[0079] Based on the calculated equivalent linewidth, an equivalent wiring region can be fitted by combining the layout positions of the first device and the second device, and the area of ​​the equivalent wiring region can be calculated to obtain the wiring area between the first device and the second device.

[0080] Figure 3B A schematic diagram of the equivalent wiring area according to an embodiment of the present invention is shown.

[0081] like Figure 3B As shown, the first device is positioned at (X1, Y1), the second device at (X2, Y2), and the equivalent trace width of the signal trace between the first and second devices is F. Therefore, the four endpoints of the equivalent routing region can be determined, with coordinates (X1, Y1-F / 2), (X1, Y1+F / 2), (X2, Y2-F / 2), and (X2, Y2+F / 2). The quadrilateral region defined by these four endpoints is the equivalent routing region.

[0082] The wiring area between the first device and the second device can be obtained by calculating the area of ​​the equivalent wiring region. This wiring area can be expressed as Sx=(X2-X1)*[(Y1+F / 2)-(Y2-F / 2)]-(X2-X1)*[(Y1+F / 2)-(Y2+F / 2)] / 2-(X2-X1)*[(Y1-F / 2)-(Y2-F / 2)] / 2.

[0083] Based on the above calculation formula for wiring area and Table 4, the wiring areas between chip U1, chip U2, connector J1 and connector J2 can be calculated respectively. Specifically, the wiring area between chip U1 and chip U2 can be Su1_u2, the wiring area between chip U1 and connector J1 can be Su1_j1, the wiring area between chip U1 and connector J2 can be Su1_j2, the wiring area between chip U2 and connector J1 can be Su2_j1, and the wiring area between chip U2 and connector J2 can be Su2_j2.

[0084] Combining Tables 3 and 4, based on the calculated areas of the multiple first layouts and multiple wiring areas, the area occupied by the four first-type devices can be summed to obtain S1 = Su1 + Su2 + Sj1 + Sj2 + Su1_u2 + Su1_j1 + Su1_j2 + Su2_j1 + Su2_j2.

[0085] Optionally, the multiple devices may include at least one power module, and correspondingly, the area occupied by the board to be developed may include the area occupied by the at least one power module.

[0086] Before developing the board to be developed, the configuration information of the power module that needs to be configured for the board can be determined in advance based on the power requirements document. This configuration information can be pre-stored in a specified location for easy retrieval. Optionally, the power module can be divided into single-phase power module and multi-phase power module. Each type of power module can be configured with multiple power topologies based on different combinations of electrical parameters.

[0087] Optionally, based on the electrical parameters of the power module, the target power topology to which the power module belongs can be determined; based on the target power topology to which the power module belongs and the electrical parameters of the power module, the second layout area of ​​the power module can be obtained to obtain the occupied area.

[0088] When determining the through-hole development process for the board to be developed, configuration information can be retrieved from a specified location to determine the number of items and corresponding electrical parameters for each power module, as shown in Table 5. In Table 5, the board to be developed may include power module 1 and power module 2. Power module 1 has an input voltage of 12V, an output voltage of 3.3V, an input current of 0.2A, an output current of 0.7A, and a number of items of 1. Power module 2 has an input voltage of 12V, an output voltage of 0.9V, an input current of 0.9A, an output current of 12A, and a number of items of 7.

[0089] Table 5

[0090]

[0091] Based on the number of items and corresponding electrical parameters of each power module group, the target power topology for each power module group can be determined. Specifically, the combination of different electrical parameters can be represented as a combination of input voltage and output voltage. A target topology set can be determined based on the number of items in the power module; and a target power topology can be determined from multiple power topologies included in the target topology set based on the input and output voltages of the power modules.

[0092] For example, for power module 1, which has 1 item, the target topology set corresponding to power module 1 can be determined as the power topology set for single-phase power modules. Based on the combination of input voltage 12V and output voltage 3.3V, the target power topology 1 corresponding to power module 1 can be determined from the multiple power topologies included in the power topology set of single-phase power modules. Similarly, for power module 2, which has 7 items, the target topology set corresponding to power module 2 can be determined as the power topology set for multi-phase power modules. Based on the combination of input voltage 12V and output voltage 0.9V, the target power topology 2 corresponding to power module 2 can be determined from the multiple power topologies included in the power topology set of multi-phase power modules.

[0093] After determining the target power topology of the power module, the second layout area of ​​the power module can be calculated based on the components included in the target power topology.

[0094] Figure 4A A schematic diagram of the power topology of a single-phase power module according to an embodiment of the present invention is shown.

[0095] like Figure 4A As shown, the power topology of a single-phase power module may include an input current via area, an input inductor, an input capacitor, a power chip, an output inductor, an output capacitor, and an output current via area.

[0096] Figure 4B A schematic diagram of the power topology of a multi-power supply module according to an embodiment of the present invention is shown.

[0097] like Figure 4B As shown, the power topology of a multi-power supply module can include multiple branches. The input inductor of this power topology can receive current supplied from the input current via region and supply the current to the multiple branches respectively. Each branch can include an input capacitor, a power chip, an output inductor, an output capacitor, and an output current via region.

[0098] according to Figure 4A and Figure 4B As can be seen, the area occupied by the power supply topology can be calculated based on the length and width of each component in the power supply topology, as well as the area occupied by the vias in the input and output areas, thus obtaining the second layout area of ​​the power supply module.

[0099] Optionally, the number of input vias and the number of output vias can be obtained based on the input current, the output current, and the via current carrying value; the via region length can be obtained based on the number of input vias and the number of output vias; the equivalent length of the power module can be obtained based on the via region length and the equivalent length of the target power topology; and the second layout area of ​​the power module can be obtained based on the equivalent length of the power module and the equivalent width of the target power topology.

[0100] Specifically, for each power supply topology, information on all components of that topology can be pre-obtained based on its schematic diagram and categorized to record the configuration information for the second category of components. Alternatively, after determining the target power supply topology, information on all components of that topology can be obtained based on its schematic diagram and categorized to record the configuration information for the second category of components. The method of categorizing the components included in the power supply topology is not limited here. For example, the definitions of the pins connected to the two ends of an inductor and the pins connected to the two ends of a capacitor can be retrieved to classify multiple inductors as input inductors and output inductors, and multiple capacitors as input capacitors and output capacitors, respectively.

[0101] The second category of devices can refer to the components that make up a power supply module, including capacitors, inductors, power chips, etc. that make up the power supply module.

[0102] For electrical parameters including input current and output current, the number of input vias to be set in the input area and the number of output vias to be set in the output area can be determined based on the current carrying capacity of each via.

[0103] After determining the number of input vias, the number of output vias, and the configuration information of the second type of devices included in the target power supply topology, the equivalent length and equivalent width of the equivalent occupied area of ​​the power supply module can be calculated respectively. The area of ​​the equivalent occupied area of ​​the power supply module can be expressed as the second layout area of ​​the power supply module.

[0104] When calculating the equivalent length of the power module, the via region length and the equivalent length of the target power topology can be determined separately, and the via region length and the equivalent length of the target power topology can be added together to obtain the equivalent length of the power module.

[0105] Optionally, when the vias are arranged in a single row, the length of the input via region can be obtained based on the number of input vias, and the length of the output via region can be obtained based on the number of output vias. Taking the calculation of the length of the input via region as an example, the length of the input via region Lin1 = 2 × r1 × n1 + (n1 + 2) × w3, where r1 can represent the radius of the via, n1 can represent the number of input vias, and w3 can represent the spacing between the vias.

[0106] Optionally, when the process is arranged in multiple rows, the length of the input via region and the length of the output via region can be obtained based on the preset number of vias per row. Taking the calculation of the length of the input via region as an example, the length of the input via region Lin2 = 2 × r1 × n2 + (n2 + 2) × w3, where n2 can be represented as the preset number of vias per row.

[0107] The equivalent length of the target power supply topology can be calculated during the process of determining the board hole development process of the board to be developed, or it can be calculated in advance, and there is no limitation here.

[0108] Optionally, regardless of whether the power module is a single-phase or multi-phase power module, the equivalent length of the corresponding target power topology will not change with the number of phases, provided that the electrical parameters remain unchanged. Therefore, the equivalent length of the target power topology can be obtained based on the lengths of the input inductor, input capacitor, power chip, output inductor, and output capacitor included in the target power topology.

[0109] For example, the equivalent length of the target power module can be expressed as: Equivalent Length = Input Inductor Length + First Redundancy + Input Capacitor Length + Second Redundancy + Power Chip Length + Third Redundancy + Output Capacitor Length + Fourth Redundancy + Output Inductor Length. The first, second, third, and fourth redundancies can represent the spacing between components; their values ​​can be set based on product design experience or actual product requirements, and are not limited here.

[0110] Accordingly, the equivalent length of the power module can be the sum of the length of the input via region, the length of the output via region, and the equivalent length of the target power module.

[0111] The width of the components included in a power module is generally greater than the width of the via area; therefore, the width of the via area can be ignored in the calculation of the equivalent width. The main difference between multi-phase and single-phase power modules is that a multi-phase power module can include multiple branches. Therefore, under the same electrical parameters, the equivalent widths of multi-phase and single-phase power modules may differ.

[0112] For example, when the target power supply topology is a single-phase power supply topology, the equivalent width of the target power supply topology can be obtained based on the maximum width of each of the multiple second-type devices included in the target power supply topology.

[0113] Specifically, the equivalent width of the target power supply topology can be obtained by taking the maximum width value from the widths of the various second-type devices included in the target power supply topology and adding the maximum width value to a preset safety distance value.

[0114] For example, when the target power supply topology consists of multiple power supply topologies, the equivalent width of the input capacitors can be obtained based on the number and width of the input capacitors included in the target power supply topology; the equivalent width of the power chips can be obtained based on the number and width of the power chips included in the target power supply topology; the equivalent width of the output inductors can be obtained based on the number and width of the output inductors included in the target power supply topology; the equivalent width of the output capacitors can be obtained based on the number and width of the output capacitors included in the target power supply topology; and the equivalent width of the target power supply topology can be obtained based on the maximum value among the equivalent widths of the input capacitors, the power chips, the output inductors, and the output capacitors.

[0115] Optionally, the equivalent width of an input capacitor can be expressed as the product of the number of input capacitors and the width of a single capacitor. Similarly, the equivalent width of a power supply chip can be expressed as the product of the number of power supply chips and the width of a single power supply chip; the equivalent width of an output inductor can be expressed as the product of the number of output inductors and the width of a single output inductor; and the equivalent width of an output capacitor can be expressed as the product of the number of output capacitors and the width of a single output capacitor.

[0116] Optionally, when calculating the equivalent width of the input capacitor, the equivalent width of the power supply chip, the equivalent width of the output inductor, and the equivalent width of the output capacitor, a safety distance value can be added. This safety distance value can be determined by the number of devices and the safety interval between devices, and is not limited here.

[0117] After obtaining the equivalent width of the input capacitor, the equivalent width of the power supply chip, the equivalent width of the output inductor, and the equivalent width of the output capacitor, these four values ​​can be compared, and the maximum value can be taken as the equivalent width of the target power supply topology.

[0118] The equivalent width of the target power supply topology can also be used as the equivalent length of the power supply module. After obtaining the equivalent length and equivalent width of the power supply module, the equivalent length and equivalent width can be multiplied to obtain the second layout area of ​​the power supply module. The sum of the second layout areas of the at least one power supply module can be represented, for example, as S2.

[0119] Optionally, the plurality of devices may also include a plurality of third-class devices. The third-class devices may refer to all devices in the plurality of devices other than the first-class devices and the second-class devices included in the power module, including various surface-mount devices, through-hole devices, etc., without limitation.

[0120] For surface mount devices in the third category, the body area of ​​the surface mount device can be used as the third layout area of ​​the device.

[0121] For through-hole devices in the third category, the third layout area of ​​the through-hole device can be obtained by combining the number of pins of the through-hole device and the body area of ​​the through-hole device.

[0122] Specifically, the via area of ​​the third type of device can be determined based on the number of pins of the third type of device; and the third layout area of ​​the third type of device can be obtained based on the body area and via area of ​​the third type of device, so as to obtain the occupied area of ​​the board to be developed.

[0123] For example, the total number of pins n3 can be obtained by counting the pins of all third-class devices. If the radius of the via of the pin is r2 and the spacing between the vias of the pin is w4, then the sum of the areas of all third-class devices can be expressed as S3=∑Sbody+n3×n4×(r2+2×w4) ×(r2+2×w4), where S3 can represent the sum of the areas of multiple third-class devices, ∑Sbody can represent the sum of the body areas of all third-class devices, and n4 can represent the number of routing layer changes.

[0124] Optionally, based on the types of devices included in the board to be developed, the area occupied by the board can be calculated based on at least one of the sum of the areas of multiple first-type devices (S1), the sum of the areas of at least one power supply module (S2), and the sum of the areas of multiple third-type devices (S3). For example, the area occupied by the board can be Suse = S1 + S2 + S3, where Suse represents the area occupied by the board.

[0125] Subsequently, the via development process of the board to be developed can be determined by comparing the effective area S0 with the occupied area Suse of the board to be developed, which will not be elaborated here.

[0126] Alternatively, considering calculation errors and the impact of obstacles such as pillars on component layout and wiring, the effective area and occupied area can be weighted separately. By comparing the weighted effective area and the weighted occupied area, it can be determined whether the board under development is suitable for through-hole technology or special processes such as POFV. Optionally, the weight corresponding to the effective area can be a value less than 1, so that the weighted effective area can be smaller than the effective area, and the weight corresponding to the occupied area can be a value greater than 1, so that the weighted occupied area can be larger than the occupied area, thereby compensating for the impact of obstacles on component layout and wiring between components.

[0127] According to embodiments of the present invention, comprehensive data processing is performed on the design requirements of PCB boards across various fields, including structural design, manufacturing processes, and signal transmission, transforming these dispersed and multi-dimensional requirements into quantifiable and computable parameter information. Subsequently, combined with the actual environmental parameters of the board to be developed, such as board size, component layout planning, and pin distribution, a pre-set algorithm is used for comprehensive calculation. During the calculation process, the effective area of ​​areas on the board that cannot be used for layout and routing is calculated, based on the space required to complete routing under conventional through-hole technology, encompassing key factors such as through-hole space occupation and routing channel width. The calculated effective area is then compared with the layout and routing area to determine the through-hole development process for the board. This scheme scientifically and rationally determines the process category to be adopted for PCB board development, effectively solving key technical and cost problems such as over-design, increased costs, and large amounts of rework caused by relying on subjective judgment of processes, providing strong support for the efficient, low-cost, and high-quality development of storage product boards.

[0128] Figure 5 A block diagram of an electronic device suitable for implementing a method for determining board hole development process according to an embodiment of the present invention is shown.

[0129] like Figure 5 As shown, an electronic device 500 according to an embodiment of the present invention includes a processor 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage portion 508 into a random access memory (RAM) 503. The processor 501 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0130] RAM 503 stores various programs and data required for the operation of electronic device 500. Processor 501, ROM 502, and RAM 503 are interconnected via bus 504. Processor 501 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 502 and / or RAM 503. It should be noted that the programs may also be stored in one or more memories other than ROM 502 and RAM 503. Processor 501 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0131] According to an embodiment of the present invention, the electronic device 500 may further include an input / output (I / O) interface 505, which is also connected to a bus 504. The electronic device 500 may also include one or more of the following components connected to the input / output (I / O) interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the input / output (I / O) interface 505 as needed. A removable medium 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 510 as needed so that computer programs read from it can be installed into the storage section 508 as needed.

[0132] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0133] According to embodiments of the present invention, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, the computer-readable storage medium may include ROM 502 and / or RAM 503 and / or one or more memories other than ROM 502 and RAM 503 described above.

[0134] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the methods provided in the embodiments of the present invention.

[0135] When the computer program is executed by the processor 501, it performs the functions defined in the system / apparatus of this invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0136] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 509, and / or installed from a removable medium 511. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0137] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by processor 501, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0138] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0139] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0140] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0141] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for determining the process of developing perforated plates, characterized in that, include: Determining the effective area of ​​the board to be developed based on its shape includes: parsing the board structure file of the board to be developed to obtain multiple shape elements; determining at least one first target shape element and at least one second target shape element from the multiple shape elements based on the type of the shape elements and the board layer level where the shape elements are located; and determining the effective area of ​​the board to be developed based on the area of ​​the at least one first target shape element and the area of ​​the at least one second target shape element. Based on the layout information of multiple devices associated with the board to be developed, the area occupied by the body layout of the multiple devices and the area occupied by the wiring between the multiple devices are determined under the through-hole process, thus obtaining the area occupied by the board to be developed; and Based on the effective area and the occupied area, the through-hole development process of the board to be developed is determined.

2. The method according to claim 1, characterized in that, The plurality of said devices include a plurality of first-type devices; The step of determining the area occupied by the physical layout of the multiple devices and the area occupied by the wiring between the multiple devices under the through-hole process, based on the layout information of the multiple devices related to the board to be developed, to obtain the area occupied by the board to be developed, includes: The board layout file of the board to be developed is parsed to determine the connection topology of multiple first-type devices and their respective layout positions; Based on the connection topology, the first layout area of ​​the plurality of first-type devices is determined; Based on the connection topology and the respective layout positions of the plurality of first-type devices, the wiring area between the plurality of first-type devices is determined; and The occupied area is obtained based on the first layout area and the wiring area.

3. The method according to claim 2, characterized in that, Determining the first layout area of ​​the plurality of first-type devices based on the connection topology includes: Based on the connection topology, determine the number of outgoing lines for the first type of device; Based on the number and type of outgoing wires of the first type of device, the outgoing wire area of ​​the first type of device is determined; and The first layout area is obtained based on the outgoing line area and the body area of ​​the first type of device.

4. The method according to claim 2, characterized in that, Determining the wiring area between the multiple first-type devices based on the connection topology and their respective layout positions includes: For a first device and a second device among multiple devices of the first type, the number of signal traces between the first device and the second device is determined based on the connection topology between the first device and the second device; Based on the layout positions of the first device and the second device, the number of signal traces, and the preset signal line width, an equivalent wiring area is determined; and Based on the area of ​​the equivalent wiring region, the wiring area between the first device and the second device is obtained.

5. The method according to claim 1, characterized in that, The plurality of said devices include at least one power supply module; The step of determining the area occupied by the physical layout of the multiple devices and the area occupied by the wiring between the multiple devices under the through-hole process, based on the layout information of the multiple devices related to the board to be developed, to obtain the area occupied by the board to be developed, includes: Based on the electrical parameters of the power module, the target power topology to which the power module belongs is determined; and Based on the target power topology to which the power module belongs and the electrical parameters of the power module, the second layout area of ​​the power module is obtained, and the area occupied by the board to be developed includes the second layout area of ​​the power module.

6. The method according to claim 5, characterized in that, The electrical parameters include input voltage and output voltage; The step of determining the target power topology to which the power module belongs based on the electrical parameters of the power module includes: Based on the number of items in the power module, determine the target topology set; and Based on the input voltage and output voltage of the power module, the target power topology is determined from the multiple power topologies included in the target topology set.

7. The method according to claim 5, characterized in that, The electrical parameters also include input current and output current; The step of obtaining the second layout area of ​​the power module based on the target power topology to which the power module belongs and the electrical parameters of the power module includes: Based on the input current, the output current, and the via current carrying value, the number of input vias and the number of output vias are obtained; The via region length is obtained based on the number of input vias and the number of output vias; Based on the via region length and the equivalent length of the target power supply topology, the equivalent length of the power supply module is obtained; and The second layout area of ​​the power module is obtained based on the equivalent length of the power module and the equivalent width of the target power topology.

8. The method according to claim 7, characterized in that, The method further includes: Based on the lengths of the input inductor, input capacitor, power chip, output inductor, and output capacitor included in the target power topology, the equivalent length of the target power topology is obtained.

9. The method according to claim 7, characterized in that, The method further includes: When the target power supply topology is a single-phase power supply topology, the equivalent width of the target power supply topology is obtained based on the maximum width of each of the multiple second-type devices included in the target power supply topology.

10. The method according to claim 7, characterized in that, The method further includes: When the target power supply topology is a multi-power supply topology, the equivalent width of the input capacitor is obtained based on the number of input capacitors included in the target power supply topology and the width of the input capacitors. Based on the number of power chips included in the target power topology and the width of the power chips, the equivalent width of the power chips is obtained. Based on the number of output inductors and the width of the output inductors included in the target power supply topology, the equivalent width of the output inductors is obtained; Based on the number of output capacitors and the width of the output capacitors in the target power supply topology, the equivalent width of the output capacitors is obtained; and The equivalent width of the target power supply topology is obtained based on the maximum value among the equivalent width of the input capacitor, the equivalent width of the power supply chip, the equivalent width of the output inductor, and the equivalent width of the output capacitor.

11. The method according to claim 1, characterized in that, The plurality of said devices includes a plurality of third-class devices; The step of determining the area occupied by the physical layout of the multiple devices and the area occupied by the wiring between the multiple devices under the through-hole process, based on the layout information of the multiple devices related to the board to be developed, to obtain the area occupied by the board to be developed, includes: Based on the number of pins of the third type of device, determine the via area of ​​the third type of device; and Based on the body area of ​​the third type of device and the area of ​​the via region, the third layout area of ​​the third type of device is obtained, and the area occupied by the board to be developed includes the third layout area of ​​the third type of device.

12. The method according to claim 1, characterized in that, The step of determining at least one first target shape element and at least one second target shape element from a plurality of shape elements based on the type of the shape element and the layer level of the shape element includes: If the type of the shape element is a circuit board geometry and the layer level of the shape element is a border layer, then the shape element is determined to be the first target shape element. If the type of the shape element is a circuit board geometry and the layer level of the shape element is a cut-off layer, then the shape element is determined to be the second target shape element. If the shape element is of type "no routing area" and the board layer level where the shape element is located is the first or second surface layer of the board to be developed, then the shape element is determined to be the second target shape element; and If the shape element is of type Restricted Layout Area, the shape element is located in the first surface layer, and the component height threshold of the shape element is less than a preset value, then the shape element is determined to be the second target shape element.

13. The method according to claim 1, characterized in that, Determining the effective area of ​​the board to be developed based on the area of ​​the first target shape element and the area of ​​at least one second target shape element includes: The area of ​​the invalid region is obtained based on the sum of the areas of the at least one second target shape element; and The effective area of ​​the board to be developed is obtained by subtracting the area of ​​the invalid region from the sum of the areas of the at least one first target shape element.

14. An electronic device comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 13.

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