Preparation method of multi-layer printed circuit board, multi-layer printed circuit board and electronic equipment

Abstract

The invention discloses a preparation method and device of a multilayer printed circuit board, electronic equipment and a storage medium. The embodiment of the invention relates to the technical field of cloud technology and the like. The method comprises the following steps: providing a first core board which is used for bearing each sub-circuit in a first middle circuit layer and is matched with the corresponding performance requirement grade according to the performance requirement grade of each sub-circuit on the first middle circuit layer in a plurality of circuit layers on the core board; the plurality of circuit layers also at least comprise a top circuit layer and a bottom circuit layer; processing corresponding to-be-borne sub-circuits on the surface of each first core board; and stacking and laminating the at least two first core boards on which the sub-circuits on the first middle circuit layer are processed, a first substrate for bearing the top circuit layer and a second substrate for bearing the bottom circuit layer to form the multi-layer printed circuit board bearing the plurality of circuit layers. According to the method provided by the invention, the cost of the multi-layer printed circuit board is reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and more specifically, to a method for preparing a multilayer printed circuit board, a multilayer printed circuit board, and an electronic device. Background Art

[0002] Printed circuit boards are important electronic components, supporting the electronic components and serving as a carrier for the electrical connection between the electronic components.

[0003] In some circuits, complex electrical connections require the construction of multilayer printed circuit boards (PCBs). Core boards are one of the raw materials used to make these boards, and prices vary depending on the performance of the core boards. This has led to high production costs for multilayer PCBs in related technologies. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a method for preparing a multilayer printed circuit board, a multilayer printed circuit board, and an electronic device.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a multilayer printed circuit board, the method comprising: providing a first core board for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirement level according to the performance requirement level of each sub-circuit on the first intermediate circuit layer among multiple circuit layers to the core board, the first intermediate circuit layer refers to an intermediate circuit layer among multiple circuit layers that includes at least two sub-circuits with different performance requirement levels for the core board; the multiple circuit layers also include at least a top circuit layer and a bottom circuit layer; processing the corresponding sub-circuit to be carried on the surface of each first core board; based on at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, a first substrate for carrying the top circuit layer and a second substrate for carrying the bottom circuit layer are stacked and pressed to form a multilayer printed circuit board carrying multiple circuit layers.

[0006] In a second aspect, an embodiment of the present application provides a multilayer printed circuit board, which is manufactured according to the method for manufacturing the multilayer printed circuit board of the first aspect.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, comprising the multilayer printed circuit board in the aforementioned second aspect.

[0008] Embodiments of the present application provide a method for preparing a multilayer printed circuit board, a multilayer printed circuit board, and an electronic device. In the present application, according to the performance requirement level of each sub-circuit on the first intermediate circuit layer among multiple circuit layers to the core board, a first core board for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirement level is provided. The first core board of each sub-circuit in the same first intermediate circuit layer is a core board that matches the performance requirement level of each sub-circuit to the core board, thereby achieving targeted selection of core boards according to the performance requirement level of the sub-circuit to the core board, instead of using the core board that carries the sub-circuit with the highest performance requirement level to the core board in the first intermediate circuit layer as the core board for carrying the first intermediate circuit layer. This avoids the problem of high cost of the multilayer printed circuit board caused by using a core board with a higher performance requirement level to carry a circuit with a lower performance requirement level to the core board. As a result, the cost of the multilayer printed circuit board is reduced by processing at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer, thereby achieving preparation of the multilayer printed circuit board by regional lamination. Since the first core board provided for each sub-circuit can meet the corresponding performance requirements, the performance of the manufactured multi-layer printed circuit board is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 A flow chart showing a method for preparing a multilayer printed circuit board according to an embodiment of the present application is shown;

[0011] Figure 2 A schematic diagram of a first intermediate circuit layer in an embodiment of the present application is shown;

[0012] Figure 3 A schematic diagram of a top circuit layer in an embodiment of the present application is shown;

[0013] Figure 4 A schematic diagram of a bottom circuit layer in an embodiment of the present application is shown;

[0014] Figure 5 A schematic diagram of a first core plate in an embodiment of the present application is shown;

[0015] Figure 6 A schematic diagram of another first intermediate circuit layer in an embodiment of the present application is shown;

[0016] Figure 7Shown with Figure 6 A schematic diagram of a first core board after processing edge contours matching each sub-circuit in the first intermediate circuit layer;

[0017] Figure 8 A schematic diagram showing a process for preparing a first printed circuit board in an embodiment of the present application is shown;

[0018] Figure 9 A flow chart showing a method for preparing a multilayer printed circuit board according to another embodiment of the present application is shown;

[0019] Figure 10 A flow chart showing a method for preparing a multilayer printed circuit board according to another embodiment of the present application is shown;

[0020] Figure 11 A flow chart showing a method for preparing a multilayer printed circuit board according to another embodiment of the present application is shown;

[0021] Figure 12 A schematic diagram showing the cooperation between a positioning device and a prepreg board in an embodiment of the present application is shown;

[0022] Figure 13 A schematic diagram showing a process for preparing a multilayer printed circuit board in an embodiment of the present application is shown;

[0023] Figure 14 A schematic diagram of a punched first core board in an embodiment of the present application is shown;

[0024] Figure 15 A schematic diagram of a first core board carrying circuits in an embodiment of the present application is shown;

[0025] Figure 16 A schematic diagram of stacking a core board, a prepreg board, and a substrate using a positioning jig in an embodiment of the present application is shown;

[0026] Figure 17 Shown Figure 16 Schematic diagram of the superposition result obtained by the superposition process shown;

[0027] Figure 18 Shown according to Figure 17 Schematic diagram of a multilayer printed circuit board prepared by the stacking result shown;

[0028] Figure 19 Shown Figure 18 The schematic diagram of the multilayer printed circuit board after the positioning holes are cut out is shown;

[0029] Figure 20 Shown Figure 19 Schematic diagram of a cross section of a multilayer printed circuit board is shown. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of this application without making creative efforts are within the scope of protection of this application.

[0031] In the following description, the terms "first\second" are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application. It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0033] For ease of understanding, before explaining the technical solutions of the embodiments of the present application, the terms involved in the embodiments of the present application are first explained:

[0034] Core: An insulating layer with conductive material on both sides. The conductive material can be copper.

[0035] Prepreg: An insulating layer with an adhesive. Prepreg is typically sandwiched between two adjacent core sheets.

[0036] The embodiments of the present application relate to fields such as cloud technology. Cloud technology refers to a hosting technology that unifies hardware, software, network and other resources within a wide area network or a local area network to achieve data computing, storage, processing and sharing.

[0037] Cloud technology is a general term for network technology, information technology, integration technology, management platform technology, and application technology based on the cloud computing business model. It can form a resource pool for on-demand, flexible and convenient use. Cloud computing technology will become a key support. Backend services of technical network systems, such as video websites, image websites, and more portals, require extensive computing and storage resources. With the rapid development and application of the internet industry, every item will likely have its own unique identification mark, which will need to be transmitted to backend systems for logical processing. Different levels of data will be processed separately. All types of industry data require strong system support, which can only be achieved through cloud computing.

[0038] The multilayer printed circuit board prepared according to the embodiments of the present application can be used in electronic devices, servers, etc. that provide cloud services (such as cloud conferencing, cloud storage, cloud computing, etc.).

[0039] In the related art, inner layer circuits are first processed on both sides of a core board with copper foil on both sides, and then a prepreg board with adhesive is sandwiched between the multi-layer core boards. After lamination, a multi-layer printed circuit board with inner layer circuits is formed.

[0040] If the circuits in a certain circuit layer include both sub-circuits with high core board performance requirements and sub-circuits with low core board requirements, a high-performance core board is selected to carry multiple sub-circuits of the circuit layer, so that the core board can simultaneously carry sub-circuits with low core board requirements and sub-circuits with high core board requirements. However, the cost of sub-circuits with higher performance is higher, resulting in a higher preparation cost of the multi-layer printed circuit board.

[0041] In view of this, an embodiment of the present application provides a method for preparing a multilayer printed circuit board. In the present application, according to the performance requirement level of each sub-circuit on the first intermediate circuit layer among multiple circuit layers to the core board, a first core board for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirement level is provided. The first core board of each sub-circuit in the same first intermediate circuit layer is a core board that matches the performance requirement level of each sub-circuit to the core board, thereby achieving targeted selection of core boards according to the performance requirement level of the sub-circuit to the core board, instead of using the core board that carries the sub-circuit with the highest performance requirement level to the core board in the first intermediate circuit layer as the core board for carrying the first intermediate circuit layer. This avoids the problem of high cost of the multilayer printed circuit board caused by using a core board with a higher performance requirement level to carry a circuit with a lower performance requirement level to the core board. As a result, based on at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer, the cost of the multilayer printed circuit board is reduced, and the multilayer printed circuit board is prepared by regional lamination. Since the first core board provided for each sub-circuit can meet the corresponding performance requirements, the performance of the manufactured multi-layer printed circuit board is guaranteed.

[0042] See also Figure 1 , Figure 1 A flowchart of a method for preparing a multilayer printed circuit board according to an embodiment of the present application is shown. The method may include:

[0043] S110 , according to the performance requirement level of each sub-circuit on the first intermediate circuit layer among the multiple circuit layers to the core board, provide a first core board for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirement level.

[0044] The term "first intermediate circuit layer" refers to an intermediate circuit layer within the multiple circuit layers that includes at least two sub-circuits with different performance requirements for the core board. The number of first intermediate circuit layers within the multiple circuit layers can be one or more. The circuits in each of the multiple circuit layers are pre-designed by the designer. During the fabrication of a multilayer printed circuit board, the circuits designed for each circuit layer need to be fabricated onto the printed circuit board. The number of sub-circuits within the first intermediate circuit layer can be two or more, depending on the function of the circuits within the first intermediate circuit layer.

[0045] The multiple circuit layers include a middle circuit layer, a top circuit layer, and a bottom circuit layer. In other words, in this application, the circuit layers are at least three layers. The top circuit layer refers to the circuit layer on which the circuits need to be processed on the first conductive layer of the multilayer printed circuit board. The first conductive layer of the multilayer printed circuit board is the conductive layer used to mount electronic components (such as capacitors, resistors, transistors, etc.); the bottom circuit layer refers to the circuit layer on which the circuits need to be processed on the bottommost conductive layer of the multilayer printed circuit board.

[0046] Each circuit layer (any one of the middle circuit layer, top circuit layer and bottom circuit layer) includes at least one sub-circuit, each sub-circuit may include at least one circuit, and different circuits in each sub-circuit have the same performance requirement level for the core board; different sub-circuits in the same circuit layer may have the same performance requirement level for the core board, and different sub-circuits in the same circuit layer may also have different performance requirement levels for the core board; different sub-circuits in different circuit layers may have the same performance requirement level for the core board, and different sub-circuits in different circuit layers may also have different performance requirement levels for the core board.

[0047] Among them, the performance requirements of the core board for the lines on each line layer are determined by the function of the line. For example, if a line is a line for transmitting signals with a higher frequency, the core board used to carry the line needs to be a core board that supports the transmission of high-frequency signals (or high-speed signals). That is, the higher the frequency of the signal to be transmitted on the line, the higher the signal transmission rate requirement for the core board; for another example, if a line is a line for transmitting current with a larger current value, the core board used to carry the line needs to be a core board with a higher rated current, for example, the thickness of the conductive material of the core board is larger, that is, the larger the current value to be transmitted on the line, the larger the rated current of the core board carrying the line.

[0048] Based on this, the correspondence between the frequency of the signal and the signal transmission rate requirement level, as well as the correspondence between the current and the current requirement level can be pre-set. Then, according to the correspondence, as well as the frequency of the signal on the sub-circuit on each circuit layer and the current value of the current on the sub-circuit, the signal transmission rate requirement level and the corresponding current requirement level corresponding to the core board carrying each sub-circuit can be determined.

[0049] A core board that matches the performance requirement level of a sub-circuit pair of core boards is the core board with the lowest performance level among the core boards that meet the performance requirement level of the sub-circuit pair of core boards. For example, if the performance requirement level of a sub-circuit pair of core boards is K, and core boards A1, A2, A3, and A4 are determined among the candidate core boards to meet performance requirement level K, but core board A1 has a higher performance level than core board A2, which in turn has a higher performance level than core board A3, which in turn has a higher performance level than core board A4, then core board A4 is determined to match the performance requirement level of the sub-circuit pair of core boards.

[0050] For core boards, the higher the current requirement level, the higher the rated current of the core board. Different current requirement levels correspond to different core boards. Generally speaking, the thicker the conductive material on the core board surface, the higher the rated current of the core board. Therefore, the current requirement level of the core board can be converted into a requirement for the thickness of the conductive material of the core board. For example, if the current requirement level k1 is greater than the current requirement level k2, the thickness of the conductive material on the core board surface that matches the current requirement level k1 is greater than the thickness of the conductive material on the core board surface that matches the current requirement level k2.

[0051] In some embodiments, if the sub-circuit is a circuit for transmitting signals with a frequency exceeding a first frequency threshold, the performance requirement level of the sub-circuit for the core board is a first signal transmission rate requirement level; if the sub-circuit is a circuit for transmitting signals with a frequency not exceeding the first frequency threshold, the performance requirement level of the sub-circuit for the core board is a second signal transmission rate requirement level, wherein the signal transmission rate required by the second signal transmission rate requirement level is lower than the signal transmission rate required by the first signal transmission rate requirement level; if the sub-circuit is a circuit for transmitting current exceeding a current threshold, the performance requirement level of the sub-circuit for the core board is a first current requirement level; if the sub-circuit is a circuit for transmitting current not exceeding the current threshold, the performance requirement level of the sub-circuit for the core board is a second current requirement level, wherein the current value required by the first current requirement level is greater than the current value required by the second current requirement level. The first frequency threshold, the second frequency threshold, and the current threshold can be values ​​set based on demand, for example, the first frequency threshold is 50 Hz, the second frequency threshold is 30 Hz, and the current threshold is 300 mA.

[0052] It can be understood that the aforementioned division of the signal transmission rate requirement levels into the first signal transmission rate requirement level and the second signal transmission rate requirement level based on the line-aggregated signal transmission rate is only an example. Multiple signal transmission rate intervals can also be set, and each signal transmission rate interval matches a signal transmission rate requirement level. For example, the signal transmission rate is divided into 5 signal transmission rate intervals, and each signal transmission rate interval matches a signal transmission rate requirement level. At this time, the determined signal transmission rate requirement levels are 5.

[0053] Similarly, dividing the current requirement levels into a first current requirement level and a second current requirement level based on the magnitude of the line current is also an example. Alternatively, multiple current intervals may be set, with each current interval matching a current requirement level. For example, if the current is divided into four current intervals, with each current interval matching a current requirement level, then four current requirement levels are determined.

[0054] In the present application, a user can design multiple circuit layers based on the layout of the various components to be connected by the multiple circuit layers. At the same time, the user can also determine the layout information corresponding to the multiple circuit layers. The layout information may include the hierarchical order of the multiple circuit layers, the relative positional relationship between the sub-circuits in the same intermediate circuit layer, and the circuit path of each sub-circuit. The hierarchical order refers to the stacking relationship of multiple circuits; for example, the hierarchical order is the top circuit layer, the first intermediate circuit layer a1, the first intermediate circuit layer a2, and the bottom circuit layer stacked in sequence from top to bottom, and the relative positional relationship is that the sub-circuit a11 in the first intermediate circuit layer a1 is to the left of the sub-circuit a12, and the sub-circuit a21 in the first intermediate circuit layer a2 is to the left of the sub-circuit a22.

[0055] Different performance requirement levels are matched to different pre-installed core boards. For example, when the performance requirement levels include a first signal transmission rate requirement level, a second signal transmission rate requirement level, a first current requirement level, and a second current requirement level, the pre-installed core boards include a first pre-installed core board that matches the first signal transmission rate requirement level, a second pre-installed core board that matches the second signal transmission rate requirement level, a third pre-installed core board that matches the first current requirement level, and a fourth pre-installed core board that matches the second current requirement level. In some scenarios, the fourth pre-installed core board that matches the second current requirement level can be the same as the second pre-installed core board that matches the second signal transmission rate requirement level, that is, the fourth pre-installed core board can simultaneously match the second signal transmission rate requirement level and the second current requirement level.

[0056] For each sub-circuit in the first intermediate circuit layer, a matching pre-installed core board is determined as the first core board for carrying each sub-circuit according to the performance requirements of each sub-circuit on the core board. For example, Figure 2 As shown, the first intermediate circuit layer 302 includes two sub-circuits: sub-circuit 3021 and sub-circuit 3022, wherein sub-circuit 3021 includes 2 lines and sub-circuit 3022 includes 5 lines; the performance requirement level of the 2 lines included in sub-circuit 3021 to the core board is the first signal transmission rate requirement level, and the first preset core board is determined as the first core board carrying sub-circuit 3021; ​​the performance requirement level of the 5 lines included in sub-circuit 3022 to the core board is the first current requirement level, and the third preset core board is determined as the first core board carrying sub-circuit 3022.

[0057] It is worth mentioning that conductive materials are attached to both sides of the core board, and both sides of the core board can carry circuits, that is, one core board carries the circuits of two intermediate circuit layers: the upper surface of the core board carries the circuits of the upper circuit layer, and the lower surface of the core board carries the circuits of the lower circuit layer; at this time, a preset core board that matches the performance requirements of both circuit layers can be obtained as the first core board.

[0058] For example, the circuits of the first intermediate circuit layer a3 and the circuits of the first intermediate circuit layer a4 are carried by both sides of the core board. The first intermediate circuit layer a3 includes a sub-circuit a31 with a first signal transmission rate requirement level for the core board performance and a sub-circuit a31 with a third signal transmission rate requirement level for the core board performance. The first intermediate circuit layer a4 includes a sub-circuit a41 with a second signal transmission rate requirement level for the core board performance and a sub-circuit a42 with a fourth signal transmission rate requirement level for the core board performance, wherein the first signal transmission rate requirement level is higher than the second signal transmission rate requirement level. The second signal transmission rate requirement level is higher than the third signal transmission rate requirement level, and the third signal transmission rate requirement level is higher than the fourth signal transmission rate requirement level. At this time, a preset core board that matches the first signal transmission rate requirement level is obtained as the first core board x1 that carries sub-circuit a31 and sub-circuit a42, and a preset core board that matches the second signal transmission rate requirement level is obtained as the first core board x2 that carries sub-circuit a32 and sub-circuit a41, wherein both sides of the first core board x1 are used for processing sub-circuit a31 and sub-circuit a42, and both sides of the first core board x2 are used for processing sub-circuit a32 and sub-circuit a41.

[0059] The substrate used to carry the top circuit layer serves as the first substrate, and the substrate used to carry the bottom circuit layer serves as the second substrate. The surface of the first substrate used to carry the top circuit layer may have a conductive material (for example, the surface of the first substrate has a prepreg board with a conductive material), so that the circuits in the top circuit layer can be directly processed on the surface of the first substrate used to carry the top circuit layer. The surface of the first substrate used to carry the top circuit layer may also not have a conductive material (for example, the first substrate is a prepreg board), and the surface of the first substrate used to carry the top circuit layer may be plated with a conductive material, and then the circuits in the top circuit layer may be processed on the surface plated with the conductive material. Similarly, the surface of the second substrate used to carry the bottom circuit layer may have a conductive material, so that the circuits in the bottom circuit layer can be directly processed on the surface of the second substrate used to carry the bottom circuit layer. The surface of the second substrate used to carry the bottom circuit layer may also not have a conductive material, and the surface of the second substrate used to carry the bottom circuit layer may be plated with a conductive material, and then the circuits in the bottom circuit layer may be processed on the surface plated with the conductive material. The conductive material can be copper, aluminum, silver, etc., which are not specifically limited here.

[0060] It should be noted that the performance requirement level of each sub-circuit in the top circuit layer to the core board can be the same, and the performance requirement level of each sub-circuit in the top circuit layer to the core board can also be different. However, the first substrate used to support the top circuit layer is usually a whole. When selecting the first substrate with a conductive material on the surface, the highest performance requirement level of each sub-circuit in the top circuit layer to the core board is determined to be the top circuit layer performance requirement level, and then a substrate with a conductive material on the surface that matches the performance requirement level of the top circuit layer is obtained as the first substrate; if the surface of the first substrate does not have a conductive material, then when the first substrate is plated with conductive material, the plated conductive material matches the performance requirement level of the top circuit layer (matching the conductive material with the performance requirement level means that the thickness, impedance and other parameters of the conductive material match the performance requirement level. For different performance requirement levels, the thickness, impedance and other parameters of the matched conductive material may be different).

[0061] Similarly, the performance requirement level of each sub-circuit in the bottom circuit layer for the core board can be the same, and the performance requirement level of each sub-circuit in the bottom circuit layer for the core board can also be different. However, the second substrate used to support the bottom circuit layer is usually an integral whole. When selecting the second substrate with a conductive material on the surface, the performance requirement level of each sub-circuit in the bottom circuit layer for the core board is determined to be the highest as the bottom circuit layer performance requirement level. Then, a substrate with a conductive material on the surface that matches the performance requirement level of the bottom circuit layer is obtained as the second substrate. If the surface of the second substrate does not have a conductive material, then when the first substrate is plated with conductive material, the plated conductive material matches the performance requirement level of the bottom circuit layer.

[0062] For example, Figure 3 A schematic diagram of the top circuit layer 301 is shown. The top circuit layer includes four circuits. Circuits 3011 and 3012 have the same performance requirement level for the core board. Circuits 3011 and 3012 can be used as a sub-circuit. Circuits 3013 and 3014 have the same performance requirement level for the core board. Circuits 3013 and 3012 have different performance requirements for the core board. Circuits 3014 and 3013 can be used as a sub-circuit. The performance requirement level for the core board of circuit 3011 is higher than that of circuit 3013. A substrate having a conductive material on its surface that matches the performance requirement level of circuit 3013 for the core board is obtained as the first substrate. Alternatively, a conductive material matching the performance requirement level of circuit 3013 for the core board is plated on the surface of the first substrate that does not have a conductive material and is used to support the top circuit layer.

[0063] For example, Figure 4A schematic diagram of the bottom circuit layer 303 is shown. The bottom circuit layer includes four circuits. The performance requirement level of each circuit to the core board is the same. The four circuits can be used as a sub-circuit. The performance requirement level of the four circuits to the core board is the first signal transmission rate requirement level. A substrate with a conductive material on the surface and the conductive material matching the performance requirement level of any circuit to the core board is obtained as the second substrate. Alternatively, a conductive material matching the performance requirement level of any circuit to the core board is plated on the surface of the second substrate without conductive material for carrying the bottom circuit layer.

[0064] It is worth mentioning that in different printed circuit board usage scenarios, the determined first frequency threshold, second frequency threshold and current threshold may be different, so that the performance of the preset core board set for each performance requirement level may also be different. The multi-layer printed circuit board formed is for computing scenarios with higher computing power requirements (such as training of large models), and the determined first frequency threshold, second frequency threshold and current threshold may be higher, and the performance of the first preset core board for the first signal transmission rate requirement level, the performance of the second preset core board for the second signal transmission rate requirement level, the third preset core board for the first current requirement level and the performance of the fourth preset core board for the second current requirement level are all higher; for example, the formed multi-layer printed circuit board is for computing scenarios with lower computing power requirements (such as compilation of document files), and the determined first frequency threshold, second frequency threshold and current threshold may be lower, and the determined first frequency threshold, second frequency threshold and current threshold may be higher, and the performance of the first preset core board for the first signal transmission rate requirement level, the performance of the second preset core board for the second signal transmission rate requirement level, the third preset core board for the first current requirement level and the performance of the fourth preset core board for the second current requirement level are all lower.

[0065] S120 , processing the sub-circuits to be carried on the surface of each first core board.

[0066] After each first core board is determined, the sub-circuit to be carried can be processed on the surface of each first core board.

[0067] In some embodiments, the formed multilayer printed circuit board has a fixed size, and the size of the first core board used to carry different sub-circuits in the same first intermediate circuit layer corresponds to the area occupied by the carried sub-circuits (corresponding means that the size of the first core board is not less than the area occupied by the carried sub-circuits), and the size of the first core boards used to carry different sub-circuits in the same first intermediate circuit layer after splicing is the same as the size of the multilayer printed circuit board. In this case, the corresponding sub-circuits to be carried can be directly processed on the surface of each first core board, and there is no need to process the first core board.

[0068] The first intermediate circuit layer is Figure 2In the case shown, the first core board is determined as Figure 5 As shown, the first core board 202 is used to carry the sub-circuit 3021, and the first core board 203 is used to carry the sub-circuit 3022, and the size of the rectangle obtained by splicing the first core board 202 and the first core board 203 is the same as the size of the multi-layer printed circuit board formed. At this time, the sub-circuit 3021 can be directly processed on the first core board 202, and the sub-circuit 3022 can be directly processed on the first core board 203.

[0069] In some embodiments, the dimensions of the first core boards used to carry different sub-circuits in the same first intermediate circuit layer correspond to the area occupied by the carried sub-circuits, but the dimensions of the first core boards used to carry different sub-circuits in the same first intermediate circuit layer after being spliced ​​together differ from the dimensions of the multilayer printed circuit board. In this case, before S120, the method further includes: processing a splicing profile between different first core boards corresponding to the same first intermediate circuit layer. The splicing profile refers to the profile of the splicing point between different first core boards in the same first intermediate circuit layer. The splicing profile between different first core boards corresponding to the same first intermediate circuit layer can be processed based on the layout of different sub-circuits in the same first intermediate circuit layer.

[0070] For example, the first intermediate circuit layer is Figure 6 As shown, the first intermediate circuit layer includes sub-circuits 401 and sub-circuits 402 with different performance requirements for the chip. The first core boards corresponding to the sub-circuits 401 and sub-circuits 402 are determined respectively, and the sizes of the first core boards corresponding to the sub-circuits 401 and sub-circuits 402 are the same as the sizes of the multi-layer printed circuit board to be formed, that is, the sizes of the first core boards corresponding to the sub-circuits 401 and sub-circuits 402 after splicing are the same as or different from the sizes of the multi-layer printed circuit board. At this time, according to the layout of the sub-circuits 401 and sub-circuits 402 (the sub-circuits 401 are narrow at the top and wide at the bottom, and the sub-circuits 402 are wide at the top and narrow at the bottom), the splicing contours between the first core boards corresponding to the sub-circuits 401 and sub-circuits 402 are processed. The processed first core boards are as shown in FIG. Figure 7 As shown, the sub-circuit 401 corresponds to the processed first core board 501 , the sub-circuit 402 corresponds to the processed first core board 502 , and the splicing profile 5010 of the first core board 501 matches the splicing profile 5020 of the second core board 502 .

[0071] As mentioned above, both sides of the core board can carry circuits. At this time, the splicing contours between different first core boards corresponding to the same first intermediate circuit layer can be processed based on the area occupied by the sub-circuits that need to be processed on both sides of the first core board corresponding to the same first intermediate circuit, and the performance requirements of each sub-circuit in the same first intermediate circuit for the core board.

[0072] For example, the first intermediate circuit layer a5 is stacked on the first intermediate circuit layer a6, the sub-circuit a51 in the first intermediate circuit layer a5 has a performance requirement level of the first signal transmission rate requirement level for the core board, the sub-circuit a52 in the first intermediate circuit layer a5 has a performance requirement level of the second signal transmission rate requirement level for the core board, the sub-circuit a61 in the first intermediate circuit layer a6 has a performance requirement level of the first signal transmission rate requirement level for the core board, and the sub-circuit a62 in the first intermediate circuit layer a6 has a performance requirement level of the second signal transmission rate requirement level for the core board. The transmission rate requirement level is determined, wherein the first core boards are respectively the first pre-set core board (for carrying sub-circuits a51 and a61) and the second pre-set core board (for carrying sub-circuits a52 and a62), wherein the sizes of the first pre-set core board and the second pre-set core board are the same as the sizes of the multi-layer printed circuit board to be formed. If sub-circuit a51 is on the left side of sub-circuit a52, and the areas occupied by sub-circuit a51 and sub-circuit a52 are half of the first pre-set core board, sub-circuit a61 is on the left side of sub-circuit a62, and sub-circuit a61 The area occupied by the sub-circuit a62 is two-thirds of the second pre-installed core board, and the area occupied by the sub-circuit a62 is one-third of the second pre-installed core board. At this time, it is determined that the area of ​​the sub-circuit a51 used for carrying is smaller than the area used for carrying the sub-circuit a61, and the performance requirement level of the sub-circuit a51 on the core board is higher than the performance requirement level of the sub-circuit a52 on the core board (similarly, the performance requirement level of the sub-circuit a61 on the core board is higher than the performance requirement level of the sub-circuit a62 on the core board). At this time, it is determined that the first pre-installed core board is reserved for two-thirds, and the second pre-installed core board is reserved for One third is left, among which, a part of the upper surface of the first pre-set core board after cutting is used to process sub-circuit a51 (occupying one-half of the upper surface of the first pre-set core board), a part is used to process a part of sub-circuit a52 (occupying one-sixth of the upper surface of the first pre-set core board), the upper surface of the second pre-set core board after cutting is used to process a part of sub-circuit a62, the lower surface of the first pre-set core board after cutting is used to process the entire sub-circuit a61, and the lower surface of the second pre-set core board after cutting is used to process the entire sub-circuit a62.

[0073] It should be noted here that in order to avoid the situation where the lines of the same sub-circuit are separated on different first core boards, when designing multiple circuit layers, for the sub-circuits distributed on both sides of the same core board, the areas occupied by the sub-circuits with the same performance requirements for the core board should be as close as possible, and the positions should be corresponding (the corresponding positions can mean that the sub-circuit distributed on the upper surface of the core board is exactly above the sub-circuit distributed on the upper surface of the core board). Therefore, after cutting the splicing contour, the sub-circuits carried by the upper and lower surfaces of the cut first core board are all sub-circuits with the same performance requirements for the core board, and the areas occupied are corresponding. It will not happen that one surface of the same first core board needs to carry sub-circuits with different performance requirements.

[0074] S130. Based on at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, a first substrate for carrying the top circuit layer and a second substrate for carrying the bottom circuit layer are stacked and pressed together to form a multilayer printed circuit board carrying multiple circuit layers.

[0075] In this embodiment, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer can be stacked and pressed in sequence in the vertical direction to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0076] Optionally, before stacking and laminating, the circuit on the top circuit layer can be processed on the upper surface of the first substrate; the circuit on the bottom circuit layer can be processed on the lower surface of the second substrate; then, at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, the first substrate carrying the circuit on the top circuit layer, and the second substrate carrying the circuit on the bottom circuit layer are stacked and pressed to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0077] For example, in some embodiments, before S130, the circuit on the top circuit layer can be processed on the upper surface of the first substrate; the circuit on the bottom circuit layer can be processed on the lower surface of the second substrate; accordingly, S130 includes: stacking and pressing at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, the first substrate carrying the circuit on the top circuit layer, and the second substrate carrying the circuit on the bottom circuit layer to obtain a fourth printed circuit board, and then connecting the different circuit layers in the fourth printed circuit board to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0078] For example, the first intermediate circuit layer is a layer, and the first intermediate circuit layer includes a sub-circuit s11 with a performance requirement level of s1 and a sub-circuit s22 with a performance requirement level of s2, and s11 is located on the left side of s22. Figure 8As shown, a matching first core board 202 is determined for the sub-circuit s11, and a matching first core board 203 is determined for the sub-circuit s22, and the sub-circuit s11 is processed on the first core board 202, and the sub-circuit s22 is processed on the first core board 203. At the same time, the top circuit layer circuit can be processed on the upper surface of the first substrate 204, and the bottom circuit layer circuit can be processed on the lower surface of the second substrate 201. Afterwards, the second substrate 201 is placed on the bottom layer, and the first core board 202 and the first core board 202 are superimposed on the second substrate (the first core board 202 is spliced ​​on the left side of the first core board 203), and then the first substrate 204 is superimposed on the first core board 202 and the first core board 202. Afterwards, the superimposed first substrate 204, the first core board 202, the first core board 202 and the second substrate 201 are pressed together to obtain a fourth printed circuit board.

[0079] The circuits between different circuit layers in the fourth printed circuit board are not connected. To connect the circuits between different circuit layers in the resulting multilayer printed circuit board, the different circuit layers in the fourth printed circuit board need to be connected. In this embodiment, vertical through-holes can be machined on the fourth printed circuit board, and then conductive material can be plated on the inner walls of the vertical through-holes to achieve connectivity between the different circuit layers in the fourth printed circuit board, thereby obtaining a multilayer printed circuit board carrying multiple circuit layers. It can be understood that the vertical through-holes machined on the fourth printed circuit board pass through at least one circuit on each circuit layer, thereby ensuring connectivity between the circuit layers.

[0080] It should be noted that in the aforementioned example, sub-circuits in a first intermediate circuit layer with the same core board performance requirement level are distributed on first core boards with different performance requirement levels. In this case, the sub-circuits distributed on different first core boards and with the same core board performance requirement level can be connected by the aforementioned means of connecting different circuit layers. For example, in the aforementioned example, a portion of sub-circuit a52 carried on the first pre-installed core board and another portion of sub-circuit a52 carried on the second pre-installed core board can be connected by the aforementioned means of connection (a portion of sub-circuit a52 is distributed on the first pre-installed core board, and another portion is distributed on the second pre-installed core board).

[0081] In this embodiment, based on the hierarchical order, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate carrying circuits on the top circuit layer, and a second substrate carrying circuits on the bottom circuit layer can be stacked and pressed together to obtain a fourth printed circuit board.

[0082] In some embodiments, at least two first core boards, a first substrate, and a second substrate processed with sub-circuits on the first intermediate circuit layer may be stacked and pressed together to obtain an intermediate printed circuit board; the circuit on the top circuit layer may be processed on the upper surface of the intermediate printed circuit board, and the circuit on the bottom circuit layer may be processed on the lower surface of the intermediate printed circuit board to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0083] It's worth noting that during the stacking process, at least two first core boards corresponding to the same first intermediate circuit layer are located on the same layer. Furthermore, after stacking and laminating the at least two first core boards with sub-circuits processed on the first intermediate circuit layer, the first substrate carrying the circuits on the top circuit layer, and the second substrate carrying the circuits on the bottom circuit layer, the circuits on the different circuit layers need to be connected to ensure electrical connectivity between them.

[0084] For example, in some embodiments, S130 may include: stacking and pressing at least two first core boards, a first substrate, and a second substrate on which sub-circuits on the first intermediate circuit layer have been processed to obtain a fifth printed circuit board; processing the circuit on the top circuit layer on the upper surface of the fifth printed circuit board, and processing the circuit on the bottom circuit layer on the lower surface of the fifth printed circuit board; then, connecting different circuit layers in the fifth printed circuit board to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0085] In this embodiment, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, the first substrate, and the second substrate may be stacked and pressed together based on the hierarchical order to obtain a fifth printed circuit board.

[0086] It is worth mentioning that if the upper surface of the first substrate used to support the top circuit layer has a conductive material, and the lower surface of the second substrate used to support the bottom circuit layer has a conductive material, then the aforementioned steps of "processing the circuit on the top circuit layer on the upper surface of the first substrate; processing the circuit on the bottom circuit layer on the lower surface of the second substrate" can be directly performed to realize the processing of the top circuit layer and the bottom circuit, or, step S130 can be executed to press together to obtain the fifth printed circuit board.

[0087] If the upper surface of the first substrate used to support the top circuit layer does not have a conductive material, and the lower surface of the second substrate used to support the bottom circuit layer does not have a conductive material, a conductive material can be plated on the upper surface of the first substrate used to support the top circuit layer, and a conductive material can be plated on the lower surface of the second substrate used to support the bottom circuit layer. Then, the aforementioned steps of "processing the circuit on the top circuit layer on the upper surface of the first substrate; processing the circuit on the bottom circuit layer on the lower surface of the second substrate" are performed to realize the processing of the top circuit layer and the bottom circuit. Alternatively, step S130 is performed to press together to obtain a fifth printed circuit board.

[0088] In some embodiments, when there are multiple first intermediate circuit layers, S130 may include: stacking and pressing at least two first core boards processed with sub-circuits on the first intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer in sequence in the vertical direction to obtain a multilayer printed circuit board carrying multiple circuit layers, wherein two adjacent layers of first core boards in the first printed circuit board are separated by a prepreg board. The two adjacent layers of first core boards are separated by the prepreg board to avoid direct contact between the circuits of the two adjacent layers of first core boards, which may cause a short circuit or incorrect current flow during the use of the multilayer printed circuit board. Among them, a layer of prepreg board can be placed between the two adjacent layers of first core boards.

[0089] As mentioned above, the hierarchical order can include the stacking relationship between each circuit layer. At this time, based on the hierarchical order, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer can be stacked and pressed in sequence in the vertical direction to obtain a multilayer printed circuit board.

[0090] In the present application, according to the performance requirement level of each sub-circuit on the first intermediate circuit layer among multiple circuit layers, a first core board is provided for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirement level. The first core board of each sub-circuit in the same first intermediate circuit layer is a core board that matches the performance requirement level of each sub-circuit to the core board, thereby realizing targeted selection of core boards according to the performance requirement level of the sub-circuit to the core board, instead of using the core board that carries the sub-circuit with the highest performance requirement level to the core board in the first intermediate circuit layer as the core board for carrying the first intermediate circuit layer. This avoids the problem of high cost of the multi-layer printed circuit board caused by using a core board with a higher performance requirement level to carry a circuit with a lower performance requirement level to the core board. As a result, the cost of the multi-layer printed circuit board is reduced by processing at least two first core boards on the sub-circuit on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer, thereby realizing the preparation of the multi-layer printed circuit board by regional lamination. Since the first core board provided for each sub-circuit can meet the corresponding performance requirements, the performance of the prepared multi-layer printed circuit board is guaranteed.

[0091] In some cases, when different sub-circuits with different performance requirements for the core board are located in different intermediate circuit layers, if the layout of the sub-circuits is simple, the different sub-circuits with different performance requirements for the core board can be aggregated into one intermediate circuit layer, thereby replacing the sub-circuits distributed in different intermediate circuit layers with the sub-circuits of one intermediate circuit layer, effectively reducing the number of layers of the intermediate circuit layer, thereby reducing the number of layers of the prepared multi-layer printed circuit board and reducing the production cost of the multi-layer printed circuit board.

[0092] In one embodiment, before S120, the method further includes: processing the splicing contours between different first core boards corresponding to the same first intermediate circuit layer and the edge contours of the different first core boards in the same first intermediate circuit layer. By processing the edge contours of the different first core boards in the same first intermediate circuit layer, it is ensured that the different first core boards in the same first intermediate circuit layer can be matched based on the edge contours, so that the dimensions of the processed first core boards corresponding to the same first intermediate circuit layer after splicing are the same as the dimensions of the formed multi-layer printed circuit board.

[0093] After processing the splicing outline of the first core board, the sub-circuits to be carried can be processed on the surface of each first core board according to the circuit layout. After processing the splicing outline of the first core board, the sub-circuits to be carried can be processed on the surface of the first core board. This facilitates positioning during the processing of the sub-circuits and avoids the possibility that the sub-circuits processed earlier may be close to the edge of the first core board, resulting in the sub-circuits being cut off during the subsequent processing of the splicing outline.

[0094] See also Figure 9 , Figure 9 A flowchart of a method for preparing a multilayer printed circuit board according to another embodiment of the present application is shown. In this embodiment, the middle circuit layer among the plurality of circuit layers further includes a second middle circuit layer. The method may include:

[0095] S210. According to the performance requirement level of each sub-circuit on the first intermediate circuit layer among the multiple circuit layers for the core board, provide a first core board for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirement level; process the surface of each first core board corresponding to the sub-circuit to be carried.

[0096] The description of S210 refers to the description of S110 to S120 above and will not be repeated here.

[0097] S220. According to the performance requirement level of the circuits on the second intermediate circuit layer for the core board, provide a second core board for carrying the circuits on the second intermediate circuit layer and matching the corresponding performance requirement level; and process the circuits on the second intermediate circuit layer on the surface of the second core board.

[0098] In this embodiment, the multiple circuit layers also include a second intermediate circuit layer, and the different sub-circuits on the second intermediate circuit layer have the same performance requirement level for the core board; based on the performance requirement level of the circuits on the second intermediate circuit layer to the core board, a preset core board for carrying the circuits on the second intermediate circuit layer and matching the corresponding performance requirement level can be determined as the second core board, and then the circuits on the second intermediate circuit layer are processed on the surface of the second core board.

[0099] Based on the description of the aforementioned embodiment, it can be seen that both sides of the core board can be used to carry circuits. Therefore, the same second core board needs to carry the circuits of two second intermediate circuit layers, and the performance requirement levels for the core board also involve at most two. Therefore, a pre-installed core board that matches the higher of the two performance requirement levels can be obtained as the second core board. For example, the performance requirement level of the second intermediate circuit layer a9 for the core board is the first signal transmission rate requirement level, and the performance requirement level of the second intermediate circuit layer 109 for the core board is the second signal transmission rate requirement level. In this case, a first pre-installed core board that matches the first signal transmission rate requirement level is obtained as the second core board for carrying the second intermediate circuit layer a9 and the second intermediate circuit layer a10.

[0100] S230. At least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are stacked and pressed in sequence to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0101] Among them, in a multi-layer printed circuit board, two adjacent core boards are separated by a prepreg board, thereby avoiding direct contact between the circuits of the two adjacent core boards, which may cause short circuits or incorrect current flow during the use of the multi-layer printed circuit board.

[0102] In this embodiment, the hierarchical sequence includes the stacking relationship between each circuit layer. Based on the hierarchical sequence, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer can be directly stacked. Then, the stacked result is pressed to obtain a pressed printed circuit board as a multilayer printed circuit board carrying multiple circuit layers.

[0103] In some embodiments, before S230, the circuit on the top circuit layer can be processed on the upper surface of the first substrate; the circuit on the bottom circuit layer can be processed on the lower surface of the second substrate; accordingly, S240 includes: stacking and pressing at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, a second core board on which the circuits on the second intermediate circuit layer are processed, at least one prepreg board, a first substrate carrying the circuits on the top circuit layer, and a second substrate carrying the circuits on the bottom circuit layer to obtain a sixth printed circuit board, and then connecting the different circuit layers in the sixth printed circuit board to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0104] In this embodiment, based on the hierarchical order, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate carrying circuits on the top circuit layer, and a second substrate carrying circuits on the bottom circuit layer can be stacked and pressed together to obtain a sixth printed circuit board. Then, the different circuit layers in the sixth printed circuit board are connected to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0105] In other embodiments, S230 may include: stacking and pressing at least two first core boards on which sub-circuits on the first intermediate circuit layer are processed, a second core board on which circuits on the second intermediate circuit layer are processed, at least one prepreg board, a first substrate, and a second substrate to obtain a seventh printed circuit board; processing the circuit on the top circuit layer on the upper surface of the seventh printed circuit board, and processing the circuit on the bottom circuit layer on the lower surface of the seventh printed circuit board; then, connecting different circuit layers in the seventh printed circuit board to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0106] In this embodiment, based on the hierarchical order, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate and a second substrate can be stacked and pressed together to obtain a seventh printed circuit board.

[0107] In this embodiment, the multilayer printed circuit board also includes a second intermediate circuit layer, and the core boards of the two adjacent layers are separated by a prepreg board, thereby preventing direct contact between the circuits of the two adjacent core boards, which could lead to short circuits or incorrect current flow during use of the multilayer printed circuit board, thereby improving the success rate of preparing the multilayer printed circuit board. At the same time, in this embodiment, the core boards are selected specifically for sub-circuits with different performance requirements of the core boards, rather than using the core board that carries the sub-circuits with the highest performance requirements in the first intermediate circuit layer as the core board for each sub-circuit of the first intermediate circuit layer. This avoids the waste of core boards with higher performance requirements when using core boards with higher matching performance requirements as core boards for sub-circuits with lower performance requirements. As a result, the cost of the multilayer printed circuit board formed by processing at least two first core boards for the sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer is low, effectively reducing resource waste.

[0108] See also Figure 10 , Figure 10 A flowchart of a method for preparing a multilayer printed circuit board according to another embodiment of the present application is shown. The method may include:

[0109] S310 , according to the performance requirement level of each sub-circuit on the first intermediate circuit layer among the multiple circuit layers for the core board, provide a first core board for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirement level.

[0110] S320 , processing the sub-circuits to be carried on the surface of each first core board.

[0111] The description of S310-S320 refers to the description of S110-S120 above and will not be repeated here.

[0112] S330, stack and press together in sequence in the vertical direction at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer to obtain a first printed circuit board.

[0113] In this embodiment, based on the hierarchical order, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer can be stacked and pressed in sequence in the vertical direction to obtain a first printed circuit board.

[0114] Optionally, S330 may include: stacking and pressing at least two first core boards processed with sub-circuits on the first intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer in sequence in the vertical direction to obtain a first printed circuit board, in which two adjacent layers of first core boards in the first printed circuit board are separated by the prepreg board.

[0115] Based on the foregoing content, it can be known that the lines of the same first intermediate circuit layer are carried by at least two first core boards, and different first core boards located on the same layer constitute a core board layer. Conductive materials are attached to both sides of at least two first core boards constituting a core board layer, that is, the core board layer can carry the lines of two first intermediate circuit layers. When there are more lines in the first intermediate circuit layer, there are also multiple core board layers used to carry the first intermediate circuit layer, and the two adjacent core board layers are separated by the prepreg board. At this time, the two adjacent first core boards are also separated by the prepreg board.

[0116] In some embodiments, S330 may include: splicing at least two first core boards processed with sub-circuits on the first intermediate circuit layer to obtain a spliced ​​core board corresponding to the first intermediate circuit layer; stacking and pressing the spliced ​​core board corresponding to the first intermediate circuit layer, the first substrate for carrying the top circuit layer, and the second substrate for carrying the bottom circuit layer in sequence in the vertical direction to obtain a first printed circuit board.

[0117] The circuits of the same first intermediate circuit layer are carried by at least two first core boards, and the first core boards used to carry the circuits of the same first intermediate circuit layer are spliced ​​to obtain a spliced ​​core board. Then, based on the hierarchical order, the spliced ​​core board corresponding to the first intermediate circuit layer, the first substrate used to carry the top circuit layer, and the second substrate used to carry the bottom circuit layer are stacked and pressed in sequence in the vertical direction to obtain a first printed circuit board.

[0118] In this embodiment, an insulating adhesive may be applied to the splicing contours of the first core boards, and the first core boards of the same first intermediate circuit layer may be spliced ​​together using the insulating adhesive at the splicing contours to obtain a spliced ​​core board.

[0119] S340: Processing a vertical through hole on the first printed circuit board; plating a conductive material on the inner wall of the vertical through hole to obtain a second printed circuit board.

[0120] After obtaining the first printed circuit board, vertical through-holes can be machined on the first printed circuit board, and conductive material can be plated on the inner walls of the vertical through-holes so that the through-holes plated with conductive material can connect circuits between different circuit layers, thereby obtaining a second printed circuit board. The vertical through-holes machined on the first printed circuit board can be one or more, and the multiple vertical through-holes can be separated.

[0121] In this embodiment, a conductive material is applied to the upper surface of the first substrate and the lower surface of the second substrate in a second printed circuit board, and the conductive material is plated on the inner walls of the vertical through-holes to obtain the second printed circuit board. This includes: plating the conductive material on the surface of the first printed circuit board and the inner walls of the vertical through-holes to obtain the second printed circuit board. Plating the conductive material on the surface of the first printed circuit board results in the conductive material being applied to the upper surface of the first substrate and the lower surface of the second substrate in the obtained second printed circuit board.

[0122] In the above embodiment, the first substrate and the second substrate can also be prepreg boards. Since there is no conductive material on the surface of the prepreg board, conductive material is plated before processing the circuits on the top circuit layer and the circuits on the bottom circuit layer. The conductive material can be plated once to ensure that the upper surface of the first substrate, the lower surface of the second substrate, and the inner wall of the vertical through hole are all plated with conductive material, without the need for multiple conductive material platings, thereby shortening the preparation process of the multi-layer printed circuit board.

[0123] It is worth mentioning that if conductive material is attached to the upper surface of the first substrate and the lower surface of the second substrate in the first printed circuit board, the conductive material may not be plated on the surface of the first printed circuit board to save costs. Alternatively, the conductive material may be plated on the surface of the first printed circuit board so that the conductive material attached to the upper surface of the first substrate and the lower surface of the second substrate of the obtained second printed circuit board is more uniform.

[0124] S350, processing the circuits on the top circuit layer on the upper surface of the first substrate in the second printed circuit board, and processing the circuits on the bottom circuit layer on the lower surface of the second substrate in the second printed circuit board to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0125] After obtaining the second printed circuit board, the circuits on the top circuit layer can be directly processed on the upper surface of the first substrate in the second printed circuit board, and the circuits on the bottom circuit layer can be processed on the lower surface of the second substrate in the second printed circuit board, so that the second printed circuit board carries the circuits of the top circuit layer and the circuits of the bottom circuit layer, and a multilayer printed circuit board carrying multiple circuit layers is obtained.

[0126] In this embodiment, targeted selection of core boards for sub-circuits with different performance requirement levels of the core boards is achieved, and the core board that carries the sub-circuit with the highest performance requirement level for the core board in the first intermediate circuit layer is no longer used as the core board for carrying each sub-circuit of the first intermediate circuit layer. This avoids the waste of core boards with higher performance requirement levels when using core boards with higher matching performance requirement levels as core boards for carrying sub-circuits with lower performance requirement levels. As a result, the cost of the multi-layer printed circuit board formed by processing at least two first core boards for the sub-circuits on the first intermediate circuit layer, the first substrate for carrying the top circuit layer, and the second substrate for carrying the bottom circuit layer is low, effectively reducing waste of resources.

[0127] See also Figure 11 , Figure 11 A flowchart of a method for preparing a multilayer printed circuit board according to another embodiment of the present application is shown. The method may include:

[0128] S410. According to the performance requirement level of each sub-circuit on the first intermediate circuit layer among the multiple circuit layers for the core board, provide a first core board for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirement level; and process the surface of each first core board corresponding to the sub-circuit to be carried.

[0129] The description of S410 refers to the description of S110 to S120 above and will not be repeated here.

[0130] S420. According to the performance requirement level of the circuits on the second intermediate circuit layer for the core board, provide a second core board for carrying the circuits on the second intermediate circuit layer and matching the corresponding performance requirement level; and process the circuits on the second intermediate circuit layer on the surface of the second core board.

[0131] The description of S420 refers to the description of S230 above and will not be repeated here.

[0132] S430: At least two first core substrates processed with sub-circuits on the first intermediate circuit layer, a second core substrate processed with circuits on the second intermediate circuit layer, at least one prepreg, a first substrate for supporting the top circuit layer, and a second substrate for supporting the bottom circuit layer are sequentially stacked and pressed together to form a first printed circuit board. In the first printed circuit board, adjacent core substrates are separated by the prepreg.

[0133] In this embodiment, the hierarchical sequence includes the stacking relationship between each circuit layer. Based on the hierarchical sequence, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate, and a second substrate can be directly stacked, and then the stacked results are pressed to obtain a first printed circuit board.

[0134] In some embodiments, before S430, the method may further include: processing positioning holes that cooperate with the positioning posts on the positioning device on at least two first core boards, the first substrate, the second substrate, the second core board, and the prepreg board respectively; correspondingly, S430 may include: according to the hierarchical order of multiple circuit layers, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are sequentially stacked on the positioning device and pressed together to obtain a first printed circuit board, and the positioning holes cooperate with the positioning posts on the positioning device.

[0135] The positioning device may refer to a positioning fixture having a positioning column. Figure 12 As shown, the positioning device 12 includes a positioning column 121 .

[0136] Based on the positioning columns of the positioning device, positioning holes that match the positioning columns on the positioning device can be processed on at least two first core plates, the first substrate, the second substrate, the second core plate, and the prepreg plate. For example, the positioning device can be used as a Figure 12 Take the positioning fixture shown in the figure as an example to process the positioning holes on the prepreg board. Figure 12 As shown, positioning holes 123 matching the positioning posts 121 are processed on the prepreg plate 122 .

[0137] The positioning hole cooperates with the positioning post on the positioning device. Figure 12 As shown, the positioning column 121 of the positioning device 12 matches the positioning hole 123 on the prepreg plate 122. Figure 12 The dashed lines in the figure represent matching locating posts and holes—the locating posts connected by the same dashed line pass through the locating holes connected by the dashed line, thereby achieving the desired fit between the locating posts and the locating holes. It should be understood that the positions of the locating holes correspond to the positions of the locating posts on the locating device, ensuring that the locating holes and locating posts fit together during the stacking process.

[0138] S440. Processing a vertical through hole on the first printed circuit board; plating a conductive material on the inner wall of the vertical through hole to obtain a second printed circuit board; processing the circuit on the top circuit layer on the upper surface of the first substrate in the second printed circuit board, and processing the circuit on the bottom circuit layer on the lower surface of the second substrate in the second printed circuit board to obtain a multilayer printed circuit board carrying multiple circuit layers.

[0139] The description of S440 refers to the description of S340-S350 above and will not be repeated here.

[0140] In some embodiments, the positioning holes are distributed along an edge of the multilayer printed circuit board; after S440 , the method may further include: cutting out the positioning holes in the multilayer printed circuit board.

[0141] Positioning holes are distributed along the edge of the multilayer printed circuit board. Since no circuits exist at the locations where the positioning holes are located, the positioning holes can be cut out. This removes the positioning holes and the space occupied by the unused positioning holes in the multilayer printed circuit board, thereby reducing the size of the multilayer printed circuit board and improving the space utilization of the multilayer printed circuit board. In a specific embodiment, the positioning holes in the multilayer printed circuit board can be removed by wire cutting.

[0142] In this embodiment, the coordination of the positioning holes and the positioning posts enables precise stacking of the substrates and core boards, improving the accuracy and efficiency of stacking the substrates and core boards, thereby improving the accuracy and efficiency of the resulting multilayer printed circuit board. Simultaneously, the positioning holes are removed, eliminating the space occupied by unused positioning holes in the multilayer printed circuit board, thereby reducing the size of the multilayer printed circuit board and improving its space utilization.

[0143] For ease of understanding, the preparation method of the multilayer printed circuit of the present application will be explained below with reference to an example. Figure 13 shown.

[0144] S510: Design multiple circuit layers based on the layout of the components to be connected by the multiple circuit layers. At this point, the hierarchical order of the multiple circuit layers, the layout relationship between the sub-circuits in the same intermediate circuit layer, and the circuit layout of each sub-circuit can also be determined.

[0145] In this example, the hierarchical order is top circuit layer e5, second intermediate circuit layer e1, second intermediate circuit layer e2, first intermediate circuit layer e3, first intermediate circuit layer e4 and bottom circuit layer e6 stacked in sequence from top to bottom; the layout relationship is: the first intermediate circuit layer e3 includes a sub-circuit e31 with a performance requirement level of the core board being a first signal transmission rate requirement level and a sub-circuit e32 with a performance requirement level of the core board being a second signal transmission rate requirement level (sub-circuit e31 is on the left side of sub-circuit e32), the first intermediate circuit layer e4 includes a performance requirement level of the core board being a first signal transmission rate requirement level The sub-circuit e41 has a first signal transmission rate requirement level, and the sub-circuit e42 has a second signal transmission rate requirement level for the core board (the sub-circuit e41 is on the left side of the sub-circuit e42). The second intermediate circuit layer e1 includes sub-circuits with a second signal transmission rate requirement level for the core board, and the second intermediate circuit layer e2 includes sub-circuits with a second signal transmission rate requirement level for the core board. In addition, the area occupied by the sub-circuit e31 is the same as that of the sub-circuit e41, and the area occupied by the sub-circuit e32 is the same as that of the sub-circuit e42.

[0146] S520: Determine a first core board that matches the performance level required of each sub-circuit for the core board.

[0147] Specifically, a pre-built core board that matches the first signal transmission rate requirement level is determined as the first core board f1 (the upper surface of the first core board f1 is used to carry the sub-circuit e31, and the lower surface of the first core board f1 is used to carry the sub-circuit e41), a pre-built core board that matches the second signal transmission rate requirement level is determined as the first core board f2 (the upper surface of the first core board f2 is used to carry the sub-circuit e32, and the lower surface of the first core board f2 is used to carry the sub-circuit e42), and a pre-built core board that matches the second signal transmission rate requirement level is determined as the second core board f3 (used to carry the second intermediate circuit layer e1 and the circuits on the second intermediate circuit layer e2).

[0148] S530 , processing the splicing contours between different first core boards corresponding to the same first intermediate circuit layer, processing the positioning holes of each core board, the positioning holes of the prepreg board, and processing the circuits to be carried on each core board.

[0149] For example, the first core plate f1 and the first core plate f2 are spliced ​​together according to the first intermediate circuit layer e3 and the first intermediate circuit layer e4, and positioning holes are punched in the processed first core plate f1 and the first core plate f2. Figure 14 As shown, the first core plate f1 has a positioning hole f11 , and the first core plate f2 has a positioning hole f21 .

[0150] After the above processing is completed, each core board can be processed to carry the circuit. Figure 14 After the first core board f1 and the first core board f2 in the figure are processed with the corresponding circuits, the first core board f1 and the first core board f2 carrying the circuits are as follows: Figure 15 As shown. The upper surface of the first core plate f1 carries sub-circuit e31, and the upper surface of the first core plate f2 carries sub-circuit e32. The lower surface of the first core plate f1 carries sub-circuit e41, and the lower surface of the first core plate f2 carries sub-circuit e42 (wherein, the circuits carried by the lower surfaces of the first core plate f1 and the first core plate f2 are not shown).

[0151] S540: stack and press the two first core boards, the second core board, and the prepreg board to obtain a first printed circuit board.

[0152] After completing the processing of the core board and the prepreg board according to the above-mentioned step S530, the first substrate, the second substrate, the two first core boards, the second core board and the prepreg board are stacked and pressed together by a positioning fixture to obtain a first printed circuit board.

[0153] In this embodiment, a prepreg board can be used as the first substrate and a prepreg board can be used as the second substrate. Of course, prepreg boards for separating different layers of core boards are also provided.

[0154] like Figure 16 As shown, the second substrate f5 is placed on the positioning fixture 100, and the positioning column 1101 of the positioning fixture 100 passes through the positioning hole f51 of the second substrate f5; the first core board f1 and the first core board f2 are superimposed on the second substrate f5, and the positioning column 1101 of the positioning fixture 100 passes through the positioning hole f11 of the first core board f1 and the positioning hole f21 of the first core board f2; the prepreg board f6 is superimposed on the first core board f1 and the first core board f2, and the positioning column 1101 of the positioning fixture 100 passes through the positioning hole f61 of the prepreg board f6; the second core board f3 is superimposed on the prepreg board f6, and the positioning column 1101 of the positioning fixture 100 passes through the positioning hole f31 of the second core board f3; finally, the first substrate f4 is superimposed on the second core board f3, and the positioning column 1101 of the positioning fixture 100 passes through the positioning hole f41 of the first substrate f4 to obtain the superposition result. The superposition result is shown as follows. Figure 17 As shown, the positioning posts connected by the dotted lines pass through the positioning holes connected by the dotted lines to achieve the matching between the positioning holes and the positioning posts. The stacked result is then pressed together to obtain the first printed circuit board.

[0155] S550 , drilling holes in the first printed circuit board and plating a conductive material to obtain a second printed circuit board.

[0156] After obtaining the first printed circuit board, vertical through holes can be drilled in the first printed circuit board, and copper can be plated on the surface of the first printed circuit board and the inner wall of the through holes to achieve surface processable circuits on the first printed circuit board and conduction between different circuit layers.

[0157] S560: Processing surface circuits on the second printed circuit board to obtain a multilayer printed circuit board.

[0158] After obtaining the second printed circuit board according to the above process, the top circuit layer circuit is processed on the upper surface of the second printed circuit board, and the bottom circuit layer circuit is processed on the lower surface of the first printed circuit board to obtain a multilayer printed circuit board. The obtained multilayer printed circuit board is as follows: Figure 18 shown.

[0159] S570, cutting out the positioning holes of the multilayer printed circuit board.

[0160] like Figure 18 As shown, the positioning holes are distributed at the edge of the multilayer printed circuit board. The positioning holes can be cut off to obtain the multilayer printed circuit board after the positioning holes are cut off. The multilayer printed circuit board after the positioning holes are cut off is as shown in FIG. Figure 19 shown.

[0161] like Figure 19 The cross-sectional view of the multilayer printed circuit board shown in FIG. Figure 20 As shown, the surface of the first substrate f4 in a multilayer printed circuit board (PCB) carries the circuits of the top circuit layer e5. The layer below the first substrate f5 includes a second core board f3. The upper surface of the second core board f3 carries the circuits of the circuit layer e1, and the lower surface of the second core board f3 carries the circuits of the circuit layer e2. The layer below the second core board f3 is a prepreg board f6. The layer below the prepreg board f6 includes two first core boards, namely the first core board f1 and the first core board f2. The upper surface of the first core board f1 carries sub-circuit e31, and the lower surface of the first core board f1 carries sub-circuit e41. The upper surface of the first core board f2 carries sub-circuit e32, and the lower surface of the first core board f2 carries sub-circuit e42. The layer below the first core boards f1 and f2 is the second substrate f5. The lower surface of the second substrate f5 carries the circuits of the bottom circuit layer e6. The multilayer printed circuit board also includes a through hole h1 with a conductive material plated on the inner wall, which is used to conduct electricity between the circuits of different circuit layers.

[0162] As another aspect, an embodiment of the present application further provides a multilayer printed circuit board, which is prepared by the method of any of the aforementioned embodiments.

[0163] The present application also provides an electronic device including the multilayer printed circuit board prepared in the above embodiment. The electronic device may be a smartphone, tablet computer, laptop computer, desktop computer, intelligent voice interaction device, smart home appliance, vehicle-mounted terminal, aircraft, etc. The electronic device may also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms, but is not limited thereto.

[0164] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. Among them, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, and the above-mentioned module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0165] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in this application. It should be understood that this application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of this application is limited only by the appended claims.

[0166] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a multilayer printed circuit board, characterized in that: The method comprises: providing, based on performance requirements of the core board for each sub-circuit on a first intermediate circuit layer among the multiple circuit layers, a first core board for carrying each sub-circuit in the first intermediate circuit layer and matching the corresponding performance requirements, wherein the first intermediate circuit layer is an intermediate circuit layer among the multiple circuit layers that includes at least two sub-circuits having different performance requirements for the core board; the multiple circuit layers further include at least a top circuit layer and a bottom circuit layer; Processing the sub-circuits to be carried on the surface of each of the first core boards; Based on at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer and a second substrate for carrying the bottom circuit layer are stacked and pressed together to form a multilayer printed circuit board carrying the multiple circuit layers.

2. The method according to claim 1, characterized in that The at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are stacked and pressed together to form a multilayer printed circuit board carrying the multiple circuit layers, including: At least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are stacked and pressed in sequence in a vertical direction to obtain a first printed circuit board; Processing vertical through holes on the first printed circuit board; Plating a conductive material on the inner wall of the vertical through hole to obtain a second printed circuit board; The circuits on the top circuit layer are processed on the upper surface of the first substrate in the second printed circuit board, and the circuits on the bottom circuit layer are processed on the lower surface of the second substrate in the second printed circuit board to obtain a multilayer printed circuit board carrying the multiple circuit layers.

3. The method according to claim 2, characterized in that Conductive material is attached to the upper surface of the first substrate and the lower surface of the second substrate in the second printed circuit board; Plating a conductive material on the inner wall of the vertical through hole to obtain a second printed circuit board comprises: Conductive material is plated on the surface of the first printed circuit board and the inner wall of the vertical through hole to obtain a second printed circuit board.

4. The method according to claim 2, characterized in that There are multiple first intermediate circuit layers; at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are sequentially stacked and pressed in a vertical direction to obtain a first printed circuit board, including: At least two first core boards processed with sub-circuits on the first intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are stacked and pressed in sequence in the vertical direction to obtain a first printed circuit board, in which two adjacent layers of first core boards are separated by the prepreg board.

5. The method according to claim 2, characterized in that The multiple circuit layers further include a second intermediate circuit layer, and different sub-circuits on the second intermediate circuit layer have the same performance requirements for the core board; Before obtaining the first printed circuit board, the method further comprises: stacking and pressing the at least two first core boards processed with the sub-circuits on the first intermediate circuit layer, the first substrate for carrying the top circuit layer, and the second substrate for carrying the bottom circuit layer in sequence in a vertical direction. According to the performance requirement level of the circuits on the second intermediate circuit layer for the core board, providing a second core board for carrying the circuits on the second intermediate circuit layer and matching the corresponding performance requirement level; Processing the circuit on the second intermediate circuit layer on the surface of the second core board; At least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are sequentially stacked and pressed in a vertical direction to obtain a first printed circuit board, comprising: At least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are stacked and pressed in sequence to obtain a first printed circuit board, in which two adjacent core boards in the first printed circuit board are separated by the prepreg board.

6. The method according to claim 5, characterized in that Before obtaining the first printed circuit board, the method further comprises: sequentially stacking and pressing at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer to obtain the first printed circuit board; Positioning holes that match the positioning columns on the positioning device are respectively processed on the at least two first core plates, the first substrate, the second substrate, the second core plate, and the prepreg plate; The first printed circuit board is obtained by sequentially stacking and pressing at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer, comprising: According to the hierarchical order of the multiple circuit layers, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a second core board processed with circuits on the second intermediate circuit layer, at least one prepreg board, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are sequentially stacked on the positioning device and pressed together to obtain a first printed circuit board, and the positioning holes cooperate with the positioning columns on the positioning device.

7. The method according to claim 6, characterized in that The positioning holes are distributed along the edge of the multilayer printed circuit board; After processing the circuits on the top circuit layer on the upper surface of the first substrate in the second printed circuit board, and processing the circuits on the bottom circuit layer on the lower surface of the second substrate in the second printed circuit board to obtain a multilayer printed circuit board carrying the multiple circuit layers, the method further includes: The positioning holes in the multilayer printed circuit board are cut out.

8. The method according to claim 2, characterized in that At least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are sequentially stacked and pressed in a vertical direction to obtain a first printed circuit board, comprising: splicing at least two first core boards processed with sub-circuits on the first intermediate circuit layer to obtain a spliced ​​core board corresponding to the first intermediate circuit layer; The spliced ​​core board corresponding to the first intermediate circuit layer, the first substrate for carrying the top circuit layer, and the second substrate for carrying the bottom circuit layer are stacked and pressed in sequence in a vertical direction to obtain a first printed circuit board.

9. The method according to claim 2, characterized in that The conductive material is copper.

10. The method according to claim 1, characterized in that Before processing the surface of each of the first core boards corresponding to the sub-circuits to be carried, the method further includes: Process the splicing contours between different first core boards corresponding to the same first intermediate circuit layer.

11. The method according to claim 1, characterized in that Before stacking and laminating at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer to form a multilayer printed circuit board carrying the multiple circuit layers, the method further includes: Processing the circuit on the top circuit layer on the upper surface of the first substrate; Processing the circuit on the bottom circuit layer on the lower surface of the second substrate; The at least two first core boards on which the sub-circuits on the first intermediate circuit layer are processed, a first substrate for carrying the top circuit layer, and a second substrate for carrying the bottom circuit layer are stacked and pressed together to form a multilayer printed circuit board carrying the multiple circuit layers, including: According to the hierarchical order of the multiple circuit layers, at least two first core boards processed with sub-circuits on the first intermediate circuit layer, a first substrate carrying circuits on the top circuit layer, and a second substrate carrying circuits on the bottom circuit layer are stacked and pressed together to obtain a fourth printed circuit board; Different circuit layers in the fourth printed circuit board are connected to obtain a multilayer printed circuit board carrying the multiple circuit layers.

12. The method according to any one of claims 1 to 11, characterized in that If the sub-circuit is a circuit for transmitting signals with a frequency exceeding a first frequency threshold, the performance requirement level of the sub-circuit for the core board is a first signal transmission rate requirement level; if the sub-circuit is a circuit for transmitting signals with a frequency not exceeding the first frequency threshold, the performance requirement level of the sub-circuit for the core board is a second signal transmission rate requirement level, and the signal transmission rate required by the second signal transmission rate requirement level is lower than the signal transmission rate required by the first signal transmission rate requirement level; If the sub-circuit is a circuit for passing a current exceeding the current threshold, the performance requirement level of the sub-circuit for the core board is the first current requirement level; if the sub-circuit is a circuit for passing a current not exceeding the current threshold, the performance requirement level of the sub-circuit for the core board is the second current requirement level, and the current value required by the first current requirement level is greater than the current value required by the second current requirement level.

13. A multilayer printed circuit board, characterized in that: The multilayer printed circuit board is manufactured according to the method according to any one of claims 1 to 12.

14. An electronic device, characterized in that: Comprising the multilayer printed circuit board as claimed in claim 13.

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