Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The method and the device are used for solving the technical problem of how to improve the poor uniformity of a plurality of gaps formed by transverse etching. The manufacturing method comprises the following steps: forming a laminated structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers which are alternately stacked on a substrate; the plurality of sacrificial layers comprise a plurality of first sacrificial layers and a plurality of second sacrificial layers, and the distance between any second sacrificial layer and the substrate is greater than the distance between any first sacrificial layer and the substrate; the thickness of any second sacrificial layer in the vertical direction is greater than that of any first sacrificial layer in the vertical direction; forming a groove which extends along the first horizontal direction and penetrates through the laminated structure; transversely etching each sacrificial layer through the groove so as to form a gap between two adjacent semiconductor layers; and the widths of any two gaps in the second horizontal direction are the same. Therefore, accurate side digging of the sacrificial layer in the upper and lower laminated layers can be realized, and the width uniformity of each formed gap is further improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Each memory cell in a dynamic random access memory (DRAM) typically consists of a transistor and a capacitor. The transistor's gate is coupled to a word line (also known as a word line structure), one of the transistor's source and drain is coupled to a bit line (also known as a bit line structure), and the other of the transistor's source and drain is coupled to a capacitor (also known as a capacitor structure or capacitor).

[0003] With the continuous advancement of semiconductor technology, DRAM is moving towards a three-dimensional structure with higher integration and smaller size. DRAM with a three-dimensional architecture is commonly referred to as three-dimensional DRAM (3D DRAM). Currently, 3D DRAM still needs further improvement. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers stacked alternately; wherein the plurality of sacrificial layers comprise a plurality of first sacrificial layers and a plurality of second sacrificial layers, the distance between any one of the second sacrificial layers and the substrate being greater than the distance between any one of the first sacrificial layers and the substrate; the thickness of any one of the second sacrificial layers in a vertical direction being greater than the thickness of any one of the first sacrificial layers in the vertical direction, the vertical direction being perpendicular to the main surface of the substrate; forming a groove extending along a first horizontal direction and passing through the stacked structure, the first horizontal direction being parallel to the main surface of the substrate; laterally etching each of the sacrificial layers through the groove to form a gap between two adjacent semiconductor layers; wherein the width of any two of the gaps in the second horizontal direction is the same, the second horizontal direction being parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

[0005] In some embodiments, the manufacturing method further includes: thinning each of the semiconductor layers through the gap to form a plurality of semiconductor patterns spaced apart along the vertical direction; based on the plurality of semiconductor patterns, forming a plurality of transistors stacked along the vertical direction; wherein the plurality of transistors include a plurality of first transistors and a plurality of second transistors, and the distance between any one of the second transistors and the substrate is greater than the distance between any one of the first transistors and the substrate; the spacing between the semiconductor patterns of any two adjacent second transistors in the vertical direction is greater than the spacing between the semiconductor patterns of any two adjacent first transistors in the vertical direction.

[0006] In some embodiments, any two of the plurality of second sacrificial layers have the same thickness in the vertical direction.

[0007] In some embodiments, along a direction away from the substrate, the thickness gradient of the plurality of second sacrificial layers in the vertical direction increases.

[0008] In some embodiments, the material of each of the semiconductor layers includes silicon, and the material of each of the sacrificial layers includes silicon germanium; wherein the germanium content of any of the second sacrificial layers is greater than the germanium content of any of the first sacrificial layers.

[0009] According to a second aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate and a plurality of transistors stacked on the substrate in a vertical direction; wherein the plurality of transistors include a plurality of first transistors and a plurality of second transistors, and the distance between any one of the second transistors and the substrate is greater than the distance between any one of the first transistors and the substrate; each of the transistors includes a semiconductor pattern extending in a horizontal direction, and the spacing between the semiconductor patterns of any two adjacent second transistors in the vertical direction is greater than the spacing between the semiconductor patterns of any two adjacent first transistors in the vertical direction, the vertical direction is perpendicular to the main surface of the substrate, and the horizontal direction is parallel to the main surface of the substrate.

[0010] In some embodiments, the semiconductor patterns of any two transistors have the same width in the horizontal direction.

[0011] In some embodiments, the semiconductor patterns of any two adjacent second transistors in the plurality of second transistors have the same spacing in the vertical direction.

[0012] In some embodiments, along a direction away from the substrate, a pitch gradient of the semiconductor patterns of every two adjacent second transistors in the plurality of second transistors increases in the vertical direction.

[0013] In some embodiments, the semiconductor structure further includes: a plurality of stacked capacitors, the plurality of capacitors including a plurality of first capacitors and a plurality of second capacitors, the first lower electrodes of the first capacitors being connected to the first transistor, and the second lower electrodes of the second capacitors being connected to the second transistor; wherein the spacing between any two adjacent second lower electrodes is greater than the spacing between any two adjacent first lower electrodes.

[0014] According to a third aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers stacked alternately; wherein the plurality of sacrificial layers comprise a plurality of first sacrificial layers and a plurality of second sacrificial layers, the distance between any one of the second sacrificial layers and the substrate being greater than the distance between any one of the first sacrificial layers and the substrate; the material of each of the sacrificial layers comprises silicon germanium, the germanium content of any one of the second sacrificial layers being greater than the germanium content of any one of the first sacrificial layers; forming a groove extending along a first horizontal direction and passing through the stacked structure, the first horizontal direction being parallel to the main surface of the substrate; laterally etching each of the sacrificial layers through the groove to form a gap between two adjacent semiconductor layers; wherein the width of any two of the gaps in the second horizontal direction is the same, the second horizontal direction being parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

[0015] In some embodiments, any two of the plurality of second sacrificial layers have the same germanium content.

[0016] In some embodiments, the germanium content of the plurality of second sacrificial layers increases gradually in a direction away from the substrate.

[0017] In the disclosed embodiments, because the thickness of any second sacrificial layer is greater than the thickness of any first sacrificial layer, or the germanium content of any second sacrificial layer is greater than the germanium content of any first sacrificial layer, the amount of lateral etching of each sacrificial layer can be better controlled, thereby resolving the issue of slow side etching of the sacrificial layer (i.e., the second sacrificial layer) in the upper stack during the lateral etching process, resulting in each gap having the same width. This allows for precise side etching of the sacrificial layers in both the upper and lower stacks, thereby improving the uniformity of the width of each gap formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0019] Figure 1 It is a schematic diagram showing how the warpage of the wafer changes with the number of stacked layers; Figure 2 Schematic diagram of the warpage of wafers corresponding to silicon germanium layers with different germanium compositions; Figure 3 This is a cross-sectional view of the wafer after lateral etching corresponding to the silicon germanium layer with different germanium compositions; Figure 4 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 5 is a partial cross-sectional view after a groove is formed according to an embodiment of the present disclosure; Figure 6 is a partial cross-sectional view after a gap is formed according to an embodiment of the present disclosure; Figure 7 is a partial cross-sectional view after a semiconductor pattern is formed according to an embodiment of the present disclosure; Figure 8 is a partial cross-sectional view of a transistor after formation provided by an embodiment of the present disclosure; Figure 9 is a partial cross-sectional view after forming a bit line according to an embodiment of the present disclosure; Figure 10 is a partial cross-sectional view of a capacitor after formation provided by an embodiment of the present disclosure; Figure 11 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 12 is a flow chart of another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 13 is a partial cross-sectional view after a groove is formed according to another embodiment of the present disclosure; Figure 14 is a schematic diagram showing that the etching rate of silicon germanium varies with the germanium content, provided by an embodiment of the present disclosure; Figure 15 This is a schematic diagram showing how the etching rate of silicon germanium varies with the thickness of the silicon germanium layer, provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0021] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0022] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0023] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0024] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0025] Before introducing the embodiments of the present disclosure, we first define the various directions that may be involved below. The direction perpendicular to the main surface of the substrate is defined as the vertical direction (denoted as the Z direction in the accompanying drawings). A first horizontal direction (denoted as the X direction in the accompanying drawings) and a second horizontal direction (denoted as the Y direction in the accompanying drawings) that are perpendicular to each other are defined in a plane parallel to the main surface of the substrate. Specifically, the X and Y directions are perpendicular and parallel to the main surface of the substrate, and the Z direction is perpendicular to the main surface of the substrate.

[0026] Conventional processes typically build 3D DRAM structures based on periodic superlattice growth of silicon (Si) / silicon germanium (SiGe) layers. Specifically, the lengths of the capacitors and transistors in the memory cells can be precisely defined by laterally etching the SiGe layer.

[0027] Figure 1 This is a schematic diagram showing how the warpage of a wafer changes with the number of stacked layers. Figure 1 As shown in Figure 1, as the number of Si / SiGe layers increases, the wafer warpage increases, even exceeding the limits of existing memory devices. To reduce wafer warpage, the Ge component (also known as the Ge content) in the SiGe layer can be reduced.

[0028] Figure 2 Schematic diagram of the warpage of wafers corresponding to silicon germanium layers with different germanium compositions. Figure 2 As the Ge content in Figures (a), (b), and (c) increases, for example, at 15%, 20%, and 25%, the corresponding wafer warpage increases. This means that reducing the Ge content in the SiGe layer can reduce wafer warpage. However, reducing the Ge content in the SiGe layer also leads to poor lateral etching uniformity (also known as undercutting).

[0029] Figure 3 This is a cross-sectional view of the wafer after lateral etching corresponding to the silicon germanium layer with different germanium components. Figure 3 As shown in Figure 2, lateral etching can form a gap between two adjacent Si layers. Figure 3 The Ge content of the SiGe layer in (b) (e.g., 15%) is less than Figure 3 The Ge composition of the SiGe layer in (a) (e.g., 25%) leads to Figure 3 In Figure (b), the uniformity of the upper SiGe layer after lateral etching is significantly deteriorated. For example, the uniformity of the width of each gap deteriorates, which will affect the uniformity of the subsequently formed capacitors and transistors, and further affect the uniformity of each memory cell.

[0030] Based on one or more of the above technical problems, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.

[0031] Figure 4 This is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Figure 4 As shown, the production method comprises at least the following steps: Step S110: providing a substrate; Step S120: forming a stacked structure on a substrate, the stacked structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers alternately stacked; wherein the plurality of sacrificial layers comprise a plurality of first sacrificial layers and a plurality of second sacrificial layers, the distance between any second sacrificial layer and the substrate being greater than the distance between any first sacrificial layer and the substrate; and the thickness of any second sacrificial layer in a vertical direction being greater than the thickness of any first sacrificial layer in the vertical direction, the vertical direction being perpendicular to the main surface of the substrate; Step S130: forming a trench extending along a first horizontal direction and penetrating the stacked structure, wherein the first horizontal direction is parallel to the main surface of the substrate; Step S140: Laterally etching each sacrificial layer through the trench to form a gap between two adjacent semiconductor layers; wherein any two gaps have the same width in a second horizontal direction, and the second horizontal direction is parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

[0032] Figures 5 to 10 This is a schematic diagram of a semiconductor structure manufacturing process provided by an embodiment of the present disclosure. Figure 4 、 Figures 5 to 10 The method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is exemplarily described.

[0033] In step S110, refer to Figure 5 As shown, a substrate 202 is provided. The substrate 202 has a front surface and a back surface opposite to each other along the Z direction. Figure 5 The stacked structure 204 may be formed on the front side of the substrate 202. In some embodiments, the main surface of the substrate 202 may be the front side of the substrate 202.

[0034] The material of the substrate 202 may include a single-element semiconductor material (e.g., silicon (Si) or germanium (Ge)), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art.

[0035] In step S120, refer to Figure 5As shown, a stacked structure 204 is formed on a substrate 202, and the stacked structure 204 includes a plurality of sacrificial layers and a plurality of semiconductor layers 206 that are alternately stacked; wherein the plurality of sacrificial layers include a plurality of first sacrificial layers 208 and a plurality of second sacrificial layers 210, and the distance between any second sacrificial layer 210 and the substrate 202 is greater than the distance between any first sacrificial layer 208 and the substrate 202; the thickness of any second sacrificial layer 210 in the Z direction is greater than the thickness of any first sacrificial layer 208 in the Z direction, and the Z direction is perpendicular to the main surface of the substrate 202.

[0036] The formation process of the sacrificial layer and the semiconductor layer 206 includes, but is not limited to, an epitaxial growth process, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0037] Each semiconductor layer 206 is made of silicon, and each sacrificial layer is made of silicon germanium. For example, silicon germanium can be epitaxially grown on a single crystal silicon surface. Silicon germanium can be selectively and directionally grown on the single crystal silicon surface, resulting in a simple and controllable process. Of course, other semiconductor materials can be used for the semiconductor layer 206, and other sacrificial materials that have an etch selectivity ratio with the semiconductor layer 206 can be used for the sacrificial layer. This disclosure does not specifically limit this.

[0038] The stacked structure 204 may include a lower stack 204A and an upper stack 204B. The multiple sacrificial layers in the lower stack 204A may be referred to as first sacrificial layers 208, and the multiple sacrificial layers in the upper stack 204B may be referred to as second sacrificial layers 210. Because the lower stack 204A is located between the substrate 202 and the upper stack 204B, the distance between any second sacrificial layer 210 and the substrate 202 is greater than the distance between any first sacrificial layer 208 and the substrate 202.

[0039] In some embodiments, the thickness of any sacrificial layer in the upper stack 204B is greater than the thickness of any sacrificial layer in the lower stack 204A, that is, the thickness of any second sacrificial layer 210 is greater than the thickness of any first sacrificial layer 208 . Figure 5 The thickness of the second sacrificial layer 210 is H2, and the thickness of the first sacrificial layer 208 is H1, where H2>H1. In practical applications, the thickness of each sacrificial layer can be controlled by controlling the process parameters for forming each sacrificial layer. For example, the thickness of the SiGe layer can be controlled by controlling the epitaxial growth time on the single crystal silicon surface.

[0040] In some embodiments, any two second sacrificial layers 210 among the multiple second sacrificial layers 210 have the same thickness in the Z direction, that is, the thickness of each second sacrificial layer 210 in the upper stack 204B is the same, and the thickness of each second sacrificial layer 210 is greater than the thickness of any first sacrificial layer 208.

[0041] In some other embodiments, the thickness of the plurality of second sacrificial layers 210 increases gradually in the Z direction in a direction away from the substrate 202. Here, the thickness of the plurality of second sacrificial layers 210 may increase in the same or different gradient increments.

[0042] As an example, the thicknesses of the plurality of second sacrificial layers 210 increase sequentially in a direction away from the substrate 202 , and the thickness of the bottommost second sacrificial layer 210 in the upper stack 204B is greater than the thickness of any first sacrificial layer 208 .

[0043] As another example, the thicknesses of the plurality of second sacrificial layer groups increase sequentially in a direction away from the substrate 202 , the thickness of each second sacrificial layer 210 in the second sacrificial layer group is the same, and the second sacrificial layer group may include at least two second sacrificial layers 210 .

[0044] In the above two embodiments, the thicknesses of the plurality of second sacrificial layers 210 vary regularly. However, in other examples, the thicknesses of the plurality of second sacrificial layers 210 may vary irregularly, as long as the thickness of any second sacrificial layer 210 is greater than the thickness of any first sacrificial layer 208. This disclosure does not impose any particular limitation on this.

[0045] It should be noted that in this embodiment, there is no limit on the number of sacrificial layers and semiconductor layers 206. In practical applications, they can be reasonably set according to needs. In this embodiment and below, the thickness refers to the size of a structure or film layer in the Z direction, and will not be repeated hereafter.

[0046] In some embodiments, any two first sacrificial layers 208 in the plurality of first sacrificial layers 208 have the same thickness in the Z direction, that is, each first sacrificial layer 208 in the lower stack 204A has the same thickness. Of course, in other embodiments, any two first sacrificial layers 208 in the lower stack 204A may have different thicknesses.

[0047] In some embodiments, any two semiconductor layers 206 in the plurality of semiconductor layers 206 have the same thickness in the Z direction, that is, the thickness of each semiconductor layer 206 in the upper stack 204B and the lower stack 204A is the same.

[0048] In some embodiments, the germanium content of any sacrificial layer in the upper stack 204B is greater than the germanium content of any sacrificial layer in the lower stack 204A. That is, the germanium content of any second sacrificial layer 210 is greater than the germanium content of any first sacrificial layer 208. In practical applications, the germanium content of each sacrificial layer can be controlled by controlling the process parameters for forming each sacrificial layer. For example, the germanium content of the SiGe layer can be controlled by controlling the flow rate of the germanium source gas used for epitaxial growth on the surface of single crystal silicon. The germanium source gas can include GeH4 gas, Ge solid, or other Ge-containing reaction sources.

[0049] In step S130, refer to Figure 5 As shown, a trench 214 is formed extending along the X direction and penetrating the stacked structure 204 , where the X direction is parallel to the main surface of the substrate 202 .

[0050] The process for forming the groove 214 includes, but is not limited to, a dry etching process. For example, a patterned mask layer 212 is formed on the stacked structure 204; the stacked structure 204 is etched downward using a dry etching process until the substrate 202 is exposed, thereby forming a groove 214 that penetrates the stacked structure 204. The groove 214 can extend along the X direction. Of course, the substrate 202 can be further etched downward so that the bottom of the groove 214 extends into the substrate 202, as shown in FIG. Figure 5 shown.

[0051] In step S140, refer to Figure 5 and Figure 6 As shown, each sacrificial layer is laterally etched through the trench 214 to form a gap 216 between two adjacent semiconductor layers 206; wherein any two gaps 216 have the same width in the Y direction, which is parallel to the main surface of the substrate 202 and perpendicular to the X direction.

[0052] The process for forming the gap 216 includes, but is not limited to, a wet etching process. For example, a wet etching process is used to selectively etch each first sacrificial layer 208 and each second sacrificial layer 210 exposed by the trench 214, thereby forming a gap 216 at each location where the first sacrificial layer 208 and the second sacrificial layer 210 are removed. The plurality of gaps 216 may be arranged at intervals along the Z direction, and each gap 216 has a width W.

[0053] In some embodiments, the plurality of gaps 216 include a plurality of first gaps and a plurality of second gaps. The first gaps are formed between two adjacent semiconductor layers 206 of the lower stack 204A, and the second gaps are formed between two adjacent semiconductor layers 206 of the upper stack 204B. The size of the second gaps in the Z direction is larger than the size of the first gaps in the Z direction. In this embodiment, the first gaps are formed at locations where the first sacrificial layer 208 is removed, and the second gaps are formed at locations where the second sacrificial layer 210 is removed.

[0054] In some embodiments, the lateral etching rate of the second sacrificial layer 210 is the same as the lateral etching rate of the first sacrificial layer 208. In this way, the lateral etching amount of the second sacrificial layer 210 and the lateral etching amount of the first sacrificial layer 208 can be made the same.

[0055] In the disclosed embodiment, because the thickness of any second sacrificial layer 210 is greater than the thickness of any first sacrificial layer 208, the amount of lateral etching of each sacrificial layer can be better controlled, thereby resolving the issue of slow side etching of the sacrificial layer (i.e., second sacrificial layer 210) in the upper stack 204B during the lateral etching process, resulting in each gap 216 having the same width. This allows for precise side etching of the sacrificial layers in the upper and lower stacks 204A, thereby improving the uniformity of the width of each gap 216 formed.

[0056] In some embodiments, reference Figure 6 and Figure 7 As shown, the manufacturing method further includes: thinning each semiconductor layer 206 through the gap 216 to form a plurality of semiconductor patterns 218 arranged at intervals along the Z direction.

[0057] The process of thinning the semiconductor layer 206 may include but is not limited to a dry etching process. The structure after thinning the semiconductor layer 206 is as follows: Figure 7 As shown, the semiconductor layer 206 is thinned to form a semiconductor pattern 218 , and the thickness of the semiconductor pattern 218 is less than the thickness of the semiconductor layer 206 .

[0058] Thinning the semiconductor layer 206 can increase the size of the gap 216 in the Z direction. It should be noted that part of the word line will be formed in the gap 216. By thinning the semiconductor layer 206, the space for forming the word line can be increased, which is conducive to reducing the coupling between adjacent word lines.

[0059] In some embodiments, reference Figure 7 As shown, the semiconductor pattern 218 may include a first portion, a second portion, and a third portion arranged sequentially along the Y direction, with the first portion contacting the unthinned semiconductor layer 206. The thickness of the semiconductor pattern 218 in the Z direction gradually decreases from the first portion toward the third portion. The first portion may be either a source or a drain, the second portion may be a channel, and the third portion may be the other of the source or the drain.

[0060] In some embodiments, reference Figure 7 and Figure 8As shown, the above-mentioned manufacturing method also includes: forming a plurality of transistors stacked along the Z direction based on a plurality of semiconductor patterns 218; wherein the plurality of transistors include a plurality of first transistors Tr1 and a plurality of second transistors Tr2, and the distance between any second transistor Tr2 and the substrate 202 is greater than the distance between any first transistor Tr1 and the substrate 202; the spacing between the semiconductor patterns 218 of any two adjacent second transistors Tr2 in the Z direction is greater than the spacing between the semiconductor patterns 218 of any two adjacent first transistors Tr1 in the Z direction.

[0061] In this embodiment, a first transistor Tr1 can be formed based on the semiconductor pattern 218 exposed by the enlarged first gap. The distance between the semiconductor patterns 218 of two adjacent first transistors Tr1 in the Z direction is the enlarged first gap. A second transistor Tr2 can be formed based on the semiconductor pattern 218 exposed by the enlarged second gap. The distance between the semiconductor patterns 218 of two adjacent second transistors Tr2 in the Z direction is the enlarged second gap. Because the size of the enlarged second gap in the Z direction is larger than the size of the enlarged first gap in the Z direction, the distance between the semiconductor patterns 218 of any two adjacent second transistors Tr2 in the Z direction is larger than the distance between the semiconductor patterns 218 of any two adjacent first transistors Tr1 in the Z direction.

[0062] It should be noted that the distance between two adjacent semiconductor patterns 218 may be the distance between the top surface of the lower semiconductor pattern 218 and the bottom surface of the upper semiconductor pattern 218 .

[0063] In some embodiments, reference Figure 7 and Figure 8 As shown, the above-mentioned process of forming multiple transistors stacked along the Z direction based on multiple semiconductor patterns 218 includes: forming a first dielectric layer 220 on the sacrificial layer exposed by the gap 216, the first dielectric layer 220 covering a first portion of the semiconductor pattern 218; forming an initial word line structure on the first dielectric layer 220, the initial word line structure covering a second portion of the semiconductor pattern 218; forming an initial second dielectric layer on the initial word line structure, the initial second dielectric layer covering a third portion of the semiconductor pattern 218; etching the initial second dielectric layer and the initial word line structure to form a word line isolation trench; and filling the word line isolation trench with an isolation material to form a word line isolation structure.

[0064] The formation processes for the first dielectric layer 220, the initial wordline structure, and the initial second dielectric layer include, but are not limited to, CVD, PVD, ALD, or any combination thereof. The material for the first dielectric layer 220 includes, but is not limited to, silicon nitride, and the material for the initial second dielectric layer includes, but is not limited to, silicon oxide. The wordline isolation trench formation process includes, but is not limited to, a dry etching process.

[0065] The wordline isolation structure can separate the initial wordline structure into two wordline structures 222 and the initial second dielectric layer into two second dielectric layers 224. Each wordline structure 222 can include a gate dielectric layer and a gate structure, with the gate dielectric layer located between the channel and the gate structure. Multiple gate structures arranged along the X direction are coupled to each other to form a wordline, and the gate structure and wordline can refer to the same structure. Portions of the wordline located on the channel sidewalls can serve as gate structures in transistors. In other words, multiple transistors arranged along the X direction can be coupled to the same wordline, while multiple transistors arranged along the Z direction can be coupled to different wordlines.

[0066] It should be noted that transistors can be classified as single-gate, dual-gate, or gate-all-around (GAA) transistors, depending on how much of the channel sidewalls the gate structure covers. In practical applications, the transistor type can be appropriately set based on requirements.

[0067] In some embodiments, reference Figure 8 and Figure 9 As shown, the manufacturing method further includes: forming a bit line 228 in the trench 214, the bit line 228 connecting a plurality of transistors arranged along the Z direction, for example, the bit line connects the third portion.

[0068] It should be noted that the multiple transistors arranged along the Z direction are coupled to the same bit line 228, and the multiple transistors arranged along the X direction are coupled to different bit lines 228. Figure 9 FIG. 2 shows that transistors located on opposite sides of the trench 214 along the Y direction are connected to different bit lines 228. Figure 10 The figure shows a bitline isolation structure 238 that physically isolates two bitlines 228 arranged along the Y direction in the trench 214. However, in other embodiments, transistors located on opposite sides of the trench 214 along the Y direction may share a bitline 228 (i.e., be connected to the same bitline 228). The material of the bitline isolation structure 238 includes, but is not limited to, silicon oxide.

[0069] In some embodiments, reference Figure 9 and Figure 10As shown, the above-mentioned manufacturing method further includes: removing the remaining semiconductor layer to form a cavity; and sequentially forming a lower electrode 230, a capacitor dielectric layer 232, and an upper electrode 234 in the cavity; wherein the lower electrode 230 is connected to the first portion of the transistor. The lower electrode 230, the capacitor dielectric layer 232, and the upper electrode 234 can form a capacitor.

[0070] The capacitor formation process may include: forming a capacitor hole extending through the stacked structure 204; removing the remaining semiconductor layer through the capacitor hole to form a cavity connected to the capacitor hole, wherein the cavity exposes the first portion of the transistor; forming a lower electrode 230 that conformally covers the capacitor hole and the cavity; forming a capacitor dielectric layer 232 that conformally covers the lower electrode 230; and forming an upper electrode 234 that conformally covers the capacitor dielectric layer 232. It should be noted that the upper electrodes 234 of multiple capacitors may be connected within the capacitor hole to form a common terminal.

[0071] In some embodiments, reference Figure 10 As shown, the above manufacturing method further includes: removing a portion of the sacrificial layer, and forming an insulating layer 236 at the position where the portion of the sacrificial layer is removed. The material of the insulating layer 236 includes but is not limited to silicon oxide.

[0072] Based on the above-mentioned method for manufacturing a semiconductor structure, an embodiment of the present disclosure provides a semiconductor structure, which can be formed using the manufacturing method of any of the above-mentioned embodiments.

[0073] Figure 11 FIG2 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. The semiconductor structure includes but is not limited to 3D DRAM.

[0074] Reference Figure 11 As shown, the semiconductor structure 300 includes: a substrate 302 and a plurality of transistors stacked along the Z direction on the substrate 302; wherein the plurality of transistors include a plurality of first transistors Tr1 and a plurality of second transistors Tr2, and the distance between any second transistor Tr2 and the substrate 302 is greater than the distance between any first transistor Tr1 and the substrate 302; each transistor includes a semiconductor pattern 318 extending along the Y direction, and the spacing in the Z direction between the semiconductor patterns 318 of any two adjacent second transistors Tr2 is greater than the spacing in the Z direction between the semiconductor patterns 318 of any two adjacent first transistors Tr1, the Z direction is perpendicular to the main surface of the substrate 302, and the Y direction is parallel to the main surface of the substrate 302. For more information about the substrate 302, the first transistor Tr1, the second transistor Tr2, and the semiconductor pattern 318, please refer to Figures 5 to 10 The descriptions of the middle substrate 202 , the first transistor Tr1 , the second transistor Tr2 , and the semiconductor pattern 218 are not repeated here.

[0075] In some embodiments, the widths of the semiconductor patterns 318 of any two transistors in the Y direction are the same.

[0076] In this embodiment, due to the lateral etching Figure 6 The width of each gap 216 is the same, so the width of the semiconductor layer exposed by each gap 216 is also the same. After thinning the semiconductor layer, Figure 7 The widths of the semiconductor patterns 218 formed in the transistor are also the same, that is, the widths of the semiconductor patterns of any two transistors in the Y direction are the same.

[0077] In some embodiments, the intervals between the semiconductor patterns 318 of any two adjacent second transistors Tr2 in the plurality of second transistors Tr2 in the Z direction are the same.

[0078] In this embodiment, Figure 5 If any two second sacrificial layers 210 have the same thickness in the Z direction, the second gaps formed by lateral etching will also have the same size in the Z direction. If any two semiconductor layers 206 have the same thickness in the Z direction, the enlarged second gaps formed by thinning the semiconductor layers will also have the same size in the Z direction. Therefore, the distance between the semiconductor patterns 318 of any two adjacent second transistors Tr2 in the Z direction is the same. Here, the enlarged second gap refers to the distance between the semiconductor patterns 318 of any two adjacent second transistors Tr2 in the Z direction.

[0079] In some other embodiments, along a direction away from the substrate 302 , a pitch gradient between every two adjacent second transistors Tr2 in the plurality of second transistors Tr2 increases in the Z direction.

[0080] In this embodiment, Figure 5 When the thickness of the plurality of second sacrificial layers 210 in the Z direction increases gradually away from the substrate 202, the size of each second gap formed by lateral etching also increases gradually away from the substrate 202. When the thickness of any two semiconductor layers 206 in the Z direction is the same, the size of each enlarged second gap formed by thinning the semiconductor layers also increases gradually away from the substrate 202. Therefore, the spacing between the semiconductor patterns 318 of each adjacent pair of second transistors Tr2 in the Z direction increases gradually away from the substrate 302.

[0081] In some embodiments, the semiconductor structure 300 further includes a first dielectric layer 320, and the first dielectric layer 320 covers the first portion of the semiconductor pattern 318. For details about the first dielectric layer 320, please refer to Figure 8 The description of the first dielectric layer 220 is omitted here.

[0082] In some embodiments, the semiconductor structure 300 further includes a word line structure 322, and the word line structure 322 covers the second portion of the semiconductor pattern 318. Figure 8 The description of the middle wordline structure 222 will not be repeated here.

[0083] In some embodiments, the semiconductor structure 300 further includes a second dielectric layer 324, and the second dielectric layer 324 covers the third portion of the semiconductor pattern 318. Figure 8 The description of the second dielectric layer 224 is omitted here.

[0084] In some embodiments, the semiconductor structure 300 further includes a word line isolation structure 326, which is located between two adjacent word line structures 322 and two adjacent second dielectric layers 324. Figure 8 The description of the middle wordline isolation structure 226 is omitted here.

[0085] In some embodiments, the semiconductor structure 300 further includes a bit line 328, which extends along the Z direction and connects a plurality of transistors arranged along the Z direction. Figure 9 The description of the median line 228 is omitted here.

[0086] In some embodiments, the semiconductor structure 300 further includes a plurality of stacked capacitors, each of which includes a lower electrode 330, a capacitor dielectric layer 332, and an upper electrode 334. The lower electrode 330, the capacitor dielectric layer 332, and the upper electrode 334 can be referred to in detail. Figure 10 The description of the lower middle electrode 230 , the capacitor dielectric layer 232 and the upper electrode 234 will not be repeated here.

[0087] In some embodiments, the multiple capacitors include multiple first capacitors Cap1 and multiple second capacitors Cap2, the first lower electrode of the first capacitor Cap1 is connected to the first transistor Tr1, and the second lower electrode of the second capacitor Cap2 is connected to the second transistor Tr2; wherein, the spacing between any two adjacent second lower electrodes is greater than the spacing between any two adjacent first lower electrodes.

[0088] In this embodiment, the distance between any two adjacent second lower electrodes is the thickness of the second sacrificial layer 210, and the distance between any two adjacent first lower electrodes is the thickness of the first sacrificial layer 208. Since the thickness of any second sacrificial layer 210 is greater than the thickness of any first sacrificial layer 208, the distance between any two adjacent second lower electrodes is greater than the distance between any two adjacent first lower electrodes.

[0089] In some embodiments, the semiconductor structure 300 further includes an insulating layer 336, which is located between two adjacent lower electrodes 330. Figure 10 The description of the middle insulating layer 236 is omitted here.

[0090] Based on the above technical problems, the embodiments of the present disclosure further provide another method for manufacturing a semiconductor structure.

[0091] Figure 12 is a flow chart of another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, Figure 13 This is a partial cross-sectional view after forming a groove according to another embodiment of the present disclosure, referring to Figure 12 As shown, the manufacturing method at least includes steps S410 to S440.

[0092] In step S410, refer to Figure 12 and Figure 13 As shown, a substrate 402 is provided. For step S410, reference may be made to the relevant description of step S110, which will not be repeated here.

[0093] In step S420, refer to Figure 12 and Figure 13 As shown, a stacked structure 404 is formed on a substrate 402, and the stacked structure 404 includes a plurality of sacrificial layers and a plurality of semiconductor layers 406 stacked alternately; wherein the plurality of sacrificial layers include a plurality of first sacrificial layers 408 and a plurality of second sacrificial layers 410, and the distance between any second sacrificial layer 410 and the substrate 402 is greater than the distance between any first sacrificial layer 408 and the substrate 402; the material of each sacrificial layer includes silicon germanium, and the germanium content of any second sacrificial layer 410 is greater than the germanium content of any first sacrificial layer 408.

[0094] The stacked structure 404 may include a lower stack 404A and an upper stack 404B. The multiple sacrificial layers in the lower stack 404A may be referred to as first sacrificial layers 408, and the multiple sacrificial layers in the upper stack 404B may be referred to as second sacrificial layers 410. Because the lower stack 404A is located between the substrate 402 and the upper stack 404B, the distance between any second sacrificial layer 410 and the substrate 402 is greater than the distance between any first sacrificial layer 408 and the substrate 402.

[0095] In some embodiments, the germanium content of any sacrificial layer in the upper stack 404B is greater than the germanium content of any sacrificial layer in the lower stack 404A, that is, the germanium content of any second sacrificial layer 410 is greater than the germanium content of any first sacrificial layer 408 .

[0096] In practical applications, the germanium content of each sacrificial layer can be controlled by controlling the process parameters for forming each sacrificial layer. For example, the germanium content of the SiGe layer can be controlled by controlling the flow rate of the germanium source gas used for epitaxial growth on the surface of single-crystal silicon. The germanium source gas can include GeH4 gas, solid Ge, or other Ge-containing reaction sources.

[0097] In some embodiments, the germanium content of any two second sacrificial layers 410 among the multiple second sacrificial layers 410 is the same, that is, the germanium content of each second sacrificial layer 410 in the upper stack 404B is the same, and the germanium content of each second sacrificial layer 410 is greater than the germanium content of any first sacrificial layer 408.

[0098] In some embodiments, the germanium content of the plurality of second sacrificial layers 410 increases in a gradient along a direction away from the substrate 402. Here, the germanium content of the plurality of second sacrificial layers 410 may increase in the same or different gradient increments.

[0099] As an example, the germanium contents of the plurality of second sacrificial layers 410 increase sequentially in a direction away from the substrate 402 , and the germanium content of the bottom second sacrificial layer 410 in the upper stack 404B is greater than the germanium content of any first sacrificial layer 408 .

[0100] As another example, the germanium content of the plurality of second sacrificial layer groups increases sequentially in a direction away from the substrate 402 , the germanium content of each second sacrificial layer 410 in the second sacrificial layer group is the same, and the second sacrificial layer group may include at least two second sacrificial layers 410 .

[0101] In the two aforementioned embodiments, the germanium content of the plurality of second sacrificial layers 410 varies regularly. However, in other examples, the germanium content of the plurality of second sacrificial layers 410 may vary irregularly, as long as the germanium content of any second sacrificial layer 410 is greater than the germanium content of any first sacrificial layer 408. This disclosure does not impose any particular limitation on this.

[0102] It should be noted that the number of sacrificial layers and semiconductor layers 406 is not limited in this embodiment. In practical applications, they can be reasonably set according to needs. The germanium content in this embodiment and below refers to the atomic percentage of germanium in the silicon germanium layer, and will not be further described.

[0103] In some embodiments, the germanium content of any two first sacrificial layers 408 in the plurality of first sacrificial layers 408 is the same, that is, the germanium content of each first sacrificial layer 408 in the lower stack 404A is the same. Of course, in other embodiments, the germanium content of any two first sacrificial layers 408 in the lower stack 404A may be different.

[0104] In some embodiments, the thickness of any sacrificial layer in the upper stack 404B is the same as the thickness of any sacrificial layer in the lower stack 404A, that is, the thickness of any second sacrificial layer 410 is the same as the thickness of any first sacrificial layer 408, that is, the thickness of each sacrificial layer is the same.

[0105] In some embodiments, any two semiconductor layers 406 in the plurality of semiconductor layers 406 have the same thickness in the Z direction, that is, the thickness of each semiconductor layer 406 in the upper stack 404B and the lower stack 404A is the same.

[0106] In step S430, refer to Figure 12 and Figure 13 As shown, a trench 414 is formed extending along a first horizontal direction and penetrating the stacked structure 404, wherein the first horizontal direction is parallel to the main surface of the substrate 402. For step S430, reference may be made to the description of step S130, which will not be repeated here.

[0107] In step S440, refer to Figure 12 and Figure 13 As shown, each sacrificial layer is laterally etched through trenches 414 to form a gap between two adjacent semiconductor layers 406. Any two gaps have the same width in a second horizontal direction, which is parallel to the main surface of substrate 402 and perpendicular to the first horizontal direction. For step S440, reference can be made to the description of step S140 and will not be repeated here.

[0108] In some embodiments, the plurality of gaps include a plurality of first gaps and a plurality of second gaps, the first gaps being formed between two adjacent semiconductor layers 406 of the lower stack 404A, the second gaps being formed between two adjacent semiconductor layers 406 of the upper stack 404B, and the size of the second gaps in the Z direction being equal to the size of the first gaps in the Z direction.

[0109] In this embodiment, the first gap is formed at the location where the first sacrificial layer 408 is removed, and the second gap is formed at the location where the second sacrificial layer 410 is removed. Since the second sacrificial layer 410 and the first sacrificial layer 408 have the same thickness, the size of the second gap in the Z direction is also the same as the size of the first gap in the Z direction.

[0110] In some embodiments, the lateral etching rate of the second sacrificial layer 410 is the same as the lateral etching rate of the first sacrificial layer 408. In this way, the lateral etching amount of the second sacrificial layer 410 and the lateral etching amount of the first sacrificial layer 408 can be made the same.

[0111] In the disclosed embodiment, because the germanium content of any second sacrificial layer 410 is greater than the germanium content of any first sacrificial layer 408, the lateral etching amount of each sacrificial layer can be better controlled, thereby resolving the issue of slow side etching of the sacrificial layer (i.e., second sacrificial layer 410) in the upper stack 404B during the lateral etching process, resulting in each gap having the same width. This, firstly, allows for precise side etching of the sacrificial layers in the upper and lower stacks 404A, thereby improving the width uniformity of each gap formed. Secondly, the reduced germanium content in some silicon-germanium layers can alleviate wafer warpage, thereby facilitating reduction of wafer warpage.

[0112] In some embodiments, the manufacturing method further includes: thinning each semiconductor layer 406 through the gaps to form a plurality of semiconductor patterns spaced apart along the Z direction.

[0113] In some embodiments, the above-mentioned manufacturing method further includes: forming a plurality of transistors stacked along the Z direction based on a plurality of semiconductor patterns; wherein the plurality of transistors include a plurality of first transistors and a plurality of second transistors, the distance between any second transistor and the substrate 402 is greater than the distance between any first transistor and the substrate 402; the spacing between the semiconductor patterns of any two adjacent second transistors in the Z direction is equal to the spacing between the semiconductor patterns of any two adjacent first transistors in the Z direction. For the formation process of the transistor, please refer to Figure 10 The relevant description will not be repeated here.

[0114] In some embodiments, the manufacturing method further includes: forming a bit line in the trench 414 , wherein the bit line connects a plurality of transistors arranged along the Z direction.

[0115] In some embodiments, the above-mentioned manufacturing method further includes: removing the remaining semiconductor layer 406 to form a cavity; forming a lower electrode, a capacitor dielectric layer, and an upper electrode in the cavity in sequence; wherein the lower electrode is connected to the first part of the transistor. The lower electrode, the capacitor dielectric layer, and the upper electrode can form a capacitor. For the formation process of the capacitor, please refer to Figure 10 The relevant description will not be repeated here.

[0116] In some embodiments, the above-mentioned manufacturing method further comprises: removing a portion of the sacrificial layer, and forming an insulating layer at the position where the portion of the sacrificial layer is removed. Figure 10 The description of the middle insulating layer 236 is omitted here.

[0117] Figure 14 Schematic diagram showing the change of silicon germanium etching rate with the change of germanium content provided by the embodiment of the present disclosure. Figure 14As shown in the figure, as the germanium content in the silicon germanium layer increases, the silicon germanium etching rate also increases. Therefore, by controlling the germanium content of the silicon germanium layers in the upper and lower stacks, for example, by increasing the germanium content of each sacrificial layer in the upper stack, that is, the germanium content of any second sacrificial layer is greater than the germanium content of any first sacrificial layer, the lateral etching amount of the silicon germanium layers in the upper and lower stacks can be controlled to remain consistent during the lateral etching process, thereby ensuring the uniformity of the multiple gaps formed.

[0118] Figure 15 Schematic diagram showing how the etching rate of silicon germanium varies with the thickness of the silicon germanium layer, provided by an embodiment of the present disclosure. Figure 15 As shown in the figure, as the thickness of the silicon germanium layer increases, the silicon germanium etching rate also increases. Therefore, by controlling the thickness of the silicon germanium layers in the upper and lower stacks, for example, by increasing the thickness of each sacrificial layer in the upper stack, that is, by making the thickness of any second sacrificial layer greater than the thickness of any first sacrificial layer, the lateral etching amount of the silicon germanium layers in the upper and lower stacks can be controlled to remain consistent during the lateral etching process, thereby ensuring the uniformity of the multiple gaps formed.

[0119] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0120] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0121] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0122] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0123] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers alternately stacked; wherein the plurality of sacrificial layers comprise a plurality of first sacrificial layers and a plurality of second sacrificial layers, the distance between any one of the second sacrificial layers and the substrate being greater than the distance between any one of the first sacrificial layers and the substrate; and the thickness of any one of the second sacrificial layers in a vertical direction being greater than the thickness of any one of the first sacrificial layers in the vertical direction, the vertical direction being perpendicular to the main surface of the substrate; forming a groove extending along a first horizontal direction and penetrating the stacked structure, wherein the first horizontal direction is parallel to the main surface of the substrate; Each sacrificial layer is laterally etched through the groove to form a gap between two adjacent semiconductor layers; wherein any two of the gaps have the same width in a second horizontal direction, and the second horizontal direction is parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The production method further comprises: thinning each of the semiconductor layers through the gap to form a plurality of semiconductor patterns spaced apart along the vertical direction; Based on the multiple semiconductor patterns, multiple transistors stacked along the vertical direction are formed; wherein the multiple transistors include multiple first transistors and multiple second transistors, and the distance between any one of the second transistors and the substrate is greater than the distance between any one of the first transistors and the substrate; the spacing between the semiconductor patterns of any two adjacent second transistors in the vertical direction is greater than the spacing between the semiconductor patterns of any two adjacent first transistors in the vertical direction.

3. The method for manufacturing a semiconductor structure according to claim 1 or 2, wherein: Any two of the plurality of second sacrificial layers have the same thickness in the vertical direction.

4. The method for manufacturing a semiconductor structure according to claim 1 or 2, wherein: Along a direction away from the substrate, the thickness gradient of the plurality of second sacrificial layers in the vertical direction increases.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of each semiconductor layer includes silicon, and the material of each sacrificial layer includes silicon germanium; wherein the germanium content of any one of the second sacrificial layers is greater than the germanium content of any one of the first sacrificial layers.

6. A semiconductor structure, characterized in that include: substrate; A plurality of transistors are stacked in a vertical direction on the substrate; wherein the plurality of transistors include a plurality of first transistors and a plurality of second transistors, and the distance between any one of the second transistors and the substrate is greater than the distance between any one of the first transistors and the substrate; each of the transistors includes a semiconductor pattern extending in a horizontal direction, and the spacing between the semiconductor patterns of any two adjacent second transistors in the vertical direction is greater than the spacing between the semiconductor patterns of any two adjacent first transistors in the vertical direction, the vertical direction is perpendicular to the main surface of the substrate, and the horizontal direction is parallel to the main surface of the substrate.

7. The semiconductor structure according to claim 6, wherein: The semiconductor patterns of any two transistors have the same width in the horizontal direction.

8. The semiconductor structure according to claim 6 or 7, characterized in that: The semiconductor patterns of any two adjacent second transistors in the plurality of second transistors have the same spacing in the vertical direction.

9. The semiconductor structure according to claim 6 or 7, characterized in that: Along a direction away from the substrate, a pitch gradient of the semiconductor patterns of every two adjacent second transistors in the plurality of second transistors increases in the vertical direction.

10. The semiconductor structure according to claim 6, wherein: The semiconductor structure further comprises: A plurality of stacked capacitors, the plurality of capacitors comprising a plurality of first capacitors and a plurality of second capacitors, wherein the first lower electrodes of the first capacitors are connected to the first transistor, and the second lower electrodes of the second capacitors are connected to the second transistor; wherein the spacing between any two adjacent second lower electrodes is greater than the spacing between any two adjacent first lower electrodes.

11. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers alternately stacked; wherein the plurality of sacrificial layers comprise a plurality of first sacrificial layers and a plurality of second sacrificial layers, the distance between any one of the second sacrificial layers and the substrate being greater than the distance between any one of the first sacrificial layers and the substrate; the material of each of the sacrificial layers comprises silicon germanium, and the germanium content of any one of the second sacrificial layers is greater than the germanium content of any one of the first sacrificial layers; forming a groove extending along a first horizontal direction and penetrating the stacked structure, wherein the first horizontal direction is parallel to the main surface of the substrate; Each sacrificial layer is laterally etched through the groove to form a gap between two adjacent semiconductor layers; wherein any two of the gaps have the same width in a second horizontal direction, and the second horizontal direction is parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: Any two of the plurality of second sacrificial layers have the same germanium content.

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: The germanium content of the plurality of second sacrificial layers increases gradually in a direction away from the substrate.

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