Semiconductor process method

Abstract

The invention provides a semiconductor process method, relates to the technical field of semiconductor processing, and aims to solve the problem that etching side walls of an OX layer and a W layer are uneven in the etching process of a laminated structure in the prior art. The semiconductor process method comprises a main etching step, a first process gas is used for etching a laminated structure, the laminated structure is formed by OX layers and W layers which are alternately arranged, and the first process gas comprises Cl-based gas and F-based gas. The side wall of the groove can be flatter.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to a semiconductor processing method. Background Art

[0002] Tungsten (W) metal is widely used in the manufacture of 3D NAND (Three-Dimensional NAND) devices due to its excellent properties, including high melting point, low resistivity, high thermal conductivity, high chemical inertness, and corrosion resistance. For example, W is often paired with the dielectric material silicon oxide (OX) to form an OX-W-OX-W-OX stacked structure, achieving synergistic charge storage, electrical isolation, and signal transmission. However, when etching this stacked structure, the different properties of OX and W result in different etching resistance. When the OX and W layers are etched separately with process gases, the etching of each material does not proceed in a straight line from the trench sidewall to the solid part. Specifically, the reaction rate is faster at the upper and / or lower edges of the sidewall surface of each layer in the trench, resulting in uneven discontinuities at the junction of the OX and W layers. During multiple stacking cycles, these defects are amplified, increasing the difficulty of subsequent processing. Summary of the Invention

[0003] The object of the present invention is to provide a semiconductor process method to solve the technical problem of uneven sidewalls of the OX layer and the W layer during the etching process of the stacked structure.

[0004] The semiconductor process method provided by the present invention comprises:

[0005] In the main etching step, a first process gas is used to etch the stacked structure, where the stacked structure is formed by alternating OX layers and W layers. The first process gas includes a Cl-based gas and a F-based gas.

[0006] The beneficial effects brought about by the semiconductor process method of the present invention are:

[0007] In the main etch step, Cl-based gas can be used to etch the W layer, while F-based gas can be used to etch the OX layer. While the first process gas is used to etch the stacked structure, this allows for simultaneous etching of the Cl-based and F-based gases. This eliminates the need for purge gas in the process of etching and recycling the two separately, reducing the total duration of the main etch step and improving process efficiency. Furthermore, the simultaneous etching of the W layer with Cl-based gas and the F-based gas with F-based gas allows for continuous etching of the W and OX layers. This eliminates the need to restart etching of a separate material after etching of the other material is complete or nearly complete. This significantly reduces the unevenness at the junction of the W and OX layers, improving the smoothness of the trench sidewalls.

[0008] In an optional technical solution, in the main etching step, the etching temperature is 80°C to 300°C.

[0009] In an optional technical solution, in the main etching step, the Cl-based gas includes Cl2, the F-based gas includes NF3, the flow rate of Cl2 is 30 sccm to 150 sccm, and the flow rate of NF3 is 10 sccm to 100 sccm.

[0010] In an optional technical solution, in the main etching step, the Cl-based gas further includes SiCl 4 , and the flow rate of the SiCl 4 is 20 sccm to 200 sccm.

[0011] In an optional technical solution, in the main etching step, the first process gas further includes N2 and He, the flow rate of N2 is 20 sccm to 120 sccm, and the flow rate of He is 50 sccm to 300 sccm.

[0012] In an optional technical solution, in the main etching step, the excitation power is 800w-1800w, and the bias power is 800w-1800w.

[0013] In an optional technical solution, in the main etching step, the process pressure is 5 mtorr to 30 mtorr.

[0014] In an optional technical solution, before the main etching step, the semiconductor process method further includes:

[0015] In the oxide layer opening step, a second process gas is used to etch the top oxide layer above the stacked structure to expose the stacked structure. The second process gas includes CF4, CHF3 and a rare gas.

[0016] In an optional technical solution, in the oxide layer opening step, the flow rate of CF4 is 50 sccm to 350 sccm, the flow rate of CHF3 is 50 sccm to 150 sccm, the rare gas is Ar, and the flow rate of Ar is 50 sccm to 200 sccm.

[0017] In an optional technical solution, in the oxide layer opening step, the process pressure is 5mtorr to 25mtorr, the etching temperature is 30°C to 80°C, the excitation power is 400w to 650w, and the bias power is 300w to 700w. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the following briefly introduces the drawings required for use in the embodiments or the background technology description. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0019] Figure 1 Schematic diagram of the etching process of the stacked structure in the related art.

[0020] Figure 2 A flowchart of a semiconductor process method provided by an embodiment of the present invention.

[0021] Figure 3 This is a structural diagram of the semiconductor process method provided by an embodiment of the present invention after the main etching step is completed.

[0022] Figure 4 A schematic diagram of the structure of a semiconductor etched by the semiconductor process method provided by an embodiment of the present invention.

[0023] Figure 5 This is a schematic diagram of the structure after the oxide layer opening step is completed in the semiconductor process method provided by an embodiment of the present invention.

[0024] Description of reference numerals:

[0025] 10 - top oxide layer; 21 - W layer; 22 - OX layer. DETAILED DESCRIPTION

[0026] In related technologies, the OX layer 22 and the W layer 21 are primarily etched in separate steps. Specifically, the OX layer is etched using a F-based gas, while the W layer is etched using a Cl-based gas. This etching is repeated in a cyclic manner, where the OX layer 22 is etched once, the W layer 21 is etched once, and then the OX layer 22 is etched once again, and this cycle repeats. Generally, if several pairs of OX / W stacks need to be etched, several cyclic etching cycles are required.

[0027] The relevant technology mainly etches the OX layer 22 and the W layer 21 separately through different gas precursors. Due to the differences in the film layer structures and the impact on the upper structure during the etching of the lower layer structure, it is difficult to form a smooth surface transition at the connection between the two different film layer structures, so unevenness will appear, which is difficult to meet the etching requirements. At the same time, the cyclic etching method also increases the complexity of the process and reduces production efficiency.

[0028] like Figure 1The figure illustrates the etching process of an OX / W stacked structure in a related art. In the figure, the first, third, fifth, and seventh layers, from top to bottom, are OX layers 22, while the second, fourth, and sixth layers are W layers 21. If the aforementioned cyclic etching method is used, assuming that the trench sidewalls can remain vertical during the etching of each layer, no issues are apparent with the etching of the first and second layers. However, since both the first and third layers are OX layers 22, etching the third layer (i.e., the second OX layer 22) will also affect the first layer. Due to plasma motion, the etching rate of the upper portion of the trench sidewall corresponding to the first layer will be greater than that of the lower portion, resulting in the first layer exhibiting a tapered shape. Since both the second and fourth layers are W layers 21, etching the fourth layer (i.e., the second W layer 21) will also affect the second layer. Similarly, the second layer will also exhibit a tapered shape, and the corner of the second layer adjacent to the first layer will appear recessed relative to the first layer. Similarly, when etching the fifth layer, the third layer will also have the same problem as the second layer; when etching the sixth layer, the fourth layer will also have the same problem as the second layer. Therefore, the cyclic etching method will cause the OX layer 22 and the W layer 21 to have unevenness at the junction, thereby affecting the quality of the trench sidewall. It should be noted that the figure only schematically shows the slope and shape of the trench sidewall. In the actual etching process, the trench sidewall may not be as Figure 1 The shape is not necessarily like Figure 1 So ideal.

[0029] In an embodiment of the present invention, for a stacked structure having alternating OX layers 22 and W layers 21, after the top oxide layer is opened in an oxide layer opening step, the stacked structure is plasma etched in a main etching step using a first process gas comprising a Cl-based gas and a F-based gas. This allows for simultaneous etching of the OX layers 22 and the W layers 21, thereby shortening the total duration of the main etching step while meeting the required etching time for each layer. Furthermore, since each layer is etched continuously, the consumption of each layer's material is also continuous and consistent, and there is no situation where etching of a particular layer is completed or nearly completed before the etching of that layer is restarted. Consequently, the flatness of the sidewalls of each layer is improved, significantly reducing the unevenness at the junction of the W and OX layers 21 and 22.

[0030] To make the above features and advantages of the present invention more clearly understood, the following describes in detail the specific embodiments of the present invention with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0031] like Figure 2-Figure 5As shown, the semiconductor process method provided by an embodiment of the present invention includes a main etching step, in which a first process gas is used to etch the stacked structure, the stacked structure being formed by alternating OX layers 22 and W layers 21, and the first process gas includes a Cl-based gas and a F-based gas.

[0032] In the main etching step, the W layer 21 can be etched using a Cl-based gas, and the OX layer 22 can be etched using an F-based gas. The stacked structure is then etched using the first process gas. This allows for simultaneous etching of the Cl-based and F-based gases, eliminating the need for purge gas in the process of etching the two separately and cycling them. This reduces the total duration of the main etching step and improves process efficiency. Furthermore, the simultaneous etching of the W layer 21 with the Cl-based gas and the F-based gas with the F-based gas allows for continuous etching of the W layer 21 and the OX layer 22. This eliminates the need to initiate etching of a separate material after etching of the respective material is complete or nearly complete. This significantly reduces the unevenness at the junction of the W and OX layers 21 and 22, improving the smoothness of the trench sidewalls.

[0033] In an embodiment of the present invention, the etching temperature in the main etching step is 80°C to 300°C. Increasing the etching temperature to the above range in the main etching step can increase the etching selectivity of the Cl-based gas to the W layer 21 and the etching selectivity of the F-based gas to the OX layer 22, so that the etching rates of the W layer 21 and the OX layer 22 are close, achieving a continuous sidewall effect. In addition, this temperature can also increase the energy of the active particles in the plasma, thereby increasing the collision frequency with the surfaces of the W layer 21 and the OX layer 22, and increasing the etching reaction rate. It can also reduce local hot spots that may appear during the etching process and improve etching uniformity.

[0034] In an embodiment of the present invention, in the main etching step, the Cl-based gas includes Cl2 and the F-based gas includes NF3. The flow rate of Cl2 is 30 sccm to 150 sccm, and the flow rate of NF3 is 10 sccm to 100 sccm. By setting the flow rate of Cl2 gas for etching the W layer 21 to the above flow rate and selecting the flow rate of NF3 gas for etching the OX layer 22 to the above flow rate, the etching rates of the W layer 21 and the OX layer 22 can be similar, making the trench sidewalls more continuous and improving the flatness of the etched surface on the trench side.

[0035] In the embodiment of the present invention, the Cl-based gas also includes SiCl4 in the main etching step, and the flow rate of SiCl4 is 20 sccm to 200 sccm. The use of SiCl4 gas in the main etching step not only provides sidewall protection but also produces a partial etching effect, thereby reducing the amount of Cl2 used.

[0036] In an embodiment of the present invention, during the main etching step, the first process gas also includes N2 and He. The N2 flow rate is 20 sccm to 120 sccm, and the He flow rate is 50 sccm to 300 sccm. N2 can provide sidewall protection and act as a dilution gas. He, as a dilution gas, helps ensure uniform gas mixing and can also adjust the concentration of active gases in the plasma, thereby controlling the etching rate and selectivity.

[0037] In an embodiment of the present invention, in the main etching step, the excitation power is 800w~1800w, and the bias power is 800w~1800w. In the main etching step, increasing the excitation power can increase the number of active particles in the plasma, thereby increasing the plasma density. In addition, it will also increase the energy of the active particles. Increasing the bias power to the above range can increase the traction effect of the lower electrode, pulling positive ions to enhance the base effect. It is not only conducive to achieving a relatively straight groove sidewall, but also can achieve the overall downward etching of the bottom morphology, and improve the flatness of the bottom of the groove.

[0038] In the embodiment of the present invention, the process pressure in the main etching step is 5mtorr to 30mtorr. Using a lower process pressure in the main etching step helps increase the mean free path of the particles, thereby increasing the acceleration distance, enhancing the energy of the particles, and strengthening the bombardment effect, thereby helping to etch the entire bottom morphology downward and achieve a flat bottom effect.

[0039] like Figure 2 、 Figure 4 and Figure 5 As shown, in an embodiment of the present invention, before the main etching step, the semiconductor process method further includes: an oxide layer opening step, using a second process gas to etch the top oxide layer 10 located above the stacked structure to expose the stacked structure, and the second process gas includes CF4, CHF3 and a rare gas.

[0040] The film layer structure that needs to be etched in this embodiment includes a top oxide layer 10. Although the top oxide layer 10 is also an OX layer 22, its thickness is significantly greater than the OX layer 22 and the W layer 21 alternately arranged below. Therefore, it is necessary to adopt an oxide layer opening step to open the top oxide layer 10. In the oxide layer opening step, the use of CF4 can increase the etching rate, and the use of CHF3 can produce carbon polymers during the etching process to be deposited on the sidewalls of the grooves of the top oxide layer 10, thereby protecting the sidewalls of the grooves and reducing the risk of lateral dimensional expansion. The use of rare gases is mainly used for physical bombardment in order to cooperate with chemical etching to achieve a faster etching rate. The above gas combination can achieve a balance between etching rate and morphology protection.

[0041] In an embodiment of the present invention, in the oxide layer opening step, the flow rate of CF4 is 50 sccm to 350 sccm, the flow rate of CHF3 is 50 sccm to 150 sccm, and Ar is selected as a rare gas, with a flow rate of Ar being 50 sccm to 200 sccm. By setting the flow rates of the various components of the first process gas to the above ranges, a larger flow rate of CF4 can be used to complete the etching of the top oxide layer 10 more quickly, while a small amount of CHF3 can be used to protect the sidewalls and reduce the risk of lateral dimensional expansion. Using a medium flow rate of Ar can take on the main task of physical bombardment. In addition, although there are some positive ions with bombardment effects after CF4 dissociation, the bombardment effect is significantly smaller than that of Ar. The physical bombardment is mainly the bombardment of Ar, supplemented by the bombardment of CF4 dissociation.

[0042] In the embodiment of the present invention, during the oxide layer opening step, the process pressure is 5 mtorr to 25 mtorr, the etching temperature is 30°C to 80°C, the excitation power is 400 W to 650 W, and the bias power is 300 W to 700 W. The above process pressure, combined with a relatively high bias power, can achieve a strong physical bombardment effect, thereby improving the straightness of the trench sidewalls of the top oxide layer 10 and reducing interference with the trenches in the alternating stacked structure.

[0043] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

[0044] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0045] In the above embodiments, the descriptions of directions such as “upper” and “lower” are all based on the drawings.

[0046] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention.

[0047] Thus, the present invention will not be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor process method, characterized in that: include: In the main etching step, a first process gas is used to etch the stacked structure, wherein the stacked structure is formed by alternately arranged OX layers (22) and W layers (21), and the first process gas includes a Cl-based gas and a F-based gas.

2. The semiconductor process method according to claim 1, wherein: In the main etching step, the etching temperature is 80° C. to 300° C.

3. The semiconductor process method according to claim 2, wherein: In the main etching step, the Cl-based gas includes Cl2, the F-based gas includes NF3, the flow rate of Cl2 is 30 sccm to 150 sccm, and the flow rate of NF3 is 10 sccm to 100 sccm.

4. The semiconductor process method according to claim 3, wherein: In the main etching step, the Cl-based gas further includes SiCl 4 , and the flow rate of the SiCl 4 is 20 sccm to 200 sccm.

5. The semiconductor process method according to claim 3, wherein: In the main etching step, the first process gas further includes N2 and He, the flow rate of N2 is 20 sccm to 120 sccm, and the flow rate of He is 50 sccm to 300 sccm.

6. The semiconductor process method according to any one of claims 1 to 5, characterized in that: In the main etching step, the excitation power is 800W to 1800W, and the bias power is 800W to 1800W.

7. The semiconductor process method according to claim 6, wherein: In the main etching step, the process pressure is 5 mtorr to 30 mtorr.

8. The semiconductor process method according to any one of claims 1 to 5, characterized in that: Before the main etching step, the semiconductor process method further includes: In the oxide layer opening step, a second process gas is used to etch the top oxide layer (10) located above the stacked structure to expose the stacked structure. The second process gas includes CF4, CHF3 and a rare gas.

9. The semiconductor process method according to claim 8, wherein: In the oxide layer opening step, the flow rate of CF4 is 50 sccm to 350 sccm, the flow rate of CHF3 is 50 sccm to 150 sccm, and the rare gas is Ar, with a flow rate of 50 sccm to 200 sccm.

10. The semiconductor process method according to claim 8, wherein: In the oxide layer opening step, the process pressure is 5mtorr to 25mtorr, the etching temperature is 30°C to 80°C, the excitation power is 400W to 650W, and the bias power is 300W to 700W.

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