Preparation method of magnetic random access memory
By using alignment mark protrusions and concave structures as alignment marks in MRAM chip manufacturing, the MRAM chip manufacturing process is simplified, the yield rate is improved and the cost is reduced, and the alignment deviation and metal damage problems caused by multiple mask layers in the existing technology are solved.
Patent Information
- Application Number
- CN202410371064.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-29
- Publication Date
- 2025-09-30
AI Technical Summary
The existing MRAM chip manufacturing process is cumbersome and requires multiple mask layers, resulting in large alignment deviations, high costs and low yields. In particular, the bottom metal in the substrate is easily damaged during the etching process of the bottom interconnect structure.
By forming an alignment mark protrusion structure as Alignment mark 1 on the substrate, etching the bottom interconnect layer is performed, and by removing the alignment mark protrusion structure to form an alignment mark concave structure as Alignment mark 2, etching of the magnetic tunnel junction film is completed, reducing the use of masks and simplifying the process flow.
The method improves the yield rate of magnetic random access memory, reduces the preparation cost, effectively avoids damage to the bottom metal in the substrate, and simplifies the process flow.
Smart Images
Figure CN120730745A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a magnetic random access memory. Background Art
[0002] With the rise of emerging sectors such as automotive electronics, 5G (5th Generation Mobile Communication Technology), the Internet of Things, and wearables, memory chips will play an even more crucial role in the entire industry chain. In recent years, new memory technologies such as MRAM (Magnetic Random Access Memory) have emerged as promising next-generation non-volatile memories, offering advantages over existing memory technologies such as fast read and write speeds, unlimited erase and write cycles, non-volatility, and compatibility with current semiconductor processes.
[0003] In the MRAM chip manufacturing process, magnetic tunnel junctions (MTJs) are integrated into the back-end metal layers. A simple and efficient process integration method is the goal of many companies and research institutions. Relatively few mask layers can reduce the impact of defects introduced by process steps, thereby improving chip yield, a goal pursued by major memory manufacturers.
[0004] However, the existing MRAM chip manufacturing process is cumbersome and requires the formation of at least two Alignmentmark (AM) masks to form two concave Alignment marks, namely Alignmentmark1 and Alignmentmark2, to respectively complete the etching of the bottom interconnect layer 5 and the magnetic tunnel junction film 6, and form the bottom interconnect structure 51 and the magnetic tunnel junction 61 above the substrate 1. Figure 1 、 Figure 2 and Figure 3 This will not only increase the alignment deviation, but also introduce defects in the process flow. In addition, the large number of mask layers will increase the cost of the MRAM chip manufacturing process.
[0005] In particular, in the process of etching the bottom interconnect structure 51 through the Alignment mark 1, the substrate needs to be etched to form the Alignment mark 1. However, in this process, bottom metal is etched into the substrate, thereby affecting the yield of the MRAM chip. Summary of the Invention
[0006] To solve the above problems, the present invention provides a method for preparing a magnetic random access memory, which realizes etching of the bottom interconnect layer by forming an alignment mark protrusion structure, effectively avoiding damage to the bottom metal in the substrate and improving the yield of the magnetic random access memory.
[0007] The present invention provides a method for preparing a magnetic random access memory, the method comprising:
[0008] Providing a substrate, wherein a bottom metal and a bottom through-hole conductive structure are formed in the substrate, wherein the bottom through-hole conductive structure is located above the bottom metal and electrically connected to the bottom metal;
[0009] depositing a first dielectric material on the substrate to form a first dielectric layer;
[0010] Photolithography the first dielectric layer to form an alignment mark protrusion structure above the substrate;
[0011] Depositing a metal material on the substrate to form a bottom interconnect layer, wherein the bottom interconnect layer is raised upward at a location where the alignment mark protrusion structure is located;
[0012] According to the position of the alignment mark protruding structure, the bottom interconnection layer is etched to form a bottom interconnection structure on the substrate and expose the alignment mark protruding structure. The bottom interconnection structure is electrically connected to the bottom through-hole conductive structure.
[0013] Optionally, the thickness of the alignment mark protrusion structure is not less than the thickness of the bottom interconnect structure;
[0014] The method further includes: depositing a second dielectric material on the substrate to form a second dielectric layer, wherein the second dielectric layer covers the alignment mark protrusion structure and the bottom interconnect structure; wherein, under the same etching conditions, the etching rate of the second dielectric material is lower than the etching rate of the first dielectric material;
[0015] planarizing the second dielectric layer to expose the alignment mark protrusion structure and the bottom interconnect structure; removing the alignment mark protrusion structure to form an alignment mark concave structure in the second dielectric layer; or planarizing the second dielectric layer to expose only the alignment mark protrusion structure; removing the alignment mark protrusion structure to form an alignment mark concave structure in the second dielectric layer; and continuing to planarize the second dielectric layer to expose the bottom interconnect structure;
[0016] Depositing a magnetic tunnel junction material on the second dielectric layer to form a magnetic tunnel junction film, wherein the magnetic tunnel junction film is concave downward at a position of the alignment mark concave structure;
[0017] According to the position of the concave structure of the alignment mark, the magnetic tunnel junction film is etched to form a magnetic tunnel junction, and the magnetic tunnel junction is electrically connected to the bottom interconnection structure.
[0018] Optionally, according to the location of the alignment mark protruding structure, the step of etching the bottom interconnect layer includes:
[0019] Depositing a photoresist material on the bottom interconnect layer to form a first photoresist layer, wherein the first photoresist layer protrudes upward at a location where the alignment mark protrusion structure is located;
[0020] Aligning the position of the alignment mark protrusion structure, patterning the first photoresist layer; and,
[0021] etching the bottom interconnect layer according to the patterned first photoresist layer to form a bottom interconnect structure on the substrate and expose the alignment mark protrusion structure;
[0022] According to the location of the concave structure of the alignment mark, the steps of etching the magnetic tunnel junction film include:
[0023] Depositing a photoresist material on the magnetic tunnel junction film to form a second photoresist layer, wherein the second photoresist layer is recessed downward at a position of the alignment mark recessed structure;
[0024] Aligning the position of the alignment mark recess structure, patterning the second photoresist layer; and,
[0025] The magnetic tunnel junction film is etched based on the patterned second photoresist layer to form a magnetic tunnel junction.
[0026] Optionally, the step of depositing a photoresist material on the bottom interconnect layer to form a first photoresist layer includes:
[0027] depositing an anti-reflective material on the bottom interconnect layer to form a first anti-reflective layer; and,
[0028] depositing a photoresist material on the first anti-reflective layer to form a first photoresist layer;
[0029] The step of etching the bottom interconnect layer according to the patterned first photoresist layer includes:
[0030] etching the first anti-reflection layer and the bottom interconnection layer according to the patterned first photoresist layer to form a bottom interconnection structure on the substrate and expose the alignment mark protrusion structure; and
[0031] removing the remaining first photoresist layer and first anti-reflective layer above the bottom interconnect structure;
[0032] The step of depositing a photoresist material on the magnetic tunnel junction film to form a second photoresist layer includes:
[0033] depositing an anti-reflection material on the magnetic tunnel junction film to form a second anti-reflection layer; and
[0034] depositing a photoresist material on the second anti-reflective layer to form a second photoresist layer;
[0035] The step of etching the magnetic tunnel junction film according to the patterned second photoresist layer to form a magnetic tunnel junction includes:
[0036] etching the second anti-reflection layer and the magnetic tunnel junction film according to the patterned second photoresist layer to form a magnetic tunnel junction; and
[0037] The remaining second photoresist layer and the second anti-reflection layer above the magnetic tunnel junction are removed.
[0038] Optionally, the step of photolithographically etching the first dielectric layer to form an alignment mark protrusion structure above the substrate includes:
[0039] depositing an anti-reflection material on the first dielectric layer to form a third anti-reflection layer;
[0040] depositing a photoresist material on the third anti-reflective layer to form a third photoresist layer;
[0041] patterning the third photolithography layer to form a positioning protrusion structure on the third anti-reflection layer;
[0042] Etching the third anti-reflection layer and the first dielectric layer according to the positioning protrusion structure; and
[0043] The positioning protrusion structure and the remaining third anti-reflection layer are removed to form an alignment mark protrusion structure above the substrate.
[0044] Optionally, after the step of removing the alignment mark protruding structure to form the alignment mark concave structure in the second dielectric layer, the method further includes:
[0045] A bottom of the alignment mark recess structure is etched to extend the alignment mark recess structure into the substrate.
[0046] Optionally, an etching selectivity ratio between the first dielectric material and the second dielectric material ranges from 10 to 20:1.
[0047] Optionally, before depositing a first dielectric material on the substrate to form a first dielectric layer, the method further comprises: depositing a conductive material above and below the substrate to form an etch stop layer, the etch stop layer being electrically connected to the bottom through-hole conductive structure;
[0048] The step of photolithographically etching the first dielectric layer to form an alignment mark protrusion structure above the substrate includes: photolithographically etching the first dielectric layer and stopping at an etch stop layer to form an alignment mark protrusion structure above the substrate;
[0049] The step of depositing a metal material on the substrate to form a bottom interconnect layer includes: depositing a metal material on the etch stop layer to form the bottom interconnect layer;
[0050] The step of etching the bottom interconnect layer according to the position of the alignment mark protrusion structure to form the bottom interconnect structure on the substrate and expose the alignment mark protrusion structure includes:
[0051] According to the position of the alignment mark protruding structure, the bottom interconnection layer and the etch stop layer are etched to form the bottom interconnection structure on the substrate and expose the alignment mark protruding structure.
[0052] Optionally, the step of providing a substrate includes:
[0053] A through hole is opened on the top of the substrate, the through hole is connected to the bottom metal; and
[0054] Coating a conductive material on the inner wall of the through hole and embedding a third dielectric material inside the side wall formed by the conductive material to form a bottom through hole conductive structure;
[0055] Under the same etching conditions, the etching rate of the first dielectric material is greater than the etching rate of the third dielectric material.
[0056] Optionally, an etching selectivity ratio of the first dielectric material to the third dielectric material is not less than 10:1.
[0057] Optionally, the conductive material includes at least one of Cu, Ta, TaN, Ti, TiN, W, and WN;
[0058] The material of the bottom metal includes at least one of Cu, Ta, TaN, Ti, TiN, W, and WN.
[0059] Optionally, the step of removing the alignment mark protruding structure includes:
[0060] The alignment mark protrusion structure is removed by etching.
[0061] Optionally, after the step of etching the magnetic tunnel junction thin film according to the patterned second photoresist layer, the method further comprises:
[0062] A fourth dielectric material is deposited on the second dielectric layer to form a protection layer covering the magnetic tunnel junction.
[0063] Optionally, the material of the substrate includes at least one of SiN, SiO, SiON and SiOC.
[0064] The method for fabricating a magnetic random access memory (MRAM) provided by an embodiment of the present invention forms a raised alignment mark structure by photolithography on a first dielectric layer. This raised alignment mark structure serves as Alignment Mark 1 to etch the bottom interconnect layer, effectively avoiding damage to the bottom metal in the substrate and improving the yield rate of the MRAM. The raised alignment mark structure is then removed to form a recessed alignment mark structure, which serves as Alignment Mark 2 to etch the magnetic tunnel junction thin film. This eliminates the need for a separate second Alignment Mark mask to form Alignment Mark 2, thereby reducing the complexity of the MRAM fabrication process and, in turn, the MRAM manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0065] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0066] Figure 1 FIG. 1 is a schematic structural diagram of a conventional process of etching a bottom interconnection layer through Alignment mark 1;
[0067] Figure 2 A schematic structural diagram of a conventional process of etching a magnetic tunnel junction thin film through Alignment mark 2;
[0068] Figure 3 A schematic structural diagram of a conventional magnetic random access memory preparation process;
[0069] Figure 4 1 is a schematic flow chart of a method for preparing an MRAM according to an embodiment of the present application;
[0070] Figures 5 to 16 Schematic structural diagram of a method for preparing an MRAM in corresponding stages according to an embodiment of the present application;
[0071] Figures 17 to 19 Schematic structural diagram of a method for preparing an MRAM in corresponding stages according to an embodiment of the present application;
[0072] Figures 20 to 26 Schematic structural diagram of a method for preparing an MRAM in corresponding stages according to an embodiment of the present application.
[0073] Reference numerals:
[0074] 1. Substrate; 21. First dielectric layer; 211. Alignment mark protrusion structure; 22. Second dielectric layer; 221. Alignment mark concave structure; 31. First anti-reflection layer; 32. Second anti-reflection layer; 33. Third anti-reflection layer; 41. First photolithography layer; 42. Second photolithography layer; 43. Third photolithography layer; 431. Positioning protrusion structure; 5. Bottom interconnect layer; 51. Bottom interconnect structure; 6. Magnetic tunnel junction film; 61. Magnetic tunnel junction; 71. Bottom metal; 72. Bottom through-hole conductive structure; 73. Protective layer; 74. Top metal; 75. Etch stop layer. DETAILED DESCRIPTION
[0075] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0076] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.
[0077] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0078] It should be noted that when an element is referred to as being "fixedly connected" to another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be an intermediate element. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.
[0079] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
[0080] Example 1
[0081] This embodiment provides a method for preparing an MRAM, which includes the following steps:
[0082] Providing a substrate; wherein a bottom metal and a bottom through-hole conductive structure are formed in the substrate, and the bottom through-hole conductive structure is located above the bottom metal and electrically connected to the bottom metal;
[0083] depositing a first dielectric material on the substrate to form a first dielectric layer;
[0084] Photolithography the first dielectric layer to form an alignment mark protrusion structure above the substrate;
[0085] Depositing a metal material on the substrate to form a bottom interconnection layer; the bottom interconnection layer is raised upward at the location where the alignment mark protrusion structure is located;
[0086] According to the position of the alignment mark protruding structure, the bottom interconnection layer is etched to form a bottom interconnection structure on the substrate and expose the alignment mark protruding structure; the bottom interconnection structure is electrically connected to the bottom through-hole conductive structure.
[0087] The MRAM fabrication method provided in this embodiment forms an alignment mark protrusion structure by photolithography on the first dielectric layer, and uses the alignment mark protrusion structure as Alignment Mark 1 to complete the etching of the bottom interconnect layer, effectively avoiding damage to the bottom metal in the substrate and improving the yield rate of the magnetic random access memory.
[0088] Example 1
[0089] This embodiment provides a method for preparing an MRAM, which includes steps S101 to S109:
[0090] Step S101: providing a substrate.
[0091] In this embodiment, a bottom metal and a bottom via conductive structure are formed within the substrate; the bottom via conductive structure is located above and electrically connected to the bottom metal. Furthermore, a front-end CMOS (Complementary Metal Oxide Semiconductor) is formed on the substrate. This front-end CMOS is formed on the substrate during the MRAM fabrication process, prior to forming the bottom interconnect structure, and includes components other than the bottom metal and bottom via conductive structure, such as field-effect transistors and contact holes. This embodiment does not specifically limit this aspect.
[0092] It should be noted that the material of the substrate includes at least one of SiN, SiO, SiON, and SiOC; and the material of the bottom metal includes at least one of Cu, Ta, TaN, Ti, TiN, W, and WN. The substrate may be a single-layer structure or a multi-layer structure. When the substrate is a multi-layer structure, the material of each layer may be the same as or different from the materials of the other layers. In this embodiment, the substrate is a three-layer structure stacked from bottom to top, wherein the bottom metal is located in the bottom layer structure of the substrate, and the bottom through-hole conductive structure penetrates the middle layer structure and the top layer structure of the substrate. This embodiment does not specifically limit the specific materials of the various layer structures in the substrate and the specific materials of the bottom metal.
[0093] In an optional embodiment, the step of providing a substrate includes steps S1011 to S1012:
[0094] Step S1011: opening a through hole on the top of the substrate.
[0095] The through hole is connected to the bottom metal.
[0096] Step S1012: coating the inner wall of the through hole with a conductive material and embedding a third dielectric material inside the side wall formed by the conductive material to form a bottom through hole conductive structure.
[0097] The etching selectivity ratio of the first dielectric material to the third dielectric material is not less than 10:1, such as 15:1 or 20:1. In addition, the conductive material includes at least one of Cu, Ta, TaN, Ti, TiN, W and WN, which is not specifically limited in this optional embodiment.
[0098] Step S102: depositing a first dielectric material on the substrate to form a first dielectric layer.
[0099] It should be noted that under the same etching conditions, the etching rate of the first dielectric material is greater than the etching rate of the substrate top structure and greater than the etching rate of the third dielectric material. This can effectively avoid damage to the substrate and the bottom through-hole conductive structure during the etching process of the first dielectric layer.
[0100] Step S103: photolithography the first dielectric layer to form an alignment mark protrusion structure above the substrate.
[0101] Step S104: depositing metal material on the substrate to form a bottom interconnection layer.
[0102] The bottom interconnect layer protrudes upward at the location where the alignment mark protrusion structure is located, that is, the bottom interconnect layer covers the alignment mark protrusion structure and protrudes upward along with the alignment mark protrusion structure.
[0103] Step S105: etching the bottom interconnect layer according to the location of the alignment mark protruding structure to form a bottom interconnect structure on the substrate and expose the alignment mark protruding structure.
[0104] The bottom interconnection structure is electrically connected to the bottom through-hole conductive structure, and the thickness of the alignment mark protrusion structure in the up-down direction is not less than the thickness of the bottom interconnection structure.
[0105] It can be understood that the position of the alignment mark protruding structure in step S105 is determined by the upwardly protruding portion of the bottom interconnection layer, which will not be described in detail in this embodiment.
[0106] Step S106: depositing a second dielectric material on the substrate to form a second dielectric layer.
[0107] The second dielectric layer covers the alignment mark protrusion structure and the bottom interconnection structure; under the same etching conditions, the etching rate of the second dielectric material is lower than the etching rate of the first dielectric material.
[0108] Furthermore, the etching selectivity ratio of the first dielectric material to the second dielectric material ranges from 10 to 20:1, such as 12:1, 15:1, or 18:1, etc., which is not specifically limited in this embodiment.
[0109] Step S107: planarizing the second dielectric layer to expose the alignment mark protrusion structure and the bottom interconnect structure; removing the alignment mark protrusion structure to form an alignment mark concave structure in the second dielectric layer; or planarizing the second dielectric layer to expose only the alignment mark protrusion structure; removing the alignment mark protrusion structure to form an alignment mark concave structure in the second dielectric layer; and continuing to planarize the second dielectric layer to expose the bottom interconnect structure.
[0110] Furthermore, the step of removing the alignment mark protrusion structure includes: removing the alignment mark protrusion structure by etching. It should be noted that the etching method can be wet etching or dry etching, which is not specifically limited in this embodiment.
[0111] Step S108: depositing a magnetic tunnel junction material on the second dielectric layer to form a magnetic tunnel junction thin film.
[0112] The magnetic tunnel junction film is recessed downward at the location of the alignment mark recessed structure.
[0113] Step S109: etching the magnetic tunnel junction film according to the location of the alignment mark recessed structure to form a magnetic tunnel junction.
[0114] The magnetic tunnel junction is electrically connected to the bottom interconnect structure. It is understandable that the position of the alignment mark concave structure in step S111 is determined by the downwardly concave portion of the magnetic tunnel junction film, which will not be described in detail in this embodiment.
[0115] The MRAM fabrication method provided in this embodiment is simple to operate. In the MRAM back-end process, only one photomask needs to be produced during step S103. This allows for rapid and accurate alignment marks during the fabrication of the MRAM's bottom interconnect structure and magnetic tunnel junction. Compared to existing technologies, this method can eliminate one alignment mark mask, thereby reducing the cost of MRAM fabrication.
[0116] Specifically, an alignment mark protrusion structure is formed by photolithography on the first dielectric layer, and the alignment mark protrusion structure is used as Alignment mark 1 to complete the etching of the bottom interconnect layer. Thereafter, the alignment mark protrusion structure is removed to form an alignment mark concave structure, and the alignment mark concave structure is used as Alignment mark 2 to complete the etching of the magnetic tunnel junction film, without the need to separately prepare a second Alignment mark mask to form Alignment mark 2, thereby reducing the complexity of the MRAM preparation process and further reducing the production cost of the MRAM. In addition, the present application etches the bottom interconnect layer by forming the alignment mark protrusion structure as the Alignment mark, so that there is no need to etch the substrate to form the Alignment mark, thereby effectively preventing the circuit structure in the substrate from being damaged by etching.
[0117] Example 2
[0118] Based on the first embodiment, this embodiment provides a method for preparing an MRAM, which includes steps S201 to S222:
[0119] Step S201: providing a substrate 1.
[0120] Step S202: Deposit a first dielectric material on the substrate 1 to form a first dielectric layer 21, Figure 5 .
[0121] Step S203 : depositing an anti-reflection material on the first dielectric layer 21 to form a third anti-reflection layer 33 .
[0122] Step S204 : depositing a photoresist material on the third anti-reflection layer 33 to form a third photoresist layer 43 .
[0123] Step S205: patterning the third photolithography layer 43 to form a positioning protrusion structure 431 on the third anti-reflection layer 33, Figure 6 .
[0124] It can be understood that patterning the third photoresist layer 43 is to perform exposure and development operations on the third photoresist layer 43 , which is not specifically limited in this embodiment.
[0125] Step S206 : etching the third anti-reflection layer 33 and the first dielectric layer 21 according to the positioning protrusion structure 431 .
[0126] Step S207: removing the positioning protrusion structure 431 and the remaining third anti-reflection layer 33 to form an alignment mark protrusion structure 211 above the substrate 1. Figure 7 .
[0127] Step S208: Deposit metal material on substrate 1 to form bottom interconnect layer 5, Figure 8 .
[0128] Step S209 : depositing an anti-reflection material on the bottom interconnection layer 5 to form a first anti-reflection layer 31 .
[0129] Step S210 : depositing a photoresist material on the first anti-reflection layer 31 to form a first photoresist layer 41 .
[0130] The first photoresist layer 41 protrudes upward at the location of the alignment mark protruding structure 211 , that is, the first photoresist layer 41 covers the protruding portion of the bottom interconnection layer 5 and protrudes upward along with the protruding portion of the bottom interconnection layer 5 .
[0131] Step S211: Align the position of the alignment mark protrusion structure 211, pattern the first photoresist layer 41, and combine Figure 9 .
[0132] It can be understood that patterning the first photoresist layer 41 is to perform exposure and development operations on the first photoresist layer 41 , which is not specifically limited in this embodiment.
[0133] Step S212: etching the first anti-reflection layer 31 and the bottom interconnection layer 5 according to the patterned first photoresist layer 41 to form a bottom interconnection structure 51 on the substrate 1 and expose the alignment mark protrusion structure 211. Figure 10 .
[0134] Step S213 : removing the remaining first photoresist layer 41 and first anti-reflection layer 31 above the bottom interconnect structure 51 .
[0135] Step S214 : depositing a second dielectric material on the substrate 1 to form a second dielectric layer 22 .
[0136] Step S215: planarize the second dielectric layer 22 to expose the alignment mark protrusion structure 211 and the bottom interconnect structure 51, and then Figure 11 .
[0137] Step S216: selectively etching the alignment mark protruding structure 211 to form an alignment mark concave structure 221 in the second dielectric layer 22. Figure 12 .
[0138] Step S217: Deposit magnetic tunnel junction 61 material on the second dielectric layer 22 to form a magnetic tunnel junction film 6. Figure 13 .
[0139] Step S218 : depositing an anti-reflection material on the magnetic tunnel junction film 6 to form a second anti-reflection layer 32 .
[0140] Step S219 : depositing a photoresist material on the second anti-reflection layer 32 to form a second photoresist layer 42 .
[0141] The second photoresist layer 42 is recessed downward at the location of the alignment mark recess structure 221 .
[0142] Step S220: Align the position of the alignment mark concave structure 221, pattern the second photoresist layer 42, and combine Figure 14 .
[0143] It can be understood that patterning the second photoresist layer 42 is to perform exposure and development operations on the second photoresist layer 42 , which is not specifically limited in this embodiment.
[0144] Step S221 : etching the second anti-reflection layer 32 and the magnetic tunnel junction film 6 based on the patterned second photoresist layer 42 to form a magnetic tunnel junction 61 .
[0145] Step S222: Remove the remaining second photoresist layer 42 and second anti-reflection layer 32 above the magnetic tunnel junction 61, and then Figure 15 .
[0146] In this embodiment, the first photoresist layer 41, the second photoresist layer 42 and the third photoresist layer 43 are all photoresists (PR), which can also be different types of materials; the first anti-reflection layer 31, the second anti-reflection layer 32 and the third anti-reflection layer 33 are all bottom anti-reflective coatings (BARC).
[0147] In an optional embodiment, after removing the second photoresist layer 42 and the second anti-reflection layer 32 remaining above the magnetic tunnel junction 61, the method further includes: depositing a fourth dielectric material on the second dielectric layer 22 to form a protective layer 73 covering the magnetic tunnel junction 61, Figure 15 By forming the protective layer 73 , the magnetic tunnel junction 61 can be effectively prevented from being oxidized by air.
[0148] In an optional embodiment, the step S215 in the above can be replaced by: planarizing the second dielectric layer 22 to expose only the alignment mark protrusion structure 211, and combining Figure 17 At the same time, after the above step S216, it is necessary to continue to planarize the second dielectric layer 22 to expose the bottom interconnect structure 51, combined with Figure 18 and Figure 19 .
[0149] In an optional embodiment, after the step of removing the alignment mark protruding structure 211 to form the alignment mark recessed structure 221 in the second dielectric layer 22 , the method further includes: etching the bottom of the alignment mark recessed structure 221 to extend the alignment mark recessed structure 221 into the substrate 1 .
[0150] It is understood that the alignment mark recessed structure 221 may extend into the top structure or the middle structure of the substrate 1. In this optional embodiment, the alignment mark recessed structure 221 only penetrates the top structure of the substrate 1. This not only improves the identification accuracy of the alignment mark recessed structure 221, but also prevents damage to the bottom metal 71 of the substrate 1.
[0151] It should be noted that after executing step S222, the method can also continue with subsequent process flows, such as forming a top metal electrically connected to the magnetic tunnel junction above the magnetic tunnel junction, and combining the top metal with the top metal. Figure 16 , this embodiment does not make any specific limitation on this.
[0152] Example 3
[0153] This embodiment provides a method for preparing an MRAM. Compared with the first or second embodiment, the difference is that: in this embodiment, before depositing a first dielectric material on a substrate 1 to form a first dielectric layer 21, the method further includes: depositing a conductive material on the upper and lower surfaces of the substrate 1 to form an etch stop layer 75, the etch stop layer 75 being electrically connected to the bottom through-hole conductive structure 72; the step of depositing the first dielectric material on the substrate 1 to form the first dielectric layer 21 includes: depositing the first dielectric material on the etch stop layer 75 to form the first dielectric layer 21, and combining the first dielectric material and the conductive material. Figure 20 .
[0154] In the first or second embodiment, the step of photolithography of the first dielectric layer 21 to form the alignment mark protrusion structure 211 above the substrate 1 is as follows: photolithography of the first dielectric layer 21 and stopping at the etch stop layer 75 to form the alignment mark protrusion structure 211 above the substrate 1, combined with Figure 21 .
[0155] In the first or second embodiment, the step of depositing a metal material on the substrate 1 to form the bottom interconnection layer 5 is as follows: depositing a metal material on the etch stop layer 75 to form the bottom interconnection layer 5, and combining the metal material on the etch stop layer 75 to form the bottom interconnection layer 5. Figure 22 .
[0156] In the second embodiment, according to the patterned first photoresist layer 41, the first anti-reflective layer 31 and the bottom interconnection layer 5 are etched to form a bottom interconnection structure 51 on the substrate 1 and expose the alignment mark protrusion structure 211. In this embodiment, the first anti-reflective layer 31, the bottom interconnection layer 5 and the etch stop layer 75 are etched to form a bottom interconnection structure 51 on the substrate 1 and expose the alignment mark protrusion structure 211. Figure 23 .
[0157] It should be noted that the materials of the bottom interconnect layer 5 and the etch stop layer 75 may be the same or different. In this embodiment, the materials of the bottom interconnect layer 5 and the etch stop layer 75 are the same, and this embodiment does not impose any further limitation on this.
[0158] In addition, it can be understood that, in this embodiment, the bottom interconnect structure 51 is formed by etching the bottom interconnect layer 5 and the etch stop layer 75 .
[0159] The method for preparing the MRAM provided in this embodiment can protect the substrate 1 and effectively prevent the bottom metal 71 in the substrate 1 from being damaged during the etching process.
[0160] It should also be noted that in the second embodiment, the step of etching the bottom of the alignment mark concave structure 221 to extend the alignment mark concave structure 221 into the substrate 1 requires etching away the remaining etch stop layer 75 at the bottom of the alignment mark concave structure 221 during the execution of this embodiment. It is understood that during the process of forming the alignment mark concave structure 221 by dry etching, the etching gas needs to be replaced, which will not be further described in this embodiment.
[0161] In addition, combined Figures 24 to 26In this embodiment, when preparing the MRAM by using the steps of "planarizing the second dielectric layer 22 to expose only the alignment mark protruding structure 211; selectively etching the alignment mark protruding structure 211 to form the alignment mark concave structure 221 in the second dielectric layer 22; and further planarizing the second dielectric layer 22 to expose the bottom interconnect structure 51" in the second embodiment, damage to the bottom interconnect structure 51 during the etching process of the remaining etch stop layer 75 can be effectively avoided.
[0162] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.
[0163] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0164] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A method for preparing a magnetic random access memory, characterized in that: The method comprises: Providing a substrate (1), wherein a bottom metal (71) and a bottom through-hole conductive structure (72) are formed in the substrate (1), and the bottom through-hole conductive structure (72) is located above the bottom metal (71) and electrically connected to the bottom metal (71); Depositing a first dielectric material on the substrate (1) to form a first dielectric layer (21); Photoetching the first dielectric layer (21) to form an alignment mark protrusion structure (211) above the substrate (1); Depositing a metal material on the substrate (1) to form a bottom interconnection layer (5), wherein the bottom interconnection layer (5) protrudes upward at the location where the alignment mark protruding structure (211) is located; According to the location of the alignment mark protruding structure (211), the bottom interconnection layer (5) is etched to form a bottom interconnection structure (51) on the substrate (1) and expose the alignment mark protruding structure (211); the bottom interconnection structure (51) is electrically connected to the bottom through-hole conductive structure (72).
2. The method according to claim 1, characterized in that The thickness of the alignment mark protruding structure (211) is not less than the thickness of the bottom interconnection structure (51); The method further comprises: depositing a second dielectric material on the substrate (1) to form a second dielectric layer (22), wherein the second dielectric layer (22) covers the alignment mark protruding structure (211) and the bottom interconnect structure (51); wherein, under the same etching conditions, the etching rate of the second dielectric material is lower than the etching rate of the first dielectric material; planarizing the second dielectric layer (22) to expose the alignment mark protruding structure (211) and the bottom interconnection structure (51); removing the alignment mark protruding structure (211) to form an alignment mark concave structure (221) in the second dielectric layer (22); or planarizing the second dielectric layer (22) to expose only the alignment mark protruding structure (211); removing the alignment mark protruding structure (211) to form an alignment mark concave structure (221) in the second dielectric layer (22); and continuing to planarize the second dielectric layer (22) to expose the bottom interconnection structure (51); Depositing a magnetic tunnel junction (61) material on the second dielectric layer (22) to form a magnetic tunnel junction film (6), wherein the magnetic tunnel junction film (6) is recessed downward at the position of the alignment mark recessed structure (221); According to the location of the alignment mark concave structure (221), the magnetic tunnel junction film (6) is etched to form a magnetic tunnel junction (61), and the magnetic tunnel junction (61) is electrically connected to the bottom interconnection structure (51).
3. The method according to claim 2, characterized in that The step of etching the bottom interconnect layer (5) according to the location of the alignment mark protruding structure (211) comprises: Depositing a photolithographic material on the bottom interconnect layer (5) to form a first photolithographic layer (41), wherein the first photolithographic layer (41) protrudes upward at the location where the alignment mark protruding structure (211) is located; Aligning the position of the alignment mark protruding structure (211) and patterning the first photolithography layer (41); and Etching the bottom interconnect layer (5) according to the patterned first photoresist layer (41) to form a bottom interconnect structure (51) on the substrate (1) and expose an alignment mark protrusion structure (211); The step of etching the magnetic tunnel junction film (6) according to the location of the alignment mark recessed structure (221) comprises: Depositing a photolithographic material on the magnetic tunnel junction film (6) to form a second photolithographic layer (42), wherein the second photolithographic layer (42) is recessed downward at the position of the alignment mark recessed structure (221); Aligning the position of the alignment mark concave structure (221) and patterning the second photolithography layer (42); and, The magnetic tunnel junction film (6) is etched based on the patterned second photoresist layer (42) to form a magnetic tunnel junction (61).
4. The method according to claim 3, characterized in that The step of depositing a photolithography material on the bottom interconnect layer (5) to form a first photolithography layer (41) comprises: depositing an anti-reflection material on the bottom interconnect layer (5) to form a first anti-reflection layer (31); and, depositing a photolithography material on the first anti-reflection layer (31) to form the first photolithography layer (41); The step of etching the bottom interconnect layer (5) according to the patterned first photoresist layer (41) comprises: etching the first anti-reflection layer (31) and the bottom interconnection layer (5) according to the patterned first photoresist layer (41) to form a bottom interconnection structure (51) on the substrate (1) and expose an alignment mark protrusion structure (211); and removing the first photolithography layer (41) and the first anti-reflection layer (31) remaining above the bottom interconnect structure (51); The step of depositing a photolithographic material on the magnetic tunnel junction film (6) to form a second photolithographic layer (42) comprises: Depositing an anti-reflection material on the magnetic tunnel junction film (6) to form a second anti-reflection layer (32); and, depositing a photoresist material on the second anti-reflection layer (32) to form the second photoresist layer (42); The step of etching the magnetic tunnel junction film (6) based on the patterned second photoresist layer (42) to form a magnetic tunnel junction (61) comprises: etching the second anti-reflection layer (32) and the magnetic tunnel junction film (6) according to the patterned second photoresist layer (42) to form a magnetic tunnel junction (61); and The remaining second photolithography layer (42) and the second anti-reflection layer (32) above the magnetic tunnel junction (61) are removed.
5. The method according to claim 1, wherein The step of photoetching the first dielectric layer (21) to form an alignment mark protrusion structure (211) above the substrate (1) comprises: depositing an anti-reflection material on the first dielectric layer (21) to form a third anti-reflection layer (33); depositing a photolithography material on the third anti-reflection layer (33) to form a third photolithography layer (43); patterning the third photolithography layer (43) to form a positioning protrusion structure (431) on the third anti-reflection layer (33); Etching the third anti-reflection layer (33) and the first dielectric layer (21) according to the positioning protrusion structure (431); and The positioning protrusion structure (431) and the remaining third anti-reflection layer (33) are removed to form an alignment mark protrusion structure (211) above the substrate (1).
6. The method according to claim 2, characterized in that After the step of removing the alignment mark protruding structure (211) to form an alignment mark concave structure (221) in the second dielectric layer (22), the method further comprises: The bottom of the alignment mark recessed structure (221) is etched to extend the alignment mark recessed structure (221) into the substrate (1).
7. The method according to claim 2, characterized in that The etching selectivity ratio between the first dielectric material and the second dielectric material is in the range of 10 to 20:
1.
8. The method according to claim 1, characterized in that Before the step of depositing a first dielectric material on the substrate (1) to form a first dielectric layer (21), the method further comprises: depositing a conductive material above and below the substrate (1) to form an etch stop layer (75), wherein the etch stop layer (75) is electrically connected to the bottom through-hole conductive structure (72); The step of photoetching the first dielectric layer (21) to form an alignment mark protruding structure (211) above the substrate (1) comprises: photoetching the first dielectric layer (21) and stopping at the etching stop layer (75) to form an alignment mark protruding structure (211) above the substrate (1); The step of depositing a metal material on the substrate (1) to form a bottom interconnection layer (5) comprises: depositing a metal material on the etch stop layer (75) to form a bottom interconnection layer (5); The step of etching the bottom interconnect layer (5) according to the location of the alignment mark protruding structure (211) to form a bottom interconnect structure (51) on the substrate (1) and expose the alignment mark protruding structure (211) comprises: According to the location of the alignment mark protruding structure (211), the bottom interconnection layer (5) and the etching stop layer (75) are etched to form a bottom interconnection structure (51) on the substrate (1) and expose the alignment mark protruding structure (211).
9. The method according to claim 2, characterized in that The step of providing a substrate (1) comprises: A through hole is opened on the top of the substrate (1), wherein the through hole is connected to the bottom metal (71); and Coating the inner wall of the through hole with a conductive material and embedding a third dielectric material inside the side wall formed by the conductive material to form the bottom through hole conductive structure (72); Under the same etching conditions, the etching rate of the first dielectric material is greater than the etching rate of the third dielectric material.
10. The method according to claim 9, characterized in that An etching selectivity ratio between the first dielectric material and the third dielectric material is not less than 10:
1.
11. The method according to claim 9, characterized in that The conductive material includes at least one of Cu, Ta, TaN, Ti, TiN, W and WN; The material of the bottom metal (71) includes at least one of Cu, Ta, TaN, Ti, TiN, W and WN.
12. The method according to claim 2, characterized in that The step of removing the alignment mark protruding structure (211) comprises: The alignment mark protrusion structure (211) is removed by etching.
13. The method according to claim 2, characterized in that After the step of etching the magnetic tunnel junction film (6) based on the patterned second photoresist layer (42), the method further comprises: A fourth dielectric material is deposited on the second dielectric layer (22) to form a protective layer (73) covering the magnetic tunnel junction (61).
14. The method according to any one of claims 1 to 11, characterized in that The material of the substrate (1) includes at least one of SiN, SiO, SiON and SiOC.