Semiconductor memory device

Abstract

A semiconductor memory device includes a plurality of memory chips 1-1, 1-2 stacked with each other, and has a novel structure different from the prior art. The semiconductor memory device includes the memory chips 1-1, 1-2 stacked with each other. The memory chips 1-1, 1-2 include circuit elements and wirings arranged in the same layout between the memory chips 1-1, 1-2. The memory chips 1-1, 1-2 each have a surface and a back surface opposite to each other, and a plurality of first terminals arranged on the surface. In each of the memory chips 1-1, 1-2, the plurality of first terminals are arranged in mirror symmetry with respect to a symmetry plane orthogonal to the surface and the back surface. The memory chips 1-1, 1-2 are stacked in a manner that the surface of the memory chip 1-1 is in contact with the surface of the memory chip 1-2, and the plurality of first terminals of the memory chip 1-1 are connected to the plurality of first terminals of the memory chip 1-2.

Description

[0001] Cross-reference to related applications

[0002] This disclosure claims priority to Japanese Patent Application No. 2025-030357, filed on February 27, 2025, entitled "Semiconductor Memory Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor memory device. Background Technology

[0004] In recent years, with the improvement of GPU (Graphics Processing Unit) and CPU (Central Processing Unit) performance, the requirements for high-capacity, high-performance semiconductor storage devices have become extremely high. However, in order to meet the power supply constraints and / or thermal management constraints of the entire system, it is necessary to achieve low power consumption while maintaining high performance.

[0005] Existing technologies have proposed a semiconductor memory device that uses three-dimensional stacking of semiconductor chips to solve this problem. JEDEC (Joint Electron Device Engineering Council) has also standardized the HBM (High Bandwidth Memory) series, and the products are already on the market.

[0006] For example, Japanese Patent Publication No. 2011-166147 discloses a semiconductor memory device having multiple semiconductor chips stacked on top of each other. Summary of the Invention

[0007] According to the semiconductor memory device in Patent Document 1, multiple semiconductor chips are stacked by repeatedly connecting the back surfaces of other semiconductor chips to the front surface of one semiconductor chip. Hereinafter, this connection of semiconductor chips will be referred to as an "F2B (face to back) connection".

[0008] In order to provide high-capacity, high-performance, low-power 3D memory at a low cost, it is not only necessary to have F2B connectivity, but also various forms of semiconductor memory devices.

[0009] The purpose of this disclosure is to provide a semiconductor memory device comprising a plurality of semiconductor chips stacked on top of each other and having a novel structure different from the prior art.

[0010] An aspect of the present disclosure relates to a semiconductor storage device, and the semiconductor storage device includes a plurality of semiconductor chips stacked with each other,

[0011] The plurality of semiconductor chips includes circuit elements and wirings configured between the plurality of semiconductor chips in the same layout,

[0012] The plurality of semiconductor chips each has a first face and a second face opposite to each other, and a plurality of first terminals configured on the first face,

[0013] In each of the plurality of semiconductor chips, the plurality of first terminals are configured in mirror symmetry with respect to a symmetry plane orthogonal to the first face and the second face,

[0014] The plurality of semiconductor chips includes a first semiconductor chip and a second semiconductor chip,

[0015] The first semiconductor chip and the second semiconductor chip are stacked with the first face of the first semiconductor chip abutting the first face of the second semiconductor chip, and the plurality of first terminals of the first semiconductor chip are connected to the plurality of first terminals of the second semiconductor chip.

[0016] According to an aspect of the present disclosure, it is possible to provide a semiconductor storage device having a novel structure different from the existing F2B connection. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a plan view showing a terminal layout of memory chips 1-1, 1-2 of a semiconductor storage device according to a first embodiment.

[0018] Figure 2 is a longitudinal sectional view showing a structure of the semiconductor storage device according to the first embodiment.

[0019] Figure 3 is a plan view showing a terminal layout of memory chips 2-1, 2-2 of a semiconductor storage device according to a first comparative example.

[0020] Figure 4 is a longitudinal sectional view showing a structure of the semiconductor storage device according to the first comparative example.

[0021] Figure 5 is a plan view showing a terminal layout of memory chips 3-1, 3-2 of a semiconductor storage device according to a second comparative example.

[0022] Figure 6 is a longitudinal sectional view showing a structure of the semiconductor storage device according to the second comparative example.

[0023] Figure 7is a longitudinal sectional view showing other structures of the semiconductor storage device according to the first embodiment.

[0024] Figure 8 is a plan view showing a terminal layout of the memory chip 4-1 to 4-4 of the semiconductor storage device according to the second embodiment.

[0025] Figure 9 is a longitudinal sectional view showing a wiring layout of the memory chip 4-1 of Figure 8

[0026] Figure 10 is a longitudinal sectional view showing structures of the semiconductor storage device according to the second embodiment.

[0027] Figure 11 is a diagram showing multipoint connection of the semiconductor storage device.

[0028] Figure 12 is a diagram showing spiral connection of the semiconductor storage device.

[0029] Figure 13 is a diagram showing manufacturing steps of the semiconductor storage device of Figure 10

[0030] Figure 14 is a longitudinal sectional view showing structures of the semiconductor storage device according to the third comparative example.

[0031] Figure 15 is a longitudinal sectional view showing structures of the semiconductor storage device according to the third comparative example.

[0032] Figure 16 is a plan view showing a terminal layout of the memory chip 7-1 to 7-4 of the semiconductor storage device according to the modified example of the second embodiment.

[0033] REFERENCE NUMERALS: 1-1 to 1-4, 4-1, 4-4, 7-1 to 7-4 memory chip; 10-1 to 10-4 semiconductor substrate; 10a-1 to 10a-4 surface of semiconductor substrate; 10b-1 to 10b-4 back surface of semiconductor substrate; 11-1 to 11-4 circuit element; 21-1 to 28-4 terminal of surface; 31-1 to 38-4 terminal of surface; 41, 41-1 to 41-4 wiring layer; 42, 42-1 to 42-4 wiring via; 43, 43-1 to 43-4 TSV (through silicon via). DETAILED DESCRIPTION

[0034] Hereinafter, a semiconductor storage device according to an embodiment of the present disclosure will be described with reference to the drawings. In each drawing, the same reference numerals denote the same constituent elements.​​

[0035] [First Implementation]

[0036] Figure 1 This is a plan view showing the terminal layout of memory chips 1-1 and 1-2 of the semiconductor memory device according to the first embodiment. Figure 2 This is a longitudinal sectional view showing the structure of the semiconductor memory device according to the first embodiment. Figure 1 and Figure 2 The semiconductor memory device includes memory chips 1-1 and 1-2 stacked on top of each other.

[0037] exist Figure 1 and Figure 2 In the diagram, Xa, Ya, Za represent the local coordinate system of memory chip 1-1, and Xb, Yb, Zb represent the local coordinate system of memory chip 1-2. Furthermore, X, (Y,)Z represents the global coordinate system of the semiconductor memory device. Other figures also refer to the local and global coordinate systems.

[0038] Memory chips 1-1 and 1-2 are examples of semiconductor chips that have circuit elements for memory formed on a semiconductor substrate. Memory chips 1-1 and 1-2 generally have the same structure as each other. At least memory chips 1-1 and 1-2 include circuit elements and wiring arranged in the same layout between memory chips 1-1 and 1-2.

[0039] Please refer to Figure 1 The memory chip 1-1 has a semiconductor substrate with a surface 10a-1 and a back surface 10b-1 facing each other. Furthermore, the memory chip 1-1 has terminals 21-1 to 28-1 disposed on the surface 10a-1 and terminals 31-1 to 38-1 disposed on the back surface 10b-1. Terminals 21-1 to 28-1 are arranged in a mirror-symmetric configuration about a plane of symmetry orthogonal to the surface 10a-1 and the back surface 10b-1. Similarly, terminals 31-1 to 38-1 are also arranged in a mirror-symmetric configuration about the same plane of symmetry.

[0040] Similarly, memory chip 1-2 has a semiconductor substrate with a surface 10a-2 and a back surface 10b-2 facing each other. Memory chip 1-2 has terminals 21-2 to 28-2 disposed on surface 10a-2 and terminals 31-2 to 38-2 disposed on the back surface 10b-2. Terminals 21-2 to 28-2 are arranged in a mirror-symmetric configuration about a plane of symmetry orthogonal to surface 10a-2 and back surface 10b-2. Similarly, terminals 31-2 to 38-2 are also arranged in a mirror-symmetric configuration about the same plane of symmetry.

[0041] In this document, the surface of the semiconductor substrate is also referred to as the "first surface," and the reverse side is also referred to as the "second surface." Furthermore, in this document, the terminals disposed on the surface of the semiconductor substrate are also referred to as the "first terminal," and the terminals disposed on the reverse side of the semiconductor substrate are also referred to as the "second terminal."

[0042] The memory chip 1-1 includes circuit elements 11-1 to 14-1 formed on an inner layer of a semiconductor substrate. Circuit elements 11-1 to 14-1 are associated with predetermined functions of the semiconductor memory device, such as including memory elements, input / output circuits, address (e.g., row address) decoders, command decoders, and power supplies. Circuit element 11-1 is connected to terminals 21-1, 22-1, 31-1, and 32-1. Circuit element 12-1 is connected to terminals 23-1, 24-1, 33-1, and 34-1. Circuit element 13-1 is connected to terminals 25-1, 26-1, 35-1, and 36-1. Circuit element 14-1 is connected to terminals 27-1, 28-1, 37-1, and 38-1.

[0043] Similarly, the memory chip 1-2 includes circuit elements 11-2 to 14-2 formed on an inner layer of a semiconductor substrate. Circuit elements 11-2 to 14-2 are associated with predetermined functions of the semiconductor memory device. Circuit element 11-2 is connected to terminals 21-2, 22-2, 31-2, and 32-2. Circuit element 12-2 is connected to terminals 23-2, 24-2, 33-2, and 34-2. Circuit element 13-2 is connected to terminals 25-2, 26-2, 35-2, and 36-2. Circuit element 14-2 is connected to terminals 27-2, 28-2, 37-2, and 38-2.

[0044] like Figure 2 As shown, memory chips 1-1 and 1-2 are stacked such that surface 10a-2 of memory chip 1-2 is in contact with surface 10a-1 of memory chip 1-1. Therefore, terminals 21-2 to 28-2 of memory chip 1-2 are connected to terminals 21-1 to 28-1 of memory chip 1-1. Hereinafter, this type of memory chip connection will be referred to as an "F2F (face-to-face) connection." When memory chips 1-1 and 1-2 are stacked in this manner, Figure 1 In the figure, each pair of terminals, which are given the same reference numerals A to H, are interconnected. Terminal 21-1 of memory chip 1-1 is connected to terminal 24-2 of memory chip 1-2 (reference numeral A), terminal 22-1 of memory chip 1-1 is connected to terminal 23-2 of memory chip 1-2 (reference numeral B), and the others are connected in the same way. Terminal 28-1 of memory chip 1-1 is connected to terminal 25-2 of memory chip 1-2 (reference numeral H).

[0045] exist Figure 1In the diagram, thick dashed lines indicate that two memory chips are stacked with their surfaces or backs touching each other.

[0046] Memory chip 1-1 has wiring formed on an inner layer of semiconductor substrate 10-1, including wiring layer 41-1, wiring via 42-1, and TSV (through silicon via) 43-1. Terminal 21-1 is connected to circuit element 11-1 of memory chip 1-1 via wiring layer 41-1, wiring via 42-1, and TSV 43-1. Similarly, memory chip 1-2 has wiring formed on an inner layer of semiconductor substrate 10-2, including wiring layer 41-2, wiring via 42-2, and TSV 43-2. ​​Terminal 24-2 is connected to circuit element 12-2 of memory chip 1-2 via wiring layer 41-2, wiring via 42-2, and TSV 43-2. ​​By interconnecting terminals 21-1 and 24-2, the wiring and circuit elements of different memory chips 1-1 and 1-2 are interconnected. For the sake of simplicity, Figure 2 Only the portions related to terminals 21-1 and 24-2 are shown; the remaining terminals are similarly connected to the wiring and circuit elements of memory chips 1-1 and 1-2.

[0047] Please refer to Figure 1 In memory chip 1-1, terminals 21-1 to 28-1, each pair of terminals arranged in a mirror-symmetric configuration with respect to the plane of symmetry, are connected to wiring associated with the same function. Similarly, in memory chip 1-2, terminals 21-2 to 28-2, each pair of terminals arranged in a mirror-symmetric configuration with respect to the plane of symmetry, are connected to wiring associated with the same function. These wirings include data signal lines, address signal lines, command signal lines, power supply lines, etc.

[0048] For example, assume that circuit elements 11-1 to 14-1 of memory chip 1-1 and circuit elements 11-2 to 14-2 of memory chip 1-2 constitute a memory array. In this case, terminals 21-1 and 22-1 of memory chip 1-1 are connected to the address signal line RA0 and data signal line DQ0 of circuit element 11-1, respectively. Additionally, terminals 23-1 and 24-1 of memory chip 1-1 are connected to the data signal line DQ0 and address signal line RA0 of circuit element 12-1, respectively. Furthermore, terminals 25-1 and 26-1 of memory chip 1-1 are connected to the address signal line RA0 and data signal line DQ0 of circuit element 13-1, respectively. Finally, terminals 27-1 and 28-1 of memory chip 1-1 are connected to the data signal line DQ0 and address signal line RA0 of circuit element 14-1, respectively. Similarly, terminals 21-2 to 28-2 of memory chip 1-2 are also connected to the address signal lines and data signal lines of circuit elements 11-2 to 14-2.

[0049] When memory chips 1-1 and 1-2 are stacked via an F2F connection, as mentioned earlier, terminal 21-1 of memory chip 1-1 is connected to terminal 24-2 of memory chip 1-2. At this time, terminals 21-1 and 24-2 are both connected to the address signal line RA0 of the memory array. Therefore, the address is transmitted normally via terminals 21-1 and 24-2 and the wiring connected to them. Similarly, address and data can be transmitted normally via each other pair of interconnected terminals of memory chips 1-1 and 1-2 and the wiring connected to them.

[0050] Thus, in each of memory chips 1-1 and 1-2, the terminals connected to the wiring associated with the same function are arranged in a mirror-symmetric configuration about the plane of symmetry. Therefore, each pair of terminals interconnecting memory chips 1-1 and 1-2, that is... Figure 1 Each pair of terminals, which are assigned the same reference numerals A to H, is connected to wiring associated with the same function.

[0051] The terminals of memory chips 1-1 and 1-2 are arranged in a mirror-symmetric configuration about the plane of symmetry, while other components of memory chips 1-1 and 1-2, such as circuit elements and wiring, may not be arranged in a mirror-symmetric configuration.

[0052] Memory chips 1-1 and 1-2 include circuit elements and wiring arranged in the same layout between memory chips 1-1 and 1-2. Therefore, memory chips 1-1 and 1-2 can be manufactured using substantially the same mask set. Here, "substantially the same mask set" means that all or part of the mask set used to form the layers of the memory chip is identical. Even if the masks of layers unrelated to the features of this embodiment are partially different, they are still included in the "substantially the same mask set".

[0053] Here, for reference Figure 3 to Figure 6 The semiconductor memory device involved in the comparative example will be described.

[0054] Figure 3 This is a plan view showing the terminal layout of memory chips 2-1 and 2-2 of the semiconductor memory device involved in the first comparative example. Figure 4 This is a longitudinal cross-sectional view showing the structure of the semiconductor memory device involved in the first comparative example. Figure 3 and Figure 4 The semiconductor memory device includes memory chips 2-1 and 2-2 stacked on top of each other.

[0055] Memory chips 2-1 and 2-2 generally have the same structure.

[0056] Please refer to Figure 3Memory chip 2-1 has a surface 10a-1 and a back surface 10b-1. Furthermore, memory chip 2-1 has terminals 21-1 to 24-1 disposed on surface 10a-1 and terminals 31-1 to 34-1 disposed on back surface 10b-1. Additionally, memory chip 2-1 includes circuit elements 11-1 and 12-1. Similarly, memory chip 2-2 has a surface 10a-2 and a back surface 10b-2. Memory chip 2-2 has terminals 21-2 to 24-2 disposed on surface 10a-2 and terminals 31-2 to 34-2 disposed on back surface 10b-2. Additionally, memory chip 2-2 includes circuit elements 11-2 and 12-2.

[0057] like Figure 4 As shown, memory chips 2-1 and 2-2 are stacked via an F2B connection, with the reverse side 10b-2 of memory chip 2-2 connected to the surface 10a-1 of memory chip 2-1. Thus, terminals 31-2 to 34-2 of memory chip 2-2 are connected to terminals 21-1 to 24-1 of memory chip 2-1. When memory chips 2-1 and 2-2 are stacked in this manner, Figure 3 In the figure, each pair of terminals, which are given the same reference numerals A to D, are connected to each other.

[0058] according to Figure 3 and Figure 4 The semiconductor memory device can easily connect the corresponding terminals of memory chips 2-1 and 2-2 by stacking them with F2B connection using memory chips 2-1 and 2-2 that have the same structure.

[0059] Figure 5 This is a plan view showing the terminal layout of memory chips 3-1 and 3-2 in the semiconductor memory device involved in the second comparative example. Figure 6 This is a longitudinal cross-sectional view showing the structure of the semiconductor memory device involved in the second comparative example. Figure 5 and Figure 6 The semiconductor memory device includes memory chips 3-1 and 3-2 stacked on top of each other.

[0060] Please refer to Figure 5 Memory chip 3-1 has a surface 10a-1 and a back surface 10b-1. Furthermore, memory chip 3-1 has terminals 21-1 to 24-1 disposed on surface 10a-1 and terminals 31-1 to 34-1 disposed on back surface 10b-1. Additionally, memory chip 3-1 includes circuit elements 11-1 and 12-1. Similarly, memory chip 3-2 has a surface 10a-2 and a back surface 10b-2. Memory chip 3-2 has terminals 21-2 to 24-2 disposed on surface 10a-2 and terminals 31-2 to 34-2 disposed on back surface 10b-2. Additionally, memory chip 3-2 includes circuit elements 11-2 and 12-2.

[0061] like Figure 6 As shown, memory chips 3-1 and 3-2 are stacked via an F2F connection, with surface 10a-2 of memory chip 3-2 connected to surface 10a-1 of memory chip 3-1. Thus, terminals 21-2 to 24-2 of memory chip 3-2 are connected to terminals 21-1 to 24-1 of memory chip 3-1. When memory chips 3-1 and 3-2 are stacked in this manner... Figure 5 In the figure, each pair of terminals, which are given the same reference numerals A to D, are connected to each other.

[0062] according to Figure 5 and Figure 6 In order to stack memory chips 3-1 and 3-2 via F2F connections to connect corresponding terminals of memory chips 2-1 and 2-2, memory chips 3-1 and 3-2 need to have terminals configured with different layouts. Therefore, at least two sets of mask groups with different portions related to the terminals are required, increasing manufacturing costs.

[0063] On the other hand, according to Figure 1 and Figure 2 The semiconductor memory device according to the first embodiment shown stacks memory chips 1-1 and 1-2, which have terminals arranged in a mirror-symmetric configuration about a plane of symmetry, via an F2F connection. This provides a semiconductor memory device with both existing F2B connections and novel structures different from existing F2F connections. According to the semiconductor memory device of the first embodiment, memory chips 1-1 and 1-2 can be manufactured using substantially the same mask set; therefore, with… Figure 5 and Figure 6 Compared to conventional semiconductor memory devices, this reduces manufacturing costs. Therefore, the semiconductor memory device according to the first embodiment can provide a high-capacity, high-performance, and low-power semiconductor memory device at a low cost.

[0064] Next, the terminals of the memory chip and other wiring connections will be explained.

[0065] In each of memory chips 1-1 and 1-2, each pair of terminals configured in a mirror-symmetric manner about the plane of symmetry is not limited to being connected to wiring associated with the same function, but may also be connected to wiring associated with different functions. In this case, in each of memory chips 1-1 and 1-2, the plurality of terminals on surface 10a-1 include a first terminal group and a second terminal group, which are configured in a mirror-symmetric manner about the plane of symmetry. The first terminal group and the second terminal group are connected to a plurality of wirings associated with the same functional group. Here, "functional group" refers to, for example, a plurality of bits of address, command, or data, and "a plurality of wirings associated with the same functional group" refers to a plurality of signal lines that transmit a plurality of bits of address, command, or data.

[0066] Please refer to Figure 1 The terminals 21-1 to 28-1 of memory chip 1-1 include, for example, a first terminal group 21-1, 22-1 and a second terminal group 23-1, 24-1, which are mirror-symmetrically arranged about a plane of symmetry. In this case, the first terminal groups 21-1 and 22-1 can be connected to the address signal lines RA0 and RA1 of circuit element 11-1, respectively, and the second terminal groups 23-1 and 24-1 can be connected to the address signal lines RA0 and RA1 of circuit element 12-1, respectively. In other words, the first terminal groups 21-1 and 22-1 and the second terminal groups 23-1 and 24-1 are connected to multiple wirings associated with the same functional group. Although the pair of terminals 21-1 and 24-1, which are mirror-symmetrically arranged about a plane of symmetry, are included in the same functional group, they are respectively connected to wirings associated with different functions, namely address signal lines RA0 and RA1. Similarly, although the pair of terminals 22-1 and 23-1, which are mirror-symmetrical about the plane of symmetry, are included in the same functional group, they are respectively connected to wiring associated with different functions, namely address signal lines RA1 and RA0.

[0067] Similarly, the terminals 21-2 to 28-2 of the memory chip 1-2 may also include a first terminal group and a second terminal group, which are configured in a mirror-symmetric manner about a plane of symmetry and are connected to multiple wirings associated with the same functional group.

[0068] Each pair of terminals, arranged in a mirror-symmetric configuration, is connected to signal lines for different bits of the transmitted address. The first and second terminal groups as a whole are connected to multiple wirings associated with the same multiple bits of the address. The address is transmitted normally via the first and second terminal groups as a whole and the wirings connected to them.

[0069] However, when testing a memory array, if the address, command, or data signals do not have a pattern that can apply appropriate noise or stress to the memory array, defects in the memory array may not be detected. Considering this, a first terminal group and a second terminal group that can apply appropriate noise or stress to the memory array during testing can be selected.

[0070] Next, other structures of the semiconductor memory device according to the first embodiment will be described.

[0071] Figure 7 This is a longitudinal sectional view showing other structures of the semiconductor memory device according to the first embodiment. Figure 7 The semiconductor memory device includes memory chips 1-1 to 1-4 stacked on top of each other.

[0072] Figure 7 The configuration of memory chips 1-1 to 1-2 is similar to Figure 1 and Figure 2 The memory chips 1-1 to 1-2 are the same.

[0073] The configuration of memory chips 1-3 to 1-4 and Figure 1 and Figure 2 The memory chips 1-1 to 1-2 are identical. Memory chips 1-3 and 1-4 are stacked with the surface of memory chip 1-4 connected to the surface of memory chip 1-3, i.e., via an F2F connection. Therefore, the terminals on the surface of memory chip 1-4 are connected to the terminals on the surface of memory chip 1-3.

[0074] Memory chips 1-2 and 1-3 are stacked with the reverse side of memory chip 1-3 connected to the reverse side of memory chip 1-2. Therefore, the terminals on the reverse side of memory chip 1-3 are connected to the terminals on the reverse side of memory chip 1-2. Hereinafter, this type of memory chip connection will be referred to as a "B2B (back to back) connection".

[0075] In each of memory chips 1-1 to 1-4, each pair of terminals on the reverse side of the memory chip, arranged in a mirror-symmetric configuration about a plane of symmetry, can be connected to wiring associated with the same function. Additionally, in each of memory chips 1-1 to 1-4, the multiple terminals on the reverse side of the memory chip may include a third terminal group and a fourth terminal group, which are mirror-symmetric configurations about a plane of symmetry and connected to multiple wirings associated with the same functional group. The third and fourth terminal groups can be selected to apply appropriate noise or stress to the memory array during testing.

[0076] according to Figure 7In a semiconductor memory device, memory chips 1-1 to 1-4 are stacked alternately via F2F and B2B connections. Similarly, more than four memory chips can also be stacked alternately via F2F and B2B connections.

[0077] [Second Implementation]

[0078] In the second embodiment, the method of reducing the load on the signal lines connected to the terminals of the memory chip to improve the signal transmission speed is explained.

[0079] Figure 8 This is a plan view showing the terminal layout of the memory chips 4-1 to 4-4 of the semiconductor memory device according to the second embodiment.

[0080] Memory chips 4-1 to 4-4 generally have the same structure as each other. At least memory chips 4-1 to 4-4 include circuit elements and wiring arranged in the same layout between memory chips 4-1 to 4-4.

[0081] The memory chip 4-1 has a surface 10a-1 and a back surface 10b-1. Furthermore, the memory chip 4-1 has terminals 21-1 to 28-1 disposed on the surface 10a-1 and terminals 31-1 to 38-1 disposed on the back surface 10b-1. Terminals 21-1 to 28-1 are arranged in a mirror-symmetric configuration about a plane of symmetry orthogonal to the surface 10a-1 and the back surface 10b-1. Similarly, terminals 31-1 to 38-1 are also arranged in a mirror-symmetric configuration about the same plane of symmetry.

[0082] The memory chip 4-2 has a surface 10a-2 and a back surface 10b-2. The memory chip 4-2 has terminals 21-2 to 28-2 disposed on the surface 10a-2 and terminals 31-2 to 38-2 disposed on the back surface 10b-2. Terminals 21-2 to 28-2 are arranged in a mirror-symmetric configuration about a plane of symmetry orthogonal to the surface 10a-2 and the back surface 10b-2. Similarly, terminals 31-2 to 38-2 are also arranged in a mirror-symmetric configuration about the same plane of symmetry.

[0083] The memory chip 4-3 has a surface 10a-3 and a back surface 10b-3. Furthermore, the memory chip 4-3 has terminals 21-3 to 28-3 disposed on the surface 10a-3 and terminals 31-3 to 38-3 disposed on the back surface 10b-3. Terminals 21-3 to 28-3 are arranged in a mirror-symmetric configuration about a plane of symmetry orthogonal to the surface 10a-3 and the back surface 10b-3. Similarly, terminals 31-3 to 38-3 are also arranged in a mirror-symmetric configuration about the same plane of symmetry.

[0084] The memory chip 4-4 has a surface 10a-4 and a back surface 10b-4. Furthermore, the memory chip 4-4 has terminals 21-4 to 28-4 disposed on the surface 10a-4 and terminals 31-4 to 38-4 disposed on the back surface 10b-4. Terminals 21-4 to 28-4 are arranged in a mirror-symmetric configuration about a plane of symmetry orthogonal to the surface 10a-4 and the back surface 10b-4. Similarly, terminals 31-4 to 38-4 are also arranged in a mirror-symmetric configuration about the same plane of symmetry.

[0085] The memory chip 4-1 includes circuit elements 11-1 and 12-1 formed on an inner layer of a semiconductor substrate. Circuit element 11-1 is connected to terminals 22-1 and 31-1. Circuit element 12-1 is connected to terminals 28-1 and 37-1.

[0086] The memory chip 4-2 has circuit elements 11-2 and 12-2 formed on an inner layer of a semiconductor substrate. Circuit element 11-2 is connected to terminals 22-2 and 31-2. Circuit element 12-2 is connected to terminals 28-2 and 37-2.

[0087] The memory chip 4-3 has circuit elements 11-3 and 12-3 formed on an inner layer of a semiconductor substrate. Circuit element 11-3 is connected to terminals 22-3 and 31-3. Circuit element 12-3 is connected to terminals 28-3 and 37-3.

[0088] The memory chip 4-4 has circuit elements 11-4 and 12-4 formed on an inner layer of a semiconductor substrate. Circuit element 11-4 is connected to terminals 22-4 and 31-4. Circuit element 12-4 is connected to terminals 28-4 and 37-4.

[0089] Figure 9 It is shown Figure 8 A longitudinal cross-sectional view of the wiring layout of memory chip 4-1. Memory chip 4-1 has wiring formed on an inner layer of semiconductor substrate 10-1, including wiring layer 41, wiring vias 42, and TSVs 43. Terminals 21-1 to 28-1 on surface 10a-1 are connected to the intermediate wiring layer 41 via wiring vias 42. The intermediate wiring layer 41 is connected to terminals 31-1 to 38-1 on the reverse side 10b-1 via TSVs 43. Wiring vias 42 and TSVs 43 are connected to wiring layer 41 at mutually offset locations in the horizontal direction.

[0090] Terminals 21-1 to 28-1 on surface 10a-1 include a first terminal group 21-1 to 24-1 and a second terminal group 25-1 to 28-1, which are mirror-symmetrical about a plane of symmetry. Terminals 31-1 to 38-1 on reverse side 10b-1 include a third terminal group 31-1 to 34-1 and a fourth terminal group 35-1 to 38-1, which are mirror-symmetrical about a plane of symmetry. The first terminal group 21-1 to 24-1 and the third terminal group 31-1 to 34-1 are located on the same side of the plane of symmetry. Figure 9 (On the left side). The second terminal group 25-1 to 28-1 and the fourth terminal group 35-1 to 38-1 are also arranged on the same side of the plane of symmetry. Figure 9 (on the right side).

[0091] The first terminal groups 21-1 to 24-1 and the third terminal groups 31-1 to 34-1 are interconnected via a first wiring group. Specifically, terminals 21-1 to 24-1 are connected to terminals 34-1, 31-1, 32-1, and 33-1, respectively. Additionally, the second terminal groups 25-1 to 28-1 and the fourth terminal groups 35-1 to 38-1 are interconnected via a second wiring group. Specifically, terminals 25-1 to 28-1 are connected to terminals 38-1, 35-1, 36-1, and 37-1, respectively.

[0092] The first and second wiring groups have an asymmetrical layout relative to the plane of symmetry. For example, as... Figure 9 As shown, the second wiring group has a layout that is a translation of the first wiring group, that is, a layout that is symmetrical to the translation of the first wiring group.

[0093] As previously described, circuit element 11-1 is connected to terminals 22-1 and 31-1, and circuit element 12-1 is connected to terminals 28-1 and 37-1. Therefore, only the wiring in the first wiring group that connects terminals 22-1 and 31-1 is connected to circuit element 11-1; the remaining wiring in the first wiring group is not connected to any circuit element. Similarly, only the wiring in the second wiring group that connects terminals 28-1 and 37-1 is connected to circuit element 12-1; the remaining wiring in the second wiring group is not connected to any circuit element. In memory chip 4-1, the wiring not connected to any of circuit elements 11-1 or 11-2 is connected to any of the circuit elements 11-2 to 11-4 of the other memory chips 4-2 to 4-3, as described later.

[0094] Figure 8 The configuration of memory chips 4-2 to 4-4 is also similar to Figure 9 The memory chip 4-1 is the same.

[0095] Figure 10This is a longitudinal sectional view showing the structure of the semiconductor memory device according to the second embodiment. Figure 10 Simplified illustration Figure 9 Wiring. Figure 10 Semiconductor memory devices include those with Figure 7 Similarly, memory chips 4-1 to 4-4 are stacked alternately via F2F and B2B connections. When memory chips 4-1 to 4-4 are stacked in this manner, Figure 8 In this configuration, terminals labeled A through H are interconnected directly or via wiring from memory chips 4-1 through 4-4.

[0096] Please refer to Figure 10 The terminal designated A and the wiring connecting them are connected only to circuit element 11-1, with no other circuit elements connected. Similarly, the terminal designated B and the wiring connecting them are connected only to circuit element 11-2, with no other circuit elements connected. Furthermore, the terminal designated C and the wiring connecting them are connected only to circuit element 11-3, with no other circuit elements connected. Finally, the terminal designated D and the wiring connecting them are connected only to circuit element 11-4, with no other circuit elements connected. Therefore, Figure 10 The semiconductor memory device uses a spiral connection to connect the circuit elements 11-1 to 11-4 to the memory chips 4-1 to 4-4.

[0097] Figure 11 This is a diagram showing the multi-point connections of a semiconductor memory device. Figure 11 The semiconductor memory device includes memory chips 5-1 to 5-4 stacked on top of each other. Reference numerals A to D indicate signal lines spanning multiple memory chips 5-1 to 5-4, including terminals of each memory chip 5-1 to 5-4 and wiring connecting the terminals. Memory chip 5-1 has four circuit elements 11-1 to 14-1, and other memory chips 5-2 to 5-3 also each have four circuit elements. These circuit elements are, for example, transceiver circuits for signals transmitted via signal lines. Signal line A has four circuit elements 11-1 to 11-4 connected to it, and other signal lines B to D also have four circuit elements connected to them respectively. Figure 11 This illustrates a "multi-point connection" where multiple circuit elements, including multiple memory chips 5-1 to 5-4, are connected to each signal line. For example, when the controller of the semiconductor memory device (not shown) communicates with circuit element 11-1 via signal line A, circuit elements 11-2 to 11-4 connected to the same signal line A are in a non-operating state, ceasing signal transmission and reception. However, even when circuit elements 11-2 to 11-4 are in a non-operating state, they still act as a load for circuit element 11-1. Therefore, multi-point connections are not suitable for high-speed signal transmission.

[0098] Figure 12 This is a diagram showing the spiral connection of a semiconductor memory device. Figure 12 Equivalent to show Figure 10 The structure of a semiconductor memory device. For example... Figure 12 As shown, signal line A is only connected to circuit element 11-1, and no other circuit elements are connected. Similarly, signal line B is only connected to circuit element 11-2, and no other circuit elements are connected. Signal line C is only connected to circuit element 11-3, and no other circuit elements are connected. Signal line D is only connected to circuit element 11-4, and no other circuit elements are connected. Figure 12 This illustrates a "spiral connection" where the connection points of signal lines and circuit elements shift as the memory chip moves. Circuit elements 11-1 to 11-4 can operate in parallel or simultaneously. No circuit elements that would constitute an additional load are connected to signal lines A to D, making it suitable for high-speed signal transmission.

[0099] Memory chips 4-1 to 4-4 include circuit elements and wiring arranged in the same layout between memory chips 4-1 to 4-4. Therefore, memory chips 4-1 to 4-4 can be manufactured using substantially the same mask set.

[0100] Figure 13 It is shown Figure 10 A diagram illustrating the manufacturing process of a semiconductor memory device. (Reference) Figure 13 This section explains how a spiral connection is achieved by alternately stacking memory chips 4-1 to 4-4 using F2F and B2B connections. As mentioned earlier, memory chips 4-1 to 4-4 generally have the same structure, therefore... Figure 13 Memory chips 4-1 and 4-2 also have the same structure. The terminal groups of memory chips 4-1 and 4-2 are arranged in a mirror-symmetric configuration about the plane of symmetry, and the wiring groups of memory chips 4-1 and 4-2 have a mutually translated symmetrical layout. Therefore, memory chip 4-2, after being rotated 180 degrees, has essentially the same structure as before the rotation. Memory chips 4-1 to 4-4 are alternately stacked using F2F and B2B connections to obtain… Figure 10 The semiconductor memory device achieves a spiral connection.

[0101] Figure 14 This is a diagram illustrating the manufacturing process of the semiconductor memory device involved in the third comparative example. Figure 15 This is a longitudinal sectional view showing the structure of the semiconductor memory device involved in the third comparative example. Figure 14 and Figure 15The semiconductor memory device includes memory chips 6-1 to 6-4 stacked on top of each other. Each of the memory chips 6-1 to 6-4 has two sets of wiring groups that are mirror-symmetrical with respect to the plane of symmetry. At this time, memory chip 6-2, rotated 180 degrees... Figure 14 Terminals 31-2 to 38-2 on the reverse side 10b-2 of the middle section are connected to terminals 31-1 to 38-1 on the reverse side 10b-2 of the memory chip 6-1 via wiring. As a result, it can be seen that... Figure 15 As shown, even if memory chips 6-1 to 6-4 are stacked alternately through F2F and B2B connections, a spiral connection cannot be achieved.

[0102] When the circuit elements 11-1 to 11-4 are connected to the wiring of each memory chip 4-1 to 4-4 in a spiral manner, the wiring included in the first wiring group and the second wiring group of each memory chip 4-1 to 4-4 can be associated with the same functional group. Furthermore, the wiring included in the first wiring group of each memory chip 4-1 to 4-4 can be associated with at least two functions, and the wiring included in the second wiring group can be associated with at least two functions.

[0103] For example, please refer to Figure 10 On surfaces 10a-1 to 10a-4 of each memory chip 4-1 to 4-4, the odd-numbered terminals on the left side of the symmetry plane (e.g., terminals 21-1, 23-1) and the even-numbered terminals on the right side of the symmetry plane (e.g., terminals 26-1, 28-1) have the same function. Similarly, the even-numbered terminals on the left side of the symmetry plane (e.g., terminals 22-1, 24-1) need to have the same function as the odd-numbered terminals on the right side of the symmetry plane (e.g., terminals 25-1, 27-1). In other combinations, terminals for signals with different functions and / or power supplies with different levels can be arranged in a mirror symmetry configuration. Assuming that terminal 31-1 of memory chip 4-1 is connected to the address decoder, and terminal 38-1 at its mirror symmetry position is connected to the input / output circuit, then terminal 28-2 of memory chip 4-2 is connected to a different signal line than terminal 31-1, so that address and signal can be transmitted normally even if they are not associated with the same function. Terminal 21-3 of memory chip 4-3 has the same coordinates as terminal 21-1 of memory chip 4-1 in the XY plane. Therefore, terminal 21-3 is connected to the address decoder. Similarly, terminal 28-4 of memory chip 4-4 is connected to a different signal line than terminal 31-1, so address and signal can be transmitted normally even if they are not associated with the same function.

[0104] according to Figure 8 to Figure 10The semiconductor memory device according to the second embodiment shown can alternately stack memory chips 4-1 to 4-4 having terminals arranged in a mirror-symmetric configuration about the plane of symmetry via F2F connections and B2B connections. Furthermore, according to the semiconductor memory device according to the second embodiment, by having a terminal group arranged in a mirror-symmetric configuration about the plane of symmetry and a translationally symmetrical wiring group, the memory chips 4-1 to 4-4 can be alternately stacked via F2F connections and B2B connections to achieve a spiral connection. Thus, a semiconductor memory device with a novel structure different from the existing F2F connections can be provided. According to the semiconductor memory device according to the second embodiment, the memory chips 4-1 to 4-4 can be manufactured using substantially the same mask set, thereby reducing manufacturing costs. Therefore, the semiconductor memory device according to the second embodiment can provide a high-capacity, high-performance, and low-power semiconductor memory device at a low cost.

[0105] Among them, spiral connection means that as the memory chip moves, if the connection points of signal lines and circuit elements are logically offset, the wiring does not need to have a physical spiral shape.

[0106] Figure 16 This is a plan view showing the terminal layout of memory chips 7-1 to 7-4 in a semiconductor memory device according to a modified example of the second embodiment. Memory chips 7-1 to 7-4 generally have the same structure as each other. At least memory chips 7-1 to 7-4 include circuit elements and wiring arranged in the same layout between memory chips 7-1 to 7-4. Memory chips 7-1 to 7-4 have terminals arranged in the same layout as... Figure 8 Terminals configured with different layouts. Figure 16 Semiconductor memory devices are also related to Figure 8 to Figure 10 Similarly, semiconductor memory devices can achieve a spiral connection by alternately stacking memory chips 7-1 to 7-4 through F2F and B2B connections.

[0107] [Other Implementation Methods]

[0108] Semiconductor memory devices can have more than four memory chips.

[0109] Semiconductor memory devices may have a different terminal layout than those described above.

[0110] When using F2F and / or B2B connections, the layout of the terminals on the surface of each memory chip may differ from the layout of the terminals on the reverse side.

[0111] [Summary of Implementation Methods]

[0112] The first aspect of this disclosure relates to a semiconductor memory device comprising a plurality of semiconductor chips stacked on top of each other.

[0113] The plurality of semiconductor chips include circuit elements and wiring arranged in the same layout among the plurality of semiconductor chips.

[0114] Each of the plurality of semiconductor chips has a first surface and a second surface that are opposite to each other, and a plurality of first terminals disposed on the first surface.

[0115] In each of the plurality of semiconductor chips, the plurality of first terminals are arranged in a mirror-symmetric configuration with respect to a symmetry plane orthogonal to the first and second surfaces.

[0116] The plurality of semiconductor chips includes a first semiconductor chip and a second semiconductor chip.

[0117] The first semiconductor chip and the second semiconductor chip are stacked such that the first surface of the first semiconductor chip is in contact with the first surface of the second semiconductor chip, and the plurality of first terminals of the first semiconductor chip are connected to the plurality of first terminals of the second semiconductor chip.

[0118] According to the semiconductor memory device of the second aspect of this disclosure, in the semiconductor memory device of the first aspect,

[0119] In each of the plurality of semiconductor chips, each pair of first terminals, which are configured in a mirror-symmetric manner about the plane of symmetry, is connected to wiring associated with the same function.

[0120] According to the semiconductor memory device of the third aspect of this disclosure, in the semiconductor memory device of the first aspect,

[0121] In each of the plurality of semiconductor chips, the plurality of first terminals include a first terminal group and a second terminal group, the first terminal group and the second terminal group being configured in a mirror-symmetric manner about the symmetry plane, and the first terminal group and the second terminal group being connected to a plurality of wirings associated with the same functional group.

[0122] According to the fourth aspect of this disclosure, in the semiconductor memory device of one of the first to third aspects,

[0123] Each of the plurality of semiconductor chips further has a plurality of second terminals disposed on the second surface.

[0124] In each of the plurality of semiconductor chips, the plurality of second terminals are arranged in a mirror-symmetric configuration about the symmetry plane.

[0125] The plurality of semiconductor chips includes a third semiconductor chip and a fourth semiconductor chip.

[0126] The third semiconductor chip and the fourth semiconductor chip are stacked such that the first surface of the third semiconductor chip is in contact with the first surface of the fourth semiconductor chip, and the plurality of first terminals of the third semiconductor chip are connected to the plurality of first terminals of the fourth semiconductor chip.

[0127] The second semiconductor chip and the third semiconductor chip are stacked such that the second surface of the second semiconductor chip is in contact with the second surface of the third semiconductor chip, and the plurality of second terminals of the second semiconductor chip are connected to the plurality of second terminals of the third semiconductor chip.

[0128] According to the semiconductor memory device of the fifth aspect of this disclosure, in the semiconductor memory device of the fourth aspect,

[0129] In each of the plurality of semiconductor chips, each pair of second terminals, which are configured in a mirror-symmetric manner about the plane of symmetry, is connected to wiring associated with the same function.

[0130] According to the semiconductor memory device according to the sixth aspect of this disclosure, in the semiconductor memory device according to the fourth aspect,

[0131] In each of the plurality of semiconductor chips, the plurality of second terminals include a third terminal group and a fourth terminal group, the third terminal group and the fourth terminal group being configured in a mirror-symmetric manner about the symmetry plane, the third terminal group and the fourth terminal group being connected to a set of wiring associated with the same functional group.

[0132] According to the semiconductor memory device of the seventh aspect of this disclosure, in the semiconductor memory device of any one of the fourth to sixth aspects, in each of the plurality of semiconductor chips,

[0133] The plurality of first terminals include a first terminal group and a second terminal group, wherein the first terminal group and the second terminal group are configured in a mirror-symmetrical manner about the symmetry plane.

[0134] The plurality of second terminals include a third terminal group and a fourth terminal group, the third terminal group and the fourth terminal group being arranged in a mirror-symmetrical configuration about the plane of symmetry.

[0135] The first terminal group and the third terminal group are configured on the same side of the plane of symmetry.

[0136] The first terminal group and the third terminal group are interconnected via the first wiring group.

[0137] The second terminal group and the fourth terminal group are interconnected via the second wiring group.

[0138] The first wiring group and the second wiring group have an asymmetrical layout relative to the plane of symmetry.

[0139] According to the semiconductor memory device according to the eighth aspect of this disclosure, in the semiconductor memory device according to the seventh aspect,

[0140] In each of the plurality of semiconductor chips, the second wiring group has a layout that is translationally symmetrical to the first wiring group.

[0141] According to the semiconductor memory device according to the ninth aspect of this disclosure, in the semiconductor memory device according to the seventh or eighth aspect,

[0142] In each of the plurality of semiconductor chips,

[0143] In the first wiring group, only one wire is connected to a circuit element; the remaining wires in the first wiring group are not connected to any circuit element.

[0144] In the second wiring group, only one wire is connected to the circuit element, and the remaining wires in the second wiring group are not connected to the circuit element.

[0145] According to the tenth aspect of this disclosure, in the semiconductor memory device according to any one of the seventh to ninth aspects,

[0146] In each of the plurality of semiconductor chips, the wiring included in the first wiring group and the second wiring group is associated with the same function.

[0147] According to the tenth aspect of this disclosure, in the semiconductor memory device according to any one of the seventh to ninth aspects,

[0148] In each of the plurality of semiconductor chips,

[0149] The wiring included in the first wiring group is associated with at least two functions.

[0150] The wiring included in the second wiring group is associated with the at least two functions.

[0151] [Industrial Availability]

[0152] According to one aspect of this disclosure, a semiconductor memory device is provided having a novel structure that differs from existing F2B connections.

Claims

1. A semiconductor memory device comprising a plurality of semiconductor chips stacked with each other, wherein the plurality of semiconductor chips comprises circuit elements and wirings arranged between the plurality of semiconductor chips in a same layout, the plurality of semiconductor chips each has a first face and a second face opposite to each other, and a plurality of first terminals arranged on the first face, in each of the plurality of semiconductor chips, the plurality of first terminals are arranged in mirror symmetry with respect to a symmetry plane orthogonal to the first face and the second face, the plurality of semiconductor chips comprises a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip are stacked with the first face of the first semiconductor chip abutting the first face of the second semiconductor chip, and the plurality of first terminals of the first semiconductor chip are connected to the plurality of first terminals of the second semiconductor chip, wherein the plurality of semiconductor chips each further has a plurality of second terminals arranged on the second face, wherein in each of the plurality of semiconductor chips, the plurality of first terminals comprises a first terminal group and a second terminal group, the first terminal group and the second terminal group are arranged in mirror symmetry with respect to the symmetry plane, the plurality of second terminals comprises a third terminal group and a fourth terminal group, the third terminal group and the fourth terminal group are arranged in mirror symmetry with respect to the symmetry plane, the first terminal group and the third terminal group are arranged on a same side of the symmetry plane, the first terminal group and the third terminal group are connected to each other via a first wiring group, the second terminal group and the fourth terminal group are connected to each other via a second wiring group, the first wiring group and the second wiring group have asymmetric layouts with respect to the symmetry plane; wherein in each of the plurality of semiconductor chips, only one wiring of the first wiring group is connected to a circuit element, and the remaining wirings of the first wiring group are not connected to a circuit element, only one wiring of the second wiring group is connected to a circuit element, and the remaining wirings of the second wiring group are not connected to a circuit element. In each of the plurality of semiconductor chips, each pair of first terminals arranged in mirror symmetry with respect to the symmetry plane is connected to a wiring associated with a same function.

2. The semiconductor memory device according to claim 1, wherein In each of the plurality of semiconductor chips, the plurality of first terminals comprises a first terminal group and a second terminal group arranged in mirror symmetry with respect to the symmetry plane, and the first terminal group and the second terminal group are connected to a plurality of wirings associated with a same group of functions.

3. The semiconductor memory device according to claim 1, wherein In each of the plurality of semiconductor chips, the plurality of second terminals are arranged in mirror symmetry with respect to the symmetry plane, 4. The semiconductor memory device according to claim 1, wherein the plurality of semiconductor chips comprises a third semiconductor chip and a fourth semiconductor chip, the third semiconductor chip and the fourth semiconductor chip are stacked with the first face of the third semiconductor chip abutting the first face of the fourth semiconductor chip, and the plurality of first terminals of the third semiconductor chip are connected to the plurality of first terminals of the fourth semiconductor chip, ​ The second semiconductor chip and the third semiconductor chip are stacked with the second face of the second semiconductor chip and the second face of the third semiconductor chip abutting, and the plurality of second terminals of the second semiconductor chip are connected to the plurality of second terminals of the third semiconductor chip.

5. The semiconductor memory device according to claim 4, wherein In each of the plurality of semiconductor chips, each pair of second terminals configured in mirror symmetry with respect to the symmetry plane is connected to wiring associated with the same function.

6. The semiconductor memory device according to claim 4, wherein In each of the plurality of semiconductor chips, the plurality of second terminals include a third terminal group and a fourth terminal group configured in mirror symmetry with respect to the symmetry plane, and the third terminal group and the fourth terminal group are connected to a group of wiring associated with the same function group.

7. The semiconductor memory device according to claim 1, wherein In each of the plurality of semiconductor chips, the second wiring group has a layout that is translationally symmetric to the first wiring group.

8. The semiconductor memory device according to claim 1, wherein In each of the plurality of semiconductor chips, the wiring included in the first wiring group and the second wiring group is associated with the same function group.

9. The semiconductor memory device according to claim 1, wherein, In each of the plurality of semiconductor chips, The wiring included in the first wiring group is associated with at least two functions, The wiring included in the second wiring group is associated with the at least two functions.

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