Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises the following steps: providing a semiconductor substrate of a first conductive type; forming a drift region above the semiconductor substrate; simultaneously forming a first trench and a second trench in the drift region, wherein the second trench is located on both sides of the second trench in a first direction, and the opening width of the first trench is greater than that of the second trench, and the depth of the first trench is less than that of the second trench; forming a shielding layer of a second conductive type outside the sidewall and the bottom of the second trench based on the second trench; forming a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure; and forming a first metal layer filling the second trench and covering the interlayer dielectric layer. The semiconductor structure and the preparation method thereof can significantly reduce the process complexity and cost, improve the manufacturing efficiency and yield, effectively reduce the electric field concentration effect at the corner of the trench gate structure, and significantly improve the device withstand voltage performance and reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] As the third-generation wide-bandgap semiconductor power device, silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) has significant advantages such as high withstand voltage, high frequency, high temperature and low loss, and is widely used in new energy vehicles, power grids, motor drives and other high-voltage and high-power fields. Compared with traditional planar MOSFET, SiC MOSFET with trench structure can significantly improve the performance of the device, and has become the focus of current research and industrial development.

[0003] In existing trench-type SiC MOSFETs, a single trench structure or a dual trench structure is generally used for design. Among them, the dual trench structure can effectively improve the electric field distribution of the device and reduce the local electric field intensity on the gate oxide layer by introducing an auxiliary trench (also known as a dummy trench or source trench) on both sides of the gate, thereby improving the anti-breakdown capability and reliability of the device.

[0004] However, the existing dual trench structure generally has the following deficiencies: the typical dummy trench structure is filled with metal materials (such as aluminum, tungsten, etc.), which requires multiple deposition and patterning steps. In particular, when achieving simultaneous consideration of the heavy-doped shielding layer and metal contact, additional high-energy ion implantation is required to improve the electric field distribution, which not only increases the manufacturing cost, but also reduces the process yield and repeatability. In some structures, there is an interface stress concentration problem between the dummy trench filling material and the surrounding layer structure, which easily leads to an excessively high electric field on the gate oxide layer, limiting the breakdown voltage of the device. At the same time, the design of the heavy-doped shielding layer is limited by the size of the trench structure, making it difficult to further reduce the on-resistance of the device. In some dual trench structures, the source contact metal is deeply embedded into the substrate, which easily forms a parasitic capacitance with the gate structure, resulting in a decrease in switching speed and efficiency of the device in high-frequency application scenarios.

[0005] Therefore, how to simplify the trench process flow, reduce the manufacturing cost, and further optimize the electric field distribution and on-state characteristics while ensuring high withstand voltage, high frequency, and high reliability of the device has become a key technical problem in the design and manufacture of the dual trench SiC MOSFET structure. SUMMARY

[0006] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof to solve the problems of complex process, high manufacturing cost, and difficult to balance the pressure resistance and conduction performance of the trench gate device structure in the prior art.

[0007] To achieve the above-mentioned purpose, in one aspect, the present application provides a semiconductor structure, comprising:

[0008] a semiconductor substrate of a first conductive type is provided;

[0009] a drift region is formed above the semiconductor substrate;

[0010] a first trench and a second trench are simultaneously formed in the drift region, wherein the second trench is located on both sides of the second trench in a first direction, and the opening width of the first trench is greater than the opening width of the second trench, and the depth of the first trench is less than the depth of the second trench;

[0011] a shielding layer of a second conductive type is formed outside the sidewall and bottom of the second trench based on the second trench;

[0012] a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure are formed;

[0013] a first metal layer filling the second trench and covering the interlayer dielectric layer is formed.

[0014] In one embodiment, the first trench and the second trench are simultaneously formed in the drift region, comprising:

[0015] a patterned photoresist layer is formed on the drift region, wherein the photoresist layer includes a first opening with a first opening width and a second opening with a second opening width, the first opening width is greater than the second opening width, and the first opening width and the second opening width correspond to the opening width of the first trench and the second trench, respectively;

[0016] based on the patterned photoresist layer, the drift region is etched to simultaneously form the first trench and the second trench, and the depth of the first trench is less than the depth of the second trench.

[0017] In one embodiment, the ratio of the depth of the second trench to the depth of the first trench is 1.1-2.0.

[0018] In one embodiment, the shielding layer of a second conductive type is formed outside the sidewall and bottom of the second trench based on the second trench, comprising:

[0019] forming a mask layer above the drift region, wherein a third opening is formed in the mask layer, the third opening is arranged corresponding to the second trench in a second direction, and an opening width of the third opening is greater than an opening width of the second trench, the second direction intersects the first direction;

[0020] performing ion implantation in an outer region of the second trench and the sidewall of the second trench based on the third opening to form the shielding layer.

[0021] In one of the embodiments, the forming of the drift region above the semiconductor substrate comprises:

[0022] epitaxially growing an epitaxial layer of the first conductive type above the semiconductor substrate;

[0023] performing ion implantation on an upper layer of the epitaxial layer to form a transition layer of the first conductive type, a well region of the second conductive type, and a source region of the first conductive type arranged in a stack, wherein a doping concentration of the shielding layer is greater than a doping concentration of the well region.

[0024] In one of the embodiments, the forming of the first metal layer filling the second trench and covering the interlayer dielectric layer further comprises:

[0025] forming a first dielectric layer on the sidewall of the second trench, the first dielectric layer covering the shielding layer outside the sidewall of the second trench.

[0026] In one of the embodiments, the forming of the trench gate structure filling the first trench and the interlayer dielectric layer covering the trench gate structure above further comprises:

[0027] forming a second dielectric material layer covering the inner wall of the first trench, the inner wall of the second trench, and the drift region above;

[0028] filling a gate material layer in the first trench and the second trench;

[0029] forming an interlayer dielectric material layer above the gate material layer and the second dielectric material layer;

[0030] etching the interlayer dielectric material layer to form the interlayer dielectric layer;

[0031] based on the interlayer dielectric layer, removing the gate material layer and the second dielectric material layer in the second trench, the second dielectric material layer and the gate material layer in the first trench respectively serving as the second dielectric layer and the gate layer to constitute the trench gate structure, and the interlayer dielectric layer covering the trench gate structure above.

[0032] In one embodiment, the forming the first metal layer filling the second trench and covering the interlayer dielectric layer further comprises:

[0033] forming a first contact layer above the drift region and the bottom of the second trench.

[0034] In one embodiment, the forming the first metal layer filling the second trench and covering the interlayer dielectric layer further comprises:

[0035] forming a second contact layer and a second metal layer on the backside of the semiconductor substrate.

[0036] In another aspect, the present application also provides a semiconductor structure, comprising:

[0037] a semiconductor substrate of a first conductive type;

[0038] a drift region above the semiconductor substrate;

[0039] a first trench and a second trench formed simultaneously in the drift region, wherein the second trench is located on both sides of the second trench in a first direction, and the opening width of the first trench is greater than the opening width of the second trench, and the depth of the first trench is less than the depth of the second trench;

[0040] a shielding layer of a second conductive type outside the sidewall and bottom of the second trench;

[0041] a trench gate structure filling the first trench;

[0042] an interlayer dielectric layer covering above the trench gate structure;

[0043] a first metal layer filling the second trench and covering the interlayer dielectric layer.

[0044] The semiconductor structure and the preparation method thereof simultaneously form the first trench and the second trench in the drift region, wherein the second trench is located on both sides of the first trench in the first direction, and the opening width of the first trench is greater than the opening width of the second trench, and the depth of the first trench is less than the depth of the second trench, that is, the first trench and the second trench can be etched simultaneously, the depth is controlled through the design difference of the opening width, the process complexity and cost are significantly reduced, the manufacturing efficiency and yield are improved, the electric field concentration effect at the corner of the trench gate structure is effectively reduced through the bottom injection area of the shielding layer of the shielding layer formed on the side wall and the outside of the bottom of the second trench, the maximum electric field strength borne by the gate oxide is reduced, the device voltage resistance performance and reliability are significantly improved, in addition, the shielding layer located on the side wall of the second trench can significantly reduce the lateral expansion width of the shielding layer, thereby reducing the cell spacing of the device, increasing the effective device cell density, improving the on-current per unit area, reducing the on-resistance, and optimizing the device performance. In some embodiments, the first dielectric layer is formed on the side wall of the second trench, and the first dielectric layer covers the shielding layer located outside the side wall of the second trench, which reduces the high-energy ion implantation damage of the side wall of the second trench, and at the same time, the depth of the shielding layer can be adjusted by adjusting the depth of the second trench through the design of the first dielectric layer, so as to accurately control the electric field distribution and the performance of the terminal protection structure. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0046] Figure 1 The flowchart of the preparation method of the semiconductor structure provided in an embodiment;

[0047] Figure 2 The cross-sectional structure schematic diagram after forming the well region in the preparation method of the semiconductor structure provided in an embodiment;

[0048] Figure 3 The cross-sectional structure schematic diagram after forming the source region in the preparation method of the semiconductor structure provided in an embodiment;

[0049] Figure 4 The cross-sectional structure schematic diagram after forming the first trench and the second trench in the preparation method of the semiconductor structure provided in an embodiment;

[0050] Figure 5A cross-sectional view of a semiconductor structure after forming a shielding layer in a method of fabricating the semiconductor structure according to an embodiment;

[0051] Figure 6 A cross-sectional view of a semiconductor structure after forming a second dielectric material layer in a method of fabricating the semiconductor structure according to an embodiment;

[0052] Figure 7 A cross-sectional view of a semiconductor structure after forming a gate material layer in a method of fabricating the semiconductor structure according to an embodiment;

[0053] Figure 8 A cross-sectional view of a semiconductor structure after removing the gate material layer above the drift region in a method of fabricating the semiconductor structure according to an embodiment;

[0054] Figure 9 A cross-sectional view of a semiconductor structure after forming an interlayer dielectric layer in a method of fabricating the semiconductor structure according to an embodiment;

[0055] Figure 10 A cross-sectional view of a semiconductor structure after removing the gate material layer and the second dielectric material layer in the second trench in a method of fabricating the semiconductor structure according to an embodiment;

[0056] Figure 11 A cross-sectional view of a semiconductor structure after forming a first dielectric layer and a first contact layer in a method of fabricating the semiconductor structure according to an embodiment;

[0057] Figure 12 A cross-sectional view of a semiconductor structure after forming a first metal layer in a method of fabricating the semiconductor structure according to an embodiment;

[0058] Figure 13 A cross-sectional view of a semiconductor structure after forming a second contact layer and a second metal layer in a method of fabricating the semiconductor structure according to an embodiment.

[0059] BRIEF DESCRIPTION OF DRAWINGS

[0060] 1 - semiconductor substrate, 2 - drift region, 21 - epitaxial layer, 22 - transition layer, 23 - well region, 24 - source region, 3 - first trench, 4 - second trench, 41 - first dielectric layer, 5 - shielding layer, 6 - trench gate structure, 61 - second dielectric layer, 611 - second dielectric material layer, 62 - gate layer, 621 - gate material layer, 7 - interlayer dielectric layer, 8 - first metal layer, 81 - first contact layer, 9 - second metal layer, 91 - second contact layer. DETAILED DESCRIPTION

[0061] For the purposes of the present application, the following terms are intended to have the meanings set forth below. The term "about" means approximately or nearly as understood by persons skilled in the art. For example, the term "about 90°" can mean in the range from 85° to 95°. The term "coupled" means directly or indirectly connected, linked, or associated, whether electrically, mechanically, or chemically, or any combination thereof. The term "coupled" does not require direct connection, linkage, or association, but rather means that the items connected, linked, or associated indirectly share some common element or feature.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0063] It should be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected," or "directly coupled" to another element or layer, then there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type.

[0064] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0065] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0066] Referring to Figure 1 The present application provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0067] Step S1: providing a semiconductor substrate 1 of a first conductivity type;

[0068] Step S2: forming a drift region 2 above the semiconductor substrate 1;

[0069] Step S3: simultaneously forming a first trench 3 and a second trench 4 in the drift region 2, wherein the second trench 4 is located on both sides of the second trench 4 in a first direction, and the opening width of the first trench 3 is greater than the opening width of the second trench 4, and the depth of the first trench 3 is less than the depth of the second trench 4;

[0070] Step S4: based on the second trench 4, forming a shielding layer 5 of a second conductivity type outside the sidewall and bottom of the second trench 4;

[0071] Step S5: forming a trench gate structure 6 filling the first trench 3 and an interlayer dielectric layer 7 covering above the trench gate structure 6;

[0072] Step S6: forming a first metal layer 8 filling the second trench 4 and covering the interlayer dielectric layer 7.

[0073] In the above example, the first trench 3 and the second trench 4 are formed synchronously in the drift region 2, wherein the second trench 4 is located on both sides of the first trench 3 in the first direction, and the opening width of the first trench 3 is greater than the opening width of the second trench 4, and the depth of the first trench 3 is less than the depth of the second trench 4, that is, the first trench 3 and the second trench 4 can be etched synchronously, and the depth control is realized by the design difference of the opening width, avoiding the multiple photolithography, complex etching and repeated filling process in the traditional double-trench process, significantly reducing the process complexity and cost, improving the manufacturing efficiency and yield; The shielding layer 5 is formed on the outside of the sidewall and the bottom of the second trench 4, and the bottom implantation region of the shielding layer 5 is arranged in a staggered manner with the two side corners of the first trench 3, which can effectively reduce the electric field concentration effect at the corner of the trench gate structure 6, thereby reducing the maximum electric field strength borne by the second dielectric layer 61, significantly improving the device voltage withstand performance and reliability. In addition, the shielding layer 5 located on the sidewall of the second trench 4 can significantly reduce the lateral expansion width of the shielding layer 5, thereby reducing the cell pitch of the device and increasing the effective device cell density, improving the on-current per unit area, while reducing the on-resistance, and optimizing the device performance.

[0074] Specifically, referring to Figures 2-3 , steps S1 to S2 are performed to provide a semiconductor substrate 1 of a first conductivity type; and a drift region 2 is formed above the semiconductor substrate 1.

[0075] It should be noted that the first conductivity type and the second conductivity type are opposite conductivity types, that is, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0076] The semiconductor substrate 1 is a silicon carbide material, for example, a 4H-SiC (tetragonal phase silicon carbide) single crystal substrate. Compared with traditional silicon materials, silicon carbide has higher breakdown field strength, higher thermal conductivity, wider band gap and stronger radiation resistance, and is particularly suitable for preparing high-voltage, high-frequency and high-power density power devices.

[0077] In one embodiment, as shown in Figures 2-3 , the drift region 2 is formed above the semiconductor substrate 1, comprising:

[0078] The first conductive type epitaxial layer 21 is epitaxially grown above the semiconductor substrate 1. The method for forming the epitaxial layer 21 includes chemical vapor deposition, physical vapor deposition or other suitable means for epitaxial growth of silicon carbide material, such as molecular beam epitaxy or hot plasma enhanced epitaxy. The epitaxial layer 21 is epitaxially grown on the semiconductor substrate 1, and the material of the epitaxial layer 21 is the same as that of the semiconductor substrate 1 to ensure lattice structure matching, reduce interface defects and improve device reliability. The epitaxial layer 21 and the semiconductor substrate 1 are of the same conductive type, but the doping concentration of the drift region 2 is less than that of the semiconductor substrate 1 to form a high-resistance drift region in the vertical direction, i.e., the second direction, thereby improving the breakdown voltage of the device. The thickness and doping of the epitaxial layer 21 can be adjusted according to the target breakdown voltage to ensure that the device has sufficient voltage withstand capability. In this embodiment, the thickness of the epitaxial layer 21 is greater than 4 μm.

[0079] Ion implantation is performed on the upper layer of the epitaxial layer 21 to form the first conductive type transition layer 22, the second conductive type well region 23 and the first conductive type source region 24 arranged in layers. The source region 24 is used to provide an ohmic contact area for achieving low contact resistance of the source electrode of the device. The well region 23 is used to form a channel region to form a conduction path under the action of a gate bias. The transition layer 22 (also referred to as a junction field-effect transistor layer, i.e., a JFET layer) is a part of the epitaxial layer 21 between the source and the drain, and is used to adjust the carrier flow path, control the electric field distribution, and affect the on-resistance and the breakdown voltage.

[0080] The implantation depth of the transition layer 22 is greater than that of the well region 23, and the implantation depth of the well region 23 is greater than that of the source region 24 to meet the overall requirements of the device structure for trench depth, electric field control and on-resistance. In this embodiment, the implantation depth of the transition layer 22 is 0.8-1.5 μm, the implantation depth of the well region 23 is 0.5-0.8 μm, and the implantation depth of the source region 24 is 0.1-0.4 μm. Here, the implantation depth refers to the vertical distance from the bottom of each doped region to the upper surface of the epitaxial layer 21, and can be adaptively optimized according to the device design parameters, the breakdown voltage level and the depth of the subsequent trench structure (such as the first trench 3 and the second trench 4). For example, to ensure that the shielding layer 5 can completely cover the bottom area of the first trench 3, the design of the trench structure should satisfy that the extension depth of the shielding layer 5 is greater than the implantation depth of the transition layer 22 to achieve a super-junction-like electric field expansion effect.

[0081] Specifically, please refer to Figure 4, performing step S3, synchronously forming the first trench 3 and the second trench 4 in the drift region 2, wherein the second trench 4 is located on both sides of the first trench 3 in the first direction, and the opening width of the first trench 3 is greater than that of the second trench 4, and the depth of the first trench 3 is less than that of the second trench 4.

[0082] In one embodiment, as shown in FIG. 1, the first trench 3 and the second trench 4 are synchronously formed in the drift region 2, including: Figure 4

[0083] forming a patterned photoresist layer (not shown) on the drift region 2, the photoresist layer including first openings with a first opening width and second openings with a second opening width, the first opening width being greater than the second opening width, and the first opening width and the second opening width corresponding to the opening width of the first trench 3 and the second trench 4, respectively;

[0084] etching the drift region 2 based on the patterned photoresist layer to synchronously form the first trench 3 and the second trench 4, the depth of the first trench 3 being less than that of the second trench 4, and the first trench 3 having a slower etching rate due to the larger opening, resulting in a smaller depth than the second trench 4.

[0085] The etching method for the drift region 2 includes a plasma dry etching process, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP) or other suitable methods. Since the etching rate is affected by the opening size to some extent, i.e., there is a so-called Etch Loading Effect, the area with a smaller opening (i.e., the second trench 4) has a greater etching depth, while the area with a larger opening (i.e., the first trench 3) has a relatively shallower etching depth within the same etching time.

[0086] Therefore, the two types of trench structures with different depths can be realized in one etching process, effectively avoiding the complex process of multiple photoetching and multiple trench etching in the traditional process, thereby realizing the one-time synchronous formation of the first trench 3 and the second trench 4 with different depths and widths, greatly simplifying the process steps, reducing the manufacturing cost, and improving the production efficiency and consistency.

[0087] In the present embodiment, the opening width of the first trench 3 can be about 0.4 μm to 0.8 μm, and the depth can be about 0.8 μm to 1.0 μm; the opening width of the second trench 4 is relatively small (e.g., about 0.2 μm to 0.4 μm), but the depth is large, which can be 1.2 μm to 1.5 μm.

[0088] ​It should be noted that the depth of the first groove 3 and the second groove 4 can be flexibly set according to the design target of the device. For example, the on-resistance, electric field distribution, channel length, and target breakdown voltage can be optimized and adjusted.

[0089] In this embodiment, the etching depth of the first groove 3 and the second groove 4 is less than the depth of the bottom of the transition layer 22 in the drift region 2, so as to ensure that the transition layer 22 is not etched through, thereby avoiding the shortening of the current path between the source and the drain, and reducing the voltage resistance and reliability of the device. This design helps to prevent the formation of a breakdown channel and shortening effect.

[0090] Further, in order to realize the electric field passivation at the corners on both sides of the first groove 3, the depth of the second groove 4 is 1.1 to 2 times the depth of the first groove. This design is conducive to the subsequent formation of the shielding layer 5 in the second groove 4, so that the shielding layer 5 forms protection at the place where the transverse electric field is the strongest, effectively reducing the electric field concentration effect at the edge of the trench gate structure, and improving the overall voltage resistance and reliability of the device.

[0091] In addition, the second groove 4 is arranged on the opposite sides of the first groove 3 in the planar layout, that is, the second groove 4 is symmetrically formed on the left and right sides of the first groove 3. This layout structure not only helps to improve the overall unit density, but also forms symmetric second grooves 4 and shielding layers 5 on both sides of the first groove 3, thereby improving the current output capability per unit area of the device, and improving the current uniformity and heat distribution.

[0092] Specifically, referring to Figure 5 , a step S4 is performed to form a shielding layer 5 of the second conductive type on the side wall and the bottom of the second groove 4.

[0093] In one embodiment, as shown in Figure 5 , the shielding layer 5 is formed on the side wall and the bottom of the second groove 4, including:

[0094] A mask layer (not shown) is formed above the drift region 2, and the mask layer has a third opening, wherein the opening width of the third opening is greater than the opening width of the second groove 4, and the position of the third opening corresponds to the position of the second groove 4 in the second direction, so as to ensure that the implantation region covers the side wall and the bottom of the second groove 4.

[0095] The third opening is used for ion implantation to form a shielding layer 5 in the outer region of the sidewall and bottom of the second trench 4. The shielding layer 5 is used for the electric field passivation of the high electric field region on both sides of the subsequent trench gate structure 6, inhibits the electric field concentration at the trench corner, and enhances the withstand voltage performance of the device. The shielding layer 5 forms a PN junction structure with the drift region 2, and the junction region forms an extended depletion layer in the reverse bias state. The electric field of the depletion layer superimposes the electric field in the trench gate structure 6 to weaken the field, i.e., to moderate the steep gradient of the electric field at the corner, to slow down the width of the potential abrupt change region near the subsequently formed trench gate structure 6, to inhibit the excessively concentrated electric field, and to diffuse the high electric field originally concentrated at the corner of the first trench 3 into the shielding layer 5, thereby playing a role similar to an electric field buffer region.

[0096] The maximum implantation depth of the shielding layer 5 can reach about 2 μm, and if the depth of the second trench 4 is considered, the actual effective depth of the shielding layer 5 in the second direction can reach about 4 μm, thereby forming an electric field regulation effect similar to a super-junction structure, which can realize the uniformization of the electric field distribution without increasing the trench spacing, thereby improving the breakdown voltage and without significantly increasing the on-resistance; if the cost and process simplification are considered, a shallower shielding layer 5 implantation can also be selected according to the actual design requirements, and only the implantation depth needs to be greater than that of the transition layer 22, thereby still effectively blocking the breakdown channel and preventing the electric field peak.

[0097] In the first direction, the horizontal width of the shielding layer can be optimized according to the cell design of the device. For example, when the cell density is high, i.e., the spacing between the first trench 3 and the second trench 4 is small, the horizontal width of the shielding layer 5 can be reduced as much as possible under the premise of meeting the electric field protection performance of the trench gate structure 6, thereby improving the cell density and reducing the on-resistance.

[0098] In the embodiment, the shielding layer 5 is respectively located outside the sidewall and the bottom of the second trench 4 and plays a synergistic role in device performance optimization. The shielding layer 5 located on the sidewall of the second trench 4 is mainly used for passivating the high electric field region on both sides of the trench gate structure 6, relieving the electric field concentration, and improving the anti-breakdown capability; at the same time, the shielding layer 5 vertically penetrates the source region 24 and the well region 23, can regulate the channel length, suppress the short channel effect, and facilitate the formation of ohmic contact with the source metal, realize the body-source short circuit, and improve the reliability and reverse bias current-carrying capacity of the device. The shielding layer 5 located at the bottom of the second trench 4 forms a deep injection region with the drift region 2 to form a deep PN junction structure, effectively extends the width of the depletion layer, and improves the vertical withstand voltage capability of the device; at the same time, it can simulate the electric field distribution characteristics of the super-junction, which can improve the breakdown voltage while reducing the conduction loss. In addition, the presence of the shielding layer 5 at the bottom can reduce the dependence on the thickness of the well region 23 to a certain extent, thereby further compressing the size of the device, improving the cell density and on-state current capability, and thus the shielding layer 5 located outside the sidewall and the bottom of the second trench 4 effectively optimizes the electric field distribution, on-state performance and structure integration of the device.

[0099] In addition, the doping concentration of the shielding layer 5 is higher than that of the well region 23, which helps to form a stronger barrier region at the edge of the trench gate, thereby enhancing the overall breakdown voltage capability of the device and improving the impact resistance and long-term reliability.

[0100] Specifically, after the formation of the first trench 3 and the second trench 4, further comprising:

[0101] The inner walls of the first trench 3 and the second trench 4 are subjected to defect repair treatment to improve the device interface quality and enhance the reliability.

[0102] The defect repair treatment on the inner walls of the first trench 3 and the second trench 4 includes: sequentially performing high-temperature annealing and sacrificial oxidation treatment on the inner walls of the first trench 3 and the second trench 4, wherein the annealing temperature ranges from 1200 to 1300°C, and the heat treatment effectively eliminates dislocations, defects and lattice damage formed on the surface of the drift region 2 during ion implantation in the shielding layer 5, the transition layer 22, the source region 24 and the well region 23. At the same time, the sacrificial oxidation process includes generating a layer of high-quality oxide film on the inner wall surface of the first trench 3 and the second trench 4, which will be removed in the subsequent process, and its role is to adsorb and eliminate surface residual defects and impurities, further improving the electrical performance of the subsequent gate oxide interface. Through the above treatment, the interface quality of the trench sidewall and the bottom can be significantly improved, the leakage current and early breakdown phenomenon can be suppressed, and the overall withstand voltage capability and long-term reliability of the device can be enhanced. The surface defects of the drift region caused by ion implantation for forming the shielding layer 5, the transition layer 22, the source region 24 and the well region 23 are further repaired.

[0103] Specifically, please refer to Figures 6-10After step S4, step S5 is performed to form the trench gate structure 6 filling the first trench 3 and the interlayer dielectric layer 7 covering the trench gate structure 6.

[0104] In one embodiment, as shown in FIG. 4, the trench gate structure 6 is formed in the first trench 3 and the interlayer dielectric layer 7 is formed on the trench gate structure 6, including: Figures 6-10

[0105] A second dielectric material layer 611 is formed to cover the inner wall of the first trench 3 and the inner wall of the second trench 4 and the drift region 2. The method for forming the second dielectric material layer 611 includes thermal oxidation, chemical vapor deposition or other suitable methods. The material of the second dielectric material layer 611 can be silicon dioxide (SiO2), silicon oxynitride (SiON) or the like commonly used in gate oxide layers. The thickness of the second dielectric material layer 611 is controlled according to the design of the channel, and is usually tens of nanometers to hundreds of nanometers.

[0106] A gate material layer 621 is filled in the first trench 3 and the second trench 4. The material of the gate material layer 621 includes polysilicon, and can also be doped polysilicon or metal gate material such as titanium nitride (TiN) and tungsten (W) to meet the requirements of high-performance devices. The method for forming the gate material layer 621 includes low-pressure chemical vapor deposition or other suitable methods to ensure coverage and filling.

[0107] The gate material layer 621 is filled in the first trench 3 and the second trench 4, including:

[0108] The gate material layer 621 is formed to cover the second dielectric material layer 611 and fill the first trench 3 and the second trench 4.

[0109] The gate material layer 621 located above the drift region 2 is removed. The method for removing the gate material layer 621 located above the drift region 2 includes dry etching, wet etching, chemical mechanical polishing or other suitable methods to make the gate material layer 621 flush with the surface of the drift region 2, providing convenience for subsequent processes.

[0110] An interlayer dielectric material layer (not shown) is formed on the gate material layer 621 and the second dielectric material layer 611. The material of the interlayer dielectric material layer includes tetraethoxysilane (TEOS) silicon oxide, boro-phospho-silicate glass (BPSG), SiO2, silicon nitride (SiN), which is used for electrical isolation and support layer of subsequent metal interconnection structure. The method for forming the interlayer dielectric material layer includes plasma-enhanced chemical vapor deposition, spin coating.

[0111] ​etching the interlayer dielectric material layer to form the interlayer dielectric layer 7, i.e. removing the interlayer dielectric material layer above the second trench 4, the method for etching the interlayer dielectric material layer including dry etching, wet etching or other suitable method;

[0112] Based on the interlayer dielectric layer 7, the gate material layer 621 and the second dielectric material layer 611 in the second trench 4 are removed, the second dielectric material layer 611 and the gate material layer 621 in the first trench 3 are respectively taken as the second dielectric layer 61 and the gate layer 62 to constitute the trench gate structure 6, and the interlayer dielectric layer 7 covers above the trench gate structure 6. The method for removing the gate material layer 621 and the second dielectric material layer 611 in the second trench 4 includes dry etching, wet etching or other suitable method;

[0113] The trench gate structure 6 is composed of the second dielectric layer 61 and the filled gate layer 62 in the first trench 3, forms a vertical channel structure and realizes the switching control function of the device. The trench gate structure 6 also helps to reduce the gate length, reduce the on-resistance and improve the current density per unit area.

[0114] The interlayer dielectric layer 7 is above the trench gate structure 6, which serves to electrically isolate the trench gate structure 6 from the first metal layer 8, provides good flatness and insulation support for the first metal layer 8, avoids the risk of short circuit and improves the reliability and processing compatibility of the device.

[0115] Specifically, referring to Figures 11-13 , step S6 is performed to form the first metal layer 8 filling the second trench 4 and covering the interlayer dielectric layer 7.

[0116] In one embodiment, as shown in Figure 11 , before forming the first metal layer 8 filling the second trench 4 and covering the interlayer dielectric layer 7, it further includes: forming a first dielectric layer 41 on the sidewall of the second trench 4, the first dielectric layer 41 covering the shielding layer 5 outside the sidewall of the second trench 4, and the first dielectric layer 41 being used to realize insulation isolation of the first metal layer 8, so as to prevent the metal layer from being electrically connected with the source region 24 or the transition layer 22 at the sidewall of the second trench 4, and ensure the electrical integrity and stability of the device structure.

[0117] Further, since the first dielectric layer 41 exists as a dielectric barrier between the sidewall of the second trench 4 and the source region 24 and the transition layer 22, it can effectively reduce the damage or impurity diffusion to the sidewall region of the second trench 4 in the high-energy ion implantation (IMP) process, reduce the probability of local defect generation and improve the device consistency and yield. At the same time, since the depth of the second trench 4 is adjustable, the first dielectric layer 41 can indirectly control the position and depth of the implantation region, realize the optimization adjustment of the electric field distribution at the bottom of the trench, and further improve the breakdown voltage and reliability of the device.

[0118] In addition, the first dielectric layer 41 can also extend upwards to cover the sidewall of the interlayer dielectric layer 7, further improving the electrical isolation capability of the first metal layer 8 and the surrounding structure, avoiding the risk of short circuit caused by edge overflow or sidewall climbing of the metal during deposition, and enhancing the mechanical stability and thermal reliability between the multi-layer structure, which is beneficial to the compatibility and processing window of the subsequent patterning and interconnection process of the metal layer.

[0119] Therefore, the design of the above-mentioned first dielectric layer 41 not only plays a role in electrical isolation and structure protection, but also provides flexibility in regulating the electric field distribution of the device, improving the injection accuracy and suppressing the edge damage in the structure design dimension, which is one of the key technologies to improve the device performance and process simplification.

[0120] In one embodiment, before forming the first metal layer 8 filling the second trench 4 and covering the interlayer dielectric layer 7, it further comprises: forming a first contact layer 81 above the drift region 2 and the bottom of the second trench 4, to further reduce the contact resistance between the first metal layer 8 and the semiconductor, thereby optimizing the on-state performance of the device.

[0121] Forming the first contact layer 81 above the drift region 2 and the bottom of the second trench 4 comprises:

[0122] Depositing a metal layer on the source region 24 above the drift region 2 and the bottom of the second trench 4, the material of the metal layer includes nickel, cobalt, titanium or other metal materials suitable for silicon carbide contact, and the thickness of the metal layer can be adjusted according to process requirements, which is not limited here;

[0123] Performing a first annealing treatment on the metal layer, for example, annealing at a temperature range of 950°C~1050°C for tens of seconds to several minutes, to promote the solid-phase reaction between the metal layer and the epitaxial layer 21 substrate of silicon carbide material, forming a metal silicide (such as nickel silicide Ni2Si, NiSi, etc.), which can significantly reduce the Schottky barrier of the metal / semiconductor interface and improve the ohmic contact characteristics;

[0124] Removing the metal layer that does not participate in the reaction, which can be removed by wet etching or dry etching method to avoid affecting the subsequent process steps;

[0125] Performing a second annealing treatment on the first contact layer 81, such as rapid thermal annealing at a temperature range of 400°C~600°C, to further stabilize the crystal structure of the metal silicide layer and improve its thermal stability and reliability.

[0126] Through the above process steps, the first contact layer 81 is formed at the source region 24 and the shielding layer 5, which is stable and low resistance, can effectively reduce the energy barrier of the ohmic contact interface, improve the electron injection efficiency, significantly reduce the source resistance and on-state resistance of the device, and is beneficial to improve the conduction performance and efficiency of the whole device. In addition, the formation of the first contact layer 81 also has good thermal stability and process compatibility, not only meeting the requirements of high-power silicon carbide devices for high-temperature work, but also avoiding the lattice damage and interface defects caused by traditional high-doped ion implantation, further improving the reliability and manufacturing yield of the device.

[0127] In one embodiment, as shown in Figure 13 After forming the first metal layer 8 filling the second trench 4 and covering the interlayer dielectric layer 7, it further includes:

[0128] Forming the second contact layer 91 and the second metal layer 9 on the back surface of the semiconductor substrate 1.

[0129] Exemplarily, forming the second contact layer 91 and the second metal layer 9 includes:

[0130] Thinning the back surface of the semiconductor substrate 1; the method of thinning the back surface of the semiconductor substrate 1 includes mechanical grinding, chemical mechanical polishing, dry etching or other suitable methods to reduce the on-resistance, improve the heat dissipation performance and power density of the device;

[0131] Depositing a metal layer (such as nickel) on the back surface of the thinned semiconductor substrate 1, and through annealing treatment, the metal layer reacts with the semiconductor substrate 1 to form the second contact layer 91, so as to significantly reduce the contact resistance of the second metal layer 9 and achieve good ohmic contact;

[0132] Forming the second metal layer 9 on the surface of the second contact layer 91. The structure of the second metal layer 9 includes a laminated structure of titanium / nickel / silver (Ti / Ni / Ag) or titanium / nickel / gold (Ti / Ni / Au), etc. Among them, the Ti layer can be used as an adhesion layer to improve the adhesion strength between the metal and the silicide; the Ni layer provides conductivity and blocks the diffusion of silver / gold; the Ag or Au layer has excellent conductivity and solderability, which is suitable for packaging soldering.

[0133] Through the above back surface process steps, a low-resistance, high-thermal-stability drain ohmic contact structure is finally formed on the back surface of the device, thereby completing the entire vertical conduction path together with the front surface source structure, significantly improving the overall conduction capability, breakdown voltage performance, and power density and heat dissipation efficiency of the device.

[0134] In one embodiment, the application further provides a semiconductor structure prepared by the above-mentioned method for preparing a semiconductor structure, comprising: a semiconductor substrate 1 of a first conductive type, a drift region 2, a first trench 3, a second trench 4, a shielding layer 5 of a second conductive type, a trench gate structure 6, an interlayer dielectric layer 7, and a first metal layer 8, wherein the drift region 2 is located above the semiconductor substrate 1; the first trench 3 and the second trench 4 are simultaneously formed in the drift region 2, the second trench 4 is located on both sides of the first trench 3 in a first direction, the opening width of the first trench 3 is greater than the opening width of the second trench 4, and the depth of the first trench 3 is less than the depth of the second trench 4; the shielding layer 5 of the second conductive type is located on the sidewall and outside of the bottom of the second trench 4; the trench gate structure 6 fills the first trench 3; the interlayer dielectric layer 7 covers the trench gate structure 6; and the first metal layer 8 fills the second trench 4 and covers the interlayer dielectric layer 7.

[0135] In one embodiment, the ratio of the depth of the second trench 4 to the depth of the first trench 3 is 1.1-2.0.

[0136] In one embodiment, the sidewall of the second trench 4 further forms a first dielectric layer 41, and the first dielectric layer 41 covers the shielding layer 5 located outside the sidewall of the second trench 4.

[0137] In one embodiment, the first metal layer 8 further forms a first contact layer 81 between the drift region 2 and the bottom of the second trench 4.

[0138] In one embodiment, the back surface of the semiconductor substrate 1 further forms a second contact layer 91 and a second metal layer 9.

[0139] It should be noted that the other structures of the semiconductor structure and the specific contents thereof can refer to the specific contents in the above-mentioned method for preparing a semiconductor structure, which will not be described here.

[0140] It should be understood that, although Figure 1 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 1 at least part of the steps in the above-mentioned method for preparing a semiconductor structure can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0141] In the description of the specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the description, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0142] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features of the above-described embodiments are described, however, as long as the combination of the technical features does not result in a contradiction, it should be considered within the scope of the present disclosure.

[0143] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The application relates to a semiconductor device and a manufacturing method thereof. Providing a semiconductor substrate of a first conductive type; forming a drift region above the semiconductor substrate; simultaneously forming a first trench and a second trench in the drift region, wherein the second trench is located on both sides of the first trench in a first direction, and the opening width of the first trench is greater than that of the second trench, and the depth of the first trench is less than that of the second trench; forming a shielding layer of a second conductive type outside the sidewall and bottom of the second trench based on the second trench; forming a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure; forming a first metal layer filling the second trench and covering the interlayer dielectric layer.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The simultaneously forming a first trench and a second trench in the drift region comprises: forming a patterned photoresist layer on the drift region, wherein the photoresist layer comprises a first opening with a first opening width and a second opening with a second opening width, the first opening width is greater than the second opening width, and the first opening width and the second opening width correspond to the opening width of the first trench and the second trench respectively; based on the patterned photoresist layer, etching the drift region to simultaneously form the first trench and the second trench, and the depth of the first trench is less than that of the second trench.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The ratio of the depth of the second trench to the depth of the first trench is 1.1-2.

0.

4. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The forming a shielding layer of a second conductive type outside the sidewall and bottom of the second trench based on the second trench comprises: forming a mask layer above the drift region, wherein a third opening is formed in the mask layer, the third opening is arranged in correspondence with the second trench in a second direction, the opening width of the third opening is greater than that of the second trench, and the second direction intersects the first direction; based on the third opening, ion implantation is carried out in the outer region of the sidewall and bottom of the second trench to form the shielding layer.

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The forming a drift region above the semiconductor substrate comprises: epitaxially growing an epitaxial layer of a first conductive type above the semiconductor substrate; performing ion implantation on the upper layer of the epitaxial layer to form a transition layer of a first conductive type, a well region of a second conductive type and a source region of a first conductive type arranged in layers, wherein the doping concentration of the shielding layer is greater than that of the well region.

6. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before the forming a first metal layer filling the second trench and covering the interlayer dielectric layer, the method further comprises: forming a first dielectric layer on the sidewall of the second trench, and the first dielectric layer covers the shielding layer outside the sidewall of the second trench.

7. The method of claim 1, wherein the semiconductor structure is formed by a method comprising: The forming a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure comprises: forming a second dielectric material layer covering the inner wall of the first trench, the inner wall of the second trench and the drift region above the drift region; filling a gate material layer in the first trench and the second trench; forming an interlayer dielectric material layer above the gate material layer and the second dielectric material layer; etching the interlayer dielectric material layer to form the interlayer dielectric layer; Based on the interlayer dielectric layer, the gate material layer and the second dielectric material layer in the second trench are removed, and the second dielectric material layer and the gate material layer located in the first trench are respectively taken as a second dielectric layer and a gate layer to form the trench gate structure, and the interlayer dielectric layer covers the trench gate structure.

8. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before the forming of the first metal layer filling the second trench and covering the interlayer dielectric layer, the method further comprises: forming a first contact layer above the drift region and at the bottom of the second trench.

9. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: After the forming of the first metal layer filling the second trench and covering the interlayer dielectric layer, the method further comprises: forming a second contact layer and a second metal layer on the back surface of the semiconductor substrate.

10. A semiconductor structure, characterized by Comprise: a semiconductor substrate of a first conductive type; a drift region located above the semiconductor substrate; a first trench and a second trench formed synchronously in the drift region, wherein the second trench is located on both sides of the second trench in a first direction, and the opening width of the first trench is greater than the opening width of the second trench, and the depth of the first trench is less than the depth of the second trench; a shielding layer of a second conductive type located outside the sidewall and the bottom of the second trench; a trench gate structure filling the first trench; an interlayer dielectric layer covering the trench gate structure; a first metal layer filling the second trench and covering the interlayer dielectric layer.

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